ADSP-21479BBCZ-2A - Analog Devices

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SHARC Processor

ADSP-21478/ADSP-21479

Rev. A

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SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—up to 5 Mbits of on-chip RAM, 4 Mbits of

on-chip ROM

Up to 300 MHz operating frequency

Qualified for automotive applications. See Automotive Prod-

ucts on Page 68

Code compatible with all other members of the SHARC family

The ADSP-2147x processors are available with unique audio-

centric peripherals, such as the digital applications

interface, serial ports, precision clock generators, S/PDIF

transceiver, asynchronous sample rate converters, input

data port, and more.

For complete ordering information, see Ordering Guide on

Page 69.

Figure 1. Functional Block Diagram

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 Stage

Sequencer

PEx PEy

PMD

64-BIT IOD0 32-BIT

EPD BUS 64-BIT

Core Bus

Cross Bar

S/PDIF

Tx/Rx

PCG

DPI Routing/Pins

SPI/B UART

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

AMI SDRAM

CTL

External Port Pin MUX

TIMER

SPORT

ASRC

PWM

DAG1/2 Core

Timer

PDAP/

IDP

TWI

IOD0 BUS DTCP/

MTM

PCG

PERIPHERAL BUS 32-BIT

CORE

FLAGS/

PWM3

JTAG

Internal Memory

DMD

64-BIT

PMD 64-BIT

CORE

FLAGS

IOD1

32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI Peripherals DAI Peripherals Peripherals External

Port

SIMD Core

THERMAL

DIODE

FFT

FIR

IIR

MLB

SPEP BUS

DMD

64-BIT

FLAGx/IRQx/

TMREXP

WDT

RTC

SHIFT

REG

DAI Routing/Pins

Rev. A | Page 2 of 72 | September 2011

ADSP-21478/ADSP-21479

TABLE OF CONTENTS

Summary ............................................................... 1

Product Application Restriction .................................. 2

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 7

I/O Processor Features ......................................... 11

System Design .................................................... 12

Development Tools ............................................. 12

Additional Information ........................................ 13

Related Signal Chains .......................................... 13

Pin Function Descriptions ....................................... 14

Specifications ........................................................ 19

Operating Conditions .......................................... 19

Electrical Characteristics ....................................... 20

Package Information ........................................... 22

ESD Sensitivity ................................................... 22

Maximum Power Dissipation ................................. 22

Absolute Maximum Ratings ................................... 22

Timing Specifications ........................................... 23

Output Drive Currents ......................................... 61

Test Conditions .................................................. 61

Capacitive Loading .............................................. 61

Thermal Characteristics ........................................ 62

100-LQFP_EP Lead Assignment ................................ 64

196-Ball BGA Ball Assignment .................................. 66

Outline Dimensions ................................................ 67

Surface-Mount Design .......................................... 68

Automotive Products .............................................. 68

Ordering Guide ..................................................... 69

REVISION HISTORY

9/11—Rev. 0 to Rev. A

Corrected all outstanding document errata.

Added specifications to Shift Register ......................... 57

Added product models to Ordering Guide ................... 69

PRODUCT APPLICATION RESTRICTION

Not for use in in-vivo applications for body fluid constituent

monitoring, including monitoring one or more of the compo-

nents that form, or may be a part of, or contaminate human

blood or other body fluids, such as, but not limited to, car-

boxyhemoglobin, methemoglobin total hemoglobin, oxygen

saturation, oxygen content, fractional arterial oxygen satura-

tion, bilirubin, glucose, drugs, lipids, water, protein, and pH.

ADSP-21478/ADSP-21479

Rev. A | Page 3 of 72 | September 2011

GENERAL DESCRIPTION

The ADSP-21478 and ADSP-21479 SHARC

processors are

members of the SIMD SHARC family of DSPs that feature Ana-

log Devices’ Super Harvard Architecture. The processors are

source code compatible with the ADSP-2126x, ADSP-2136x,

ADSP-2137x, ADSP-2146x, and ADSP-2116x DSPs as well as

with first generation ADSP-2106x SHARC processors in SISD

(single-instruction, single-data) mode. These processors are

32-bit/40-bit floating-point processors optimized for high per-

formance audio applications with a large on-chip SRAM,

multiple internal buses to eliminate I/O bottlenecks, and an

innovative digital applications interface (DAI).

Table 1 shows performance benchmarks for the ADSP-2147x

processors. Table 2 shows the features of the individual product

offerings.

The diagram on Page 1 shows the two clock domains (core and

I/O processor) that make up the ADSP-2147x processors. The

core clock domain contains the following features.

• Two processing elements (PEx, PEy), each of which com-

prises an ALU, multiplier, shifter, and data register file

• Two data address generators (DAG1, DAG2)

• A program sequencer with instruction cache

• PM and DM buses capable of supporting 2 × 64-bit data

transfers between memory and the core at every core pro-

cessor cycle

• One periodic interval timer with pinout

• On-chip SRAM (up to 5 Mbit)

• A JTAG test access port for emulation and boundary scan.

The JTAG provides software debug through user break-

points, which allows flexible exception handling.

The block diagram of the ADSP-2147x on Page 1 also shows the

peripheral clock domain (also known as the I/O processor),

which contains the following features:

•IOD0 (peripheral DMA) and IOD1 (external port DMA)

buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an asynchronous memory interface

(AMI) and SDRAM controller

•4 units for pulse width modulation (PWM) control

• 1 memory-to-memory (MTM) unit for internal-to-internal

memory transfers

Table 1. Processor Benchmarks

Benchmark Algorithm

Speed

(at 300 MHz)

1024 Point Complex FFT (Radix 4, with Reversal) 30.59 s

FIR Filter (per Tap)

Assumes two files in multichannel SIMD mode.

1.66 ns

IIR Filter (per Biquad)

6.65 ns

Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]

[4 × 4] × [4 × 1]

14.99 ns

26.66 ns

Divide (y/×) 11.61 ns

Inverse Square Root 18.08 ns

Table 2. ADSP-2147x Family Features

Feature ADSP-21478 ADSP-21479

Frequency Up to 300 MHz

RAM 3 Mbit 5 Mbit

ROM N/A

Pulse-Width Modulation 4 Units (3 in 100-lead package)

External Port Interface

(SDRAM, AMI)

Yes, 16-Bit

Serial Ports 8

Direct DMA from SPORTs to

External Memory

Yes

FIR, IIR, FFT Accelerator Yes

MediaLB Interface Automotive Models Only

Watch Dog Timer

Yes

Real-Time Clock

Yes

Shift Register

Yes

IDP/PDAP Yes

UART 1

DAI (SRU)/DPI (SRU2) 20/14 Pins

S/PDIF Transceiver 1

SPI 2

TWI 1

SRC SNR Performance –128 dB

Thermal Diode

Yes

VISA Support Yes

Package

196-Ball CSP_BGA

100-Lead LQFP

The 100-lead packages of the ADSP-21478 and ADSP-21479 processors do not

contain an external port. The SDRAM controller pins must be disabled when

using this package. For more information, see Pin Function Descriptions

on Page 15.

Available on the 196-ball CSP_BGA package only.

Available on the 100-lead package only.

Table 2. ADSP-2147x Family Features (Continued)

Feature ADSP-21478 ADSP-21479

Rev. A | Page 4 of 72 | September 2011

ADSP-21478/ADSP-21479

• Digital applications interface that includes four precision

clock generators (PCG), an input data port (IDP/PDAP)

for serial and parallel interconnect, an S/PDIF

receiver/transmitter, four asynchronous sample rate con-

verters, eight serial ports, a shift register, and a flexible

signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, a 2-

wire interface, one UART, two serial peripheral interfaces

(SPI), 2 precision clock generators (PCG), three pulse

width modulation (PWM) units, and a flexible signal rout-

ing unit (DPI SRU).

As shown in the SHARC core block diagram on Page 5, the pro-

cessors use two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. With its SIMD computational hard-

ware, the processors can perform 1.8 GFLOPS running at

300 MHz.

FAMILY CORE ARCHITECTURE

The processors are code compatible at the assembly level with

the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,

ADSP-21160, and ADSP-21161, and with the first generation

ADSP-2106x SHARC processors. The ADSP-2147x shares

architectural features with the ADSP-2126x, ADSP-2136x,

ADSP-2137x, ADSP-2146x, and ADSP-2116x SIMD SHARC

processors, as shown in Figure 2 and detailed in the following

sections.

SIMD Computational Engine

The processors contain two computational processing elements

that operate as a single-instruction, multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. SIMD mode allows

the processor to execute the same instruction in both processing

elements, but each processing element operates on different

data. This architecture is efficient at executing math intensive

DSP algorithms.

SIMD mode also affects the way data is transferred between

memory and the processing elements because twice the data

bandwidth is required to sustain computational operation in the

processing elements. Therefore, entering SIMD mode also dou-

bles the bandwidth between memory and the processing

elements. When using the DAGs to transfer data in SIMD

mode, two data values are transferred with each memory or reg-

ister file access.

SIMD mode is supported from external SDRAM but is not sup-

ported in the AMI.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

Timer

The processor contains a core timer that can generate periodic

software interrupts. The core timer can be configured to use

FLAG3 as a timer expired signal.

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register (16 primary, 16 secondary) register files,

combined with the processor’s enhanced Harvard architecture,

allow unconstrained data flow between computation units and

internal memory. The registers in PEX are referred to as

R0–R15 and in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that

can be activated during interrupt servicing for a fast context

switch. The data registers in the register file, the DAG registers,

and the multiplier result registers all have secondary registers.

The primary registers are active at reset, while the secondary

registers are activated by control bits in a mode control register.

Universal Registers

Universal registers can be used for general-purpose tasks. The

USTAT (4) registers allow easy bit manipulations (Set, Clear,

Toggle, Test, XOR) for all peripheral control and status

registers.

The data bus exchange register (PX) permits data to be passed

between the 64-bit PM data bus and the 64-bit DM data bus, or

between the 40-bit register file and the PM/DM data bus. These

registers contain hardware to handle the data width difference.

Single-Cycle Fetch of Instruction and Four Operands

The processors feature an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 2). With its separate program and data memory

buses and on-chip instruction cache, the processor can simulta-

neously fetch four operands (two over each data bus) and one

instruction (from the cache), all in a single cycle.

Instruction Cache

The processor includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full speed execution of core looped operations such

as digital filter multiply-accumulates, and FFT butterfly

processing.

ADSP-21478/ADSP-21479

Rev. A | Page 5 of 72 | September 2011

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The processor’s two data address generators (DAGs) are used

for indirect addressing and implementing circular data buffers

in hardware. Circular buffers allow efficient programming of

delay lines and other data structures required in digital signal

processing, and are commonly used in digital filters and Fourier

transforms. The two DAGs of the processors contain sufficient

registers to allow the creation of up to 32 circular buffers (16

primary register sets, 16 secondary). The DAGs automatically

handle address pointer wraparound, reduce overhead, increase

performance, and simplify implementation. Circular buffers can

start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

processors can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from

previous SHARC processors, the processors support new

instructions of 16 and 32 bits. This feature, called Variable

Instruction Set Architecture (VISA), drops redundant/unused

bits within the 48-bit instruction to create more efficient and

compact code. The program sequencer supports fetching these

16-bit and 32-bit instructions from both internal and external

SDRAM memory. This support is not extended to the asynchro-

nous memory interface (AMI). Source modules need to be built

using the VISA option, in order to allow code generation tools

to create these more efficient opcodes.

On-Chip Memory

The ADSP-21478 processor contains 3 Mbits of internal RAM

(Table 3) and the ADSP-21479 processor contains 5 Mbits of

internal RAM (Table 4). Each block can be configured for dif-

ferent combinations of code and data storage. Each memory

block supports single-cycle, independent accesses by the core

processor and I/O processor.

Figure 2. SHARC Core Block Diagram

SIMD Core

CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1

16×32

MRF

80-BIT

ALU

MULTIPLIER SHIFTER

Rx/Fx

PEx

16×40-BIT

JTAG

DMD/PMD 64

ASTATx

STYKx

ASTATy

STYKy

TIMER

Sx/SFx

PEy

16×40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

USTAT

4×32-BIT

64-BIT

DAG2

16×32

ALU MULTIPLIER

SHIFTER

DATA

SWAP

PM ADDRESS 24

PM DATA 48

Rev. A | Page 6 of 72 | September 2011

ADSP-21478/ADSP-21479

The processor’s SRAM can be configured as a maximum of

160k words of 32-bit data, 320k words of 16-bit data, 106.7k

words of 48-bit instructions (or 40-bit data), or combinations of

different word sizes up to 5 megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit

floating-point storage format is supported that effectively dou-

bles the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point

formats is performed in a single instruction. While each mem-

ory block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a

memory block, assures single-cycle execution with two data

transfers. In this case, the instruction must be available in the

cache.

The memory maps in Table 3 and Table 4 display the internal

memory address space of the processors. The 48-bit space sec-

tion describes what this address range looks like to an

instruction that retrieves 48-bit memory. The 32-bit section

describes what this address range looks like to an instruction

that retrieves 32-bit memory.

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2 × 64-bits at CCLK speed)

and the IOD0/1 buses (2 × 32-bit at PCLK speed).

Table 3. ADSP-21478 Internal Memory Space (3 Mbit)

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

Block 0 ROM (Reserved)

0x0008 0000–0x0008 AAA9

Block 0 ROM (Reserved)

0x0008 0000–0x0008 FFFF

Block 0 ROM (Reserved)

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

Reserved

0x0008 AAAA–0x0008 BFFF

Reserved

0x0009 0000–0x0009 1FFF

Reserved

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 CFFF

Block 0 SRAM

0x0008 C000–0x0009 1554

Block 0 SRAM

0x0009 2000–0x0009 9FFF

Block 0 SRAM

0x0012 4000–0x0013 3FFF

Reserved

0x0004 D000–0x0004 FFFF

Reserved

0x0009 1555–0x0009 FFFF

Reserved

0x0009 A000–0x0009 FFFF

Reserved

0x0013 4000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

Block 1 ROM (Reserved)

0x000A 0000–0x000A AAA9

Block 1 ROM (Reserved)

0x000A 0000–0x000A FFFF

Block 1 ROM (Reserved)

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

Reserved

0x000A AAAA–0x000A BFFF

Reserved

0x000B 0000–0x000B 1FFF

Reserved

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 CFFF

Block 1 SRAM

0x000A C000–0x000B 1554

Block 1 SRAM

0x000B 2000–0x000B 9FFF

Block 1 SRAM

0x0016 4000–0x0017 3FFF

Reserved

0x0005 D000–0x0005 FFFF

Reserved

0x000B 1555–0x000B FFFF

Reserved

0x000B A000–0x000B FFFF

Reserved

0x0017 4000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 1FFF

Block 2 SRAM

0x000C 0000–0x000C 2AA9

Block 2 SRAM

0x000C 0000–0x000C 3FFF

Block 2 SRAM

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000– 0x0006 FFFF

Reserved

0x000C 2AAA–0x000D FFFF

Reserved

0x000C 4000–0x000D FFFF

Reserved

0x0018 8000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 1FFF

Block 3 SRAM

0x000E 0000–0x000E 2AA9

Block 3 SRAM

0x000E 0000–0x000E 3FFF

Block 3 SRAM

0x001C 0000–0x001C 7FFF

Reserved

0x0007 2000–0x0007 FFFF

Reserved

0x000E 2AAA–0x000F FFFF

Reserved

0x000E 4000–0x000F FFFF

Reserved

0x001C 8000–0x001F FFFF

Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales

representative for additional details.

ADSP-21478/ADSP-21479

Rev. A | Page 7 of 72 | September 2011

ROM Based Security

The processors have a ROM security feature that provides hard-

ware support for securing user software code by preventing

unauthorized reading from the internal code. When using this

feature, the processors do not boot-load any external code, exe-

cuting exclusively from internal ROM. Additionally, the

processor is not freely accessible via the JTAG port. Instead, a

unique 64-bit key, which must be scanned in through the JTAG

or Test Access Port, is assigned to each customer. The device

ignores an incorrect key. Emulation features are available after

the correct key is scanned.

Digital Transmission Content Protection

The DTCP specification defines a cryptographic protocol for

protecting audio entertainment content from illegal copying,

intercepting, and tampering as it traverses high performance

digital buses, such as the IEEE 1394 standard. Only legitimate

entertainment content delivered to a source device via another

approved copy protection system (such as the DVD content

scrambling system) is protected by this copy protection system.

For more information on this feature, contact your local ADI

sales office.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2147x family contains a rich set of peripherals that

support a wide variety of applications including high quality

audio, medical imaging, communications, military, test equip-

ment, 3D graphics, speech recognition, motor control, imaging,

and other applications.

External Memory

The external memory interface supports access to the external

memory through core and DMA accesses. The external memory

address space is divided into four banks. Any bank can be pro-

grammed as either asynchronous or synchronous memory. The

external ports are comprised of the following modules.

Table 4. ADSP-21479 Internal Memory Space (5 Mbit)

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 7FFF

Block 0 ROM (Reserved)

0x0008 0000–0x0008 AAA9

Block 0 ROM (Reserved)

0x0008 0000–0x0008 FFFF

Block 0 ROM (Reserved)

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 8FFF

Reserved

0x0008 AAAA–0x0008 BFFF

Reserved

0x0009 0000–0x0009 1FFF

Reserved

0x0012 0000–0x0012 3FFF

Block 0 SRAM

0x0004 9000–0x0004 EFFF

Block 0 SRAM

0x0008 C000–0x0009 3FFF

Block 0 SRAM

0x0009 2000–0x0009 DFFF

Block 0 SRAM

0x0012 4000–0x0013 BFFF

Reserved

0x0004 F000–0x0004 FFFF

Reserved

0x0009 4000–0x0009 FFFF

Reserved

0x0009 E000–0x0009 FFFF

Reserved

0x0013 C000–0x0013 FFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 7FFF

Block 1 ROM (Reserved)

0x000A 0000–0x000A AAA9

Block 1 ROM (Reserved)

0x000A 0000–0x000AFFFF

Block 1 ROM (Reserved)

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 8FFF

Reserved

0x000A AAAA–0x000A BFFF

Reserved

0x000B 0000–0x000B 1FFF

Reserved

0x0016 0000–0x0016 3FFF

Block 1 SRAM

0x0005 9000–0x0005 EFFF

Block 1 SRAM

0x000A C000–0x000B 3FFF

Block 1 SRAM

0x000B 2000–0x000B DFFF

Block 1 SRAM

0x0016 4000–0x0017 BFFF

Reserved

0x0005 F000–0x0005 FFFF

Reserved

0x000B 4000–0x000B FFFF

Reserved

0x000B E000–0x000B FFFF

Reserved

0x0017 C000–0x0017 FFFF

Block 2 SRAM

0x0006 0000–0x0006 3FFF

Block 2 SRAM

0x000C 0000–0x000C 5554

Block 2 SRAM

0x000C 0000–0x000C 7FFF

Block 2 SRAM

0x0018 0000–0x0018 FFFF

Reserved

0x0006 4000– 0x0006 FFFF

Reserved

0x000C 5555–0x0000D FFFF

Reserved

0x000C 8000–0x000D FFFF

Reserved

0x0019 0000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 3FFF

Block 3 SRAM

0x000E 0000–0x000E 5554

Block 3 SRAM

0x000E 0000–0x000E 7FFF

Block 3 SRAM

0x001C 0000–0x001C FFFF

Reserved

0x0007 4000–0x0007 FFFF

Reserved

0x000E 5555–0x0000F FFFF

Reserved

0x000E 8000–0x000F FFFF

Reserved

0x001D 0000–0x001F FFFF

Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales

representative for additional details.

Rev. A | Page 8 of 72 | September 2011

ADSP-21478/ADSP-21479

• An AMI which communicates with SRAM, FLASH, and

other devices that meet the standard asynchronous SRAM

access protocol. The AMI supports 6M words of external

memory in bank 0 and 8M words of external memory in

bank 1, bank 2, and bank 3.

• An SDRAM controller that supports a glueless interface

with any of the standard SDRAMs. The SDC supports 62M

words of external memory in bank 0, and 64M words of

external memory in bank 1, bank 2, and bank 3.

• Arbitration logic to coordinate core and DMA transfers

between internal and external memory over the

external port.

External Port

The external port provides a high performance, glueless inter-

face to a wide variety of industry-standard memory devices. The

external port, available on the 196-ball CSP_BGA, may be used

to interface to synchronous and/or asynchronous memory

devices through the use of its separate internal memory control-

lers. The first is an SDRAM controller for connection of

industry-standard synchronous DRAM devices while the sec-

ond is an asynchronous memory controller intended to

interface to a variety of memory devices. Four memory select

pins enable up to four separate devices to coexist, supporting

any desired combination of synchronous and asynchronous

device types. Non-SDRAM external memory address space is

shown in Table 5.

SIMD Access to External Memory

The SDRAM controller supports SIMD access on the 64-bit

external port data bus (EPD) which allows access to the comple-

mentary registers on the PEy unit in the normal word space

(NW). This improves performance since there is no need to

explicitly load the complimentary registers (as in SISD mode).

VISA and ISA Access to External Memory

The SDRAM controller supports VISA code operation which

reduces the memory load since the VISA instructions are com-

pressed. Moreover, bus fetching is reduced because, in the best

case, one 48-bit fetch contains three valid instructions. Code

execution from the traditional ISA operation is also supported.

Note that code execution is only supported from bank 0 regard-

less of VISA/ISA. Table 6 shows the address ranges for

instruction fetch in each mode.

SDRAM Controller

The SDRAM controller, available on the ADSP-2147x in the

196-ball CSP_BGA package, provides an interface of up to four

separate banks of industry-standard SDRAM devices or

DIMMs, at speeds up to f

SDCLK

. Fully compliant with the

SDRAM standard, each bank has its own memory select line

(MS0–MS3), and can be configured to contain between

4M bytes and 256M bytes of memory. SDRAM external mem-

ory address space is shown in Table 7.

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

SDRAM and the AMI interface do not support 32-bit wide

devices.

The SDRAM controller address, data, clock, and control pins

can drive loads up to distributed 30 pF. For larger memory sys-

tems, the SDRAM controller external buffer timing should be

selected and external buffering should be provided so that the

load on the SDRAM controller pins does not exceed 30 pF.

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions as well as

32-bit data are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap.

Asynchronous Memory Controller

The asynchronous memory controller, available on the

ADSP-2147x in the 196-ball CSP_BGA package, provides a con-

figurable interface for up to four separate banks of memory or

I/O devices. Each bank can be independently programmed with

different timing parameters, enabling connection to a wide vari-

ety of memory devices including SRAM, flash, and EPROM, as

well as I/O devices that interface with standard memory control

lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3

occupy a 8M word window in the processor’s address space but,

if not fully populated, these windows are not made contiguous

by the memory controller logic.

Table 5. External Memory for Non-SDRAM Addresses

Bank

Size in

Words Address Range

Bank 0 6M 0x0020 0000–0x007F FFFF

Bank 1 8M 0x0400 0000–0x047F FFFF

Bank 2 8M 0x0800 0000–0x087F FFFF

Bank 3 8M 0x0C00 0000–0x0C7F FFFF

Table 6. External Bank 0 Instruction Fetch

Access Type

Size in

Words Address Range

ISA (NW) 4M 0x0020 0000–0x005F FFFF

VISA (SW) 10M 0x0060 0000–0x00FF FFFF

Table 7. External Memory for SDRAM Addresses

Bank

Size in

Words Address Range

Bank 0 62M 0x0020 0000–0x03FF FFFF

Bank 1 64M 0x0400 0000–0x07FF FFFF

Bank 2 64M 0x0800 0000–0x0BFF FFFF

Bank 3 64M 0x0C00 0000–0x0FFF FFFF

ADSP-21478/ADSP-21479

Rev. A | Page 9 of 72 | September 2011

External Port Throughput

The throughput for the external port, based on 133 MHz clock

and 16-bit data bus, is 88 M bytes/s for the AMI and 266 M

bytes/s for SDRAM.

MediaLB

The automotive models of the processors have an MLB interface

which allows the processor to function as a media local bus

device. It includes support for both 3-pin and 5-pin media local

bus protocols. It supports speeds up to 1024 FS (49.25 M

bits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up to

124 bytes of data per media local bus frame. For a list of auto-

motive products, see Automotive Products on Page 68.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the DAI pins

(DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The associated peripherals include eight serial ports, four preci-

sion clock generators (PCG), a S/PDIF transceiver, four ASRCs,

and an input data port (IDP). The IDP provides an additional

input path to the SHARC core, configurable as either eight

channels of serial data, or a single 20-bit wide synchronous par-

allel data acquisition port. Each data channel has its own DMA

channel that is independent from the processor’s serial ports.

Serial Ports (SPORTs)

The processors feature eight synchronous serial ports that pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive DMA

channels of audio data when all eight SPORTs are enabled, or

four full duplex TDM streams of 128 channels per frame.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard serial mode

• Multichannel (TDM) mode

•I

S mode

•Packed I

S mode

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left justified, I

S or

right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources, such as the

SPORTs, external pins, the precision clock generators (PCGs),

and are controlled by the SRU control registers.

Asynchronous Sample Rate Converter (SRC)

The sample rate converter contains four blocks and is the same

core as that used in the AD1896 192 kHz stereo asynchronous

sample rate converter. The SRC block provides up to 128 dB

SNR and is used to perform synchronous or asynchronous sam-

ple rate conversion across independent stereo channels, without

using internal processor resources. The four SRC blocks can

also be configured to operate together to convert multichannel

audio data without phase mismatches. Finally, the SRC can be

used to clean up audio data from jittery clock sources such as

the S/PDIF receiver.

Input Data Port

The IDP provides up to eight serial input channels—each with

its own clock, frame sync, and data inputs. The eight channels

are automatically multiplexed into a single 32-bit by eight-deep

FIFO. Data is always formatted as a 64-bit frame and divided

into two 32-bit words. The serial protocol is designed to receive

audio channels in I

S, left-justified sample pair, or right-justified

mode.

The IDP also provides a parallel data acquisition port (PDAP)

which can be used for receiving parallel data. The PDAP port

has a clock input and a hold input. The data for the PDAP can

be received from DAI pins or from the external port pins. The

PDAP supports a maximum of 20-bit data and four different

packing modes to receive the incoming data.

Precision Clock Generators

The precision clock generators (PCG) consist of four units, each

of which generates a pair of signals (clock and frame sync)

derived from a clock input signal. The units, A B, C, and D, are

identical in functionality and operate independently of each

other. The two signals generated by each unit are normally used

as a serial bit clock/frame sync pair.

The outputs of PCG A and B can be routed through the DAI

pins and the outputs of PCG C and D can be driven on to the

DAI as well as the DPI pins.

Rev. A | Page 10 of 72 | September 2011

ADSP-21478/ADSP-21479

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), one universal asynchro-

nous receiver-transmitter (UART), 12 flags, a 2-wire interface

(TWI), three PWM modules (PWM3–1), and two general-

purpose timers.

Serial Peripheral (Compatible) Interface (SPI)

The SPI is an industry-standard synchronous serial link,

enabling the SPI-compatible port to communicate with other

SPI compatible devices. The SPI consists of two data pins, one

device select pin, and one clock pin. It is a full-duplex synchro-

nous serial interface, supporting both master and slave modes.

The SPI port can operate in a multimaster environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The SPI-compatible periph-

eral implementation also features programmable baud rate and

clock phase and polarities. The SPI-compatible port uses open

drain drivers to support a multimaster configuration and to

avoid data contention.

UART Port

The processors provide a full-duplex Universal Asynchronous

Receiver/Transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface

standard. The UART port also includes support for 5 to 8 data

bits, 1 or 2 stop bits, and none, even, or odd parity. The UART

port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Support for bit rates ranging from (f

PCLK

/1,048,576) to

PCLK

/16) bits per second.

• Support for data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

generating 16 PWM outputs in total. Each PWM group pro-

duces two pairs of PWM signals on the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

midpoint of the PWM period. In double update mode, a second

updating of the PWM registers is implemented at the midpoint

of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

PWM signals can be mapped to the external port address lines

or to the DPI pins.

Timers

The processors have a total of three timers: a core timer that can

generate periodic software interrupts and two general-purpose

timers that can generate periodic interrupts and be indepen-

dently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watch dog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and the general-purpose timers have one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables the general-

purpose timer.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I

C bus protocol.

The TWI master incorporates the following features:

• 7-bit addressing

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

ADSP-21478/ADSP-21479

Rev. A | Page 11 of 72 | September 2011

Shift Register

The shift register can be used as a serial to parallel data con-

verter. The shift register module consists of an 18-stage serial

shift register, 18-bit latch, and three-state output buffers. The

shift register and latch have separate clocks. Data is shifted into

the serial shift register on the positive-going transitions of the

shift register serial clock (SR_SCLK) input. The data in each

flip-flop is transferred to the respective latch on a positive-going

transition of the shift register latch clock (SR_LAT) input.

The shift register’s signals can be configured as follows.

• The SR_SCLK can come from any of the SPORT0–7 SCLK

outputs, PCGA/B clock, any of the DAI pins (1–8), and one

dedicated pin (SR_SCLK).

• The SR_LAT can come from any of SPORT0–7 Frame sync

outputs, PCGA/B frame sync, any of the DAI pins (1–8),

and one dedicated pin (SR_LAT).

• The SR_SDI input can from any of SPORT0–7 serial data

outputs, any of the DAI pins (1–8), and one dedicated pin

(SR_SDI).

Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must

come from same source except in the case of where SR_SCLK

comes from PCGA/B or SR_SCLK and SR_LAT come from

PCGA/B.

If SR_SCLK comes from PCGA/B, then SPORT0–7 generates

the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT

come from PCGA/B, then SPORT0–7 generates the SR_SDI

signal.

I/O PROCESSOR FEATURES

The I/O processor provides up to 65 channels of DMA as well as

an extensive set of peripherals.

DMA Controller

The DMA controller operates independently and invisibly to

the processor core, allowing DMA operations to occur while the

core is simultaneously executing its program instructions. DMA

transfers can occur between the processor’s internal memory

and its serial ports, the SPI-compatible (serial peripheral inter-

face) ports, the IDP (input data port), the parallel data

acquisition port (PDAP) or the UART.

Up to 65 channels of DMA are available on the processors as

shown in Table 8.

Programs can be downloaded using DMA transfers. Other

DMA features include interrupt generation upon completion of

DMA transfers, and DMA chaining for automatic linked DMA

transfers.

Delay Line DMA

The processor provides delay line DMA functionality. This

allows processor reads and writes to external delay line buffers

(and therefore to external memory) with limited core

interaction.

Scatter/Gather DMA

The processor provides scatter/gather DMA functionality. This

allows processor DMA reads/writes to/from noncontiguous

memory blocks.

FFT Accelerator

The FFT accelerator implements radix-2 complex/real input,

complex output FFTs with no core intervention. The FFT accel-

erator runs at the peripheral clock frequency.

FIR Accelerator

The FIR (finite impulse response) accelerator consists of a 1024

word coefficient memory, a 1024 word deep delay line for the

data, and four MAC units. A controller manages the accelerator.

The FIR accelerator runs at the peripheral clock frequency.

IIR Accelerator

The IIR (infinite impulse response) accelerator consists of a

1440 word coefficient memory for storage of biquad coeffi-

cients, a data memory for storing the intermediate data and one

MAC unit. A controller manages the accelerator. The IIR accel-

erator runs at the peripheral clock frequency.

Watch Dog Timer (WDT)

The processors include a 32-bit watch dog timer that can be

used to implement a software watch dog function. A software

watch dog can improve system reliability by forcing the proces-

sor to a known state through generation of a system reset if the

timer expires before being reloaded by software. Software ini-

tializes the count value of the timer, and then enables the timer.

The WDT is used to supervise the stability of the system soft-

ware. When used in this way, software reloads the WDT in a

regular manner so that the downward counting timer never

expires. An expiring timer then indicates that system software

might be out of control.

The WDT resets both the core and the internal peripherals.

Software must be able to determine if the watch dog was the

source of the hardware reset by interrogating a status bit in the

watch dog timer control register.

Table 8. DMA Channels

Peripheral DMA Channels

SPORTs 16

PDAP 8

SPI 2

UART 2

External Port 2

Accelerators 2

Memory-to-Memory 2

MediaLB

Automotive models only.

Table 8. DMA Channels (Continued)

Peripheral DMA Channels

Rev. A | Page 12 of 72 | September 2011

ADSP-21478/ADSP-21479

The watch dog timer also has an internal RC oscillator that can

be used as the clock source. The internal RC oscillator can be

used as an optional alternative to using an external clock applied

to the WDT_CLIN pin.

Real-Time Clock

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the SHARC

processor. Connect RTC pins RTXI and RTXO with external

components as shown in Figure 3.

The RTC peripheral has dedicated power supply pins so that it

can remain powered up and clocked even when the rest of the

processor is in a low power state. The RTC provides several pro-

grammable interrupt options, including interrupt per second,

minute, hour, or day clock ticks, interrupt on programmable

stopwatch countdown, or interrupt at a programmed alarm

time. An RTCLKOUT signal that operates at 1 Hz is also pro-

vided for calibration.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter. When the alarm

interrupt is enabled, the alarm function generates an interrupt

when the output of the timer matches the programmed value in

the alarm control register. There are two alarms: The first alarm

is for a time of day. The second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch inter-

rupt is enabled and the counter underflows, an interrupt is

generated.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory boots at system power-up from an 8-bit

EPROM via the external port, an SPI master, or an SPI slave.

Booting is determined by the boot configuration

(BOOT_CFG2–0) pins in Table 9.

A running reset feature is used to reset the processor core and

peripherals without resetting the PLL and SDRAM controller,

or performing a boot. The functionality of the RESETOUT

/RUNRSTIN pin has now been extended to also act as the input

for initiating a running reset. For more information, see the

ADSP-214xx SHARC Processor Hardware Reference.

Power Supplies

The processors have separate power supply connections for the

internal (V

DD_INT

) and external (V

DD_EXT

), power supplies. The

internal and analog supplies must meet the V

DD_INT

specifica-

tions. The external supply must meet the V

DD_EXT

specification.

All external supply pins must be connected to the same power

supply.

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V

DD_INT

and GND.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the processors to mon-

itor and control the target board processor during emulation.

Analog Devices DSP Tools product line of JTAG emulators pro-

vides emulation at full processor speed, allowing inspection and

modification of memory, registers, and processor stacks. The

processor's JTAG interface ensures that the emulator will not

affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate emulator hardware user’s guide.

DEVELOPMENT TOOLS

The processors are supported with a complete set of CROSS-

CORE

software and hardware development tools, including

Analog Devices emulators and VisualDSP++

development

environment. The same emulator hardware that supports other

SHARC processors also fully emulates the processors.

EZ-KIT Lite Evaluation Board

For evaluation of the processors, use the EZ-KIT Lite

board

being developed by Analog Devices. The board comes with on-

chip emulation capabilities and is equipped to enable software

development. Multiple daughter cards are available.

Figure 3. External Components for RTC

RTXO

C1 C2

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

RTXI

Table 9. Boot Mode Selection

BOOT_CFG2–0

Booting Mode

000 SPI Slave Boot

001 SPI Master Boot (from Flash and Other Slaves)

010 AMI User Boot (for 8-bit Flash Boot)

011 No Boot (Processor Executes from Internal

ROM After Reset)

100 Reserved

1xx Reserved

The BOOT_CFG2 pin is not available on the 100-lead package.

ADSP-21478/ADSP-21479

Rev. A | Page 13 of 72 | September 2011

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-

circuit emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and

commands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat-

forms to use as a cost effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++ development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board Flash device to store

user-specific boot code, enabling the board to run as a stand-

alone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices JTAG

emulators to the EZ-KIT Lite board enables high speed, non-

intrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2147x

architecture and functionality. For detailed information on the

family core architecture and instruction set, refer to the SHARC

Processor Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal conditioning electronic com-

ponents that receive input (data acquired from sampling either

real-time phenomena or from stored data) in tandem, with the

output of one portion of the chain supplying input to the next.

Signal chains are often used in signal processing applications to

gather and process data or to apply system controls based on

analysis of real-time phenomena. For more information about

this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by

providing signal processing components that are designed to

work together well. A tool for viewing relationships between

specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab

site (www.analog.com/signal

chains) provides:

• Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection

guides and application information

• Reference designs applying best practice design techniques

Rev. A | Page 14 of 72 | September 2011

ADSP-21478/ADSP-21479

PIN FUNCTION DESCRIPTIONS

Table 10. Pin Descriptions

Name Type

State During/

After Reset Description

ADDR

23–0

I/O/T (ipu) High-Z/Driven

Low (Boot)

External Address. The processor outputs addresses for external memory and

peripherals on these pins. The ADDR pins can be multiplexed to support the

external memory interface address, FLAGS15–8 (I/O) and PWM (O). After reset, all

ADDR pins are in EMIF mode, and FLAG(0–3) pins are in FLAGS mode (default).

When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR

23–4

pins for parallel input data.

DATA

15–0

I/O/T (ipu) High-Z External Data. The data pins can be multiplexed to support the external memory

interface data (I/O) and FLAGS

7–0

(I/O).

AMI_ACK I (ipu) Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait

states to an external memory access. AMI_ACK is used by I/O devices, memory

controllers, or other peripherals to hold off completion of an external memory

access.

0–1

O/T (ipu) High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the

corresponding banks of external memory. The MS

1-0

lines are decoded memory

address lines that change at the same time as the other address lines. When no

external memory access is occurring the MS

1-0

lines are inactive; they are active

however when a conditional memory access instruction is executed, whether or

not the condition is true.

The MS1 pin can be used in EPORT/FLASH boot mode. For more information on

processor booting, see the ADSP-214xx SHARC Processor Hardware Reference.

AMI_RD O/T (ipu) High-Z AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word

from external memory.

AMI_WR O/T (ipu) High-Z AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to

external memory.

FLAG0/IRQ0 I/O (ipu) FLAG[0] INPUT FLAG0/Interrupt Request0.

FLAG1/IRQ1 I/O (ipu) FLAG[1] INPUT FLAG1/Interrupt Request1.

FLAG2/IRQ2/MS2 I/O (ipu) FLAG[2] INPUT FLAG2/Interrupt Request2/Memory Select2. This pin is multiplexed with MS2

in the 196-ball BGA package only.

FLAG3/TMREXP/MS3 I/O (ipu) FLAG[3] INPUT FLAG3/Timer Expired/Memory Select3. This pin is multiplexed with MS3 in the

196-ball BGA package only.

The following symbols appear in the Type column of Table 10: A = asynchronous, I= input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 k to 63 k. The

range of an ipd resistor can be 31 k to 85 k. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions

the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.

ADSP-21478/ADSP-21479

Rev. A | Page 15 of 72 | September 2011

SDRAS O/T (ipu) High-Z/

Driven High

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS O/T (ipu) High-Z/

Driven High

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction

with other SDRAM command pins, defines the operation for the SDRAM to

perform.

SDWE O/T (ipu) High-Z/

Driven High

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

SDCKE O/T (ipu) High-Z/

Driven High

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDA10 O/T (ipu) High-Z/

Driven High

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-

SDRAM accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM

accesses.

SDDQM O/T (ipu) High-Z/

Driven High

DQM Data Mask. SDRAM input mask signal for write accesses and output enable

signal for read accesses. Input data is masked when DQM is sampled high during

a write cycle. The SDRAM output buffers are placed in a High-Z state when DQM

is sam pled high dur ing a rea d cyc le. S DDQM is d rive n hig h fr om res et d e- asse r tion

until SDRAM initialization completes. Afterwards, it is driven low irrespective of

whether any SDRAM accesses occur or not.

SDCLK O/T (ipd) High-Z/

Driving

SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers.

See Figure 47 on Page 61. For models in the 100-lead package, the SDRAM

interface should be disabled to avoid unnecessary power switching by setting the

DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC

Processor Hardware Reference.

DAI _P

20–1

I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the

DAI SRU. The DAI SRU configuration registers define the combination of on-chip

audiocentric peripheral inputs or outputs connected to the pin and to the pin’s

output enable. The configuration registers of these peripherals then determines

the exact behavior of the pin. Any input or output signal present in the DAI SRU

may be routed to any of these pins.

DPI _P

14–1

I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI

SRU. The DPI SRU configuration registers define the combination of on-chip

peripheral inputs or outputs connected to the pin and to the pin's output enable.

The configuration registers of these peripherals then determine the exact

behavior of the pin. Any input or output signal present in the DPI SRU may be

routed to any of these pins.

WDT_CLKIN I Watch Dog Timer Clock Input. This pin should be pulled low when not used.

WDT_CLKO O Watch Dog Resonator Pad Output.

WDTRSTO O (ipu) Watch Dog Timer Reset Out.

THD_P I Thermal Diode Anode. When not used, this pin can be left floating.

THD_M O Thermal Diode Cathode. When not used, this pin can be left floating.

Table 10. Pin Descriptions (Continued)

Name Type

State During/

After Reset Description

The following symbols appear in the Type column of Table 10: A = asynchronous, I= input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 k to 63 k. The

range of an ipd resistor can be 31 k to 85 k. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions

the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.

Rev. A | Page 16 of 72 | September 2011

ADSP-21478/ADSP-21479

MLBCLK I Media Local Bus Clock. This clock is generated by the MLB controller that is

synchronized to the MOST network and provides the timing for the entire MLB

interface at 49.152 MHz at FS = 48 kHz. When the MLB controller is not used, this

pin should be grounded.

MLBDAT I/O/T in 3 pin

mode. I in 5 pin

mode.

High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device

and is received by all other MLB devices including the MLB controller. The

MLBDAT line carries the actual data. In 5-pin MLB mode, this pin is an input only.

When the MLB controller is not used, this pin should be grounded.

MLBSIG I/O/T in 3 pin

mode. I in 5 pin

mode

High-Z Media Local Bus Signal. This is a multiplexed signal which carries the

Channel/Address generated by the MLB Controller, as well as the Command and

RxStatus bytes from MLB devices. In 5-pin mode, this pin is input only. When the

MLB controller is not used, this pin should be grounded.

MLBDO O/T High-Z Media Local Bus Data Output (in 5 Pin Mode). This pin is used only in 5-pin MLB

mode and serves as the output data pin. When the MLB controller is not used, this

pin should be grounded.

MLBSO O/T High-Z Media Local Bus Signal Output (in 5 Pin Mode). This pin is used only in 5-pin

MLB mode and serves as the output signal pin. When the MLB controller is not

used, this pin should be grounded.

SR_SCLK I (ipu) Shift Register Serial Clock. (Active high, rising edge sensitive)

SR_CLR I (ipu) Shift Register Reset. (Active low)

SR_SDI I (ipu) Shift Register Serial Data Input.

SR_SDO O (ipu) Driven Low Shift Register Serial Data Output.

SR_LAT I (ipu) Shift Register Latch Clock Input. (Active high, rising edge sensitive)

SR_LDO

17–0

O/T (ipu) High-Z Shift Register Parallel Data Output.

RTXI I RTC Crystal Input. If RTC is not used, then the bits RTCPDN and RTC_READENB of

RTC_INIT register must be set to 1.

RTXO O RTC Crystal Output.

RTCLKOUT O (ipd) RTC Clock Output. For calibration purposes. The clock runs at 1 Hz.

TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic.

TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path.

TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine.

TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the device.

TRST I (ipu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed

low) after power-up or held low for proper operation of the processor.

EMU O/D (ipu) High-Z Emulation Status. Must be connected to the Analog Devices DSP Tools product

line of JTAG emulators target board connector only.

Table 10. Pin Descriptions (Continued)

Name Type

State During/

After Reset Description

The following symbols appear in the Type column of Table 10: A = asynchronous, I= input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 k to 63 k. The

range of an ipd resistor can be 31 k to 85 k. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions

the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.

ADSP-21478/ADSP-21479

Rev. A | Page 17 of 72 | September 2011

CLK_CFG

1–0

ICore to CLKIN Ratio Control. These pins set the start up clock frequency.

Note that the operating frequency can be changed by programming the PLL

multiplier and divider in the PMCTL register at any time after the core comes out

of reset. The allowed values are:

00 = 8:1

01 = 32:1

10 = 16:1

11 = reserved

CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It

configures the processors to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables

the internal clock generator. Connecting the external clock to CLKIN while leaving

XTAL unconnected configures the processors to use the external clock source

such as an external clock oscillator. CLKIN may not be halted, changed, or

operated below the specified frequency.

XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

RESET IProcessor Reset. Resets the processor to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input must

be asserted (low) at power-up.

RESETOUT/RUNRSTIN I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin

also has a second function as RUNRSTIN which is enabled by setting bit 0 of the

RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor

Hardware Reference.

BOOT_CFG

2–0

IBoot Configuration Select. These pins select the boot mode for the processor.

The BOOT_CFG pins must be valid before RESET (hardware and software) is de-

asserted.

Note that the BOOT_CFG2 pin is not available on the 100-lead LQFP package.

Table 10. Pin Descriptions (Continued)

Name Type

State During/

After Reset Description

The following symbols appear in the Type column of Table 10: A = asynchronous, I= input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic

levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors

cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 k to 63 k. The

range of an ipd resistor can be 31 k to 85 k. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions

the voltage is in the range of 2.3 V to 2.7 V.

In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.

Not all pins are available in the 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 59 on Page 64.

Rev. A | Page 18 of 72 | September 2011

ADSP-21478/ADSP-21479

Table 11. Pin List, Power and Ground

Name Type Description

DD_INT

PInternal Power Supply.

DD_EXT

PI/O Power Supply.

DD_RTC

PReal-Time Clock Power Supply.

GND

GGround.

DD_THD

PThermal Diode Power Supply. When not used, this pin can be left floating.

The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the

exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided

in the package. See also 100-LQFP_EP Lead Assignment on Page 64.

ADSP-21478/ADSP-21479

Rev. A | Page 19 of 72 | September 2011

SPECIFICATIONS

OPERATING CONDITIONS

100 MHz 266 MHz 300 MHz

Parameter

Specifications subject to change without notice.

Description Min Nom Max Min Nom Max Min Nom Max Unit

DD_INT

Internal (Core) Supply

Voltage

1.05 1.1 1.15 1.14 1.2 1.26 1.25 1.3 1.35 V

DD_EXT

External (I/O) Supply

Voltage

3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V

DD_THD

Thermal Diode Supply

Voltage

3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V

DD_RTC

Real-Time Clock Power

Supply Voltage

2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.6 V

IH2

Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, SDA10,

AMI_ACK, MLBCLK, MLBDAT, MLBSIG.

High Level Input Voltage @

DD_EXT

= Max

2.0 2.0 2.0 V

IL3

Applies to input pin CLKIN, WDT_CLKIN.

Low Level Input Voltage @

DD_EXT

= Min

0.8 0.8 0.8 V

IH_CLKIN3

High Level Input Voltage @

DD_EXT

= Max

2.2 V

DDEXT

2.2 V

DDEXT

2.2 V

DDEXT

IL_CLKIN

Low Level Input Voltage @

DD_EXT

= Max

–0.3 0.8 –0.3 0.8 –0.3 0.8 V

Junction Temperature

100-Lead LQFP_EP @

AMBIENT

0°C to +70°C

N/A N/A 0 105 N/A N/A °C

Applies to automotive models only. See Automotive Products on Page 68

Junction Temperature

100-Lead LQFP_EP @

AMBIENT

–40°C to +85°C

N/A N/A –40 +125 N/A N/A °C

Junction Temperature

100-Lead LQFP_EP @

AMBIENT

–40°C to +105°C

N/A N/A –40 +125 N/A N/A °C

Junction Temperature

196-Ball CSP_BGA @ T

AMBIENT

0°C to +70°C

0 105 0 105 0 100 °C

Junction Temperature

196-Ball CSP_BGA @ T

AMBIENT

–40°C to +85°C

N/A N/A –40 125 N/A N/A °C

Rev. A | Page 20 of 72 | September 2011

ADSP-21478/ADSP-21479

ELECTRICAL CHARACTERISTICS

100 MHz 266 MHz 300 MHz

UnitParameter

Description Test Conditions Min Max Min Max Min Max

OH2

High Level Output

Voltage

@ V

DD_EXT

= Min,

= –1.0 mA

2.4 2.4 2.4 V

OL2

Low Level Output Voltage @ V

DD_EXT

= Min,

= 1.0 mA

0.4 0.4 0.4 V

IH4, 5

High Level Input Current @ V

DD_EXT

= Max,

= V

DD_EXT

Max

10 10 10 µA

IL4

Low Level Input Current @ V

DD_EXT

= Max, V

= 0 V

–10 –10 –10 µA

ILPU5

Low Level Input Current

Pull-up

@ V

DD_EXT

= Max, V

= 0 V

200 200 200 µA

OZH6, 7

Three-State Leakage

Current

@ V

DD_EXT

= Max,

= V

DD_EXT

Max

10 10 10 µA

OZL6

Three-State Leakage

Current

@ V

DD_EXT

= Max, V

= 0 V

–10 –10 –10 µA

OZLPU7

Three-State Leakage

Current Pull-up

@ V

DD_EXT

= Max, V

= 0 V

200 200 200 µA

OZHPD8

Three-State Leakage

Current Pull-down

@ V

DD_EXT

= Max, V

= V

DD_EXT

Max

200 200 200 µA

DD_RTC

Current @ V

DD_RTC

= 3.0,

= 25°C

0.76 0.76 0.76 µA

DD-INTYP9

Supply Current (Internal) f

CCLK

> 0 MHz Table 13 +

Table 14 ×

ASF

Table 13 +

Table 14 ×

ASF

Table 13 +

Table 14 ×

ASF

IN10,

Input Capacitance T

CASE

= 25°C 5 5 5 pF

Specifications subject to change without notice.

Applies to output and bidirectional pins: ADDR23-0, DATA15-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT ,MLBSIG, MLBDAT, MLBDO,

MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.

See Output Drive Currents on Page 61 for typical drive current capabilities.

Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

Applies to input pins with internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pins: TDO, MLBDAT, MLBSIG, MLBDO, and MLBSO.

Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

Applies to three-statable pin with pull-down: SDCLK.

See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2147x SHARC Processors” for further information.

Applies to all signal pins.

Guaranteed, but not tested.

ADSP-21478/ADSP-21479

Rev. A | Page 21 of 72 | September 2011

Total Power Dissipation

Total power dissipation has two components:

1. Internal power consumption

2. External power consumption

Internal power consumption also comprises two components:

1. Static, due to leakage current. Table 13 shows the static cur-

rent consumption (I

DD-STATIC

) as a function of junction

temperature (T

) and core voltage (V

DD_INT

2. Dynamic (I

DD-DYNAMC

), due to transistor switching charac-

teristics and activity level of the processor. The activity level

is reflected by the Activity Scaling Factor (ASF), which rep-

resents application code running on the processor core and

having various levels of peripheral and external port activ-

ity (Table 12). Dynamic current consumption is calculated

by scaling the specific application by the ASF and using

baseline dynamic current consumption as a reference. The

ASF is combined with the CCLK frequency and V

DD_INT

dependent data in Table 14 to calculate this part.

External power consumption is due to the switching activity of

the external pins.

Table 12. Activity Scaling Factors (ASF)

See Estimating Power for ADSP-214xx SHARC Processors (EE-348) for more

information on the explanation of the power vectors specific to the ASF table.

Activity Scaling Factor (ASF)

Idle 0.31

Low 0.53

Medium Low 0.62

Medium High 0.78

Peak-Typical (50:50)

Ratio of continuous instruction loop (core) to SDRAM control code reads and

writes.

0.85

Peak-Typical (60:40)

0.93

Peak-Typical (70:30)

1.00

High Typical 1.18

High 1.28

Peak 1.34

Table 13. Static Current—I

DD-STATIC

(mA)

(°C)

DD_INT

(V)

1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V

–45 < 0.1 < 0.1 0.4 0.8 1.3 2.1 3.3

–35 < 0.1 < 0.1 0.4 0.7 1.1 1.7 2.9

–25 < 0.1 0.2 0.4 0.8 1.2 1.7 2.9

–15 < 0.1 0.4 0.6 1.0 1.4 1.9 3.2

–50.20.60.91.31.82.33.7

+50.50.91.31.82.33.04.4

+15 0.8 1.4 1.8 2.3 3.0 3.7 5.1

+25 1.3 1.9 2.5 3.1 3.9 4.7 6.2

+35 2.0 2.8 3.4 4.2 5.1 6.0 8.0

+45 3.0 3.9 4.7 5.7 6.7 7.8 10.1

+55 4.3 5.4 6.3 7.6 8.8 10.3 12.9

+65 6.0 7.3 8.6 10.1 11.7 13.5 16.4

+75 8.3 9.9 11.5 13.3 15.3 17.4 21.2

+85 11.2 13.2 15.3 17.5 19.9 22.6 27.1

+95 15.2 17.6 20.1 22.9 26.1 29.4 34.6

+100 17.4 20.2 22.9 25.9 29.4 33.0 39.2

+105 20.0 23.0 26.1 29.5 33.4 N/A N/A

+115 26.3 30.0 33.9 38.2 42.9 N/A N/A

+125 34.4 38.9 43.6 48.8 54.8 N/A N/A

Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 19.

Rev. A | Page 22 of 72 | September 2011

ADSP-21478/ADSP-21479

PACKAGE INFORMATION

The information presented in Figure 4 provides details about

the package branding. For a complete listing of product avail-

ability, see Ordering Guide on Page 69.

ESD SENSITIVITY

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note “Estimating Power Dissipation

for ADSP-2147x SHARC Processors” for detailed thermal and

power information regarding maximum power dissipation. For

information on package thermal specifications, see Thermal

Characteristics on Page 62.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 16 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in Operating Conditions on

Page 19 is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Table 14. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)

CCLK

(MHz)

Voltage (V

DD_INT

)

1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V

10075788286909598

150 111 117 122 128 134 141 146

200 N/A N/A 162 170 178 186 194

266 N/A N/A 215 225 234 246 256

300 N/A N/A N/A N/A 264 279 291

The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 20.

Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 19.

Figure 4. Typical Package Brand

Table 15. Package Brand Information

Non-automotive only. For branding information specific to automotive

products, contact Analog Devices Inc.

Brand Key Field Description

t Temperature Range

pp Package Type

Z RoHS Compliant Option

cc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

# RoHS Compliant Designation

yyww Date Code

vvvvvv.x n.n

tppZ-cc

ADSP-2147x

#yyww country_of_origin

ESD

(electrostatic

discharge)

sensitive

device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

Table 16. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V

DD_INT

) –0.3 V to +1.35 V

External (I/O) Supply Voltage (V

DD_EXT

)–0.3 V to +4.6 V

Real Time Clock Voltage (V

DD_RTC

)–0.3 V to +4.6 V

Thermal Diode Supply Voltage (V

DD_THD

)–0.3 V to +4.6 V

Input Voltage –0.5 V to +3.8 V

Output Voltage Swing –0.5 V to V

DD_EXT

+0.5 V

Storage Temperature Range –65°C to +150°C

Junction Temperature While Biased 125°C

ADSP-21478/ADSP-21479

Rev. A | Page 23 of 72 | September 2011

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 49 on Page 61 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator (VCO)

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

VCO

specified in Table 19.

• The product of CLKIN and PLLM must never exceed 1/2 of

VCO

(max) in Table 19 if the input divider is not enabled

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f

VCO

(max) in Table 19 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

VCO

= 2 × PLLM × f

INPUT

CCLK

= (2 × PLLM × f

INPUT

) ÷ PLLD

where:

VCO

= VCO output

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

PLLD = 2, 4, 8, or 16 based on the divider value programmed on

the PMCTL register. During reset this value is 2.

INPUT

is the input frequency to the PLL.

INPUT

= CLKIN when the input divider is disabled, or

CLKIN ÷ 2 when the input divider is enabled.

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in Table 17. All

of the timing specifications for the peripherals are defined in

relation to t

PCLK

. See the peripheral specific section for each

peripheral’s timing information.

Figure 5 shows core to CLKIN relationships with an external

oscillator or crystal. The shaded divider/multiplier blocks

denote where clock ratios can be set through hardware or soft-

ware using the power management control register (PMCTL).

For more information, see the ADSP-214xx SHARC Processor

Hardware Reference.

Table 17. Clock Periods

Timing

Requirements Description

CLKIN Clock Period

CCLK

Processor Core Clock Period

PCLK

Peripheral Clock Period = 2 × t

CCLK

SDCLK

SDRAM Clock Period = (t

CCLK

) × SDCKR

Rev. A | Page 24 of 72 | September 2011

ADSP-21478/ADSP-21479

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 18. While no specific power-up sequencing is required

between V

DD_EXT

and V

DD_INT

, there are some considerations

that the system designs should take into account.

• No power supply should be powered up for an extended

period of time (>200 ms) before another supply starts to

ramp up.

•If the V

DD_INT

power supply comes up after V

DD_EXT

, any

pin, such as RESETOUT and RESET, may actually drive

momentarily until the V

DD_INT

rail has powered up. Systems

sharing these signals on the board must determine if there

are any issues that need to be addressed based on this

behavior.

Note that during power-up, when the V

DD_INT

power supply

comes up after V

DD_EXT

, a leakage current of the order of three-

state leakage current pull-up, pull-down, may be observed on

any pin, even if that is an input only (for example, the RESET

pin), until the V

DD_INT

rail has powered up.

Figure 5. Core Clock and System Clock Relationship to CLKIN

LOOP

FILTER

CLKIN

PCLK

SDRAM

DIVIDER

BYPASS

MUX

PMCTL

(SDCKR)

CCLK

PLL

XTAL

CLKIN

DIVIDER

RESET

VCO

÷ (2 × PLLM)

BUF

VCO

BUF

PMCTL

(INDIV)

PLL

DIVIDER

RESETOUT

CLKOUT (TEST ONLY)*

DELAY OF

4096 CLKIN

CYCLES

PCLK

PMCTL

(PLLBP)

PMCTL

(PLLD)

VCO

fCCLK

INPUT

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f

INPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

CLK_CFGx/

PMCTL (2 × PLLM) DIVIDE

BY 2

MUX

PMCTL

(PLLBP)

CCLK

RESETOUT

CORESRST

SDCLK

BYPASS

MUX

Table 18. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

RESET Low Before V

DD_EXT

or V

DD_INT

On 0 ms

IVDDEVDD

DD_INT

On Before V

DD_EXT

–200 +200 ms

CLKVDD1

CLKIN Valid After V

DD_INT

and V

DD_EXT

Valid 0 200 ms

CLKRST

CLKIN Valid Before RESET Deasserted 10

PLLRST

PLL Control Setup Before RESET Deasserted 20

Switching Characteristic

CORERST

Core Reset Deasserted After RESET Deasserted 4096 × t

+ 2 × t

CCLK

Valid V

DD_INT

and V

DD_EXT

assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary

from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume

a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

SRST

specification in Table 20. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

ADSP-21478/ADSP-21479

Rev. A | Page 25 of 72 | September 2011

Clock Input

Figure 6. Power-Up Sequencing

Table 19. Clock Input

Parameter

100 MHz 266 MHz 300 MHz

Unit

MinMax MinMax MinMax

Timing Requirements

CLKIN Period 76

Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

100 30

100 26.66

100 ns

CKL

CLKIN Width Low 3845 1545 13.3345 ns

CKH

CLKIN Width High 38 45 15 45 13.33 45 ns

CKRF

CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 3 ns

CCLK2

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

cclk

CCLK Period 9.5 10.2 3.75 10 3.33 10 ns

VCO3

See Figure 5 on Page 24 for VCO diagram.

VCO Frequency 196 210 200 600 200 600 MHz

CKJ4, 5

Actual input jitter should be combined with ac specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN Jitter Tolerance –250 +250 –250 +250 –250 +250 ps

Figure 7. Clock Input

tRSTVDD

tCLKVDD

tCLKRST

tCORERST

tPLLRST

VDDEXT

VDDINT

CLKIN

CLK_CFG1–0

RESET

RESETOUT

tIVDDEVDD

CLKIN

tCK

tCKL

tCKH

tCKJ

Rev. A | Page 26 of 72 | September 2011

ADSP-21478/ADSP-21479

Clock Signals

The processors can use an external clock or a crystal. See the

CLKIN pin description in Table 10. Programs can configure the

processor to use its internal clock generator by connecting the

necessary components to CLKIN and XTAL. Figure 8 shows the

component connections used for a crystal operating in funda-

mental mode. Note that the clock rate is achieved using a

16.67 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

Reset

Figure 8. 266 MHz Operation (Fundamental Mode Crystal)

22pF Y1

1MΩ*

XTAL

CLKIN

22pF

16.67

47Ω*

ADSP-2147x

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’S SPECIFICATIONS

*TYPICAL VALUES

Table 20. Reset

Parameter Min Max Unit

Timing Requirements

WRST1

RESET Pulse Width Low 4 × t

SRST

RESET Setup Before CLKIN Low 8 ns

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

and CLKIN (not including start-up time of external clock oscillator).

Figure 9. Reset

CLKIN

RESET

tSRST

tWRST

ADSP-21478/ADSP-21479

Rev. A | Page 27 of 72 | September 2011

Running Reset

The following timing specification applies to RESETOUT/

RUNRSTIN pin when it is configured as RUNRSTIN.

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts, as well as the DAI_P20-1 and

DPI_P14-1 pins when they are configured as interrupts.

Table 21. Running Reset

Parameter Min Max Unit

Timing Requirements

WRUNRST

Running RESET Pulse Width Low 4 × t

SRUNRST

Running RESET Setup Before CLKIN High 8 ns

Figure 10. Running Reset

CLKIN

RUNRSTIN

tWRUNRST tSRUNRST

Table 22. Interrupts

Parameter Min Max Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

PCLK

+ 2 ns

Figure 11. Interrupts

INTERRUPT

INPUTS

tIPW

Rev. A | Page 28 of 72 | September 2011

ADSP-21478/ADSP-21479

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (TMREXP).

Timer PWM_OUT Cycle Timing

The following timing specification applies to timer0 and timer1

in PWM_OUT (pulse-width modulation) mode. Timer signals

are routed to the DPI_P14–1 pins through the DPI SRU. There-

fore, the timing specifications provided below are valid at the

DPI_P14–1 pins.

Table 23. Core Timer

Parameter Min Max Unit

Switching Characteristic

WCTIM

TMREXP Pulse Width 4 × t

PCLK

– 1.2 ns

Figure 12. Core Timer

FLAG3

(TMREXP)

tWCTIM

Table 24. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer Pulse Width Output 2 × t

PCLK

– 1.2 2 × (2

– 1) × t

PCLK

Figure 13. Timer PWM_OUT Timing

PWM

OUTPUTS

tPWMO

ADSP-21478/ADSP-21479

Rev. A | Page 29 of 72 | September 2011

Timer WDTH_CAP Timing

The following timing specification applies to timer0 and timer1,

and in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specification provided below is valid

at the DPI_P14–1 pins.

Watch Dog Timer Timing

Table 25. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

Timer Pulse Width 2 × t

PCLK

2 × (2

– 1) × t

PCLK

Figure 14. Timer Width Capture Timing

TIMER

CAPTURE

INPUTS

tPWI

Table 26. Watch Dog Timer Timing

Parameter Min Max Unit

Timing Requirement

WDTCLKPER

100 1000 ns

Switching Characteristics

RST

WDT Clock Rising Edge to Watch Dog Timer

RESET Falling Edge

37.6 ns

RSTPW

Reset Pulse Width 64 × t

WDTCLKPER1

When the internal oscillator is used, the 1/t

WDTCLKPER

varies from 1.5 MHz to 2.5 MHz and the WDT_CLKIN pin should be pulled low.

Figure 15. Watch Dog Timer Timing

WDT_CLKIN

WDTRSTO

tWDTCLKPER

tRST

tRSTPW

Rev. A | Page 30 of 72 | September 2011

ADSP-21478/ADSP-21479

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 27. DAI/DPI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid 1.5 10 ns

Figure 16. DAI Pin to Pin Direct Routing

DAI_Pn

DPI_Pn

DAI_Pm

DPI_Pm

tDPIO

ADSP-21478/ADSP-21479

Rev. A | Page 31 of 72 | September 2011

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Table 28. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit

Timing Requirements

PCGIP

Input Clock Period t

PCLK

× 4 ns

STRIG

PCG Trigger Setup Before Falling Edge of PCG Input

Clock

4.5 ns

HTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

3ns

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay

After PCG Input Clock 2.5

12.5

DTRIGCLK

PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × t

PCGIP

) 12.5 + (2.5 × t

PCGIP

)ns

DTRIGFS

PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × t

PCGIP

) 12.5 + ((2.5 + D – PH) × t

PCGIP

)ns

PCGOW1

Output Clock Period 2 × t

PCGIP

– 1 ns

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators”

chapter.

Normal mode of operation.

Figure 17. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

DPI_Pn

PCG_TRIGx_I

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

DPI_Py

PCK_CLKx_O

DAI_Pz

DPI_Pz

PCG_FSx_O

tDTRIGFS

tDTRIGCLK

tDPCGIO

tSTRIG tHTRIG

tPCGOW

tDPCGIO

tPCGIP

Rev. A | Page 32 of 72 | September 2011

ADSP-21478/ADSP-21479

Flags

The timing specifications provided below apply to ADDR23–0

and DATA7–0 when configured as FLAGS. See Table 10 on

Page 14 for more information on flag use.

Table 29. Flags

Parameter Min Max Unit

Timing Requirement

FIPW

FLAGs IN Pulse Width

2 × t

PCLK

+ 3 ns

Switching Characteristic

FOPW

FLAGs OUT Pulse Width

2 × t

PCLK

– 3.5 ns

This is applicable when the Flags are connected to DPI_P14–1, ADDR23–0, DATA7–0 and FLAG3–0 pins.

Figure 18. Flags

FLAG

INPUTS

FLAG

OUTPUTS

tFOPW

tFIPW

ADSP-21478/ADSP-21479

Rev. A | Page 33 of 72 | September 2011

SDRAM Interface Timing

Table 30. SDRAM Interface Timing

133 MHz 150 MHz

UnitParameter Min Max Min Max

Timing Requirements

SSDAT

DATA Setup Before SDCLK 0.7 0.7 ns

HSDAT

DATA Hold After SDCLK 1.66 1.5 ns

Switching Characteristics

SDCLK1

Systems should use the SDRAM model with a speed grade higher than the desired SDRAM controller speed. For example, to run the SDRAM controller at 133 MHz the

SDRAM model with a speed grade of 143 MHz or above should be used. See Engineer-to-Engineer Note “Interfacing SDRAM memory to SHARC processors (EE-286)” for

more information on hardware design guidelines for the SDRAM interface.

SDCLK Period 7.5 6.66 ns

SDCLKH

SDCLK Width High 2.5 2.2 ns

SDCLKL

SDCLK Width Low 2.5 2.2 ns

DCAD2

Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDQM, SDCKE.

Command, ADDR, Data Delay After SDCLK 5 4.75 ns

HCAD2

Command, ADDR, Data Hold After SDCLK 1 1 ns

DSDAT

Data Disable After SDCLK 6.2 5.3 ns

ENSDAT

Data Enable After SDCLK 0.3 0.3 ns

Figure 19. SDRAM Interface Timing

SDCLK

DATA (IN)

DATA (OUT)

COMMAND/ADDR

(OUT)

tSDCLKH

tSDCLKL

tHSDAT

tSSDAT

tHCAD

tDCAD

tENSDAT

tDCAD tDSDAT

tHCAD

tSDCLK

Rev. A | Page 34 of 72 | September 2011

ADSP-21478/ADSP-21479

AMI Read

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 31. AMI Read

Parameter Min Max Unit

Timing Requirements

DAD1, 2,

Address Selects Delay to Data Valid W + t

SDCLK

– 6.32 ns

DRLD1,

AMI_RD Low to Data Valid W – 3 ns

SDS4,

Data Setup to AMI_RD High 2.6 ns

HDRH

Data Hold from AMI_RD High 0.4 ns

DAAK2, 6

AMI_ACK Delay from Address Selects t

SDCLK

– 10. + W ns

DSAK

4 AMI_ACK Delay from AMI_RD Low W – 7.0 ns

Switching Characteristics

DRHA

Address Selects Hold After AMI_RD High RHC+ 0.38 ns

DARL2

Address Selects to AMI_RD Low t

SDCLK

– 5 ns

AMI_RD Pulse Width W – 1.4 ns

RWR

AMI_RD High to AMI_RD Low HI + t

SDCLK

– 1.2 ns

W = (number of wait states specified in AMICTLx register) × t

SDCLK

RHC = (number of Read Hold Cycles specified in AMICTLx register) × t

SDCLK

Where PREDIS = 0

HI = RHC: Read to Read from same bank

HI = RHC + IC: Read to Read from different bank

HI = RHC + Max (IC, (4 × t

SDCLK

)) : Read to Write from same or different bank

Where PREDIS = 1

HI = RHC + Max (IC, (4 × t

SDCLK

)) : Read to Write from same or different bank

HI = RHC + (3 × t

SDCLK

): Read to Read from same bank

HI = RHC + Max (IC, (3 × t

SDCLK

)) : Read to Read from different bank

IC = (number of idle cycles specified in AMICTLx register) × t

SDCLK

H = (number of hold cycles specified in AMICTLx register) × tSDCLK.

Data delay/setup: System must meet t

DAD

, t

DRLD

, or t

SDS.

The falling edge of MSx, is referenced.

The maximum limit of timing requirement values for t

DAD

and t

DRLD

parameters are applicable for the case where AMI_ACK is always high.

Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.

Data hold: User must meet t

HDRH

in asynchronous access mode. See Test Conditions on Page 61 for the calculation of hold times given capacitive and dc loads.

AMI_ACK delay/setup: User must meet t

daak

, or t

dsak

, for deassertion of AMI_ACK (low).

ADSP-21478/ADSP-21479

Rev. A | Page 35 of 72 | September 2011

Figure 20. AMI Read

AMI_ACK

AMI_DATA

tDRHA

tRW

tHDRH

tRWR

tDAD

tDARL

tDRLD tSDS

tDSAK

tDAAK

AMI_WR

AMI_RD

AMI_ADDR

AMI_MSx

Rev. A | Page 36 of 72 | September 2011

ADSP-21478/ADSP-21479

AMI Write

Use these specifications for asynchronous interfacing to memo-

ries. Note that timing for AMI_ACK, ADDR, DATA, AMI_RD,

AMI_WR, and strobe timing parameters only apply to asyn-

chronous access mode.

Table 32. AMI Write

Parameter Min Max Unit

Timing Requirements

DAAK

AMI_ACK Delay from Address Selects

1, 2

SDCLK

– 10.1 + W ns

DSAK

AMI_ACK Delay from AMI_WR Low

1, 3

W – 7.1 ns

Switching Characteristics

DAWH

Address Selects to AMI_WR Deasserted

SDCLK

–4.4 + W ns

DAWL

Address Selects to AMI_WR Low

SDCLK

– 4.5 ns

AMI_WR Pulse Width W – 1.3 ns

DDWH

Data Setup Before AMI_WR High t

SDCLK

– 4.3 + W ns

DWHA

Address Hold After AMI_WR Deasserted H ns

DWHD

Data Hold After AMI_WR Deasserted H ns

DATRWH

Data Disable After AMI_WR Deasserted

SDCLK

– 1.37 + H t

SDCLK

+ 6.75+ H ns

WWR

AMI_WR High to AMI_WR Low

SDCLK

– 1.5+ H ns

DDWR

Data Disable Before AMI_RD Low 2 × t

SDCLK

– 7.1 ns

WDE

AMI_WR Low to Data Enabled t

SDCLK

– 4.5 ns

W = (number of wait states specified in AMICTLx register) × t

SDCLK

H = (number of hold cycles specified in AMICTLx register) × t

SDCLK

AMI_ACK delay/setup: System must meet t

DAAK

, or t

DSAK

, for deassertion of AMI_ACK (low).

The falling edge of AMI_MSx is referenced.

Note that timing for AMI_ACK, ADDR, DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.

See Test Conditions on Page 61 for calculation of hold times given capacitive and dc loads.

For Write to Write: t

SDCLK

+ H, for both same bank and different bank. For Write to Read: 3 × t

SDCLK

+ H , for the same bank and different banks.

ADSP-21478/ADSP-21479

Rev. A | Page 37 of 72 | September 2011

Figure 21. AMI Write

AMI_ACK

AMI_DATA

tDAWH tDWHA

tWWR

tDATRWH

tDWHD

tWW

tDDWR

tDDWH

tDAWL

tWDE

tDSAK

tDAAK

AMI_RD

AMI_WR

AMI_ADDR

AMI_MSx

Rev. A | Page 38 of 72 | September 2011

ADSP-21478/ADSP-21479

Serial Ports

In slave transmitter mode and master receiver mode, the maxi-

mum serial port frequency is f

PCLK

/8. In master transmitter

mode and slave receiver mode, the maximum serial port clock

frequency is f

PCLK

/4.

To determine whether communication is possible between two

devices at clock speed, n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, Data Channel A, Data Channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 33. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements

SFSE1

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

HFSE1

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

SDRE1

Receive Data Setup Before Receive SCLK 2.5 ns

HDRE1

Receive Data Hold After SCLK 2.5 ns

SCLKW

SCLK Width (t

PCLK

× 4) ÷ 2 – 1.5 ns

SCLK

SCLK Period t

PCLK

× 4 ns

Switching Characteristics

DFSE2

Frame Sync Delay After SCLK

(Internally Generated Frame Sync in Either Transmit or Receive Mode) 15 ns

HOFSE2

Frame Sync Hold After SCLK

(Internally Generated Frame Sync in Either Transmit or Receive Mode) 2 ns

DDTE2

Transmit Data Delay After Transmit SCLK 15 ns

HDTE2

Transmit Data Hold After Transmit SCLK 2 ns

Referenced to sample edge.

Referenced to drive edge.

Table 34. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements

SFSI1

Frame Sync Setup Before SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode) 10.5 ns

HFSI1

Frame Sync Hold After SCLK

(Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns

SDRI1

Receive Data Setup Before SCLK 10.5 ns

HDRI1

Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

DFSI2

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 5 ns

HOFSI2

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0 ns

DFSIR2

Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 10.7 ns

HOFSIR2

Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0 ns

DDTI2

Transmit Data Delay After SCLK 4 ns

HDTI2

Transmit Data Hold After SCLK –1.0 ns

SCKLIW

Transmit or Receive SCLK Width 2 × t

PCLK

– 1.5 2 × t

PCLK

+ 1.5 ns

Referenced to the sample edge.

Referenced to drive edge.

ADSP-21478/ADSP-21479

Rev. A | Page 39 of 72 | September 2011

Figure 22. Serial Ports

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSIR tHFSI

tHDRI

DATA RECEIVE—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHFSI

tDDTI

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSE

tHOFSI

tHDTI

tHFSE

tHDTE

tDDTE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(FS)

DAI_P20–1

(SCLK)

tHOFSE tHFSE

tHDRE

DATA RECEIVE—EXTERNAL CLOCK

tSCLKIW

tDFSIR

tSFSI

tSDRI

tSCLKW

tDFSE

tSFSE

tSDRE

tDFSE

tSFSE

tSFSI

tDFSI

tSCLKIW tSCLKW

Rev. A | Page 40 of 72 | September 2011

ADSP-21478/ADSP-21479

Table 35. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE1

Data Delay from Late External Transmit Frame Sync or External Receive

Frame Sync with MCE = 1, MFD = 0

13.5

DDTENFS1

Data Enable for MCE = 1, MFD = 0 0.5 ns

The t

DDTLFSE

and t

DDTENFS

parameters apply to left-justified as well as DSP serial mode, and MCE = 1, MFD = 0.

Figure 23. External Late Frame Sync

This figure reflects changes made to support left-justified mode.

DRIVE SAMPLE

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

tDDTE/I

tHDTE/I

tDDTLFSE

tDDTENFS

tSFSE/I

DRIVE SAMPLE

LATE EXTERNAL TRANSMIT FS

2ND BIT

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

1ST BIT

DRIVE

tDDTE/I

tHDTE/I

tDDTLFSE

tDDTENFS

tSFSE/I

tHFSE/I

ADSP-21478/ADSP-21479

Rev. A | Page 41 of 72 | September 2011

Table 36. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DDTEN1

Data Enable from External Transmit SCLK 2 ns

DDTTE1

Data Disable from External Transmit SCLK 20 ns

DDTIN1

Data Enable from Internal Transmit SCLK –1 ns

Referenced to drive edge.

Figure 24. Enable and Three-State

DRIVE EDGE

tDDTIN

tDDTEN tDDTTE

DAI_P20–1

(SCLK, INT)

DAI_P20–1

(DATA

CHANNEL A/B)

DAI_P20–1

(SCLK, EXT)

DAI_P20–1

(DATA

CHANNEL A/B)

Rev. A | Page 42 of 72 | September 2011

ADSP-21478/ADSP-21479

The SPORTx_TDV_O output signal (routing unit) becomes

active in SPORT multichannel/packed mode. During transmit

slots (enabled with active channel selection registers), the

SPORTx_TDV_O is asserted for communication with external

devices.

Table 37. Serial Ports—TDV (Transmit Data Valid)

Parameter Min Max Unit

Switching Characteristics

DRDVEN

TDV Assertion Delay from Drive Edge of External Clock 3 ns

DFDVEN

TDV Deassertion Delay from Drive Edge of External Clock 13.25 ns

DRDVIN

TDV Assertion Delay from Drive Edge of Internal Clock –0.1 ns

DFDVIN

TDV Deassertion Delay from Drive Edge of Internal Clock 3.5 ns

Referenced to drive edge.

Figure 25. Serial Ports—TDM Internal and External Clock

DRIVE EDGE DRIVE EDGE

DAI_P20–1

(SCLK, EXT)

tDRDVEN

tDFDVEN

DRIVE EDGE DRIVE EDGE

DAI_P20–1

(SCLK, INT)

tDRDVIN

tDFDVIN

TDVx

DAI_P20-1

TDVx

DAI_P20-1

ADSP-21478/ADSP-21479

Rev. A | Page 43 of 72 | September 2011

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 38. IDP

signals are routed to the DAI_P20–1 pins using the SRU. There-

fore, the timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 38. Input Data Port (IDP)

Parameter Min Max Unit

Timing Requirements

SISFS1

Frame Sync Setup Before Serial Clock Rising Edge 3.8 ns

SIHFS1

Frame Sync Hold After Serial Clock Rising Edge 2.5 ns

SISD1

Data Setup Before Serial Clock Rising Edge 2.5 ns

SIHD1

Data Hold After Serial Clock Rising Edge 2.5 ns

IDPCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

IDPCLK

Clock Period t

PCLK

× 4 ns

The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG's

input can be either CLKIN or any of the DAI pins.

Figure 26. IDP Master Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tIPDCLK

tIPDCLKW

tSISFS tSIHFS

tSIHD

tSISD

Rev. A | Page 44 of 72 | September 2011

ADSP-21478/ADSP-21479

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 39. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the PDAP, see the

PDAP chapter of the ADSP-214xx SHARC Processor Hardware

Reference. Note that the 20 bits of external PDAP data can be

provided through the ADDR23–0 pins or over the DAI pins.

Table 39. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

SPHOLD1

PDAP_HOLD Setup Before PDAP_CLK Sample Edge 2.5 ns

HPHOLD1

PDAP_HOLD Hold After PDAP_CLK Sample Edge 2.5 ns

PDSD1

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.85 ns

PDHD1

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns

PDCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 3 ns

PDCLK

Clock Period t

PCLK

× 4 ns

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t

PCLK

+ 3 ns

PDSTRB

PDAP Strobe Pulse Width 2 × t

PCLK

– 1.5 ns

Source pins of DATA and control are ADDR23–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Figure 27. PDAP Timing

DAI_P20–1

(PDAP_CLK)

SAMPLE EDGE

DAI_P20–1

(PDAP_HOLD)

DAI_P20–1

(PDAP_STROBE)

tPDSTRB

tPDHLDD

tPDHD

tPDSD

tSPHOLD tHPHOLD

tPDCLK

tPDCLKW

DAI_P20–1/

ADDR23–4

(PDAP_DATA)

ADSP-21478/ADSP-21479

Rev. A | Page 45 of 72 | September 2011

Sample Rate Converter—Serial Input Port

The ASRC input signals are routed from the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided in

Table 40 are valid at the DAI_P20–1 pins.

Table 40. ASRC, Serial Input Port

Parameter Min Max Unit

Timing Requirements

SRCSFS1

Frame Sync Setup Before Serial Clock Rising Edge 4 ns

SRCHFS1

Frame Sync Hold After Serial Clock Rising Edge 5.5 ns

SRCSD1

Data Setup Before Serial Clock Rising Edge 4 ns

SRCHD1

Data Hold After Serial Clock Rising Edge 5.5 ns

SRCCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

SRCCLK

Clock Period t

PCLK

× 4 ns

The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

Figure 28. ASRC Serial Input Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS tSRCHFS

tSRCHD

tSRCSD

Rev. A | Page 46 of 72 | September 2011

ADSP-21478/ADSP-21479

Sample Rate Converter—Serial Output Port

For the serial output port, the frame sync is an input, and it

should meet setup and hold times with regard to the serial clock

on the output port. The serial data output has a hold time and

delay specification with regard to serial clock. Note that serial

clock rising edge is the sampling edge and the falling edge is the

drive edge.

Table 41. ASRC, Serial Output Port

Parameter Min Max Unit

Timing Requirements

SRCSFS1

Frame Sync Setup Before Serial Clock Rising Edge 4 ns

SRCHFS1

Frame Sync Hold After Serial Clock Rising Edge 5.5 ns

SRCCLKW

Clock Width (t

PCLK

× 4) ÷ 2 – 1 ns

SRCCLK

Clock Period t

PCLK

× 4 ns

Switching Characteristics

SRCTDD1

Transmit Data Delay After Serial Clock Falling Edge 13 ns

SRCTDH1

Transmit Data Hold After Serial Clock Falling Edge 1 ns

The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

Figure 29. ASRC Serial Output Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS tSRCHFS

tSRCTDD

tSRCTDH

ADSP-21478/ADSP-21479

Rev. A | Page 47 of 72 | September 2011

Pulse-Width Modulation Generators (PWM)

The following timing specifications apply when the

ADDR23–8/DPI_14–1 pins are configured as PWM.

Table 42. Pulse-Width Modulation (PWM) Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWM Output Pulse Width t

PCLK

– 2 (2

– 2) × t

PCLK

– 2 ns

PWMP

PWM Output Period 2 × t

PCLK

– 1.5 (2

– 1) × t

PCLK

– 1.5 ns

Figure 30. PWM Timing

PWM

OUTPUTS

tPWMW

tPWMP

Rev. A | Page 48 of 72 | September 2011

ADSP-21478/ADSP-21479

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left justified, I

S, or right justified with word widths of 16, 18, 20,

or 24 bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 31 shows the right-justified mode. Frame sync is high for

the left channel and low for the right channel. Data is valid on

the rising edge of serial clock. The MSB is delayed the minimum

in 24-bit output mode or the maximum in 16-bit output mode

from a frame sync transition, so that when there are 64 serial

clock periods per frame sync period, the LSB of the data is right-

justified to the next frame sync transition.

Figure 32 shows the default I

S-justified mode. The frame sync

is low for the left channel and high for the right channel. Data is

valid on the rising edge of serial clock. The MSB is left-justified

to the frame sync transition but with a delay.

Table 43. S/PDIF Transmitter Right-Justified Mode

Parameter Nominal Unit

Timing Requirement

RJD

FS to MSB Delay in Right-Justified Mode

16-Bit Word Mode

18-Bit Word Mode

20-Bit Word Mode

24-Bit Word Mode

SCLK

Figure 31. Right-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tRJD

Table 44. S/PDIF Transmitter I

S Mode

Parameter Nominal Unit

Timing Requirement

I2SD

FS to MSB Delay in I

S Mode 1 SCLK

Figure 32. I

S-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tI2SD

ADSP-21478/ADSP-21479

Rev. A | Page 49 of 72 | September 2011

Figure 33 shows the left-justified mode. The frame sync is high

for the left channel and low for the right channel. Data is valid

on the rising edge of serial clock. The MSB is left-justified to the

frame sync transition with no delay.

Table 45. S/PDIF Transmitter Left-Justified Mode

Parameter Nominal Unit

Timing Requirement

LJD

FS to MSB Delay in Left-Justified Mode 0 SCLK

Figure 33. Left-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSBMSB–1 MSB–2 LSB+2 LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tLJD

Rev. A | Page 50 of 72 | September 2011

ADSP-21478/ADSP-21479

S/PDIF Transmitter Input Data Timing

The timing requirements for the S/PDIF transmitter are given

in Table 46. Input signals are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Oversampling Clock (TxCLK) Switching Characteristics

The S/PDIF transmitter requires an oversampling clock input.

This high frequency clock (TxCLK) input is divided down to

generate the internal biphase clock.

Table 46. S/PDIF Transmitter Input Data Timing

Parameter Min Max Unit

Timing Requirements

SISFS1

Frame Sync Setup Before Serial Clock Rising Edge 3 ns

SIHFS1

Frame Sync Hold After Serial Clock Rising Edge 3 ns

SISD1

Data Setup Before Serial Clock Rising Edge 3 ns

SIHD1

Data Hold After Serial Clock Rising Edge 3 ns

SITXCLKW

Transmit Clock Width 9 ns

SITXCLK

Transmit Clock Period 20 ns

SISCLKW

Clock Width 36 ns

SISCLK

Clock Period 80 ns

The serial clock, data and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can

be either CLKIN or any of the DAI pins.

Figure 34. S/PDIF Transmitter Input Timing

SAMPLE EDGE

DAI_P20–1

(TxCLK)

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSITXCLKW tSITXCLK

tSISCLKW

tSISCLK

tSISFS tSIHFS

tSISD tSIHD

Table 47. Oversampling Clock (TxCLK) Switching Characteristics

Parameter Max Unit

Frequency for TxCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync ≤ 1/t

SITXCLK

MHz

Frequency for TxCLK = 256 × Frame Sync 49.2 MHz

Frame Rate (FS) 192.0 kHz

ADSP-21478/ADSP-21479

Rev. A | Page 51 of 72 | September 2011

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 48. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter Min Max Unit

Switching Characteristics

DFSI

FS Delay After Serial Clock 5 ns

HOFSI

FS Hold After Serial Clock –2 ns

DDTI

Transmit Data Delay After Serial Clock 5 ns

HDTI

Transmit Data Hold After Serial Clock –2 ns

SCLKIW1

Transmit Serial Clock Width 38.5 ns

Serial clock frequency is 64 × frame sync where FS = the frequency of LRCLK.

Figure 35. S/PDIF Receiver Internal Digital PLL Mode Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

DRIVE EDGE

tSCLKIW

tDFSI

tHOFSI

tDDTI

tHDTI

Rev. A | Page 52 of 72 | September 2011

ADSP-21478/ADSP-21479

SPI Interface—Master

Both the primary and secondary SPIs are available through DPI

only. The timing provided in Table 49 and Table 50 applies

to both.

Table 49. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time) 8.6 ns

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

Switching Characteristics

SPICLKM

Serial Clock Cycle 8 × t

PCLK

– 2 ns

SPICHM

Serial Clock High Period 4 × t

PCLK

– 2 ns

SPICLM

Serial Clock Low Period 4 × t

PCLK

– 2 ns

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay time) 2.5

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold time) 4 × t

PCLK

– 2 ns

SDSCIM

DPI Pin (SPI Device Select) Low to First SPICLK Edge 4 × t

PCLK

– 2 ns

HDSM

Last SPICLK Edge to DPI Pin (SPI Device Select) High 4 × t

PCLK

– 2 ns

SPITDM

Sequential Transfer Delay 4 × t

PCLK

– 1.4 ns

Figure 36. SPI Master Timing

tSPICHM

tSDSCIM tSPICLM tSPICLKM tHDSM tSPITDM

tDDSPIDM

tHSPIDM

tSSPIDM

DPI

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHASE = 1

CPHASE = 0

tHDSPIDM

tHSPIDM

tSSPIDM tSSPIDM

tDDSPIDM

tHDSPIDM

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

ADSP-21478/ADSP-21479

Rev. A | Page 53 of 72 | September 2011

SPI Interface—Slave

Table 50. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle 4 × t

PCLK

– 2 ns

SPICHS

Serial Clock High Period 2 × t

PCLK

– 2 ns

SPICLS

Serial Clock Low Period 2 × t

PCLK

– 2 ns

SDSCO

SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 2 × t

PCLK

HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t

PCLK

SSPIDS

Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

SDPPW

SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t

PCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active 0 10.25 ns

DSOE1

SPIDS Assertion to Data Out Active (SPI2) 0 10.25 ns

DSDHI

SPIDS Deassertion to Data High Impedance 0 13.25 ns

DSDHI1

SPIDS Deassertion to Data High Impedance (SPI2) 0 13.25 ns

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time) 11.5 ns

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

DSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

PCLK

The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral

Interface Port” chapter.

Figure 37. SPI Slave Timing

tSPICHS tSPICLS tSPICLKS tHDS tSDPPW

tSDSCO

tDSOE

tDDSPIDS

tDSDHI

tHDSPIDS

tHSPIDS

tSSPIDS

tDSDHI

tDDSPIDS

tDSOV

tHSPIDS

tHDSPIDS

SPIDS

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

CPHASE = 1

CPHASE = 0

SPICLK

(CP = 0,

CP = 1)

(INPUT)

Rev. A | Page 54 of 72 | September 2011

ADSP-21478/ADSP-21479

Media Local Bus

All the numbers given are applicable for all speed modes

(1024 FS, 512 FS, and 256 FS for 3-pin; 512 FS and 256 FS for

5-pin) unless otherwise specified. Please refer to MediaLB speci-

fication document rev 3.0 for more details.

Table 51. MLB Interface, 3-Pin Specifications

Parameter Min Typ Max Unit

3-Pin Characteristics

MLBCLK

MLB Clock Period

1024 FS

512 FS

256 FS

20.3

MCKL

MLBCLK Low Time

1024 FS

512 FS

256 FS

6.1

MCKH

MLBCLK High Time

1024 FS

512 FS

256 FS

9.3

MCKR

MLBCLK Rise Time (V

to V

)

1024 FS

512 FS/256 FS

MCKF

MLBCLK Fall Time (V

to V

)

1024 FS

512 FS/256 FS

MPWV1

MLBCLK Pulse Width Variation

1024 FS

512 FS/256

0.7

2.0

ns p-p

DSMCF

DAT/SIG Input Setup Time 1 ns

DHMCF

DAT/SIG Input Hold Time 1.2 ns

MCFDZ

DAT/SIG Output Time to Three-State 0 15 ns

MCDRV

DAT/SIG Output Data Delay From MLBCLK Rising Edge 8 ns

MDZH2

Bus Hold Time

1024 FS

512 FS/256

MLB

DAT/SIG Pin Load

1024 FS

512 FS/256

Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (p-p).

The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be

minimized while meeting the maximum capacitive load listed.

ADSP-21478/ADSP-21479

Rev. A | Page 55 of 72 | September 2011

Figure 38. MLB Timing (3-Pin Interface)

Table 52. MLB Interface, 5-Pin Specifications

Parameter Min Typ Max Unit

5-Pin Characteristics

MLBCLK

MLB Clock Period

512 FS

256 FS

MCKL

MLBCLK Low Time

512 FS

256 FS

MCKH

MLBCLK High Time

512 FS

256 FS

MCKR

MLBCLK Rise Time (V

to V

)6ns

MCKF

MLBCLK Fall Time (V

to V

)6ns

MPWV1

MLBCLK Pulse Width Variation 2 ns p-p

DSMCF2

DAT/SIG Input Setup Time 3 ns

DHMCF

DAT/SIG Input Hold Time 5 ns

MCDRV

DS/DO Output Data Delay From MLBCLK Rising Edge 8 ns

MCRDL3

DO/SO Low From MLBCLK High

512 FS

256 FS

mlb

DS/DO Pin Load 40 pf

Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (p-p).

Gate delays due to OR’ing logic on the pins must be accounted for.

When a node is not driving valid data onto the bus, the MLBSO and MLBDO output lines shall remain low. If the output lines can float at anytime, including while in reset,

external pull-down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven.

tMCKH

MLBSIG/

MLBDAT

(Rx, Input)

tMCKL

tMCKR

MLBSIG/

MLBDAT

(Tx, Output)

tMCFDZ

tDSMCF

MLBCLK

tMLBCLK

VALID

tDHMCF

tMCKF

tMCDRV

VALID

tMDZH

Rev. A | Page 56 of 72 | September 2011

ADSP-21478/ADSP-21479

Figure 39. MLB Timing (5-Pin Interface)

Figure 40. MLB 3-Pin and 5-Pin MLBCLK Pulse Width Variation Timing

tMCKH

MLBSIG/

MLBDAT

(Rx, Input)

tMCKL

tMCKR

MLBSO/

MLBDO

(Tx, Output)

tMCRDL

tDSMCF

MLBCLK

tMLBCLK

VALID

tDHMCF

tMCKF

tMCDRV

tMPWV tMPWV

MLBCLK

ADSP-21478/ADSP-21479

Rev. A | Page 57 of 72 | September 2011

Shift Register

Table 53. Shift Register

Parameter Min Max Unit

Timing Requirements

SSDI

SR_SDI Setup Before SR_SCLK Rising Edge 7 ns

HSDI

SR_SDI Hold After SR_SCLK Rising Edge 2 ns

SSDIDAI1

DAI_P08–01 (SR_SDI) Setup Before DAI_P08–01 (SR_SCLK) Rising Edge 7 ns

HSDIDAI1

DAI_P08–01 (SR_SDI) Hold After DAI_P08–01 (SR_SCLK) Rising Edge 2 ns

SSCK2LCK2

SR_SCLK to SR_LAT Setup 2 ns

SSCK2LCKDAI1,

DAI_P08–01 (SR_SCLK) to DAI_P08–01 (SR_LAT) Setup 2 ns

CLRREM2SCK

Removal Time SR_CLR to SR_SDCLK 3 × t

PCLK

– 5 ns

CLRREM2LCK

Removal Time SR_CLR to SR_LAT 2 × t

PCLK

– 5 ns

CLRW

SR_CLR Pulse Width 4 × t

PCLK

– 5 ns

SCKW

SR_SDCLK Clock Pulse Width 2 × t

PCLK

– 2 ns

LCKW

SR_LAT Clock Pulse Width 2 × t

PCLK

– 5 ns

MAX

Maximum Clock Frequency SR_SDCLK or SR_LAT f

CCLK

÷ 8MHz

Switching Characteristics ns

DSDO13

SR_SDO Hold After SR_SCLK Rising Edge 3 ns

DSDO23

SR_SDO Max. Delay After SR_SCLK Rising Edge 13 ns

DSDODAI11,

SR_SDO Hold After DAI_P08–01 (SR_SCLK) Rising Edge 3 ns

DSDODAI21,

SR_SDO Max. Delay After DAI_P08–01 (SR_SCLK) Rising Edge 13 ns

DSDOSP13,

SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge –2 ns

DSDOSP23,

SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge 5 ns

DSDOPCG13,

SR_SDO Hold After DAI_P20–01 (SR_SCLK) Rising Edge –2 ns

DSDOPCG23,

SR_SDO Max. Delay After DAI_P20–01 (SR_SCLK) Rising Edge 5 ns

DSDOCLR13

SR_CLR to SR_SDO Min. Delay 4 ns

DSDOCLR23

SR_CLR to SR_SDO Max. Delay 13 ns

DLDO13

SR_LDO Hold After SR_LAT Rising Edge 3 ns

DLDO23

SR_LDO Max. Delay After SR_LAT Rising Edge 13 ns

DLDODAI13

SR_LDO Hold After DAI_P08–01 (SR_LAT) Rising Edge 3 ns

DLDODAI23

SR_LDO Max. Delay After DAI_P08–01 (SR_LAT) Rising Edge 13 ns

DLDOSP13,

SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge –2 ns

DLDOSP23,

SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge 5 ns

DLDOPCG13,

SR_LDO Hold After DAI_P20–01 (SR_LAT) Rising Edge –2 ns

DLDOPCG23,

SR_LDO Max. Delay After DAI_P20–01 (SR_LAT) Rising Edge 5 ns

DLDOCLR13

SR_CLR to SR_LDO Min. Delay 4 ns

DLDOCLR23

SR_CLR to SR_LDO Max. Delay 14 ns

Any of the DAI_P08-01 pins can be routed to the shift register clock, latch clock and serial data input via the SRU.

Both clocks can be connected to the same clock source. If both clocks are connected to same clock source, then data in the 18-stage shift register is always one cycle ahead of

latch register data.

For setup/hold timing requirements of off-chip shift register interfacing devices.

SPORTx serial clock out, frame sync out, and serial data outputs are routed to shift register block internally and are also routed onto DAI_P20–01.

PCG serial clock output is routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SR_LAT and SDI internally.

PCG Serial clock and frame sync outputs are routed to SPORT and shift register block internally and are also routed onto DAI_P20–01. The SPORTs generate SDI internally.

Rev. A | Page 58 of 72 | September 2011

ADSP-21478/ADSP-21479

Figure 41. SR_SDI Setup, Hold

Figure 42. SR_ SDO Delay

Figure 43. SR_LDO Delay

DAI_P08

SR_SCLK

SSDI

SSDIDAI

tHSDI,tHSDIDAI

DAI_P08

SR_SDI

SR_SDO

SR_SCLK OR

DAI_P08-01 OR

DAI_P20-01(SPx_CLK_O) OR

DAI_P20-01(PCG_CLKx_O)

tDSDO1

tDSDO2

SR_SDO

THE TIMING PARAMETERS SHOWN FOR tDSDO1 AND tDSDO2 ARE VALID FOR tDSDODAI1,

tDSDOSP1, tDSDOPCG1, tDSDODAI2, tDSDOSP2, AND tDSDOPCG2

SR_LAT OR

DAI_P08

01 OR

DAI_P20

(SPx_FS_O)

DAI_P20

(PCG_FSx_O) tDLDO1 tDLDO2

SR_LDO

THE TIMING PARAMETERS SHOWN FOR tDLDO1 AND tDLDO2 ARE ALSO VALID FOR tDLDODAI1,

tDLDODAI2, tDLDOSP1, tDLDOSP2, tDLDOPCG1, AND tDLDOPCG2.

ADSP-21478/ADSP-21479

Rev. A | Page 59 of 72 | September 2011

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

For information on the UART port receive and transmit opera-

tions, see the ADSP-214xx SHARC Hardware Reference Manual.

2-Wire Interface (TWI)—Receive and Transmit Timing

For information on the TWI receive and transmit operations,

see the ADSP-214xx SHARC Hardware Reference Manual.

Figure 44. SR_SDCLK to SR_LAT Setup, Clocks Pulse Width and Maximum Frequency

Figure 45. Shift Register Reset Timing

SR_SCLK

DAI_P08

SR_SDI

DAI_P08

SR_LDO

SR_LAT

DAI_P08

tSSCK2LCKDAI

tSSCK2LCK

SR_SDCLK

DAI_P08

SR_LDO

SR_LAT

DAI_P08

tDSDOCLR2

tDSDOCLR1

tDLDOCLR2

tDLDOCLR1

tCLRW

tCLRREM2SCK

tCLRREM2LCK

SR_CLR

SR_SDO

Rev. A | Page 60 of 72 | September 2011

ADSP-21478/ADSP-21479

JTAG Test Access Port and Emulation

Table 54. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

TCK Period 20 ns

STAP

TDI, TMS Setup Before TCK High 5 ns

HTAP

TDI, TMS Hold After TCK High 6 ns

SSYS1

System Inputs = DATA15–0, CLK_CFG1–0, RESET, BOOT_CFG1–0, DAI_Px, DPI_Px, FLAG3–0, MLBCLK, MLBDAT, MLBSIG, SR_SCLK, SR_CLR, SR_SDI, and

SR_LAT.

System Inputs Setup Before TCK High 7 ns

HSYS1

System Inputs Hold After TCK High 18 ns

TRSTW

TRST Pulse Width 4 × t

Switching Characteristics

DTDO

TDO Delay from TCK Low 10.5 ns

DSYS2

System Outputs = DAI_Px, DPI_Px, ADDR23–0, AMI_RD, AMI_WR, FLAG3–0, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, SDCLK, MLBDAT, MLBSIG, MLBDO,

MLBSO, SR_SDO, SR_LDO and EMU.

System Outputs Delay After TCK Low t

÷ 2 + 7 ns

Figure 46. IEEE 1149.1 JTAG Test Access Port

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP tHTAP

tDTDO

tSSYS tHSYS

tDSYS

ADSP-21478/ADSP-21479

Rev. A | Page 61 of 72 | September 2011

OUTPUT DRIVE CURRENTS

Table 55 shows the driver types and the pins associated with

each driver. Figure 47 shows typical I-V characteristics for each

driver. The curves represent the current drive capability of the

output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 20 on Page 26 through Table 54 on Page 60. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 48.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 49. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 48). Figure 52 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 50, Figure 51, and Figure 52 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

Table 55. Driver Types

Driver Type Associated Pins

A FLAG[0–3], AMI_ADDR[23–0], DATA[15–0],

AMI_RD, AMI_WR, AMI_ACK, MS[1-0], SDRAS,

SDCAS, SDWE, SDDQM, SDCKE, SDA10, EMU,

TDO, RESETOUT, DPI[1–14], DAI[1–20],

WDTRSTO, MLBDAT, MLBSIG, MLBSO, MLBDO,

MLBCLK, SR_CLR, SR_LAT, SR_LDO[17–0],

SR_SCLK, SR_SDI

BSDCLK, RTCLKOUT

Figure 47. Typical Drive at Junction Temperature

Figure 49. Voltage Reference Levels for AC Measurements

SWEEP (VDDEXT) VOLTAGE (V)

03.50.5 1.0 1.5 2.0 2.5 3.0

100

200

SOURCE/SINK (V

DDEXT

) CURRENT (mA)

150

100

200

150

VOH 3.13 V, 125 °C

VOL 3.13 V, 125 °C

TYPE A

TYPE B

INPUT

OUTPUT

1.5V 1.5V

Figure 48. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 50. Typical Output Rise/Fall Time (20% to 80%,

DD_EXT

= Max)

ZO = 50:(impedance)

TD = 4.04 r 1.18 ns

2pF

TESTER PIN ELECTRONICS

50:

0.5pF

70:

400:

45:

4pF

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

VLOAD

DUT

OUTPUT

50:

LOAD CAPACITANCE (pF)

RISE AND FALL TIMES (ns)

125 20010025 17550 75 150

y = 0.0331x + 0.2662

y = 0.0184x + 0.3065

y = 0.0421x + 0.2418

y = 0.0206x + 0.2271

TYPE A DRIVE FALL

TYPE A DRIVE RISE

TYPE B DRIVE FALL

TYPE B DRIVE RISE

Rev. A | Page 62 of 72 | September 2011

ADSP-21478/ADSP-21479

THERMAL CHARACTERISTICS

The processor is rated for performance over the temperature

range specified in Operating Conditions on Page 19.

Table 56 airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6 and the junction-to-board measure-

ment complies with JESD51-8. Test board design complies with

JEDEC standards JESD51-7 (PBGA). The junction-to-case mea-

surement complies with MIL- STD-883. All measurements use a

2S2P JEDEC test board.

To determine the junction temperature of the device while on

the application PCB, use:

where:

= junction temperature °C

CASE

= case temperature (°C) measured at the top center of the

package

= junction-to-top (of package) characterization parameter is

the Typical value from Table 56.

= power dissipation

Values of θ

are provided for package comparison and PCB

design considerations. θ

can be used for a first order approxi-

mation of T

by the equation:

where:

= ambient temperature °C

Values of θ

are provided for package comparison and PCB

design considerations when an external heatsink is required.

Values of θ

are provided for package comparison and PCB

design considerations. Note that the thermal characteristics val-

ues provided in Table 56 are modeled values.

Figure 51. Typical Output Rise/Fall Time (20% to 80%,

DD_EXT

= Min)

Figure 52. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

LOAD CAPACITANCE (pF)

RISE AND FALL TIMES (ns)

25 20015050 75 100 125 175

y = 0.0567x + 0.482

y = 0.0367x + 0.4502

y = 0.0314x + 0.5729

TYPE A DRIVE FALL

TYPE A DRIVE RISE

TYPE B DRIVE RISE

TYPE B DRIVE FALL

y = 0.0748x + 0.4601

LOAD CAPACITANCE (pF)

3.5

0.5

1.5

RISE AND FALL DELAY (ns)

2.5

y = 0.015x + 1.4889

y = 0.0088x + 1.6008

y = 0.0199x + 1.1083

y = 0.0102x + 1.2726

0 25 20015050 75 100 125 175

TYPE A DRIVE FALL

TYPE A DRIVE RISE

TYPE B DRIVE RISE

TYPE B DRIVE FALL

4.5

TJTCASE

JT PD

×()+=

Table 56. Thermal Characteristics for 100-Lead LQFP_EP

Parameter Condition Typical Unit

Airflow = 0 m/s 18.1 °C/W

JMA

Airflow = 1 m/s 15.5 °C/W

JMA

Airflow = 2 m/s 14.6 °C/W

2.4 °C/W

Airflow = 0 m/s 0.22 °C/W

JMT

Airflow = 1 m/s 0.36 °C/W

JMT

Airflow = 2 m/s 0.50 °C/W

Table 57. Thermal Characteristics for 196-Ball CSP_BGA

Parameter Condition Typical Unit

Airflow = 0 m/s 29.0 °C/W

JMA

Airflow = 1 m/s 26.1 °C/W

JMA

Airflow = 2 m/s 25.1 °C/W

8.8 °C/W

Airflow = 0 m/s 0.23 °C/W

JMT

Airflow = 1 m/s 0.42 °C/W

JMT

Airflow = 2 m/s 0.52 °C/W

TJTA

JA PD

×()+=

ADSP-21478/ADSP-21479

Rev. A | Page 63 of 72 | September 2011

Thermal Diode

The processors incorporate thermal diode/s to monitor the die

temperature. The thermal diode is a grounded collector, PNP

bipolar junction transistor (BJT). The THD_P pin is connected

to the emitter and the THD_M pin is connected to the base of

the transistor. These pins can be used by an external tempera-

ture sensor (such as ADM 1021A or LM86 or others) to read the

die temperature of the chip.

The technique used by the external temperature sensor is to

measure the change in VBE when the thermal diode is operated

at two different currents. This is shown in the following

equation:

where:

n = multiplication factor close to 1, depending on process

variations

k = Boltzmann constant

T = temperature (°C)

q = charge of the electron

N = ratio of the two currents

The two currents are usually in the range of 10 μA to 300 μA for

the common temperature sensor chips available.

Table 58 contains the thermal diode specifications using the

transistor model.

ΔVBE nkT

------ In(N)××=

Table 58. Thermal Diode Parameters—Transistor Model

Symbol Parameter Min Typ Max Unit

FW2

Forward Bias Current 10 300 A

Emitter Current 10 300 A

Q3,

Transistor Ideality 1.012 1.015 1.017

T3,

Series Resistance 0.12 0.2 0.28 

Analog Devices does not recommend operation of the thermal diode under reverse bias.

Specified by design characterization.

The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: I

= I

× (e

qVBE/nqkT

–1) where I

= saturation current,

q = electronic charge, V

= voltage across the diode, k = Boltzmann constant, and T = absolute temperature (Kelvin).

The series resistance (R

) can be used for more accurate readings as needed.

Rev. A | Page 64 of 72 | September 2011

ADSP-21478/ADSP-21479

100-LQFP_EP LEAD ASSIGNMENT

Table 59 lists the lead names and their default function after

reset (in parentheses).

Table 59. 100-Lead LQFP_EP Lead Assignments (Numerical by Lead Number)

Lead Name Lead No. Lead Name Lead No. Lead Name Lead No. Lead Name Lead No.

DD_INT

DD_EXT

26 DAI_P10 51 V

DD_INT

CLK_CFG1 2 DPI_P08 27 V

DD_INT

52 FLAG0 77

BOOT_CFG0 3 DPI_P07 28 V

DD_EXT

53 V

DD_INT

DD_EXT

DD_INT

29 DAI_P20 54 V

DD_INT

5 DPI_P09 30 V

DD_INT

55 FLAG1 80

BOOT_CFG1 6 DPI_P10 31 DAI_P08 56 FLAG2 81

GND 7 DPI_P11 32 DAI_P04 57 FLAG3 82

NC 8 DPI_P12 33 DAI_P14 58 MLBCLK 83

NC 9 DPI_P13 34 DAI_P18 59 MLBDAT 84

CLK_CFG0 10 DAI_P03 35 DAI_P17 60 MLBDO 85

DD_INT

11 DPI_P14 36 DAI_P16 61 V

DD_EXT

CLKIN 12 V

DD_INT

37 DAI_P15 62 MLBSIG 87

XTAL 13 V

DD_INT

38 DAI_P12 63 V

DD_INT

DD_EXT

14 V

DD_INT

39 V

DD_INT

64 MLBSO 89

DD_INT

15 DAI_P13 40 DAI_P11 65 TRST 90

DD_INT

16 DAI_P07 41 V

DD_INT

66 EMU 91

RESETOUT/RUNRSTIN 17 DAI_P19 42 V

DD_INT

67 TDO 92

DD_INT

18 DAI_P01 43 GND 68 V

DD_EXT

DPI_P01 19 DAI_P02 44 THD_M 69 V

DD_INT

DPI_P02 20 V

DD_INT

45 THD_P 70 TDI 95

DPI_P03 21 V

DD_EXT

46 V

DD_THD

71 TCK 96

DD_INT

22 V

DD_INT

47 V

DD_INT

72 V

DD_INT

DPI_P05 23 DAI_P06 48 V

DD_INT

73 RESET 98

DPI_P04 24 DAI_P05 49 V

DD_INT

74 TMS 99

DPI_P06 25 DAI_P09 50 V

DD_INT

75 V

DD_INT

100

GND 101*

* Lead no. 101 is the GND supply (see Figure 53 and Figure 54) for the processor; this pad must be robustly connected to GND.

MLB pins (pins 83, 84, 85, 87, and 89) are available for automotive models only. For non-automotive models, these pins should be connected

to ground (GND).

ADSP-21478/ADSP-21479

Rev. A | Page 65 of 72 | September 2011

Figure 53 shows the top view of the 100-lead LQFP_EP pin con-

figuration. Figure 54 shows the bottom view of the 100-lead

LQFP_EP lead configuration.

Figure 53. 100-Lead LQFP_EP Lead Configuration (Top View)

Figure 54. 100-Lead LQFP_EP Lead Configuration (Bottom View)

LEAD 1

LEAD 25

LEAD 75

LEAD 51

LEAD 100 LEAD 76

LEAD 26 LEAD 50

LEAD 1 INDICATOR

ADSP-2147x

100-LEAD LQFP_EP

TOP VIEW

LEAD 75

LEAD 51

LEAD 1

LEAD 25

LEAD 76 LEAD 100

LEAD 50 LEAD 26

LEAD 1 INDICATOR

GND PAD

(LEAD 101)

ADSP-2147x

100-LEAD LQFP_EP

BOTTOM VIEW

Rev. A | Page 66 of 72 | September 2011

ADSP-21478/ADSP-21479

196-BALL BGA BALL ASSIGNMENT

Table 60. 196-Ball CSP_BGA Ball Assignment (Numerical by Ball No.)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

A1 GND D1 ADDR6 G1 XTAL K1 DPI_P02 N1 DPI_P14

A2 SDCKE D2 ADDR4 G2 SDA10 K2 DPI_P04 N2 SR_LDO1

A3 SDDQM D3 ADDR1 G3 ADDR11 K3 DPI_P05 N3 SR_LDO4

A4 SDRAS D4 CLK_CFG0 G4 GND K4 DPI_P09 N4 SR_LDO8

A5 SDWE D5 V

DD_EXT

G5 V

DD_INT

K5 V

DD_INT

N5 SR_LDO10

A6 DATA12 D6 V

DD_EXT

G6 GND K6 GND N6 DAI_P01

A7 DATA13 D7 V

DD_EXT

G7 GND K7 GND N7 SR_LDO9

A8 DATA10 D8 V

DD_EXT

G8 GND K8 GND N8 DAI_P02

A9 DATA9 D9 V

DD_EXT

G9 GND K9 GND N9 SR_LDO13

A10 DATA7 D10 V

DD_EXT

G10 V

DD_INT

K10 V

DD_INT

N10 SR_SCLK

A11 DATA3 D11 V

DD_EXT

G11 V

DD_EXT

K11 GND N11 DAI_P09

A12 DATA1 D12 ADDR14 G12 ADDR21 K12 DAI_P16 N12 SR_SDI

A13 DATA2 D13 ADDR20 G13 ADDR19 K13 DAI_P18 N13 SR_LDO17

A14 GND D14 WDT_CLKO G14 RTXO K14 DAI_P15 N14 DAI_P14

B1 ADDR0 E1 ADDR8 H1 ADDR13 L1 DAI_P03 P1 GND

B2 CLK_CFG1 E2 ADDR7 H2 ADDR12 L2 DPI_P10 P2 SR_LDO3

B3 BOOT_CFG0 E3 ADDR5 H3 ADDR10 L3 DPI_P08 P3 SR_LDO2

B4 TMS E4 V

DD_EXT

H4 ADDR17 L4 DPI_P06 P4 SR_LDO6

B5 RESET E5 V

DD_INT

H5 V

DD_INT

L5 V

DD_INT

P5 WDTRSTO

B6 DATA14 E6 V

DD_INT

H6 GND L6 V

DD_INT

P6 DAI_P19

B7 DATA11 E7 V

DD_INT

H7 GND L7 V

DD_INT

P7 DAI_P13

B8 DATA4 E8 V

DD_INT

H8 GND L8 V

DD_INT

P8 SR_LDO11

B9 DATA8 E9 V

DD_INT

H9 GND L9 V

DD_INT

P9 SR_LDO15

B10 DATA6 E10 V

DD_INT

H10 V

DD_INT

L10 V

DD_INT

P10 SR_CLR

B11 DATA5 E11 V

DD_EXT

H11 V

DD_EXT

L11 DAI_P10 P11 SR_LAT

B12 TRST E12 AMI_RD H12 BOOT_CFG2 L12 DAI_P20 P12 SR_LDO14

B13 FLAG1 E13 ADDR22 H13 ADDR23 L13 DAI_P17 P13 SR_LDO12

B14 DATA0 E14 FLAG2 H14 RTXI L14 DAI_P04 P14 GND

C1 ADDR2 F1 CLKIN J1 DPI_P01 M1 DPI_P13

C2 ADDR3 F2 ADDR9 J2 DPI_P03 M2 DPI_P12

C3 RTCLKOUT F3 BOOT_CFG1 J3 ADDR18 M3 SR_LDO0

C4 MS0 F4 NC J4 RESETOUT/RUNRSTIN M4 DPI_P07

C5 SDCAS F5 NC J5 V

DD_INT

M5 DPI_P11

C6 DATA15 F6 GND J6 GND M6 SR_LDO5

C7 TCK F7 GND J7 GND M7 SR_LDO7

C8 TDI F8 GND J8 GND M8 DAI_P07

C9 SDCLK F9 GND J9 GND M9 SR_LDO16

C10 EMU F10 V

DD_INT

J10 V

SS_RTC

M10 SR_SDO

C11 TDO F11 V

DD_EXT

J11 V

DD_RTC

M11 DAI_P06

C12 FLAG3 F12 ADDR15 J12 DAI_P11 M12 DAI_P05

C13 ADDR16 F13 FLAG0 J13 AMI_ACK M13 DAI_P08

C14 WDT_CLKIN F14 AMI_WR J14 MS1 M14 DAI_P12

ADSP-21478/ADSP-21479

Rev. A | Page 67 of 72 | September 2011

OUTLINE DIMENSIONS

The processors are available in 100-lead LQFP_EP and 196-ball

CSP_BGA RoHS compliant packages. For package assignment

by model, see Ordering Guide on Page 69.

Figure 55. 100-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP

]

(SW-100-2)

Dimensions shown in millimeters

For information relating to the SW-100-2 package’s exposed pad, see the table endnote on Page 64.

COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD

0.08

COPLANARITY

1.45

1.40

1.35

0.20

0.15

0.09

0.15

0.10

0.05

7°

3.5°

0°

VIEW A

ROTATED 90° CCW

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

EXPOSED

PAD

25 25

26 26

50 50

76 76100 100

75 75

51 51

0.27

0.22

0.17

0.50

BSC

LEAD PITCH

VIEW A

1.60

MAX

SEATING

PLANE

0.75

0.60

0.45

PIN 1

16.20

16.00 SQ

15.80 14.20

14.00 SQ

13.80

6.00

REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE LEAD ASSIGNMENT AND

PIN FUNCTION DESCRIPTIONS

SECTIONS OF THIS DATA SHEET.

Rev. A | Page 68 of 72 | September 2011

ADSP-21478/ADSP-21479

SURFACE-MOUNT DESIGN

For industry-standard design recommendations, refer to

IPC-7351, Generic Requirements for Surface-Mount Design

and Land Pattern Standard.

AUTOMOTIVE PRODUCTS

The ADSP-21478 and ADSP-21479 models are available with

controlled manufacturing to support the quality and reliability

requirements of automotive applications. Note that these auto-

motive models may have specifications that differ from the

commercial models, and designers should review the product

Specifications section of this data sheet carefully. Only the auto-

motive grade products shown in Table 61 are available for use in

automotive applications. Contact your local ADI account repre-

sentative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these

models.

Figure 56. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]

(BC-196-8)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARD MO-275-GGAB-1

0.80

BSC

0.80

REF

910 811121314 7 564231

BOTTOM VIEW

10.40

BSC SQ

0.35 NOM

0.30 MIN

DETAIL A

TOP VIEW

DETAIL A

COPLANARITY

0.20

BALL DIAMETER

SEATING

PLANE

12.10

12.00 SQ

11.90

A1 BALL

CORNER

A1 BALL

CORNER

1.50

1.41

1.29

1.13

1.06

0.99

0.50

0.45

0.40

Table 61. Automotive Products

Model

Temperature Range

On-Chip SRAM

Processor Instruction

Rate (Max) Package Description

Package

Option

AD21478WYSWZ2Axx –40°C to +105°C 3 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

AD21478WYSWZ2Bxx

–40°C to +105°C 3 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

AD21479WYSWZ2Axx –40°C to +105°C 5 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

AD21479WYSWZ2Bxx

–40°C to +105°C 5 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

Z = RoHS compliant part.

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 19 for junction temperature (T

)

specification, which is the only temperature specification.

Contains multichannel audio decoders from Dolby and DTS.

Contains Digital Transmission Content Protection (DTCP) from DTLA. User must have current license from DTLA to order this product.

ADSP-21478/ADSP-21479

Rev. A | Page 69 of 72 | September 2011

ORDERING GUIDE

Model

Z =RoHS compliant part.

Temperature Range

Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 19 for junction temperature (T

)

specification, which is the only temperature specification.

On-Chip SRAM

Processor Instruction

Rate (Max) Package Description

Package

Option

ADSP-21478BBCZ-2A –40°C to +85°C 3 Mbit 266 MHz 196-Ball CSP_BGA BC-196-8

ADSP-21478BSWZ-2A –40°C to +85°C 3 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21478KBCZ-1A 0°C to +70°C 3 Mbit 200 MHz 196-Ball CSP_BGA BC-196-8

ADSP-21478KBCZ-2A 0°C to +70°C 3 Mbit 266 MHz 196-Ball CSP_BGA BC-196-8

ADSP-21478KBCZ-3A 0°C to +70°C 3 Mbit 300 MHz 196-Ball CSP_BGA BC-196-8

ADSP-21478KSWZ-1A 0°C to +70°C 3 Mbit 200 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21478KSWZ-2A 0°C to +70°C 3 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21479BBCZ-2A –40°C to +85°C 5 Mbit 266 MHz 196-Ball CSP_BGA BC-196-8

ADSP-21479BSWZ-2A –40°C to +85°C 5 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21479KBCZ-1A 0°C to +70°C 5 Mbit 200 MHz 196-Ball CSP_BGA BC-196-8

ADSP-21479KBCZ-2A 0°C to +70°C 5 Mbit 266 MHz 196-Ball CSP_BGA BC-196-8

ADSP-21479KBCZ-3A 0°C to +70°C 5 Mbit 300 MHz 196-Ball CSP_BGA BC-196-8

ADSP-21479KSWZ-1A 0°C to +70°C 5 Mbit 200 MHz 100-Lead LQFP_EP SW-100-2

ADSP-21479KSWZ-2A 0°C to +70°C 5 Mbit 266 MHz 100-Lead LQFP_EP SW-100-2

Rev. A | Page 70 of 72 | September 2011

ADSP-21478/ADSP-21479

Rev. A | Page 71 of 72 | September 2011

Rev. A | Page 72 of 72 | September 2011

ADSP-21478/ADSP-21479

registered trademarks are the property of their respective owners.

D09017-0-9/11(A)