Features * High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture * * * * * * * * - 120 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Non-volatile Program and Data Memories - 1K Byte of In-System Programmable Program Memory Flash Endurance: 10,000 Write/Erase Cycles - 64 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - 64 Bytes Internal SRAM - Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features - One 8-bit Timer/Counter with Prescaler and Two PWM Channels - 4-channel, 10-bit ADC with Internal Voltage Reference - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Low Power Idle, ADC Noise Reduction, and Power-down Modes - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated Oscillator I/O and Packages - 8-pin PDIP/SOIC: Six Programmable I/O Lines Operating Voltage: - 1.8 - 5.5V for ATtiny13V - 2.7 - 5.5V for ATtiny13 Speed Grade - ATtiny13V: 0 - 6 MHz @ 1.8 - 5.5V, 0 - 12 MHz @ 2.7 - 5.5V - ATtiny13: 0 - 12 MHz @ 2.7 - 5.5V, 0 - 24 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption - Active Mode: 1 MHz, 1.8V: 240A - Power-down Mode: < 0.1A at 1.8V 8-bit Microcontroller with 1K Bytes In-System Programmable Flash ATtiny13 Preliminary Summary Pin Configurations Figure 1. Pinout ATtiny13 PDIP/SOIC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/ADC1/T0/PCINT2) PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) Rev. 2535BS-AVR-01/04 Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. Overview The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2. Block Diagram 8-BIT DATABUS STACK POINTER SRAM VCC PROGRAM COUNTER GND PROGRAM FLASH WATCHDOG OSCILLATOR CALIBRATED INTERNAL OSCILLATOR WATCHDOG TIMER TIMING AND CONTROL MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTER0 INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES GENERAL PURPOSE REGISTERS INTERRUPT UNIT X Y Z PROGRAMMING LOGIC ALU DATA EEPROM STATUS REGISTER ADC / ANALOG COMPARATOR DATA REGISTER PORT B DATA DIR. REG.PORT B PORT B DRIVERS RESET CLKI PB0-PB5 2 ATtiny13 2535BS-AVR-01/04 ATtiny13 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny13 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13 as listed on page 49. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 12 on page 30. Shorter pulses are not guaranteed to generate a reset. 3 2535BS-AVR-01/04 Register Summary 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C page 6 0x3E Reserved - - - - - - - - 0x3D SPL SP[7:0] 0x3C Reserved - 0x3B GIMSK - INT0 PCIE - - - - - page 53 0x3A GIFR - INTF0 PCIF - - - - - page 53 0x39 TIMSK0 - - - - OCIE0B OCIE0A TOIE0 - page 70 0x38 TIFR0 - - - - OCF0B OCF0A TOV0 - page 71 0x37 SPMCSR - - - CTPB RFLB PGWRT PGERS SELFPRGEN page 97 - PUD SE SM1 page 49 0x36 OCR0A 0x35 MCUCR page 8 Timer/Counter - Output Compare Register A page 70 SM0 - ISC01 ISC00 0x34 MCUSR - - - - WDRF BORF EXTRF PORF page 33 0x33 TCCR0B FOC0A FOC0B - - WGM02 CS02 CS01 CS00 page 66 0x32 TCNT0 Timer/Counter (8-bit) page 70 0x31 OSCCAL Oscillator Calibration Register page 22 0x30 Reserved - COM0A1 COM0A0 COM0B1 - COM0B0 - 0x2F TCCR0A 0x2E DWDR DWDR[7:0] 0x2D Reserved - 0x2C Reserved - 0x2B Reserved - 0x2A Reserved - 0x29 OCR0B Timer/Counter - Output Compare Register B 0x28 GTCCR TSM - - - CLKPCE - - - Reserved CLKPR 0x25 Reserved - 0x24 Reserved - 0x23 Reserved - 0x22 Reserved 0x21 WDTCR 0x20 Reserved 0x1F Reserved EEARL 0x1D EEDR 0x1C EECR WGM00 page 69 page 94 page 70 - - - PSR10 page 73 CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 24 WDE WDP2 WDP1 WDP0 page 37 - 0x27 0x26 0x1E WGM01 - WDTIF WDTIE WDP3 WDCE - - - - EEPROM Address Register page 14 EEPROM Data Register - - EEPM1 EEPM0 page 14 EERIE EEMWE EEWE EERE page 15 0x1B Reserved - 0x1A Reserved - 0x19 Reserved 0x18 PORTB - - PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 51 0x17 DDRB - - DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 51 0x16 PINB - - PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 51 0x15 PCMSK - - PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 54 0x14 DIDR0 - - ADC0D ADC2D ADC3D ADC1D EIN1D AIN0D page 76, page 91 0x13 Reserved - 0x12 Reserved - 0x11 Reserved - 0x10 Reserved - 0x0F Reserved - 0x0E Reserved - 0x0D Reserved - 0x0C Reserved - 0x0B Reserved - 0x0A Reserved - 0x09 Reserved 0x08 ACSR ACD ACBG ACO ACI ACIE - ACIS1 ACIS0 page 74 0x07 ADMUX - REFS0 ADLAR - - - MUX1 MUX0 page 88 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 89 0x05 ADCH ADC Data Register High Byte 0x04 ADCL ADC Data Register Low Byte 0x03 ADCSRB 0x02 Reserved - 0x01 Reserved - 0x00 Reserved - - - - ACME - - - page 90 page 90 ADTS2 ADTS1 ADTS0 page 91 ATtiny13 2535BS-AVR-01/04 ATtiny13 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 5 2535BS-AVR-01/04 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One's Complement Rd 0xFF - Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 - Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * (0xFF - K) Z,N,V 1 1 INC Rd Increment Rd Rd + 1 Z,N,V DEC Rd Decrement Rd Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC Z None 2 Relative Subroutine Call PC PC + k + 1 None 3 ICALL Indirect Call to (Z) PC Z None 3 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I None BRANCH INSTRUCTIONS RJMP k IJMP RCALL k 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 1 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 6 ATtiny13 2535BS-AVR-01/04 ATtiny13 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S1 S 1 CLS Clear Signed Test Flag S0 S 1 SEV Set Twos Complement Overflow. V1 V 1 CLV Clear Twos Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH Set Half Carry Flag in SREG H1 H 1 CLH Clear Half Carry Flag in SREG H0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Store Program Memory (z) R1:R0 None LPM SPM IN Rd, P In Port Rd P None OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 None 1 1 MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1 BREAK Break For On-chip Debug Only None N/A 7 2535BS-AVR-01/04 Ordering Information Power Supply 12(3) 24(3) Notes: Ordering Code Package(1) 1.8 - 5.5 ATtiny13-12PI ATtiny13-12PJ(2) ATtiny13-12SI ATtiny13-12SJ(2) ATtiny13-12SSI ATtiny13-12SSJ(2) 8P3 8P3 8S2 8S2 S8S1 S8S1 Industrial (-40C to 85C) 2.7 - 5.5 ATtiny13-24PI ATtiny13-24PJ(2) ATtiny13-24SI ATtiny13-24SJ(2) ATtiny13-24SSI ATtiny13-24SSJ(2) 8P3 8P3 8S2 8S2 S8S1 S8S1 Industrial (-40C to 85C) Speed (MHz) Operation Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative. 3. For Speed vs. VCC, see "Maximum Speed vs. VCC" on page 116. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) S8S1 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC) 8 ATtiny13 2535BS-AVR-01/04 ATtiny13 Packaging Information 8P3 E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL MIN NOM A b2 b3 b 4 PLCS Side View L 0.210 NOTE 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 0.150 2 e 3 3 0.100 BSC eA L Notes: MAX 0.300 BSC 0.115 0.130 4 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B 9 2535BS-AVR-01/04 8S2 C 1 E E1 L N Top View End View e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D Side View NOM MAX NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 0 e Notes: 1. 2. 3. 4. 5. MIN A 2, 3 8 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm. 10/7/03 R 10 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. 8S2 REV. C ATtiny13 2535BS-AVR-01/04 ATtiny13 S8S1 1 E1 E N Top View e b A A1 D Side View C L End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX E 5.79 6.20 E1 3.81 3.99 A 1.35 1.75 A1 0.1 0.25 D 4.80 4.98 C 0.17 0.25 b 0.31 0.51 L 0.4 1.27 e NOTE 1.27 BSC 0o 8o Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 7/28/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. S8S1 REV. A 11 2535BS-AVR-01/04 Errata The revision letter in this section refers to the revision of the ATtiny13 device. ATtiny13 Rev. C There are no known errata for this revision. ATtiny13 Rev. B * * * * * Wrong values read after Erase Only operation High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail Device may lock for further programming debugWIRE communication not blocked by lock-bits Watchdog Timer Interrupt disabled 1. Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem Fix/Workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail Writing to any of these locations and bits may in some occasions fail. Problem Fix/Workaround After a writing has been initiated, always observe the RDY/BSY signal. If the writing should fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in revision C. 3. Device may lock for further programming Special combinations of fuse bits will lock the device for further programming effectively turning it into an OTP device. The following combinations of settings/fuse bits will cause this effect: - 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. - 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. - 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. Problem fix/ Workaround Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem. 4. debugWIRE communication not blocked by lock-bits When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program memory and EEPROM data memory can be read even if the lock-bits are set to block further reading of the device. 12 ATtiny13 2535BS-AVR-01/04 ATtiny13 Problem fix/ Workaround Do not ship products with on-chip debug of the tiny13 enabled. 5. Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-out following an interrupt, the device works correctly. Problem fix / Workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period. ATtiny13 Rev. A Revision A has not been sampled. 13 2535BS-AVR-01/04 Datasheet Change Log for ATtiny13 Changes from Rev. 2535A-06/03 to Rev. 2535B-01/04 Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 14 Updated Figure 2 on page 2. Updated Table 12 on page 30, Table 17 on page 39, Table 37 on page 89 and Table 57 on page 116. Updated "Calibrated Internal RC Oscillator" on page 22. Updated the whole "Watchdog Timer" on page 35. Updated Figure 53 on page 103 and Figure 56 on page 108. Updated registers "MCU Control Register - MCUCR" on page 49, "Timer/Counter Control Register B - TCCR0B" on page 69 and "Digital Input Disable Register 0 - DIDR0" on page 76. Updated Absolute Maximum Ratings and DC Characteristics in "Electrical Characteristics" on page 115. Added "Maximum Speed vs. VCC" on page 116 Updated "ADC Characteristics - Preliminary Data" on page 118. Updated "ATtiny13 Typical Characteristics - Preliminary Data" on page 119. Updated "Ordering Information" on page 8. Updated "Packaging Information" on page 9. Updated "Errata" on page 12. Changed instances of EEAR to EEARL. ATtiny13 2535BS-AVR-01/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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