ATTINY13A-MMUR - Atmel - Datasheet.World

2535BS–AVR–01/04

Features

•High Performance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

•Non-volatile Program and Data Memories

– 1K Byte of In-System Programmable Program Memory Flash

Endurance: 10,000 Write/Erase Cycles

– 64 Bytes In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– 64 Bytes Internal SRAM

– Programming Lock for Self-Programming Flash Program and EEPROM Data

Security

•Peripheral Features

– One 8-bit Timer/Counter with Prescaler and Two PWM Channels

– 4-channel, 10-bit ADC with Internal Voltage Reference

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

•Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown -out Detection Circuit

– Internal Calibrated Oscillator

•I/O and Packages

– 8-pin PDIP/SOIC: Six Programmable I/O Lines

•Operating Voltage:

– 1.8 - 5.5V for ATtiny13V

– 2.7 - 5.5V for ATtiny13

•Speed Grade

– ATtiny13V: 0 - 6 MHz @ 1.8 - 5.5V, 0 - 12 MHz @ 2.7 - 5.5V

– ATtiny13: 0 - 12 MHz @ 2.7 - 5.5V, 0 - 24 MHz @ 4.5 - 5.5V

•Industrial Temperature Range

•Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 240µA

– Power-down Mode:

< 0.1µA at 1.8V

Pin C onfigurations

Figure 1. Pinout ATtiny13

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

(PCINT4/ADC2) PB4

GND

VCC

PB2 (SCK/ADC1/T0/PCINT2)

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

PDIP/SOIC

8-bit

Microcontroller

with 1K Bytes

In-System

Programmable

Flash

ATtiny13

Preliminary

Summary

Rev. 2535BS–AVR–01/04

Note : This is a summary docu ment. A compl ete document

is available on our Web site at www.atmel.com.

2ATtiny13 2535BS–AVR–01/04

Overview The ATtiny1 3 is a low-pow er CMOS 8 -bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system

design er to optimize power consumption versus processing speed.

Block Diagram Figure 2. Bloc k Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

SRAM

MCU CONTROL

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTER0

INSTRUCTION

DECODER

DATA DIR.

REG.PORT B

DATA REGISTER

PORT B

PROGRAMMING

LOGIC

TIMING AND

CONTROL

MCU STATUS

STATUS

ALU

PORT B DRIVERS

PB0-PB5

VCC

GND

CONTROL

LINES

8-BIT DATABUS

ADC /

ANALOG COMPARATOR

INTERRUPT

UNIT

CALIBRATED

RESET

CLKI

WATCHDOG

OSCILLATOR

DATA

EEPROM

ATtiny13

2535BS–AVR–01/04

The AVR core c ombines a r ic h instruct ion set with 32 ge neral purpose working r egi sters .

All th e 32 registers are d irectly co nnect ed to the Ari thmetic Lo gic Unit (ALU), allowi ng

two i ndependent r egist ers to be acces sed in one s ing le instr uction e xecut ed in one clo ck

cycl e. The resul ting arc hitect ure is more cod e effic ient while achi eving t hroug hputs up to

ten times faster than conventional CISC microcontrollers.

The A Ttiny13 prov ides the follow ing features: 1K byte of In-System P rogrammabl e

Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general pur -

pose w orking registers, one 8-bit Timer/Counter w ith compare modes , Internal and

External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with

interna l Oscil lator, and t hree software selec table power saving mod es. The Idle mo de

stops the CPU while allowin g the SRAM, Timer/Counter, ADC, Ana log Compar ator, and

Inte rrupt system to co nti nue functioning. The Power-down mode saves the regist er con-

tents , disa bling al l chi p functi ons u ntil the ne xt Inte rrupt or Hardwa re R eset. T he ADC

Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize

switching noise during ADC conversions.

The devi ce is manufactu red using Atmel’s high density non-volatile memory t echnology.

The On-chip ISP Flash allows the Program memory to be re-programmed In-System

through an S PI serial interface, b y a co nventional non -volatile memory programmer or

by an On-chip boot code running on the AVR core.

The ATtiny13 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-

cuit Emulators, and Evaluation kits.

Pin Descriptions

VCC Digital supply voltage.

GND Ground.

Port B (PB5..PB0) Port B is a 6-bit bi-direct ional I/O port with int ernal pull-up resistors (sel ected for each

bit). The Port B outpu t buffers hav e symmetrical dri ve characteri stics wi th bot h high sink

and so urce capability. As inputs, P ort B p ins that are exte rnally pulled low will sou rce

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes activ e, even if the clock is not runni ng.

Port B also serves the functions of various special features of the ATtiny13 as listed on

page 49.

RESETReset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

12 on page 30. Shorter pulses are not guaranteed to generate a reset.

4ATtiny13 2535BS–AVR–01/04

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x3F SREG I T H S V N Z C page 6

0x3E Reserved – – – – – – – –

0x3D SPL SP[7:0] page 8

0x3C Reserved –

0x3B GIMSK – INT0 PCIE – – – – – page 53

0x3A GIFR –INTF0PCIF – – – – – pag e 53

0x39 TIMSK0 –––– OCIE0B OCIE0A TOIE0 – pag e 70

0x38 TIFR0 –––– OCF0B OCF0A TOV0 – pag e 71

0x37 SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN page 97

0x36 OCR0A Timer/Counter – Output Compare Register A page 70

0x35 MCUCR – PUD SE SM1 SM0 – ISC01 ISC00 page 49

0x34 MCUSR –––– WDRF BORF EXTRF PORF page 33

0x33 TCCR0B FOC0A FOC0B –– WGM02 CS02 CS01 CS00 page 66

0x32 TCNT0 Timer/Counter (8-bit) page 70

0x31 OSCCAL Oscillator Calibration Register page 22

0x30 Reserved –

0x2F TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 –– WGM01 WGM00 p age 69

0x2E DWDR DWDR[7:0] page 94

0x2D Reserved –

0x2C Reserved –

0x2B Reserved –

0x2A Reserved –

0x29 OCR0B Timer/Counter – Output Compare Register B page 70

0x28 GTCCR TSM –––––– PSR10 page 73

0x27 Reserved –

0x26 CLKPR CLKPCE ––– CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 24

0x25 Reserved –

0x24 Reserved –

0x23 Reserved –

0x22 Reserved –

0x21 WDTCR WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 37

0x20 Reserved –

0x1F Reserved –

0x1E EEARL –– EEPROM Address Register page 14

0x1D EEDR EEPROM Data Register page 14

0x1C EECR –– EEPM1 EEPM0 EERIE EEMWE EEWE EERE page 15

0x1B Reserved –

0x1A Reserved –

0x19 Reserved –

0x18 PORTB –– PORT B5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 51

0x17 DDRB –– DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 51

0x16 PINB –– PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 51

0x15 PCMSK –– PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 54

0x14 DIDR0 –– ADC0D ADC2D ADC3D ADC1D EIN1D A IN0D page 76, page 91

0x13 Reserved –

0x12 Reserved –

0x11 Reserved –

0x10 Reserved –

0x0F Reserved –

0x0E Reserved –

0x0D Reserved –

0x0C Reserved –

0x0B Reserved –

0x0A Reserved –

0x09 Reserved –

0x08 ACSR ACD ACBG ACO ACI ACIE –ACIS1 ACIS0 page 74

0x07 ADMUX – REFS0 ADLAR –––MUX1 MUX0 page 88

0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 89

0x05 ADCH ADC Data Register High Byte p age 90

0x04 ADCL ADC Data Register Low Byte page 90

0x03 ADCSRB –ACME––– ADTS2 ADTS1 ADTS0 page 91

0x02 Reserved –

0x01 Reserved –

0x00 Reserved –

ATtiny13

2535BS–AVR–01/04

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reser ved I/O memor y addresses

should nev er be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operation the specified bit, a nd can therefore be used o n registers containing such Status F lags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

6ATtiny13 2535BS–AVR–01/04

Instruction Set S ummar y

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtr act two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl, K Subtract Imme diate from Word Rd h:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Register s Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • KZ,N,V1

OR Rd, Rr Logical OR Regi sters Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, R r Exclusive OR Regi sters Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N, V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

BRANCH INSTRUCTIONS

RJMP k Relativ e Jump PC ← PC + k + 1 None 2

IJMP Ind ire ct Jump to (Z) PC ← Z None 2

RCALL k Relat ive Subroutine Call PC ← PC + k + 1 None 3

ICAL L Ind ire ct Ca ll to (Z) PC ← ZNone3

RET Subroutine Return PC ← STACK No ne 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/ 3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 Non e 1/2/3

SBIC P, b S kip if Bit in I/O R egis ter Cle are d if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Ski p if Bit in I/O Reg ister is Set if (P(b)=1 ) PC ← PC + 2 o r 3 Non e 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Bra nch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRG E k Branch if Grea ter or Equa l, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Br anc h if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interru pt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotat e Left Through Carry Rd (0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ATtiny13

2535BS–AVR–01/04

ROR Rd Rotat e Right Throug h Carry Rd (7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1SREG(s)1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signe d Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CL V Cle ar Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr Non e 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LD I Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z + Load Indirect an d Post- Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr S tor e Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr S tore Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr S tore Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memo ry R0 ← (Z) None 3

LPM Rd, Z Load P rogr am Memory Rd ← (Z) None 3

LPM Rd, Z + Load Pr ogram Memor y and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (z) ← R1:R0 None

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr No ne 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Oper ation None 1

SLEEP Sleep (se e specifi c descr. for Sleep function) None 1

WDR Watc hdog Reset (see specific descr . for WD R/Timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

8ATtiny13 2535BS–AVR–01/04
Ordering Information
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative.
3. For Speed vs. VCC, see “Maximum Speed vs. VCC” on page 116.
Power Supply Speed (MHz) Ordering Code Package(1) Operation Range
12(3) 1.8 - 5.5
ATtiny13-12PI
ATtiny13-12PJ(2)
ATtiny13-12SI
ATtiny13-12SJ(2)
ATtiny13-12SSI
ATtiny13-12SSJ(2)
8P3
8P3
8S2
8S2
S8S1
S8S1
Industrial
(-40°C to 85°C)
24(3) 2.7 - 5.5
ATtiny13-24PI
ATtiny13-24PJ(2)
ATtiny13-24SI
ATtiny13-24SJ(2)
ATtiny13-24SSI
ATtiny13-24SSJ(2)
8P3
8P3
8S2
8S2
S8S1
S8S1
Industrial
(-40°C to 85°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
S8S1 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)

ATtiny13

2535BS–AVR–01/04

Packaging Information

8P3

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

01/09/02

8P3 B

A2 A

4 PLCS

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

A 0.210 2

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

D1 0.005 3

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

10 ATtiny13 2535BS–AVR–01/04

8S2

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8S2, 8-lead, 0.209" Body, Plastic Small

Outline Package (EIAJ)

10/7/03

8S2 C

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs are not included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.

A 1.70 2.16

A1 0.05 0.25

b 0.35 0.48 5

C 0.15 0.35 5

D 5.13 5.35

E1 5.18 5.40 2, 3

E 7.70 8.26

L 0.51 0.85

∅

0˚ 8˚

e 1.27 BSC 4

End View

Side View

∅

Top View

ATtiny13

2535BS–AVR–01/04

S8S1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small

Outline (JEDEC SOIC)

7/28/03

S8S1 A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc.

E 5.79 6.20

E1 3.81 3.99

A 1.35 1.75

A1 0.1 0.25

D 4.80 4.98

C 0.17 0.25

b 0.31 0.51

L 0.4 1.27

e 1.27 BSC

0o 8o

Top Vie w

Side View

End View

E1 E

12 ATtiny13 2535BS–AVR–01/04

Errata The revision letter in this section refers to the revision of the ATtiny1 3 device.

ATtiny13 Rev. C There are no known errata for this revisi on.

ATtiny13 Rev. B •Wrong values read after Erase Only operation

•High Voltage Serial Programm ing Flash, EEPROM, Fuse and Lock Bits may fail

•Device may lock for further programming

•debugWIRE communica tio n not blocked by l ock-bit s

•Watchdog Timer Interrupt disabled

1. Wrong values read af ter Erase Only operation

At su pply vol tages belo w 2.7 V , an E EPR OM loca tion that i s era sed b y th e Era se

Only opera tion may read as programmed (0x00).

Problem Fix/Wo rkaround

If it is ne cessar y to rea d an EEPROM locatio n after Erase Onl y, use an At omic Write

operation with 0xFF as data in or der to erase a location. In any case, the Wr ite Only

operation can be used as intended. Thus no special considerations are ne eded as

long as the erased l ocation is not read before it is programmed.

2. High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may

fail

Writing to any of these locations and bit s may in some occasions fail.

Problem Fix/Wo rkaround

After a writing has been initiated, always observe the RDY/BSY signal. If the writing

should fail, rewrite until the RDY/BSY ve rifies a correct writing. This will be fixed in

revision C.

3. Device may lock for further progr am ming

Spe ci a l c o m b i na t io n s o f fu s e b i ts will lo c k t h e d e v ic e f or f u rt h er p r o g ra m min g e ff e c-

tively turning it into an OTP device. The following combinations of settings/fuse bits

will cause this effect:

– 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time

(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled

RSTDISBL = 0.

– 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time

(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled

RSTDISBL = 0.

– 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time

(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled

RSTDISBL = 0.

Problem fix/ Workaround

Avoid the above fuse combinations. Selecting longer start-up time will eliminate the

problem.

4. debugWIRE communication not blocked by lock-bits

When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program

memory and EEPROM data memory can be read even if the lock-bits are set to

block further reading of the device.

ATtiny13

2535BS–AVR–01/04

Problem fix/ Workaround

Do not ship products with on-chip debug of the tiny13 enabled.

5. Watchdog Timer Interrupt disabled

If the watchdog timer interrupt flag is not cl eared before a new timeout occurs, the

watchdog will be disa bled, and the int errupt f lag will auto matically be cleare d. This i s

only applicable in interrupt only mode. If the Watchdog is configured to reset the

devic e in the watchdog ti me-out followi ng an int errupt, the devic e works correctly.

Problem fix / Workaround

Make sure there is enoug h time to always service the first time out event before a

new watchdog timeout occurs. This is done by selecting a long enough time-out

period.

ATtiny13 Rev. A Revision A has not been sampled.

14 ATtiny13 2535BS–AVR–01/04

Datasheet Ch ange

Log for ATtiny13 Please note that the referring page numbers in this section are referring to this docu-

ment. The referring revision in this section are referring to the document revi sion.

Changes fr om Rev.

2535A-06/03 to Rev.

2535B-01/04 1. Updated Figure 2 on page 2.

2. Update d T able 12 o n p age 3 0, Table 17 on page 39 , Tabl e 37 on p age 89

and Table 57 on page 116.

3. Updated “Calibrated Internal RC Oscillator” on page 22.

4. Updated the whole “Watchdog Timer” on page 35.

5. Updated Figure 53 on page 103 and Fi gure 56 on page 108.

6. Updated registers “MCU Control Register – MCUCR” on page 49,

“Timer/Counter Control Register B – TCCR0B” on page 69 and “Digital

Input Disable Register 0 – DIDR0” on page 76.

7. Updated Absol ute Maximum Ratin gs and DC Charact erist ics in “Elect rical

Charact eristics” on page 115.

8. Added “Maximum Speed vs. VCC” on page 116

9. Updated “ADC Charact eristics – Preliminar y Data” on page 118.

10. Updated “ATtiny13 Typical Characteristics – Preliminary Data” on page

119.

11. Updated “Ordering Information” on page 8.

12. Updated “Packaging Information” on page 9.

13. Updated “Errata” on page 12.

14. Changed instances of EEAR to EEARL.

Prin ted on recycled paper.

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