1
Data sheet acquired from Harris Semiconductor
SCHS208D
Features
Wide Analog-Input-Voltage Range . . . . . . . . . . 0V - 10V
Low “ON” Resistance
-V
CC = 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
-V
CC = 9V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Fast Switching and Propagation Delay Times
Low “OFF” Leakage Current
Wide Operating T emperature Range . . . -55oC to 125oC
HC Types
- 2V to 10V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V and 10V
HCT Types
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il1µA at VOL, VOH
Description
The ’HC4066 and CD74HCT4066 contain four independent
digitally controlled analog switches that use silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL with the low power consumption of standard CMOS
integrated circuits.
These switches feature the characteristic linear “ON”
resistance of the metal-gate CD4066B. Each switch is
turned on by a high-level voltage on its control input.
Pinout
CD54HC4066 (CERDIP)
CD74HC4066 (PDIP, SOIC, TSSOP)
CD74HCT4066 (PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC4066F3A -55 to 125 14 Ld CERDIP
CD74HC4066E -55 to 125 14 Ld PDIP
CD74HC4066M -55 to 125 14 Ld SOIC
CD74HC4066MT -55 to 125 14 Ld SOIC
CD74HC4066M96 -55 to 125 14 Ld SOIC
CD74HC4066PW -55 to 125 14 Ld TSSOP
CD74HC4066PWR -55 to 125 14 Ld TSSOP
CD74HC4066PWT -55 to 125 14 Ld TSSOP
CD74HCT4066E -55 to 125 14 Ld PDIP
CD74HCT4066M -55 to 125 14 Ld SOIC
CD74HCT4066MT -55 to 125 14 Ld SOIC
CD74HCT4066M96 -55 to 125 14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
1Y
1Z
2Z
2Y
2E
3E
GND
VCC
1E
4E
4Y
4Z
3Z
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
February 1998 - Revised August 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54HC4066, CD74HC4066,
CD74HCT4066
High-Speed CMOS Logic
Quad Bilateral Switch
[
/Title
(
CD74H
C
4066,
C
D74H
C
T4066
)
/
Subject
(
High-
S
peed
C
MOS
L
ogic
Q
uad
2
Functional Diagram
Logic Diagram
TRUTH TABLE
INPUT
nE SWITCH
L Off
HOn
H= High Level
L= Low Level
1
2
4
3
9
10
11
8
13
5
12
6
4E
3E
2E
1E 1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
GND = 7
VCC = 14
nY
nZ
nE
p
np
n
CD54HC4066, CD74HC4066, CD74HCT4066
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 10.5V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Switch Current, IO (Note 1)
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 10V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 2) θJA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 113oC/W
Maximum Junction Temperature (Hermetic Pac kage or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Incertainapplications,theexternalload-resistorcurrentmayincludebothVCC andsignal-linecomponents.ToavoiddrawingVCC current
when switch current flows into the transmission gate inputs, (terminals 1, 4, 8 and 11) the voltage drop across the bidirectional switch
must not exceed 0.6V (calculated from RON values shown in the DC Electrical Specifications Table). No VCC current will flow through
RLif the switch current flows into terminals 2, 3, 9 and 10.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) VIS (V) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
9 6.3 - - 6.3 - 6.3 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
9 - - 2.7 - 2.7 - 2.7 V
Input Leakage
Current
(Any Control)
IIL VCC or
GND -10--±0.1 - ±1-±1µA
Off-Switch Leakage
Current IZVIL VCC or
GND 10 - - ±0.1 - ±1-±1µA
CD54HC4066, CD74HC4066, CD74HCT4066
4
“ON” Resistance
IO = 1mA
(Figure 1)
RON VCC VCC or
GND 4.5 - 25 80 - 106 - 128
6 - 20 75 - 94 - 113
9 - 15 60 - 78 - 95
VCC to
GND 4.5 - 35 95 - 118 - 142
6 - 24 84 - 105 - 126
9 - 16 70 - 88 - 105
“ON” Resistance
Between Any Two
Switches
RON VCC -4.5-1-----
6 - 0.75 - ----
9-0.5-----
Quiescent Device
Current ICC VCC or
GND - 6 - - 2 - 20 - 40 µA
10 - - 16 - 160 - 320 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
Input Leakage
Current
(Any Control)
IIL VCC or
GND - 5.5 - - ±0.1 - ±1-±1µA
Off-Switch Leakage
Current IZVIL VCC or
GND 5.5 - - ±0.1 - ±1-±1µA
“ON” Resistance
IO = 1mA
(Figure 1)
RON VCC VCC or
GND 4.5 - 25 80 - 106 - 128
VCC to
GND 4.5 - 35 95 - 118 - 142
“ON” Resistance
Between Any Two
Switches
RON VCC -4.5-1-----
Quiescent Device
Current ICC VCC or
GND - 5.5 - - 2 - 20 - 40 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
ICC
(Note 3) VCC
- 2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) VIS (V) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
All 1
NOTE: Unit Load is ICC limit specified in DC Electrical Specifica-
tions table, e.g., 360µA max at 25oC.
CD54HC4066, CD74HC4066, CD74HCT4066
5
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay Time
Switch In to Out tPLH, tPHL CL= 50pF 2 - - 60 - 75 - 90 ns
4.5 - - 12 - 15 - 18 ns
9 - - 8 - 11 - 13 ns
CL= 15pF 5 - 4 - ----ns
Propagation Delay Time
Switch Turn On Delay tPZH, tPZL CL= 50pF 2 - - 100 - 125 - 150 ns
4.5 - - 20 - 25 - 30 ns
9 - - 12 - 15 - 18 ns
CL= 15pF 5 - 8 - ----ns
Propagation Delay Time
Switch Turn Off Delay tPHZ, tPLZ CL= 50pF 2 - - 150 - 190 - 225 ns
4.5 - - 30 - 38 - 45 ns
9 - - 24 - 30 - 36 ns
CL= 15pF 5 - 12 - ----ns
Input (Control) Capacitance CI- - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 4, 5) CPD - 5-25-----pF
HCT TYPES
Propagation Delay Time
Switch In to Out tPLH, tPHL CL= 50pF 4.5 - - 12 - 15 - 18 ns
CL= 15pF 5 - 4 - ----ns
Propagation Delay Time
Switch Turn On Delay tPZH, tPZL CL= 50pF 4.5 - - 24 - 30 - 36 ns
CL= 15pF 5 - 9 - ----ns
Propagation Delay Time
Switch Turn Off Delay tPHZ, tPLZ CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 14 - ----ns
Input (Control) Capacitance CI- - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 4, 5) CPD - 5-38-----pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD=C
PD VCC2fi+Σ(CL+C
S)V
CC2fowhere fi= input frequency, fo= output frequency, CL= output load capacitance, CS= switch
capacitance, VCC = supply voltage.
Analog Channel Specifications TA = 25oC
PARAMETER TEST CONDITIONS VCC (V) HC4066 CD74HCT4066 UNITS
Switch Frequency Response Bandwidth at -3dB
Figure 2 Figure 5, Notes 6, 7 4.5 200 200 MHz
Cross Talk Between Any Two Switches Figure 3 Figure 4, Notes 7, 8 4.5 -72 -72 dB
Total Harmonic Distortion Figure 6, 1kHz,
VIS = 4VP-P 4.5 0.022 0.023 %
Figure 6, 1kHz,
VIS = 8VP-P 9 0.008 N/A %
CD54HC4066, CD74HC4066, CD74HCT4066
6
Control to Switch Feedthrough Noise Figure 7 4.5 200 130 mV
9 550 N/A mV
Switch “OFF” Signal Feedthrough Figure 3 Figure 8, Notes 7, 8 4.5 -72 -72 dB
Switch Input Capacitance, CS-5 5 pF
NOTES:
6. Adjust input level for 0dBm at output, f = 1MHz.
7. VIS is centered at VCC/2.
8. Adjust input for 0dBm at VIS.
Analog Channel Specifications TA = 25oC (Continued)
PARAMETER TEST CONDITIONS VCC (V) HC4066 CD74HCT4066 UNITS
Typical Performance Curves
FIGURE 1. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL
VOLTAGE FIGURE 2. SWITCH FREQUENCY RESPONSE, VCC = 4.5V
FIGURE 3. SWITCH-OFF SIGNAL FEEDTHROUGH AND CROSSTALK vs FREQUENCY, VCC = 4.5V
VCC = 4.5V, PIN 1 TO 2
50
40
30
20
10
00123454.5 6 7 8 9 10
INPUT SIGNAL VOLTAGE, VIS (V)
“ON” RESISTANCE, RON ()
VCC = 9V, PIN 1 TO 3
TA = 25oC, GND = 0V
CL = 10pF
VCC = 4.5V
RL = 50
TA = 25oC
PIN 4 TO 3
0
-1
-2
-3
-4
CHANNEL-ON BANDWIDTH, dB
FREQUENCY, f (Hz)
104105106107108
CL = 10pF
VCC = 4.5V
RL = 50
TA = 25oC
PIN 4 TO 3
-20
-40
-60
-80
-100
CROSSTALK, dB
FREQUENCY, f (Hz)
104105106107108
0
SWITCH-OFF SIGNAL FEEDTHROUGH, dB
CD54HC4066, CD74HC4066, CD74HCT4066
7
Analog Test Circuits
FIGURE 4. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT
FIGURE 5. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 6. TOTAL HARMONIC DISTORTION TEST CIRCUIT
FIGURE 7. CONTROL-TO-SWITCH FEEDTHROUGH NOISE
TEST CIRCUIT FIGURE 8. SWITCH OFF SIGNAL FEEDTHROUGH
VCC
VIS
0.1µF
RC
VCC/2
VOS1
SWITCH
ON
VCC
VCC/2
R
RC
VCC/2
VOS2
SWITCH
OFF
dB
METER
VIS
fIS = 1MHz SINEWAVE
R = 50
C = 10pF
R
VCC
VIS
0.1µF
5010pF
VCC/2
VOS
SWITCH
ON
dB
METER
VCC
VIS
10µF
10k50pF
VCC/2
VOS
SWITCH
ON
DISTORTION
METER
VI = VIH
fIS = 1kHz TO 10kHz
VIS
SINE
WAVE
SWITCH
ALTERNATING
ON AND OFF
tr, tf 6ns
fCONT = 1MHz
50% DUTY
CYCLE SCOPE
VP-P
VOS
E
VOS
50pF
600
VCC/2
600
VCC/2
VCC VCC
VIS
0.1µF
RC
VCC/2
VOS
SWITCH
OFF
dB
METER
R
VCC/2
VC = VIL
fIS 1MHz SINEWAVE
R = 50
C = 10pF
Test Circuits and Waveforms
FIGURE 9. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 10. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD54HC4066, CD74HC4066, CD74HCT4066
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8950701CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8950701CA
CD54HC4066F3A
CD54HC4066F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8950701CA
CD54HC4066F3A
CD74HC4066E ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4066E
CD74HC4066EE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4066E
CD74HC4066M ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066M96 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066M96E4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066M96G4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066ME4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066MG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066MT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066MTE4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066MTG4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4066M
CD74HC4066PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HC4066PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HC4066PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HC4066PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC4066PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HC4066PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HC4066PWT ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HC4066PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HC4066PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4066
CD74HCT4066E ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4066E
CD74HCT4066EE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4066E
CD74HCT4066M ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066M96 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066M96E4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066M96G4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066ME4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066MG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066MT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066MTE4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
CD74HCT4066MTG4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4066M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4066, CD74HC4066, CD74HCT4066 :
Catalog: CD74HC4066
Automotive: CD74HCT4066-Q1
Military: CD54HC4066
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC4066M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC4066MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC4066PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4066PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4066M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HCT4066MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4066M96 SOIC D 14 2500 367.0 367.0 38.0
CD74HC4066MT SOIC D 14 250 367.0 367.0 38.0
CD74HC4066PWR TSSOP PW 14 2000 367.0 367.0 35.0
CD74HC4066PWT TSSOP PW 14 250 367.0 367.0 35.0
CD74HCT4066M96 SOIC D 14 2500 367.0 367.0 38.0
CD74HCT4066MT SOIC D 14 250 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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