SG3524N - Philips Semiconductors / NXP Semiconductors

Philips Semiconductors Product specification

SG3524SMPS control circuit

1994 Aug 31 853-0891 13721

DESCRIPTION

This monolithic integrated circuit contains all the control circuitry for

a regulating power supply inverter or switching regulator. Included in

a 16-pin dual-in-line package is the voltage reference, error

amplifier, oscillator, pulse-width modulator, pulse steering flip-flop,

dual alternating output switches and current-limiting and shut-down

circuitry. This device can be used for switching regulators of either

polarity, transformer-coupled DC-to-DC converters, transformerless

voltage doublers and polarity converters, as well as other power

control applications. The SG3524 is designed for commercial

applications of 0°C to +70°C.

FEATURES

•Complete PWM power control circuitry

•Single ended or push-pull outputs

•Line and load regulation of 0.2%

•1% maximum temperature variation

•Total supply current is less than 10mA

•Operation beyond 100kHz

PIN CONFIGURATION

D, F, N Packages

TOP VIEW

INVERT INPUT

NON-INV INPUT

OSC OUTPUT

(+)CL SENSE

(–)CL SENSE

GROUND

VREF

VIN

EMITTER B

COLLECTOR B

COLLECTOR A

EMITTER A

SHUTDOWN

COMPENSATION

SL00174

Figure 1. Pin Configuration

ORDERING INFORMATION

DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #

16-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C SG3524N SOT38-4

16-Pin Ceramic Dual In-Line Package (CERDIP) 0 to +70°C SG3524F 0582B

16-Pin Small Outline (SO) Package 0 to +70°C SG3524D SOT109-1

BLOCK DIAGRAM

(SUBSTRATE)

VIN 15

810

–

REF

REG

OSC

ERROR

AMPINV INPUT

N.I. INPUT

+5V

OSCILLATOR

OUTPUT FLIP FLOP

+5V TO ALL

INTERNAL CIRCUITRY

NOR

–

NOR

+5V

SHUTDOWN

GROUND

(RAMP)

1k COMPENSATION

COMPARATOR

+SENSE

–SENSE

10k

+5V

VREF

+5V

SL00175

Figure 2. Block Diagram

Philips Semiconductors Product specification

SG3524SMPS control circuit

1994 Aug 31 2

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNIT

VIN Input voltage 40 V

IOUT Output current (each output) 100 mA

IREF Reference output current 50 mA

Oscillator charging current 5 mA

PDPower dissipation

Package limitation 1000 mW

Derate above 25°C 8 mW/°C

TAOperating temperature range 0 to +70 °C

TSTG Storage temperature range -65 to +150 °C

DC ELECTRICAL CHARACTERISTICS

TA=0°C to +70°C, VIN=20V, and f=20kHz, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max

UNIT

Reference section

VOUT Output voltage 4.6 5.0 5.4 V

Line regulation VIN=8 to 40V 10 30 mV

Load regulation IL=0 to 20mA 20 50 mV

Ripple rejection f=120Hz, TA=25°C 66 dB

ISC Short circuit current limit VREF=0, TA=25°C 100 mA

Temperature stability Over operating temperature range 0.3 1 %

Long-term stability TA=25°C 20 mV/kHz

Oscillator section

fMAX Maximum frequency CT=0.001 µF, RT=2kΩ300 kHz

Initial accuracy RT and CT constant 5 %

Voltage stability VIN=8 to 40V, TA=25°C 1 %

Temperature stability Over operating temperature range 2 %

Output amplitude Pin 3, TA=25°C 3.5 VP

Output pulse width CT=0.01 µF, TA=25°C 0.5 µs

Error amplifier section

VOS Input offset voltage VCM=2.5V 2 10 mV

IBIAS Input bias current VCM=2.5V 2 10 µA

Open-loop voltage gain 68 80 dB

VCM Common-mode voltage TA=25°C 1.8 3.4 V

CMRR Common-mode rejection ratio TA=25°C 70 dB

BW Small-signal bandwidth AV=0dB, TA=25°C 3 MHz

VOUT Output voltage TA=25°C 0.5 3.8 V

Comparator section

Duty cycle % each output “ON” 0 45 %

Input threshold Zero duty cycle 1 V

Input threshold Maximum duty cycle 3.5 V

IBIAS Input bias current 1 µA

Current limiting section

Sense voltage Pin 9=2V with error amplifier set for maximum out,

TA=25°C180 200 220 mV

Sense voltage T.C. 0.2 mV/°C

VCM Common-mode voltage -1 +1 V

Philips Semiconductors Product specification

SG3524SMPS control circuit

1994 Aug 31 3

DC ELECTRICAL CHARACTERISTICS (Continued)

TA = 0°C to +70°C, VIN = 20V, and f = 20kHz, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min Typ Max

UNIT

Output section (each output)

Collector-emitter voltage (breakdown) 40 V

Collector-leakage current VCE=40V 0.1 50 µA

Saturation voltage IC=50mA 1 2 V

Emitter output voltage VIN=20V 17 18 V

tRRise time RC=2kΩ, TA=25°C 0.2 µs

tFFall time RC=2kΩ, TA=25°C 0.1 µs

Total standby current

(excluding oscillator charging current,

error and current limit dividers, and

with outputs open) VIN=40V 8 10 mA

THEORY OF OPERATION

Voltage Reference

An internal series regulator provides a nominal 5V output which is

used both to generate a reference voltage and is the regulated

source for all the internal timing and controlling circuitry. This

regulator may be bypassed for operation from a fixed 5V supply by

connecting Pins 15 and 16 together to the input voltage. In this

configuration, the maximum input voltage is 6.0V.

This reference regulator may be used as a 5V source for other

circuitry. It will provide up to 50mA of current itself and can easily be

expanded to higher currents with an external PNP as shown in

Figure 3.

IL to 1.0A

DEPENDING

ON CHOICE

FOR Q1

VREF

100Ω

+VIN

10µF

GND

15 16

SG3524

REFERENCE

SECTION

SL00176

Figure 3. Expanded Reference Current Capability

TEST CIRCUIT

OSC OUT

1W 2k

OUTPUTS

5410912768

SG3524

RAMP N.I.

INPUT

INV.

INPUT COMP SHUT

DOWN

CURRENT

LIMIT

VIN

8–40V

0.1 RTCT

10k

VREF

ISVIN

SL00177

Figure 4. Test Circuit

Philips Semiconductors Product specification

SG3524SMPS control circuit

1994 Aug 31 4

TIMING CAPACITOR VALUE (C–)–(µF)

1.0

0.5

0.3

.001 .002 .005 .01 .02 .05 1

OUTPUT DEAD TIME – microseconds

SL00178

Figure 5. Output Stage Dead Time as a Function of the Timing

Capacitor Value

TIMING RESISTOR (R ) kohms

100

1005020105 200 5001ms2ms

OSCILLATOR PERIOD (µs)

SL00179

Figure 6. Oscillator Period

as a Function of RT and CT

FREQUENCY - (Hz)

VOLTAGE GAIN - dB

10 100 1k 10k 100k 1M 10M

RL = RESISTANCE FROM

PIN 9 TO GND

RL = 30kΩ

RL = 100kΩ

RL = 1MΩ

RL = 30MΩ

RL = 300kΩ

SL00180

Figure 7. Amplifiers Open-Loop Gain as a Function of

Frequency and Loading on Pin 9

Oscillator

The oscillator in the SG3524 uses an external resistor (RT) to

establish a constant charging current into an external capacitor (CT).

While this uses more current than a series-connected RC, it

provides a linear ramp voltage on the capacitor which is also used

as a reference for the comparator. The charging current is equal to

3.6 V ÷RT and should be kept within the approximate range of 30µA

to 2mA; i.e., 1.8k<RT<100k.

The range of values for CT also has limits as the discharge time of

CT determines the pulse-width of the oscillator output pulse. This

pulse is used (among other things) as a blanking pulse to both

outputs to insure that there is no possibility of having both outputs

on simultaneously during transitions. This output dead time

relationship is shown in Figure 5. A pulse width below approximately

0.5µs may allow false triggering of one output by removing the

blanking pulse prior to the flip-flop’s reaching a stable state. If small

values of CT must be used, the pulse-width may still be expanded

by adding a shunt capacitance (≅100pF) to ground at the oscillator

output. [(Note: Although the oscillator output is a convenient

oscilloscope sync input, the cable and input capacitance may

increase the blanking pulse-width slightly.)] Obviously, the upper

limit to the pulse width is determined by the maximum duty cycle

acceptable. Practical values of CT fall between 0.001 and 0.1 µF.

The oscillator period is approximately t=RTCT where t is in

microseconds when RT=Ω and CT=µF. The use of Figure 6 will allow

selection of RT and CT for a wide range of operating frequencies.

Note that for series regulator applications, the two outputs can be

connected in parallel for an effective 0-90% duty cycle and the

frequency of the oscillator is the frequency of the output. For

push-pull applications, the outputs are separated and the flip-flop

divides the frequency such that each output’s duty cycle is 0-45%

and the overall frequency is one-half that of the oscillator.

External Synchronization

If it is desired to synchronize the SG3524 to an external clock, a

pulse of ≅+3V may be applied to the oscillator output terminal with

RTCT set slightly greater than the clock period. The same

considerations of pulse-width apply. The impedance to ground at

this point is approximately 2kΩ.

If two or more SG3524s must be synchronized together, one must

be designated as master with its RTCT set for the correct period.

The slaves should each have an RTCT set for approximately 10%

longer period than the master with the added requirement that

CT(slave)=one-half CT (master). Then connecting Pin 3 on all units

together will insure that the master output pulse—which occurs first

and has a wider pulse width—will reset the slave units.

Error Amplifier

This circuit is a simple differential input transconductance amplifier .

The output is the compensation terminal, Pin 9, which is a

high-impedance node (RL≅5MΩ). The gain is

AVgMRL8 ICRL

2kT 0.002RL

and can easily be reduced from a nominal of 10,000 by an external

shunt resistance from Pin 9 to ground, as shown in Figure 7.

In addition to DC gain control, the compensation terminal is also the

place for AC phase compensation. The frequency response curves

of Figure 7 show the uncompensated amplifier with a single pole at

approximately 200Hz and a unity gain crossover at 5MHz.

Typically, most output filter designs will introduce one or more

additional poles at a significantly lower frequency. Therefore, the

best stabilizing network is a series RC combination between Pin 9

and ground which introduces a zero to cancel one of the output filter

poles. A good starting point is 50kΩ plus 0.001µF.

Philips Semiconductors Product specification

SG3524SMPS control circuit

1994 Aug 31 5

One final point on the compensation terminal is that this is also a

convenient place to insert any programming signal which is to

override the error amplifier. Internal shutdown and current limit

circuits are connected here, but any other circuit which can sink

200µA can pull this point to ground, thus shutting of f both outputs.

While feedback is normally applied around the entire regulator, the

error amplifier can be used with conventional operational amplifier

feedback and is stable in either the inverting or non-inverting mode.

Regardless of the connections, however, input common-mode limits

must be observed or output signal inversions may result. For

conventional regulator applications, the 5V reference voltage must

be divided down as shown in Figure 8. The error amplifier may also

be used in fixed duty cycle applications by using the unity gain

configuration shown in the open-loop test circuit.

Current Limiting

The current limiting circuitry of the SG3524 is shown in Figure 9.

By matching the base-emitter voltages of Q1 and Q2, and assuming

a negligible voltage drop across R1:

Threshold=VBE(Q1)+I1R2-VBE(Q2)

=I1R2≅200mV

Although this circuit provides a relatively small threshold with a

negligible temperature coefficient, there are some limitations to its

use, the most important of which is the ±1V common-mode range

which requires sensing in the ground line. Another factor to consider

is that the frequency compensation provided by R1C1 and Q1

provides a roll-off pole at approximately 300Hz.

Since the gain of this circuit is relatively low, there is a transition

region as the current limit amplifier takes over pulse width control

from the error amplifier. For testing purposes, threshold is defined as

the input voltage required to get 25% duty cycle with the error

amplifier signaling maximum duty cycle.

In addition to constant current limiting, Pins 4 and 5 may also be

used in transformer-coupled circuits to sense primary current and to

shorten an output pulse, should transformer saturation occur.

Another application is to ground Pin 5 and use Pin 4 as an additional

shutdown terminal: i.e., the output will be off with Pin 4 open and on

when it is grounded. Finally, foldback current limiting can be

provided with the network of Figure 10. This circuit can reduce the

short-circuit current (ISC) to approximately one-third the maximum

available output current (IMAX).

OUTPUT

NEGATIVE

VOLTAGES

GND

–

VREF

OUTPUT

POSITIVE

VOLTAGES

GND

–

VREF

SL00181

Figure 8. Error Amplifier Biasing Circuits

+–

R1R1

COMPARATOR

ERROR

AMPLIFIER

RAMP

SENSE

SL00182

Figure 9. Current Limiting Circuitry of the SG3524

NOTE:

Foldback current limiting can be used to reduce power dissipation

under shorted output conditions.

IMAX +1

RSVTH )

V0R2

R1)R2

ISC +

VTH

RSwhere

VTH = 200mV

VO = 5V

SA/SBR1

–

SENSE

SL00183

Figure 10. Foldback Current Limiting