LP3984IMF-1.8/NOPB - NATIONAL SEMICONDUCTOR

1PF

LP3984

VIN VOUT

VEN

3(A2)

5(B1)

2(A1)

1PF

1(B2)

Tant

LP3984

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SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

LP3984 Micropower 150 mA Ultra Low-Dropout CMOS Voltage Regulator in Subminiature

4-I/O DSBGA Package

Check for Samples: LP3984

1FEATURES DESCRIPTION

The LP3984 is designed for portable and wireless

2• Miniature 4-I/O DSBGA or SOT-23-5 Package applications with demanding performance and space

• Logic controlled enable requirements.

• Stable with Tantalum Capacitors The LP3984's performance is optimized for battery

• 1 µF Tantalum Output Capacitor powered systems to deliver extremely low dropout

• Fast Turn-On voltage and low quiescent current. Regulator ground

current increases only slightly in dropout, further

• Thermal Shutdown and Short-Circuit Current prolonging the battery life.

Limit Power supply rejection is better than 60 dB at low

KEY SPECIFICATIONS frequencies and starts to roll off at 10 kHz. High

power supply rejection is maintained down to low

• 2.5 to 6.0V Input Range input voltage levels common to battery operated

• 150 mA Output circuits.

• 60 dB PSRR at 1 kHz, 40 dB at 10 kHz @ 3.1VIN The device is ideal for mobile phone and similar

•≤1.2 µA Quiescent Current when Shut Down battery powered wireless applications. It provides up

to 150 mA from a 2.5V to 6V input. The LP3984

• Fast Turn-On Time: 20 µs (typ.) consumes less than 1.2 µA in disable mode and has

• 75 mV typ Dropout with 150 mA Load fast turn-on time less than 20 µs.

•−40 to +125°C Junction Temperature Range for The LP3984 is available in a 4-bump DSBGA and 5-

Operation pin SOT-23 packages. Performance is specified for

• 1.5V, 1.8V, 2.9V and 3.1V −40°C to +125°C temperature range and is available

in 1.5V, 1.8V, 2.9V and 3.1V output voltages. For

APPLICATIONS other output voltage options from 1.5V to 3.5V,

please contact TI sales office.

• CDMA Cellular Handsets

• Wideband CDMA Cellular Handsets

• GSM Cellular Handsets

• Portable Information Appliances

Typical Application Circuit

Note: Pin Numbers in parenthesis indicate DSBGA package.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP3984

SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

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Block Diagram

Pin Descriptions

Name DSBGA (1) SOT Function

VEN A2 3 Enable Input Logic, Enable High

GND A1 2 Common Ground

VOUT B1 5 Output Voltage of the LDO

VIN B2 1 Input Voltage of the LDO

N.C. 4 No Connection

(1) The pin numbering scheme for the DSBGA package was revised in April 2002 to conform to JEDEC standards. Only the pin numbers

were revised. No changes to the physical locations of the inputs/outputs were made. For reference purposes, the obsolete numbering

scheme had GND as pin 1, VOUT as pin 2, VIN as pin 3 and VEN as pin 4.

Connection Diagram

SOT-23-5 Package

Figure 1. Top View

See Package Number DBV

DSBGA, 4-Bump Package

Figure 2. Top View

See Package Number YPB0004

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS(1)(2)(3)

VIN, VEN −0.3 to 6.5V

VOUT –0.3 to (VIN+0.3) ≤6.5V

Junction Temperature 150°C

Storage Temperature −65°C to +150°C

Lead Temp. 235°C

Pad Temp.(4) 235°C

Maximum Power Dissipation(5) SOT-23-5 364 mW

DSBGA 235 mW

ESD Rating(6) Human Body Model 2kV

Machine Model 200V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) Additional information on pad temperature can be found in the TI AN-1112 Application Report ().

(5) The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: PD= (TJ-

TA)/θJA,where TJis the junction temperature, TAis the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The

364 mW rating for SOT23-5 appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction

temperature, 150°C, for TJ, 70°C for TA, and 220°C/W for θJA. More power can be dissipated safely at ambient temperatures below

70°C . Less power can be dissipated safely at ambient temperatures above 70°C. The Absolute Maximum power dissipation for SOT23-

5 can be increased by 4.5 mW for each degree below 70°C, and it must be derated by 4.5mW for each degree above 70°C.

(6) The human body model is 100pF discharged through 1.5kΩresistor into each pin. The machine model is a 200 pF capacitor discharged

directly into each pin.

OPERATING RATINGS(1)(2)

VIN 2.5 to 6V

VEN 0 to (VIN+0.3V) ≤6V

Junction Temperature −40°C to +125°C

Thermal Resistance θJA (SOT23-5) 220°C/W

θJA (DSBGA) 340°C/W

Maximum Power Dissipation(3) SOT-23-5 250mW

DSBGA 160mW

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The

250mW rating for SOT23-5 appearing under Operating Ratings results from substituting the maximum junction temperature for

operation, 125°C, for TJ, 70°C for TA, and 220°C/W for θJA using the formula: PD= (TJ- TA)/θJA. More power can be dissipated at

ambient temperatures below 70°C . Less power can be dissipated at ambient temperatures above 70°C. The maximum power

dissipation for operation can be increased by 4.5 mW for each degree below 70°C, and it must be derated by 4.5mW for each degree

above 70°C.

Product Folder Links: LP3984

LP3984

SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

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ELECTRICAL CHARACTERISTICS

Unless otherwise specified: VIN = 2.5V for 1.5V and 1.8V options, VIN = VOUT + 0.5 for output options higher than 2.5V, CIN = 1

µF, IOUT = 1mA, COUT = 1 µF, tantalum. Typical values and limits appearing in standard typeface are for TJ= 25°C. Limits

appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (1) (2)

Limit

Symbol Parameter Conditions Typ Units

Min Max

Output Voltage Tolerance −1.2 1.2 % of

−2.0 2.0 VOUT(nom)

Line Regulation Error VIN = 2.5V to 4.5V for 1.5V and 1.8V

options 0.05 −0.15 0.15 %/V

VIN = (VOUT + 0.5V) to 4.5V for Voltage

ΔVOUT options higher than 2.5V

Load Regulation Error(3) IOUT = 1 mA to 150 mA 0.002 0.005

LP3984IM5 (SOT-23-5) %/mA

LP3984IBP (DSBGA) 0.0009 0.002

VIN = VOUT(nom) + 0.2V,

f = 1 kHz, 60

IOUT = 50 mA, Figure 4

PSRR Power Supply Rejection Ratio dB

VIN = VOUT(nom) + 0.2V,

f = 10 kHz, 40

IOUT = 50 mA, Figure 4

IQQuiescent Current VEN = 1.4V, IOUT = 0 mA 80 125

VEN = 1.4V, IOUT = 0 to 150 mA 110 150 µA

VEN = 0.4V 0.005 1.2

Dropout Voltage(4) IOUT = 1 mA 0.6 2.5

IOUT = 50 mA 25 40 mV

IOUT = 100 mA 50 80

IOUT = 150 mA 75 120

ISC Short Circuit Current Limit Output Grounded 600 mA

(Steady State)

IOUT(PK) Peak Output Current VOUT ≥VOUT(nom) - 5% 600 300 mA

TON Turn-On Time(5) 20 µs

enOutput Noise Voltage BW = 10 Hz to 100 kHz, 90 µVrms

COUT = 1µF tant.

IEN Maximum Input Current at EN VEN = 0.4 and VIN = 6.0 ±1 nA

VIL Maximum Low Level Input Voltage VIN = 2.5 to 6.0V 0.4 V

at EN

VIH Minimum High Level Input Voltage VIN = 2.5 to 6.0V 1.4 V

at EN

COUT Output Capacitor Capacitance 1 22 µF

ESR 2 10 Ω

Thermal Shutdown Temperature 160 °C

TSD Thermal Shutdown Hysteresis 20 °C

(1) Min and Max Limits are verified by design, test, or statistical analysis. Typical (Typ.) numbers are not verified, but do represent the most

likely norm.

(2) The target output voltage, which is labeled VOUT(nom), is the desired voltage option.

(3) An increase in the load current results in a slight decrease in the output voltage and vice versa.

(4) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This

specification does not apply for input voltages below 2.5V.

(5) Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal

value.

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SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

Figure 3. Line Transient Input Test Signal

Figure 4. PSRR Input Test Signal

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SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

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TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise specified, CIN = COUT = 1 µF Tantalum, VIN = 2.5 for 1.5V and 1.8V options, VIN = VOUT + 0.2V for output

options higher than 2.5V, TA= 25°C, Enable pin is tied to VIN.

Power Supply Rejection Ratio (VIN = 3.5V) Power Supply Rejection Ratio (VIN = 3.5V)

Figure 5. Figure 6.

Power Supply Rejection Ratio (VIN = 3.5V) Power Supply Rejection Ratio (LP3984-1.5, VIN = 2.5V)

Figure 7. Figure 8.

Line Transient Response (LP3984-3.1) Line Transient Response (LP3984-3.1)

Figure 9. Figure 10.

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SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified, CIN = COUT = 1 µF Tantalum, VIN = 2.5 for 1.5V and 1.8V options, VIN = VOUT + 0.2V for output

options higher than 2.5V, TA= 25°C, Enable pin is tied to VIN.

Line Transient Response (LP3984-3.1) Line Transient Response (LP3984-3.1)

Figure 11. Figure 12.

Line Transient Response (LP3984-3.1) Line Transient Response (LP3984-3.1)

Figure 13. Figure 14.

Start Up Response Start Up Response

Figure 15. Figure 16.

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SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified, CIN = COUT = 1 µF Tantalum, VIN = 2.5 for 1.5V and 1.8V options, VIN = VOUT + 0.2V for output

options higher than 2.5V, TA= 25°C, Enable pin is tied to VIN.

Enable Response Load Transient Response (LP3984-3.1

Figure 17. Figure 18.

Load Transient Response (LP3984-3.1) Load Transient Response (VIN = 4.2V)

Figure 19. Figure 20.

Product Folder Links: LP3984

LP3984

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SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

APPLICATION HINTS

External Capacitors

Like any low-dropout regulator, the LP3984 requires external capacitors for regulator stability. The LP3984 is

specifically designed for portable applications requiring minimum board space and smallest components. These

capacitors must be correctly selected for good performance.

Input Capacitors

An input capacitance of ≊1 µF is required between the LP3984 input pin and ground (the amount of the

capacitance may be increased without limit).

This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-

impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,

it must be specified by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be

considered when selecting the capacitor to ensure the capacitance will be ≊1 µF over the entire operating

temperature range.

Output Capacitor

The LP3984 is designed specifically to work with tantalum output capacitors. A tantalum capacitor in 1 to 22 µF

range with 2Ωto 10ΩESR range is suitable in the LP3984 application circuit.

It may also be possible to use film capacitors at the output, but these are not as attractive for reasons of size and

cost.

The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR

(Equivalent Series Resistance) value which is within a stable range (2Ωto 10Ω).

No-Load Stability

The LP3984 will remain stable and in regulation with no external load. This is specially important in CMOS RAM

keep-alive applications.

On/Off Input Operation

The LP3984 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used,

the VEN pin should be tied to VIN to keep the regulator output on at all times. To assure proper operation, the

signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage

thresholds listed in the Electrical Characteristics section under VIL and VIH.

Fast On-Time

The LP3984 output is turned on after Vref voltage reaches its final value (1.23V nominal). To speed up this

process, the noise reduction capacitor at the bypass pin is charged with an internal 70 µA current source. The

current source is turned off when the bandgap voltage reaches approximately 95% of its final value. The turn-on

time is determined by the time constant of the bypass capacitor. The smaller the capacitor value, the shorter the

turn-on time, but less noise gets reduced. As a result, turn-on time and noise reduction need to be taken into

design consideration when choosing the value of the bypass capacitor.

Product Folder Links: LP3984

LP3984

SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

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DSBGA Mounting

The DSBGA package requires specific mounting techniques which are detailed in the AN-1112 Application

Report (SNVA009). Referring to the section PCB Layout ; note that the pad style which must be used with the 5-

pin package is NSMD (non-solder mask defined) type.

For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the

DSBGA device.

DSBGA Light Sensitivity

Exposing the DSBGA device to direct sunlight will cause mis-operation of the device. Light sources such as

halogen lamps can affect electrical performance if brought near to the device.

The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent

lighting used inside most buildings has very little effect on performance. A DSBGA test board was brought to

within 1 cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a

deviation of less than 0.1% from nominal.

Product Folder Links: LP3984

LP3984

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SNVS160F –OCTOBER 2001–REVISED OCTOBER 2013

REVISION HISTORY

Changes from Revision D (May 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format; correct typos ................................................................................... 10

Changes from Revision E (May 2013) to Revision F Page

• Deleted 2.0V option which is obsoleted ................................................................................................................................ 1

• Deleted legacy ordering table ............................................................................................................................................... 3

Product Folder Links: LP3984

PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3984IMF-1.5 LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI LEAB

LP3984IMF-1.5/NOPB LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI LEAB

LP3984IMF-1.8 LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI LEBB

LP3984IMF-1.8/NOPB LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI LEBB

LP3984IMF-3.1/NOPB LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI -40 to 125 LEDB

LP3984IMFX-1.8/NOPB LIFEBUY SOT-23 DBV 5 TBD Call TI Call TI -40 to 125 LEBB

LP3984ITP-2.9/NOPB LIFEBUY DSBGA YPB 4 TBD Call TI Call TI -40 to 125

LP3984ITPX-1.8/NOPB LIFEBUY DSBGA YPB 4 TBD Call TI Call TI -40 to 125

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2017

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com

PACKAGE OUTLINE

0.575 MAX

0.15

0.11

0.5

4X 0.18

0.16

B E A

4215097/B 07/2016

DSBGA - 0.575 mm max heightYPB0004

DIE SIZE BALL GRID ARRAY

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

SYMM

BALL A1

CORNER

SEATING PLANE

BALL TYP 0.05 C

0.015 C A B

SCALE 12.000

www.ti.com

EXAMPLE BOARD LAYOUT

4X ( 0.16)

( 0.16)

METAL 0.05 MAX

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

( 0.16)

SOLDER MASK

OPENING

0.05 MIN

(0.5)

4215097/B 07/2016

DSBGA - 0.575 mm max heightYPB0004

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

SOLDER MASK DETAILS

NOT TO SCALE

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

NON-SOLDER MASK

DEFINED

(PREFERRED) SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

4X ( 0.3) (R0.05) TYP

METAL

TYP

(0.5) TYP

4215097/B 07/2016

DSBGA - 0.575 mm max heightYPB0004

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125mm THICK STENCIL

SCALE:50X

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