December 2008 Rev 4 1/25
25
STHDLS101
AC coupled HDMI level shifter
Features
■Converts low-swing alternating current (AC)
coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant
■HDMI level shifting operation up to 2.7 Gbps
per lane
■Integrated 50 Ω termination resistors for
AC-coupled differential inputs
■Input/output transition minimized differential
signaling (TMDS) enable/disable
■Output slew rate control on TMDS outputs to
minimize electromagnetic interference (EMI)
■Fail-safe outputs for backdrive protection
■No re-timing or configuration required
■Inter-pair output skew < 250 ps
■Intra-pair output skew < 10 ps
■Single power supply of 3.3 V
■ESD protection: ±6 KV HBM on all I/O pins
■Integrated display data channel (DDC) level
shifters. Pass-gate voltage limiters allow 3.3 V
termination on graphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins
■Hot-plug detect (HPD) signal level shifter from
HDMI/DVI connector
■Integrated pull-down resistor on HPD_SINK
and OE_N inputs
Applications
■Notebooks
■PC motherboards and graphic cards
■Dongles/cable adapters
Description
The STHDLS101 is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.65 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 36-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output. The
STHDLS101 supports up to 2.7 Gbps, which is
enough for 12 bits of color depth per channel, as
indicated in HDMI rev 1.3. The device operates
from a single 3.3 V supply and is available in a
48-pin QFN package.
QFN-48
(7 x 7 mm)
Table 1. Device summary
Order code Package Packing
STHDLS101QTR QFN-48 Tape and reel
www.st.com
Contents STHDLS101
2/25
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2 Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STHDLS101 Block diagram
3/25
1 Block diagram
Figure 1. STHDLS101 block diagram
System interface STHDLS101
4/25
2 System interface
Figure 2. System inferface
Figure 3. Cable adapter
Graphics chipset
(GMCH) on the
motherboard
Level shifter
STHDLS101
PCI-Express
SDVO
HDMI
HDMI output
connector
CS00374
$ONGLEOR
CABLE ADAPTER
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!-6
($-)$6)
34($,3
STHDLS101 System interface
5/25
Figure 4. DP to HDMI/DVI cable adapter
!-6
HDMI/DVI
Transmitter
PC chipset
HPD HPD_SINK
STHDLS101
HDMI/DVI Cable
Adaptor
AC_TMDS DC TMDS
DDC DDC
HDMI/DVI Connector
DP Connector
HPD_SOURCE
AC_TMDS
DDC
Pin configuration STHDLS101
6/25
3 Pin configuration
Figure 5. STHDLS101 pin configuration
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
25
26
27
28
29
30
31
32
33
34
35
36
GND
IN_D1+
IN_D2-
IN_D4+
OUT_D4+
GND
OUT_D2+
OUT_D2-
SDA_SINK
HPD_SINK
IN_D3+
VCC33
VCC33
GND
QFN-48
IN_D2+
IN_D3-
IN_D4-
FUNCTION4
FUNCTION3
VCC33
DDC_EN
OUT_D1+
VCC33
GND
SCL_SINK
GND
VCC33
OUT_D1-
GND
GND
1
2
3
4
5
6
9
7
8
10
11
12
GND
VCC33
FUNCTION2
VCC33
GND
SDA_SOURCE
FUNCTION1
SCL_SOURCE
REXT
GND
HPD_SOURCE
ANALOG2
OE_N
IN_D1-
OUT_D4-
VCC33
OUT_D3+
OUT_D3-
CS000118
STHDLS101 Pin configuration
7/25
3.1 Pin description
Table 2. Pin description
Pin
number Name Type Function
1GND PowerGround
2 VCC33 Power 3.3 V±10% DC supply
3 FUNCTION1
Vendor-specific
control or test
pins
Function pins are to enable vendor-specific features or
test modes.
For normal operation, these pins are tied to GND or
VCC33.
For consistent interoperability, GND is the preferred
default connection for these signals.
4 FUNCTION2
Vendor-specific
control or test
pins
Function pins are to enable vendor-specific features or
test modes.
For normal operation, these pins are tied to GND or
VCC33.
For consistent interoperability, GND is the preferred
default connection for these signals.
5GND PowerGround
6REXT Analog
Connection to external resistor. Resistor value
specified by device manufacturer.
Acceptable connections to this pin are:
- Resistor to GND
- Resistor to 3.3 V
- NC (direct connections to VCC or GND are through a
0Ω resistor for layout compatibility
7 HPD_SOURCE Output 0 to 3.3 V (nominal) output signal. This is level-shifted
version of the HPD_SINK signal.
8 SDA_SOURCE I/O
3.3 V DDC data I/O. Pulled-up by external termination
to 3.3 V. Connected to SDA_SINK through voltage-
limiting integrated NMOS pass-gate.
9 SCL_SOURCE Input
3.3 V DDC clock I/O. Pulled-up by external termination
to 3.3 V. Connected to SCL_SINK through voltage-
limiting integrated NMOS pass-gate.
10 ANALOG2 Analog
Analog connection determined by vendor. Acceptable
connections to this pin are:
- Resistor or capacitor to GND
- Resistor or capacitor to 3.3 V
- Short to 3.3 V or to GND
- NC
11 VCC33 Power 3.3 V ±10% DC supply
12 GND Power Ground
13 OUT_D4+ Output
HDMI 1.3 compliant TMDS output.
OUT_D4+ makes a differential output signal with
OUT_D4-.
Pin configuration STHDLS101
8/25
Pin
number Name Type Function
14 OUT_D4- Output
HDMI 1.3 compliant TMDS output.
OUT_D4- makes a differential output signal with
OUT_D4+.
15 VCC33 Power 3.3 V±10% DC supply
16 OUT_D3+ Output
HDMI 1.3 compliant TMDS output.
OUT_D3+ makes a differential output signal with
OUT_D3-.
17 OUT_D3- Output
HDMI 1.3 compliant TMDS output.
OUT_D3- makes a differential output signal with
OUT_D3+.
18 GND Power Ground
19 OUT_D2+ Output
HDMI 1.3 compliant TMDS output.
OUT_D2+ makes a differential output signal with
OUT_D2-.
20 OUT_D2- Output
HDMI 1.3 compliant TMDS output.
OUT_D2- makes a differential output signal with
OUT_D2+.
21 VCC33 Power 3.3 V±10% DC supply
22 OUT_D1+ Output HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.
23 OUT_D1- Output HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.
24 GND Power Ground
25 OE_N Input
Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables the
device when unconnected.
OE_N IN_D
termination
OUT_D
Outputs
1 High-Z High-Z
050ΩActive
26 VCC33 Power 3.3 V±10% DC supply
27 GND Power Ground
28 SCL_SINK Output
5 V DDC clock I/O. Pulled-up by external termination to
5 V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS pass-gate.
29 SDA_SINK I/O
5V DDC data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS pass-gate.
Table 2. Pin description (continued)
STHDLS101 Pin configuration
9/25
Pin
number Name Type Function
30 HPD_SINK Input
Low-frequency, 0 to 5 V (nominal) input signal. This
signal comes from the HDMI connector. Voltage high
indicates “plugged” state; voltage low indicates
“unplugged” state. HPD_SINK is pulled down by an
integrated 160 KΩ pull-down resistor.
31 GND Power Ground
32 DDC_EN Input
Enables bias voltage to the DDC pass-gate level shifter
gates. (May be implemented as a bias voltage
connection to the DDC pass-gate themselves).
DDC_EN Pass-gate
0 V Disabled
3.3 V Enabled
33 VCC33 Power 3.3 V ± 10% DC supply
34 FUNCTION3
Vendor-specific
control or test
pins
Function pins are to enable vendor-specific features or
test modes.
For normal operation, these pins are tied to GND or
VCC33.
For consistent interoperability, GND is the preferred
default connection for these signals.
35 FUNCTION4
Vendor-specific
control or test
pins
Function pins are to enable vendor-specific features or
test modes.
For normal operation, these pins are tied to GND or
VCC33.
For consistent interoperability, GND is the preferred
default connection for these signals.
36 GND Power Ground
37 GND Power Ground
38 IN_D1- Input Low-swing differential input from GMCH PCIE outputs.
IN_D1- makes a differential pair with IN_D1+.
39 IN_D1+ Input Low-swing differential input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1-.
40 VCC33 Power 3.3 V±10% DC supply
41 IN_D2- Input Low-swing differential input from GMCH PCIE outputs.
IN_D2- makes a differential pair with IN_D2+.
42 IN_D2+ Input Low-swing differential input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2-.
43 GND Power Ground
44 IN_D3- Input Low-swing differential input from GMCH PCIE outputs.
IN_D3- makes a differential pair with IN_D3+.
45 IN_D3+ Input Low-swing differential input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3-.
Table 2. Pin description (continued)
Pin configuration STHDLS101
10/25
Pin
number Name Type Function
46 VCC33 Power 3.3 V±10% DC supply
47 IN_D4- Input Low-swing differential input from GMCH PCIE outputs.
IN_D4- makes a differential pair with IN_D4+.
48 IN_D4+ Input Low-swing differential input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4-.
Table 2. Pin description (continued)
STHDLS101 Functional description
11/25
4 Functional description
This section describes the basic functionality of the STHDLS101 device.
Power supply
The STHDLS101 is powered by a single DC power supply of 3.3 V ± 10%.
Clocking
This device does not retime any data. The device contains no state machines. No inputs or
outputs of the device are latched or clocked.
Reset
This device acts as a level shifter, reset is not required.
OE_N function
When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input
termination resistors are enabled and any internal bias circuits are turned on.
The OE_N pin has an internal pull-down that enables the chip if left unconnected.
When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state.
The IN_D input buffers are disabled and the IN_D termination resistors are disabled.
Internal bias circuits for the differential inputs and outputs are turned off. Power consumption
of the chip is minimized.
The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and
SDA pass-gates are not affected by OE_N.
Table 3. OE_N description
OE_N Device state Comments
Asserted
(low level)
or unconnected
Differential input buffers and output
buffers enabled. Input impedance =
50 Ω
Normal functioning state for IN_D to
OUT_D level shifting function.
De-asserted
(high level)
Low-power state.
Differential input buffers and
terminations are disabled. Differential
input buffers are in high-impedance
state.
OUT_D level shifting outputs are
disabled. OUT_D level shifting outputs
are in a high-impedance state.
Internal bias currents are turned off.
Intended for lowest power condition
when:
• No display is plugged in or
• The level shifted data path is disabled
HPD_SINK input and HPD_SOURCE
output are not affected by OE_N.
SCL_SOURCE, SCL_SINK,
SDA_SOURCE and SDA_SINK signals
and functions are not affected by OE_N.
Functional description STHDLS101
12/25
Table 4. OE_N function
OE_N IN_Dx OUT_Dx
(TMDS outputs) Notes
De-asserted
(high level) High-Z High-Z
Device disabled.
Low power state.
Internal bias currents are
disabled.
Asserted
(low level) or
unconnected
50 Ω termination Enabled Level shifting mode
enabled.
STHDLS101 Maximum ratings
13/25
5 Maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Value Unit
VCC Supply voltage to ground potential -0.5 to +4.0 V
VIDC input voltage (TMDS and PCIe ports) -0.5 to +4.0 V
Control pins -0.5 to +4.0 V
SDA_SINK, SCL_SINK, HPD_SINK pins -0.5 to +6 V
IODC output current 120 mA
PDPower dissipation 1 W
TSTG Storage temperature -65 to +150 °C
TLLead temperature (10 sec) 300 °C
VESD
Electrostatic discharge
voltage on IOs(1)
1. In accordance with the MIL standard 883 method 3015
Human body model ±6 kV
Table 6. Thermal data
Symbol Parameter QFN-48 Unit
θJA Junction-ambient thermal coefficient 48 °C/W
Maximum ratings STHDLS101
14/25
5.1 Recommended operating conditions
5.1.1 Power supply and temperature range
5.1.2 Differential inputs (IN_D signals)
Table 7. Power supply and temperature range
Symbol Parameter Comments Min Typ Max Unit
VCC33 3.3 V power supply 3.0 3.3 3.6 V
ICC Maximum power supply current Total current from VCC
3.3 V power supply 100 mA
T Operating temperature range -40 85 oC
Table 8. Differential input characteristics for IN_D signals
Symbol Parameter Comments Min Typ Max Unit
Tbit Unit interval
Tbit is determined by the
display mode. Nominal bit
rate ranges from 250 Mbps
to 2.5 Gbps per lane.
Nominal Tbit at
2.5 Gbps = 400 ps. 360 ps
= 400 ps – 10%
360 ps
VRX-DIFFp-p
Differential input peak to peak
voltage
VRX-DIFFp-p=2*|VRX-D+ -
VRX-D-|. Applies to IN_D
signals.
0.175 1.2 V
TRX-EYE
Minimum eye width at IN_D input
pair
The level shifter may add a
maximum of 0.02UI jitter 0.8 Tbit
VCM-AC-pp
AC peak common mode input
voltage
VCM-AC-pp=|VRX-D+ +
VRX-D-|/2 – VRX-CM-DC.
VRX-CM-DC=DC(avg) of
|VRX-D+ + VRX-D-|/2
VCM-AC-pp includes all
frequencies above 30 kHz.
100 mV
ZRX-DC DC single-ended input impedance
Applies to IN_D+ as well as
IN_D- pins
(50 Ω ± 20% tolerance)
40 50 60 Ω
VRX-Bias RX input termination voltage
Intended to limit power-up
stress on chipset’s PCIE
output buffers
02V
ZRX-HIGH-Z
Single-ended input resistance for
IN_Dx when inputs are in high-Z
state
Differential inputs must be
in a high impedance state 100 KΩ
STHDLS101 Maximum ratings
15/25
5.2 TMDS outputs (OUT_D signals)
The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The
HDMI 1.3 specification is assumed to be the correct reference in instances where this
document conflicts with the HDMI 1.3 specification.
Table 9. Differential output characteristics for TMDS OUT_D signals
Symbol Parameter Comments Min Typ Max Unit
VH
Single-ended
high level output
voltage
AVCC is the DC
termination voltage in the
HDMI or DVI sink. AVCC is
nominally 3.3 V
AVCC-10 mV AVCC AVCC+10 mV V
VL
Single-ended low
level output
voltage
The open-drain output
pulls down form AVCC AVCC-600 mV AVCC-500 mV AVCC-400 mV V
VSWING
Single-ended
output swing
voltage
Swing down from TMDS
termination voltage
(3.3 V±10%)
400 mV 500 mV 600 mV V
IOFF
Single-ended
current in high-Z
state
Measured with TMDS
outputs pulled up to AVCC
max (3.6 V) through 50 Ω
resistors
10 µA
TRRise time
Maximum rise/fall time @
2.7 Gbps = 148 ps.
125 ps = 148 – 15%
125 ps 0.4 Tbit ps
TFFall time
Maximum rise/fall time @
2.7 Gbps = 148 ps.
125 ps = 148 – 15%
125 ps 0.4 Tbit ps
TSKEW-
INTRA
Intra-pair
differential skew
This differential skew
budget is in addition to the
skew presented between
D+ and D- paired input
pins.
10 ps
TSKEW-
INTER
Inter-pair lane to
lane output skew
This lane-to-lane skew
budget is in addition to the
skew between differential
input pairs.
250 ps
TJIT
Jitter added to
TMDS signals
Jitter budget for TMDS
signals as they pass
through the level shifter.
7.4 ps = 0.02 Tbit at
2.7 Gbps
7.4 ps
Maximum ratings STHDLS101
16/25
5.3 HPD input and output characteristics
Table 10. HPD_SINK input and HPS_SOURCE output
Symbol Parameter Comment Min Typ Max Unit
VIH-HPD_SINK HPD_SINK input high level Low speed input changes
state on cable plug/unplug 25.05.3V
VIL-HPD_SINK HPD_SINK input low level 0 0.8 V
IIN-HPD_SINK
HPD_SINK input leakage
current
Measured with HPD_SINK
at VIH-HPD max and VIL-
HPD min
50 µA
VOH-
HPD_SOURCE
HPD_SOURCE output high
level VCC = 3.3 V±10% 2.5 VCC V
VOL-
HPD_SOURCE
HPD_SOURCE output low level 0 0.02 V
THPD
HPD_SINK to HPD_SOURCE
propagation delay
Time from HPD_SINK
changing state to
HPD_SOURCE changing
state. Includes
HPD_SOURCE rise/fall
time
CL=10pF
200 ns
TRF-HPD HPD_SOURCE rise/fall time
Time required to transition
from
VOH-HPD_SOURCE to VOL-
HPD_SOURCE or from VOL-
HPD_SOURCE to VOH-
HPD_SOURCE
CL=10 pF
120ns
STHDLS101 Maximum ratings
17/25
5.4 DDC input and output chatacteristics
Table 11. SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics
Symb
ol Parameter Comment Min Typ Max Unit
VIInput voltage on SDA_SINK, SCL_SINK pins Voltage on the DDC pins on
connector end 05.5V
ILKG
Input leakage current on SDA_SINK, SCL_SINK
pins
VCC =3.3V
VI=0.1V
DD to 0.9 VDD to
isolated DDC inputs
VDD = external pull-up
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
-10 10 µA
IOFF
Power-down leakage current on SDA_SINK,
SCL_SINK pins
VCC =0.0V
VI=0.1V
DD to 0.9 VDD to
DDC sink inputs
VDD = external pull-up
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
SDA_SOURCE,
SCL_SOURCE = 0.0 V
-10 10 µA
CI/O Input/output capacitance (switch off) VI(pp) =1V, 100KHz
VCC = 3.3 V, T = 25 °C5pF
CI/O Input/output capacitance (switch on) VI(pp) =1V, 100KHz
VCC = 3.3 V, T = 25 °C10 pF
RON Switch resistance IO=3 mA, VO=0.4V
VCC =3.3V 27 40 Ω
TPD DDC_SINK to DDC_SOURCE propagation delay
Time from DDC_SINK
changing state to
DDC_SOURCE changing
state while the pass gate is
enabled.
CL=10 pF
RPU=1.5 K (min), 2.0 K
(max)
815ns
TSX
Switch time from DDC_EN to the valid state on
DDC_SOURCE
CL=10pF
RPU = 1.5 K (min), 2.0 K
(max)
815ns
Maximum ratings STHDLS101
18/25
5.5 OE_ input characteristics
5.6 HPD input resistor
5.7 ESD performance
Table 12. OE_N input characteristics
Symbol Parameter Comment Min Typ Max Unit
VIH-OE_N Input high level 2 VCC33 V
VIL-OE_N Input low level 0 0.8 V
IIN-OE_N Input leakage current
Measured with OE_N at
VIH-OE_N max and
VIL-OE_N mix
200 µA
Table 13. HDP input resistor
Symbol Parameter Comment Min Typ Max Unit
RHPD HPD_SINK input pull-down resistor
Guarantees HPD_SINK is
LOW when no display is
plugged in
130 K 160 K 190 K Ω
Table 14. ESD performance
Symbol Parameter Test condition Min Typ Max Unit
ESD MIL STD 883 method 3015 (all pins) Human body model
(HBM) -6 +6 kV
STHDLS101 Application information
19/25
6 Application information
6.1 Power supply sequencing
A proper power supply sequencing is advised for all CMOS devices. It is
recommended to always apply VCC before applying any signals to the input/output
or control pins.
6.2 Supply bypassing
Bypass each of the VCC pins with 0.1µF and 1nF capacitors in parallel as close to the device
as possible, with the smaller valued capacitor as close to the VCC pin of the device as
possible.
6.3 Differential traces
The high-speed inputs and TMDS outputs are the most critical parts for the device. There
are several considerations to minimize discontinuities on these transmission lines between
the connectors and the device.
a) Maintain 100 Ω differential transmission line impedance into and out of the device.
b) Keep an uninterrupted ground plane below the high-speed I/Os.
c) Keep the ground-path vias to the device as close as possible to allow the shortest
return current path.
d) Layout of the TMDS differential outputs should be with the shortest stubs from the
connectors.
Output trace characteristics affect the performance of the STHDLS101. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 °C turns and minimize the number of vias to further
prevent impedance discontinuities.
Package mechanical data STHDLS101
20/25
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
STHDLS101 Package mechanical data
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Figure 6. QFN-48 (7 x 7 mm) package outline
Package mechanical data STHDLS101
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Figure 7. QFN-48 tape information
Table 15. QFN-48 (7 x 7 mm) package mechanical data
Symbol
Millimeters Inches
Min Typ Max Min Typ Max
A 0.80 0.90 1.00 0.80 0.85 1.00
A1 0.02 0.05 0.01 0.05
A2 0.65 1.00 0.65
A3 0.25 0.20
b 0.18 0.23 0.30 0.18 0.23 0.30
D 6.85 7.00 7.15 6.90 7.00 7.10
D2 2.25 4.70 5.25 See exposed pad variations
E 6.85 7.00 7.15 6.90 7.00 7.10
E2 2.25 4.70 5.25 See exposed pad variations
e 0.45 0.50 0.55 0.45 0.50 0.55
L 0.30 0.40 0.50 0.30 0.40 0.50
ddd 0.08 0.08
STHDLS101 Package mechanical data
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Figure 8. Reel information
Table 16. Reel mechanical data (dimensions in mm)
ACNT
330.2 13 ±0.25 100 16.4
0084694_J
Revision history STHDLS101
24/25
8 Revision history
Table 17. Document revision history
Date Revision Changes
15-Apr-2008 1 Initial release.
23-Apr-2008 2 Modified: Figure 5.
10-Jun-2008 3 Document status promoted from preliminary data to datasheet.
01-Dec-2008 4
Updated: Features section, Table 2: Pin description on page 7 and
Chapter 4 and Chapter 5: Maximum ratings on page 13.
Added: Figure 3: Cable adapter on page 4, Figure 4: DP to
HDMI/DVI cable adapter on page 5, Figure 8: Reel information on
page 23 and Table 16: Reel mechanical data (dimensions in mm) on
page 23.
STHDLS101
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