VNQ7140AJ Quad channel high-side driver with MultiSense analog feedback for automotive applications Datasheet - production data - - - Loss of ground and loss of VCC Reverse battery with external components Electrostatic discharge protection Applications * Features Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 140 m Current limitation (typ) ILIMH 12 A Stand-by current (max) ISTBY 0.5 A * * * * Automotive qualified General - Quad channel smart high-side driver with MultiSense analog feedback - Very low standby current - Compatible with 3 V and 5 V CMOS outputs MultiSense diagnostic functions - Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature - Overload and short to ground (power limitation) indication - Thermal shutdown indication - OFF-state open-load detection - Output short to VCC detection - Sense enable/disable Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin May 2015 * All types of automotive resistive, inductive and capacitive loads Specially intended for automotive signal lamps (up to R10W or LED Rear Combinations) Description The device is a quad channel high-side driver manufactured using ST proprietary VIPower(R) technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices DocID027404 Rev 1 This is information on a product in full production. 1/46 www.st.com Contents VNQ7140AJ Contents 1 Block diagram and pin description ................................................ 5 2 Electrical specification.................................................................... 7 3 4 2.1 Absolute maximum ratings ................................................................ 7 2.2 Thermal data ..................................................................................... 8 2.3 Main electrical characteristics ........................................................... 8 2.4 Waveforms ...................................................................................... 20 2.5 Electrical characteristics curves ...................................................... 22 Protections..................................................................................... 26 3.1 Power limitation ............................................................................... 26 3.2 Thermal shutdown........................................................................... 26 3.3 Current limitation ............................................................................. 26 3.4 Negative voltage clamp ................................................................... 26 Application information ................................................................ 27 4.1 GND protection network against reverse battery............................. 27 4.1.1 Diode (DGND) in the ground line ..................................................... 28 4.2 Immunity against transient electrical disturbances .......................... 28 4.3 MCU I/Os protection........................................................................ 28 4.4 Multisense - analog current sense .................................................. 29 4.4.1 Principle of Multisense signal generation ......................................... 30 4.4.2 TCASE and VCC monitor ................................................................. 32 4.4.3 Short to VCC and OFF-state open-load detection ........................... 33 5 Maximum demagnetization energy (VCC = 16 V) ........................ 35 6 Package and PCB thermal data .................................................... 36 6.1 7 PowerSSO-16 thermal data ............................................................ 36 Package information ..................................................................... 39 7.1 PowerSSO-16 package information ................................................ 39 7.2 PowerSSO-16 packing information ................................................. 41 7.3 PowerSSO-16 marking information ................................................. 43 8 Order codes ................................................................................... 44 9 Revision history ............................................................................ 45 2/46 DocID027404 Rev 1 VNQ7140AJ List of tables List of tables Table 1: Pin functions ................................................................................................................................. 5 Table 2: Suggested connections for unused and not connected pins ........................................................ 6 Table 3: Absolute maximum ratings ........................................................................................................... 7 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Power section ............................................................................................................................... 8 Table 6: Switching....................................................................................................................................... 9 Table 7: Logic inputs ................................................................................................................................. 10 Table 8: Protections .................................................................................................................................. 10 Table 9: MultiSense .................................................................................................................................. 11 Table 10: Truth table ................................................................................................................................. 19 Table 11: MultiSense multiplexer addressing ........................................................................................... 19 Table 12: ISO 7637-2 - electrical transient conduction along supply line................................................. 28 Table 13: MultiSense pin levels in off-state .............................................................................................. 32 Table 14: PCB properties ......................................................................................................................... 36 Table 15: Thermal parameters ................................................................................................................. 38 Table 16: PowerSSO-16 mechanical data................................................................................................ 39 Table 17: Reel dimensions ....................................................................................................................... 41 Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 42 Table 19: Device summary ....................................................................................................................... 44 Table 20: Document revision history ........................................................................................................ 45 DocID027404 Rev 1 3/46 List of figures VNQ7140AJ List of figures Figure 1: Block diagram .............................................................................................................................. 5 Figure 2: Configuration diagram (top view)................................................................................................. 6 Figure 3: Current and voltage conventions ................................................................................................. 7 Figure 4: IOUT/ISENSE versus IOUT....................................................................................................... 16 Figure 5: Current sense precision vs. IOUT ............................................................................................. 16 Figure 6: Switching time and Pulse skew ................................................................................................. 17 Figure 7: MultiSense timings (current sense mode) ................................................................................. 17 Figure 8: Multisense timings (chip temperature and VCC sense mode) .................................................. 18 Figure 9: TDSKON .................................................................................................................................... 18 Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ...................... 20 Figure 11: Latch functionality - behavior in hard short circuit condition.................................................... 20 Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 21 Figure 13: Standby mode activation ......................................................................................................... 21 Figure 14: Standby state diagram ............................................................................................................. 22 Figure 15: OFF-state output current ......................................................................................................... 22 Figure 16: Standby current ....................................................................................................................... 22 Figure 17: IGND(ON) vs. Tcase ............................................................................................................... 23 Figure 18: Logic Input high level voltage .................................................................................................. 23 Figure 19: Logic Input low level voltage.................................................................................................... 23 Figure 20: High level logic input current ................................................................................................... 23 Figure 21: Low level logic input current .................................................................................................... 23 Figure 22: Logic Input hysteresis voltage ................................................................................................. 23 Figure 23: FaultRST Input clamp voltage ................................................................................................. 24 Figure 24: Undervoltage shutdown ........................................................................................................... 24 Figure 25: On-state resistance vs. Tcase ................................................................................................. 24 Figure 26: On-state resistance vs. VCC ................................................................................................... 24 Figure 27: Turn-on voltage slope .............................................................................................................. 24 Figure 28: Turn-off voltage slope .............................................................................................................. 24 Figure 29: Won vs. Tcase ......................................................................................................................... 25 Figure 30: Woff vs. Tcase ......................................................................................................................... 25 Figure 31: ILIMH vs. Tcase ....................................................................................................................... 25 Figure 32: OFF-state open-load voltage detection threshold ................................................................... 25 Figure 33: Vsense clamp vs. Tcase.......................................................................................................... 25 Figure 34: Vsenseh vs. Tcase .................................................................................................................. 25 Figure 35: Application diagram ................................................................................................................. 27 Figure 36: Simplified internal structure ..................................................................................................... 27 Figure 37: MultiSense and diagnostic - block diagram ............................................................................ 29 Figure 38: MultiSense block diagram ....................................................................................................... 30 Figure 39: Analogue HSD - open-load detection in off-state ................................................................... 31 Figure 40: Open-load / short to VCC condition ......................................................................................... 32 Figure 41: GND voltage shift .................................................................................................................... 33 Figure 42: Maximum turn off current versus inductance .......................................................................... 35 Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 36 Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 36 Figure 45: PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition ......................... 37 Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse .......................................... 37 Figure 47: Thermal fitting model for PowerSSO-16 .................................................................................. 38 Figure 48: PowerSSO-16 package dimensions ........................................................................................ 39 Figure 49: PowerSSO-16 reel 13" ............................................................................................................ 41 Figure 50: PowerSSO-16 carrier tape ...................................................................................................... 42 Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape .................................................. 42 Figure 52: PowerSSO-16 marking information ......................................................................................... 43 4/46 DocID027404 Rev 1 VNQ7140AJ Block diagram and pin description Figure 1: Block diagram VCC Internal supply VCC- GND Clamp Channel 3 Undervoltage shut-down Channel 2 CH 3 Channel 1 CH 2 Control & Diagnostic Channel 0 CH 1 FaultRST INPUT3 VCC - OUT Clamp INPUT2 CH 0 INPUT1 OUTPUT3 OUTPUT2 INPUT0 Gate Driver SEL2 T VCC OUTPUT1 VON Limitation SEL1 SEL0 Current Limitation SEn MUX 1 Block diagram and pin description Multisense 0 Power Limitation Overtemperature T Short to VCC Open-Load in OFF Current Sense Fault VSENSEH GND OUTPUT0 GAPGCFT00378 Table 1: Pin functions Name VCC OUTPUT0,1,2,3 GND Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode / resistor network. INPUT0,1,2,3 Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state. MultiSense Multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. SEn SEL0,1,2 FaultRST Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin. Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer. Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode. DocID027404 Rev 1 5/46 Block diagram and pin description VNQ7140AJ Figure 2: Configuration diagram (top view) PowerSSO-16 OUTPUT0 1 16 OUTPUT3 SEn 2 15 SEL1 INPUT0 3 14 INPUT3 GND 4 13 MultiSense FaultRS T 5 12 SEL0 INPUT1 6 11 INPUT2 N.C. 7 10 SEL2 OUTPUT1 8 9 OUTPUT2 TAB = V CC GAPGCFT00379 Table 2: Suggested connections for unused and not connected pins SEn, SELx, Connection / pin MultiSense N.C. Output Input Floating Not allowed X (1) X X To ground Through 1 k resistor X Not allowed Notes: (1)X: 6/46 do not care. DocID027404 Rev 1 FaultRST X Through 15 k Through 15 k resistor resistor VNQ7140AJ 2 Electrical specification Electrical specification Figure 3: Current and voltage conventions IS VCC FaultRST OUTPUT0,1,2,3 VSEn IOUT VOUT ISENSE SEn ISEL MultiSense SEL0,1,2 VSEL VFR ISEn VCC VFn IFR VSENSE IIN V IN INPUT0,1,2,3 IGND GAPGCFT00380 VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40V; RL = 4 ) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V -IGND DC reverse ground pin current 200 mA IOUT OUTPUT0,1,2,3 DC output current Internally limited A -IOUT Reverse DC output current IIN INPUT0,1,2,3 DC input current ISEn SEn DC input current ISEL SEL0,1,2 DC input current IFR FaultRST DC input current VFR FaultRST DC input voltage DocID027404 Rev 1 V 4 -1 to 10 mA 7.5 V 7/46 Electrical specification VNQ7140AJ Symbol Value Unit MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 MultiSense pin DC output current in reverse (VCC < 0 V) -20 EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 C) 10 mJ VESD Electrostatic discharge (JEDEC 22A-114F) * INPUT0,1,2,3 * MultiSense * SEn, SEL0,1,2, FaultRST * OUTPUT0,1,2,3 * VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V ISENSE Tj Tstg 2.2 Parameter mA Junction operating temperature -40 to 150 Storage temperature -55 to 150 C Thermal data Table 4: Thermal data Symbol Parameter Typ. value Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) Rthj-amb Rthj-amb (1)(2) Unit 7.7 Thermal resistance junction-ambient (JEDEC JESD 51-5) (1)(3) 61 Thermal resistance junction-ambient (JEDEC JESD 51-7) (1)(2) 26.8 C/W Notes: (1)One 2.3 channel ON. (2)Device mounted on four-layers 2s2p PCB. (3)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace. Main electrical characteristics 7 V < VCC < 28 V; -40C < Tj < 150C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. Table 5: Power section Symbol Parameter Test conditions VCC Operating supply voltage VUSD Undervoltage shutdown Min. Typ. Max. Unit 4 13 4 5 V IOUT = 1 A; Tj = 150C 280 m IOUT = 1 A; VCC = 4 V; Tj = 25C 210 VUSDReset Undervoltage shutdown reset VUSDhyst Undervoltage shutdown hysteresis 0.3 IOUT = 1 A; Tj = 25C RON 8/46 On-state resistance (1) 28 DocID027404 Rev 1 140 VNQ7140AJ Electrical specification Symbol Parameter Vclamp Test conditions Clamp voltage Supply current in standby at VCC = 13 V (2) ISTBY tD_STBY IS(ON) 38 IS = 20 mA; 25C < Tj < 150C 41 46 V 0.5 A VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1,2 = 0 V; Tj = 85C (3) 0.5 A VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1,2 = 0 V; Tj = 125C 3 A 300 550 s 10 16 mA 20 mA Supply current VCC = 13 V; VSEn = VFR = VSEL0,1,2 = 0 V; VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0 A 60 VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1,2 = 0 V; VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 1 A VIN = VOUT = 0 V; VCC = 13 V; Tj = 25C 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125C 0 0.01 0.5 A 3 Output - VCC diode voltage (1) IOUT = -1 A; Tj = 150C VF 52 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1,2 = 0 V; Tj = 25C VCC = 13 V; VIN = VOUT = VFR = VSEL0,1,2 = 0 V; VSEn = 5 V to 0 V Off-state output current at VCC = 13 V(1) IL(off) IS = 20 mA; Tj = -40C Standby mode blanking time Control stage current IGND(ON) consumption in ON state. All channels active. Min. Typ. Max. Unit 0.7 V Notes: (1)For each channel. (2)PowerMOS (3)Parameter leakage included. specified by design; not subject to production test. Table 6: Switching VCC = 13 V; -40C < Tj < 150C, unless otherwise specified Symbol Parameter td(on)(1) Turn-on delay time at Tj = 25C td(off)(1) Turn-off delay time at Tj = 25C (dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25C (dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25C WON WOFF tSKEW (1) Test conditions Min. Typ. RL = 13 RL = 13 Max. Unit 10 70 120 10 40 100 0.1 0.29 0.7 0.1 0.35 0.7 -- 0.15 0.2 (2) mJ (2) mJ Switching energy losses at turn-on (twon) RL = 13 Switching energy losses at turn-off (twoff) RL = 13 -- 0.1 0.18 Differential Pulse skew (tPHL- tPLH) RL = 13 -90 -40 10 s V/s s Notes: (1)See Figure 6: "Switching time and Pulse skew" (2)Parameter guaranteed by design and characterization; not subject to production test. DocID027404 Rev 1 9/46 Electrical specification VNQ7140AJ Table 7: Logic inputs 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V INPUT0,1,2,3 characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V 5.3 IIN = -1 mA A 7.2 -0.7 V FaultRST characteristics VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V V 5.3 IIN = -1 mA A 7.5 -0.7 V SEL0,1,2 characteristics (7 V < VCC < 18 V) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V V 5.3 IIN = -1 mA A 7.2 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage A V 5.3 IIN = -1 mA V 7.2 -0.7 V Table 8: Protections 7 V < VCC < 18 V; -40C < Tj < 150C 10/46 Symbol Parameter Test conditions ILIMH DC short circuit current VCC = 13 V 4 V < VCC < 18 V DocID027404 Rev 1 (1) Min. Typ. Max. 8 12 16 16 Unit A VNQ7140AJ Electrical specification 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions ILIML Short circuit current during thermal cycling TTSD Shutdown temperature Reset temperature TRS Thermal reset of fault diagnostic indication Thermal hysteresis (TTSD - TR)(1) TJ_SD Dynamic temperature Tj = -40C; VCC = 13 V Fault reset time for output unlatch VFR = 5 V to 0 V; VSEn = 5 V * E.g. Ch0 VIN0 = 5 V; VSEL0,1,2 = 0 V Output voltage drop limitation VON Unit 150 175 200 TRS + 1 TRS + 7 C 135 7 IOUT= 1 A; L = 6 mH; Turn-off output voltage Tj = -40C clamp IOUT= 1 A; L = 6 mH; Tj = 25C to 150C VDEMAG Max. 4 VFR = 0 V; VSEn = 5 V THYST tLATCH_RST(1) Typ. VCC = 13 V; TR < Tj < TTSD (1) TR Min. 60 3 K 10 20 s VCC - 38 V VCC - 41 VCC - 46 VCC - 52 V 20 mV IOUT = 0.07 A Notes: (1)Parameter guaranteed by design and characterization; not subject to production test. Table 9: MultiSense 7 V < VCC < 18 V; -40C < Tj < 150C Symbol VSENSE_CL Parameter MultiSense clamp voltage Test conditions VSEn = 0 V; ISENSE = 1 mA Min. Typ. Max. Unit -17 -12 VSEn = 0 V; ISENSE = -1 mA 7 V Current Sense characteristics KOL dKcal/Kcal(1)(2) KLED dKLED/KLED(1)(2) K0 dK0/K0(1)(2) IOUT = 0.01 A; VSENSE = 0.5 V; VSEn = 5 V 330 Current sense ratio IOUT = 0.01 A to 0.025 A; Ical = 17.5 mA; VSENSE = 0.5 V; drift at calibration VSEn = 5 V point -30 IOUT = 0.025 A; VSENSE = 0.5 V; VSEn = 5 V 330 Current sense ratio IOUT = 0.025 A; VSENSE = 0.5 V; drift VSEn = 5 V -25 IOUT = 0.070 A; VSENSE = 0.5 V; VSEn = 5 V 375 Current sense ratio IOUT = 0.070 A; VSENSE = 0.5 V; drift VSEn = 5 V -20 IOUT/ISENSE IOUT/ISENSE IOUT/ISENSE DocID027404 Rev 1 30 580 830 25 550 % % 720 20 % 11/46 Electrical specification VNQ7140AJ 7 V < VCC < 18 V; -40C < Tj < 150C Symbol K1 dK1/K1(1)(2) K2 dK2/K2(1)(2) K3 dK3/K3(1)(2) Parameter Min. Typ. Max. Unit IOUT = 0.15 A; VSENSE = 4 V; VSEn = 5 V 365 520 Current sense ratio IOUT = 0.15 A; VSENSE = 4 V; drift VSEn = 5 V -15 IOUT/ISENSE Test conditions IOUT = 0.7 A; VSENSE = 4 V; VSEn = 5 V 380 Current sense ratio IOUT = 0.7 A; VSENSE = 4 V; drift VSEn = 5 V -10 IOUT/ISENSE 420 IOUT/ISENSE IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V Current sense ratio IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V drift MultiSense disabled: VSEn = 0 V MultiSense disabled: -1 V < VSENSE < 5 V(1) ISENSE0 MultiSense enabled: VSEn = 5 V All channels ON; IOUTX = 0 A; ChX diagnostic selected: * E.g. Ch0: MultiSense leakage VIN0,1,2,3 = 5 V; VSEL0 = 0 V; current VSEL1,2 = 0 V; IOUT0 = 0 A; IOUT1,2,3 = 1 A MultiSense enabled: VSEn = 5 V; ChX OFF; ChX diagnostic selected: * E.g. Ch0: VIN0 = 0 V; VIN1,2,3 = 0 V; VSEL0 = 5V; VSEL1,2 = 0 V; IOUT1,2,3 = 1 A 675 15 475 570 10 470 % % 520 -5 5 0 0.5 -0.5 0.5 0 2 % A 0 2 VOUT_MSD(1) Output Voltage for MultiSense shutdown VSEn = 5 V; RSENSE = 2.7 k * E.g. Ch0: VIN0 = 5 V; VSEL0,1,2 = 0 V; IOUT0 = 1 A VSENSE_SAT MultiSense saturation voltage VCC = 7 V; RSENSE = 2.7 k; VSEn = 5 V; VIN0 = 5 V; VSEL0,1,2 = 0 V; IOUT0 = 2 A; Tj = 150C 5 V ISENSE_SAT(1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0,1,2 = 0 V; Tj = 150C 4 mA Output saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0,1,2 = 0 V; Tj = 150C 2.2 A IOUT_SAT(1) 5 V OFF-state diagnostic VOL 12/46 VSEn = 5 V; ChX OFF; ChX OFF-state opendiagnostic selected load voltage * E.g: Ch0 detection threshold VIN0 = 0 V; VSEL0,1,2 = 0 V DocID027404 Rev 1 2 3 4 V VNQ7140AJ Electrical specification 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit -15 A 700 s 60 s 30 s IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL; Tj = -40C to 125C -100 tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 9: "TDSKON") VSEn = 5 V; ChX ON to OFF transition; ChX diagnostic selected: * E.g: Ch0 VIN0 = 5 V to 0 V; VSEL0,1,2 = 0 V; VOUT0 = 4 V; IOUT0 = 0 A 100 tD_OL_V Settling time for valid OFF-state open load diagnostic indication from rising edge of SEn VIN0,1,2,3 = 0 V; VFR = 0 V; VSEL0,1,2 = 0 V; VOUT0 = 4 V; VSEn = 0 V to 5 V tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VSEn = 5 V; ChX OFF; ChX diagnostic selected: * E.g: Ch0 VIN0 = 0 V; VSEL0,1,2 = 0 V; VOUT0 = 0 V to 4 V 350 5 Chip temperature analog feedback VSEn = 5 V; VSEL0 = 0 V; VSEL1,2 = 5 V; VIN0,1,2,3 = 0 V; RSENSE = 1 k; Tj = -40C VSENSE_TC dVSENSE_TC/dT(1) MultiSense output VSEn = 5 V; VSEL0 = 0 V; voltage proportional VSEL1,2 = 5 V; VIN0,1,2,3 = 0 V; to chip temperature RSENSE = 1 k; Tj = 25C all channels off VSEn = 5 V; VSEL0 = 0 V; VSEL1,2 = 5 V; VIN0,1,2,3 = 0 V; RSENSE = 1 k; Tj = 125C Temperature coefficient 2.325 2.41 2.495 V 1.985 2.07 2.155 V 1.435 1.52 1.605 V -5.5 mV/ K Tj = -40 C to 150 C Transfer function VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) VCC supply voltage analog feedback VSENSE_VCC MultiSense output VCC = 13 V; VSEn = 5 V; voltage proportional VIN0,1,2,3 = 0 V; VSEL0,1,2 = 5 V; to VCC supply RSENSE = 1 k voltage Transfer function (3) 3.16 3.23 3.3 V 6.6 V VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10: "Truth table") VSENSEH MultiSense output voltage in fault condition VCC = 13 V; RSENSE = 1 k * E.g: Ch0 in open load VIN0 = 0 V; VSEn = 5 V; VSEL0,1,2 = 0 V; IOUT0 = 0 A; VOUT0 = 4 V DocID027404 Rev 1 5 13/46 Electrical specification VNQ7140AJ 7 V < VCC < 18 V; -40C < Tj < 150C Symbol ISENSEH Parameter MultiSense output current in fault condition Test conditions VCC = 13 V; VSENSE = 5 V Min. 7 Typ. Max. Unit 20 30 mA MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense mode)")(4) tDSENSE1H Current sense settling time from rising edge of SEn tDSENSE1L Current sense disable delay time VIN = 5 V; VSEn = 0 V to 5 V; from falling edge of RSENSE = 1 k; RL = 13 SEn tDSENSE2H Current sense settling time from rising edge of INPUT tDSENSE2H tDSENSE2L VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 k; RL = 13 VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 k; RL = 13 60 s 5 20 s 100 250 s 100 s 250 s Current sense settling time from VIN = 5 V; VSEn = 5 V; rising edge of IOUT RSENSE = 1 k; ISENSE = 90 % of (dynamic response ISENSEMAX; RL = 13 to a step change of IOUT) Current sense turnoff delay time from VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 k; RL = 13 falling edge of INPUT 50 MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE3H VSENSE_TC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 0 V; VSEL1,2 = 5 V; RSENSE = 1 k 60 s tDSENSE3L VSENSE_TC disable VSEn = 5 V to 0 V; VSEL0 = 0 V; delay time from VSEL1,2 = 5 V; RSENSE = 1 k falling edge of SEn 20 s MultiSense timings (VCC voltage sense mode - see Figure 8: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE4H VSENSE_VCC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0,1,2 = 5 V; RSENSE = 1 k 60 s tDSENSE4L VSENSE_VCC disable VSEn = 5 V to 0 V; VSEL0,1,2 = 5 V; delay time from RSENSE = 1 k falling edge of SEn 20 s 20 s MultiSense timings (multiplexer transition times)(4) tD_XtoY 14/46 MultiSense transition delay from ChX to ChY VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V; VSEL1,2 = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 0 A; IOUT1 = 1A; RSENSE = 1 k DocID027404 Rev 1 VNQ7140AJ Electrical specification 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit tD_CStoTC MultiSense transition delay from current sense to TC sense VIN0 = 5 V; VSEn = 5 V; VSEL0,1 = 0 V; VSEL2 = 0 V to 5 V; IOUT0 = 0.5 A; RSENSE = 1 k 60 s tD_TCtoCS MultiSense transition delay fromTC sense to current sense VIN0 = 5 V; VSEn = 5 V; VSEL0,1 = 0 V; VSEL2 = 5 V to 0 V; IOUT0 = 0.5 A; RSENSE = 1 k 20 s tD_CStoVCC MultiSense transition delay from current sense to VCC sense VIN3 = 5 V; VSEn = 5 V; VSEL0,1 = 5 V; VSEL2 = 0 V to 5 V; IOUT3 = 0.5 A; RSENSE = 1 k 60 s tD_VCCtoCS MultiSense transition delay from VCC sense to current sense to VIN3 = 5 V; VSEn = 5 V; VSEL0,1 = 5 V; VSEL2 = 5 V to 0 V; IOUT3 = 0.5 A; RSENSE = 1 k 20 s tD_TCtoVCC MultiSense transition delay from TC sense to VCC sense VCC = 13 V; Tj = 125C; VSEn = 5 V; VSEL1,2 = 5 V; VSEL0 = 0 V to 5 V; RSENSE = 1 k 20 s tD_VCCtoTC MultiSense transition delay from VCC sense to TC sense VCC = 13 V; Tj = 125C; VSEn = 5 V; VSEL1,2 = 5 V; VSEL0 = 5 V to 0 V; RSENSE = 1 k 20 s tD_CStoVSENSEH MultiSense transition delay from stable current sense on ChX to VSENSEH on ChY VIN0 = 5 V; VIN1 = 0 V; VSEn = 5 V; VSEL1,2 = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 1 A; VOUT1 = 4 V; RSENSE = 1 k 20 s Notes: (1)Parameter (2)All (3)V specified by design; not subject to production test. values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. CC sensing and TC sensing are referred to GND potential. (4)Transition delays are measured up to +/- 10% of final conditions. DocID027404 Rev 1 15/46 Electrical specification VNQ7140AJ Figure 4: IOUT/ISENSE versus IOUT Figure 5: Current sense precision vs. IOUT 16/46 DocID027404 Rev 1 VNQ7140AJ Electrical specification Figure 6: Switching time and Pulse skew twoff twon VOUT Vcc 80% Vcc ON OFF dVOUT/dt dVOUT/dt 20% Vcc t INPUT td(off) td(on) tpHL tpLH t GAPGCFT00797 Figure 7: MultiSense timings (current sense mode) IN1 High SEn Low High SEL0 Low High SEL1 Low High SEL2 Low IOUT1 Current Sense tDSENSE 2H tDSENSE 1L tDSENSE 1H tDSENSE 2L GAPGCFT00432 DocID027404 Rev 1 17/46 Electrical specification VNQ7140AJ Figure 8: Multisense timings (chip temperature and VCC sense mode) High SEn Low High SEL0 Low High SEL1 Low High SEL2 Low VCC VSENS E = VSENSE _VC C VSENS E = VSENSE _TC M ultiSense tDS ENSE 4H tDS ENSE 4L VCC VOLTAGE SENSE MODE tDSENSE3 H tDSENSE3 L CHIP TEMPERATURE SENSE MODE GAPGCFT00816 Figure 9: TDSKON VINPU T VOU T VOU T > VOL MultiSense TDSTKON GAPG2609141140CFT 18/46 DocID027404 Rev 1 VNQ7140AJ Electrical specification Table 10: Truth table Mode Conditions All logic inputs low Standby L L L X H L H Overload or short L to GND causing: H Tj > TTSD or Tj > Tj_SD H Nominal load connected; Tj < 150C Normal Overload Under-voltage OFF-state diagnostics INX FR SEn SELX OUTX MultiSense Hi-Z L See (1) H See (1) Outputs configured for auto-restart H H See (1) Outputs configured for Latch-off X L See (1) L H See (1) Output cycles with temperature hysteresis H L See (1) Output latches-off L L Hi-Z Hi-Z Re-start when VCC > VUSD + VUSDhyst (rising) H See (1) H See (1) <0V See (1) X X Short to VCC L X Open-load L X L X Negative Inductive loads output voltage turn-off L Low quiescent current consumption L VCC < VUSD (falling) L Comments See (1) X X See (1) See (1) External pull-up Notes: (1)Refer to Table 11: "MultiSense multiplexer addressing" Table 11: MultiSense multiplexer addressing MultiSense output SEn SEL2 SEL1 SEL0 MUXchannel Nomal mode Overload OFF-state Negative diag. (1)(2)(3) output L X X X Hi-Z H L L L Channel 0 diagnostic ISENSE = 1/K * IOUT0 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L L H Channel 1 diagnostic ISENSE = 1/K * IOUT1 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H L Channel 2 diagnostic ISENSE = 1/K * IOUT2 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H H Channel 3 diagnostic ISENSE = 1/K * IOUT3 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H L L TCHIP Sense VSENSE = VSENSE_TC H H L H VCC Sense VSENSE = VSENSE_VCC H H H L TCHIP Sense VSENSE = VSENSE_TC H H H H VCC Sense VSENSE = VSENSE_VCC Notes: (1) In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic. (2) Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0 (3) Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH DocID027404 Rev 1 19/46 Electrical specification 2.4 VNQ7140AJ Waveforms Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) Figure 11: Latch functionality - behavior in hard short circuit condition 20/46 DocID027404 Rev 1 VNQ7140AJ Electrical specification Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) Figure 13: Standby mode activation DocID027404 Rev 1 21/46 Electrical specification VNQ7140AJ Figure 14: Standby state diagram 2.5 Electrical characteristics curves Figure 15: OFF-state output current 22/46 DocID027404 Rev 1 Figure 16: Standby current VNQ7140AJ Electrical specification Figure 17: IGND(ON) vs. Tcase Figure 18: Logic Input high level voltage Figure 20: High level logic input current Figure 19: Logic Input low level voltage Figure 21: Low level logic input current Figure 22: Logic Input hysteresis voltage DocID027404 Rev 1 23/46 Electrical specification VNQ7140AJ Figure 23: FaultRST Input clamp voltage Figure 24: Undervoltage shutdown VUSD [V] 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 T [C] 24/46 100 125 150 175 GAPGRI00399 Figure 25: On-state resistance vs. Tcase Figure 26: On-state resistance vs. VCC Figure 27: Turn-on voltage slope Figure 28: Turn-off voltage slope DocID027404 Rev 1 VNQ7140AJ Electrical specification Figure 29: Won vs. Tcase Figure 30: Woff vs. Tcase Figure 31: ILIMH vs. Tcase Figure 32: OFF-state open-load voltage detection threshold Figure 33: Vsense clamp vs. Tcase Figure 34: Vsenseh vs. Tcase DocID027404 Rev 1 25/46 Protections VNQ7140AJ 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing Tj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as Tj exceeds the safety level of Tj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. 26/46 DocID027404 Rev 1 VNQ7140AJ 4 Application information Application information Figure 35: Application diagram 4.1 GND protection network against reverse battery Figure 36: Simplified internal structure DocID027404 Rev 1 27/46 Application information 4.1.1 VNQ7140AJ Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12: "ISO 7637-2 electrical transient conduction along supply line". Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". Table 12: ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) 1 III -112V 500 pulses 0,5 s 2a III +55V 500 pulses 0,2 s 5s 50s, 2 3a IV -220V 1h 90 ms 100 ms 0.1s, 50 3b IV +150V 1h 90 ms 100 ms 0.1s, 50 IV -7V 1 pulse 4 (2) min max 2ms, 10 100ms, 0.01 Load dump according to ISO 16750-2:2010 Test B (3) 40V 5 pulse 1 min 400ms, 2 Notes: (1)U S 4.3 is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. (2)Test pulse from ISO 7637-2:2004(E). (3)With 40 V external suppressor referred to ground (-40C < Tj < 150C). MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs. 28/46 DocID027404 Rev 1 VNQ7140AJ Application information The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup 20 mA; VOHC 4.5 V 7.5 k Rprot 140 k. Recommended values: Rprot = 15 k 4.4 Multisense - analog current sense Diagnostic information on device and load status are provided by an analog output pin (MultiSense) delivering the following signals: * * * Current monitor: current mirror of channel output current VCC monitor: voltage propotional to VCC TCASE: voltage propotional to chip temperature Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. Figure 37: MultiSense and diagnostic - block diagram DocID027404 Rev 1 29/46 Application information 4.4.1 VNQ7140AJ Principle of Multisense signal generation Figure 38: MultiSense block diagram Current monitor When current mode is selected in the MultiSense, this output is capable to provide: * * Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K Where: * * 30/46 VSENSE is voltage measurable on RSENSE resistor ISENSE is current provided from MultiSense pin in current output mode DocID027404 Rev 1 VNQ7140AJ Application information * * IOUT is current flowing through output K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin which is switched to a "current limited" voltage source, VSENSEH. In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms section. Figure 39: Analogue HSD - open-load detection in off-state DocID027404 Rev 1 31/46 Application information VNQ7140AJ Figure 40: Open-load / short to VCC condition Table 13: MultiSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL MultiSense SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H TCASE and VCC monitor In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must be taken in case a GND network protection is used, because a voltage shift is generated between device GND and the microcontroller input GND reference. Figure 41: "GND voltage shift" shows link between VMEASURED and real VSENSE signal. 32/46 DocID027404 Rev 1 VNQ7140AJ Application information Figure 41: GND voltage shift VCC monitor Battery monitoring channel provides VSENSE = VCC / 4. Case temperature monitor Case temperature monitor is capable to provide information about the actual device temperature. Since a diode is used for temperature sensing, the following equation describes the link between temperature and output VSENSE level: VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 C to 150 C). 4.4.3 Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable VPU to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: DocID027404 Rev 1 33/46 Application information VNQ7140AJ Equation RPU < 34/46 VPU - 4 IL(off2)min @ 4V DocID027404 Rev 1 VNQ7140AJ Maximum demagnetization energy (VCC = 16 V) Figure 42: Maximum turn off current versus inductance VNQ7140AJ- Maximum turn off current versus inductance 10 I (A) 5 Maximum demagnetization energy (VCC = 16 V) 1 VNQ7140AJ - Single Pulse Repetitive pulse Tjstart=100C Repetitive pulse Tjstart=125C 0.1 0.1 1 10 L (mH) 100 1000 GAPGCFT01304 Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DocID027404 Rev 1 35/46 Package and PCB thermal data VNQ7140AJ 6 Package and PCB thermal data 6.1 PowerSSO-16 thermal data Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 14: PCB properties Dimension Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Heatsink copper area dimension (bottom layer) 36/46 Value DocID027404 Rev 1 Footprint, 2 cm2 or 8 cm2 VNQ7140AJ Package and PCB thermal data Figure 45: PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition RTHjamb RTHj_amb( C/W) 100 RTHjamb 90 80 70 60 50 40 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) GAPGCFT01305 Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse ZTH (C/W) 100 10 1 Cu=8 cm2 Cu=2 cm2 Cu=foot print 4 Layer 0.1 0.0001 0.001 0.01 0.1 Time (s) 1 10 100 1000 GAPGCFT01306 Equation: pulse calculation formula ZTH = RTH * + ZTHtp (1 - ) where = tP/T DocID027404 Rev 1 37/46 Package and PCB thermal data VNQ7140AJ Figure 47: Thermal fitting model for PowerSSO-16 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15: Thermal parameters 38/46 Area/island (cm2) Footprint R1 = R7 = R9 = R11 (C/W) 4.8 R2 = R8 = R10 = R12 (C/W) 1.8 R3 (C/W) 8 R4 (C/W) 16 R5 (C/W) 30 R6 (C/W) 26 C1 = C7 = C9 = C11 (W.s/C) 0.0002 C2 = C8 = C10 = C12 (W.s/C) 0.005 C3 (W.s/C) 0.08 C4 (W.s/C) 2 8 4L 8 8 5 6 6 4 20 10 3 20 18 7 0.2 0.3 0.3 0.4 C5 (W.s/C) 0.4 1 1 4 C6 (W.s/C) 3 5 7 18 DocID027404 Rev 1 VNQ7140AJ 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 PowerSSO-16 package information Figure 48: PowerSSO-16 package dimensions Table 16: PowerSSO-16 mechanical data Millimeters Symbol Min. Typ. Max. 0 1 0 2 5 15 3 5 15 A 8 1.70 A1 0.00 0.10 A2 1.10 1.60 DocID027404 Rev 1 39/46 Package information VNQ7140AJ Millimeters Symbol Min. b 0.20 b1 0.20 c 0.19 c1 0.19 D D1 Typ. 0.30 0.25 0.28 0.25 0.20 0.23 4.9 BSC 3.60 4.20 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 1.90 2.50 h 0.25 0.50 L 0.40 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 Tolerance of form and position aaa 40/46 Max. 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 DocID027404 Rev 1 0.85 VNQ7140AJ 7.2 Package information PowerSSO-16 packing information Figure 49: PowerSSO-16 reel 13" Table 17: Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 Notes: (1)All dimensions are in mm. DocID027404 Rev 1 41/46 Package information VNQ7140AJ Figure 50: PowerSSO-16 carrier tape 0.30 0.05 P2 P0 2.0 0.1 4.0 0.1 X 1.55 0.05 1.75 0.1 B0 W F 1.60.1 R 0.5 Typical K1 Y Y X K0 P1 A0 REF 4.18 REF 0.6 SECTION X - X REF 0.5 SECTION Y - Y GAPG2204151242CFT Table 18: PowerSSO-16 carrier tape dimensions Description Value(1) A0 6.50 0.1 B0 5.25 0.1 K0 2.10 0.1 K1 1.80 0.1 F 5.50 0.1 P1 8.00 0.1 W 12.00 0.3 Notes: (1)All dimensions are in mm. Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape 42/46 DocID027404 Rev 1 VNQ7140AJ 7.3 Package information PowerSSO-16 marking information Figure 52: PowerSSO-16 marking information Marking area 1 2 3 4 5 6 7 8 Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not in scale) GAPG0401151415CFT Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions. DocID027404 Rev 1 43/46 Order codes 8 VNQ7140AJ Order codes Table 19: Device summary Order codes Package Tape and reel PowerSSO-16 44/46 DocID027404 Rev 1 VNQ7140AJTR VNQ7140AJ 9 Revision history Revision history Table 20: Document revision history Date Revision 25-May-2015 1 Changes Initial release. DocID027404 Rev 1 45/46 VNQ7140AJ IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2015 STMicroelectronics - All rights reserved 46/46 DocID027404 Rev 1