VNQ7140AJ
Quad channel high-side driver with MultiSense analog feedback
for automotive applications
Datasheet - product ion data
Features
Max transient supply voltage VCC 40 V
Operating voltage range VCC 4 to 28 V
Typ. on-state resistance (per Ch) RON 140 mΩ
Current limitation (typ) ILIMH 12 A
Stand-by current (max) ISTBY 0.5 µA
• Automotive qualified
• General
− Quad channel smart high-side driver
with MultiSense analog feedback
− Very low standby current
− Compatible with 3 V and 5 V CMOS
outputs
• MultiSense diagnostic functions
− Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC suppl y voltage and
TCHIP device temperature
− Overload and short to ground (power
limitation) indication
− Thermal shutdown indication
− OFF-state open-load detection
− Output short to VCC detection
− Sense enabl e/d isab le
• Protections
− Undervoltage shutdown
− Overvoltage clamp
− Load current limitation
− Self limiting of fast thermal transients
− Configurable latch-off on
overtemperature or power limitation
with dedicated fault reset pin
− Loss of ground and loss of VCC
− Reverse battery with external
components
− Electrostatic discharge protection
Applications
• All types of automotive resistive, inductive
and capacitive loads
• Specially intended for automotive signal
lamps (up to R10W or LED Rear
Combinations)
Description
The device is a quad channel high-side driver
manufactured using ST proprietary VIPower®
technology and housed in Power SSO -16
package. The device is designed to drive 12 V
automotive grounded loads through a 3 V and 5
V CMOS-compatible interface, providing
protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches t he outp ut in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices
May 2015 DocID027404 Rev 1 1/46
This is information on a product in full production. www.st.com
Contents
VNQ7140AJ
Contents
1 Block diagram and pin des cr iption ................................................ 5
2 Electrical specification .................................................................... 7
2.1 Absolute maxi mu m rati ng s ................................................................ 7
2.2 Thermal dat a ..................................................................................... 8
2.3 Main electrical characteristics ........................................................... 8
2.4 Waveforms ...................................................................................... 20
2.5 Electrical characteristics curves ...................................................... 22
3 Protections..................................................................................... 26
3.1 Power limitation ............................................................................... 26
3.2 Thermal shutdown ........................................................................... 26
3.3 Current limitation ............................................................................. 26
3.4 Negative voltage clamp ................................................................... 26
4 Application information ................................................................ 27
4.1 GND protection network against reverse battery ............................. 27
4.1.1 Diode (DGND) in the ground line ..................................................... 28
4.2 Immunity agains t transient electrical disturbances .......................... 28
4.3 MCU I/Os protection ........................................................................ 28
4.4 Multisense - analog current sense .................................................. 29
4.4.1 Principle of Multisense signal generation ......................................... 30
4.4.2 TCASE and VCC monitor ................................................................. 32
4.4.3 Short to VCC and OFF-state open-l oad det ec tio n ........................... 33
5 Maxim um demagne t izati on e nergy (VCC = 16 V) ........................ 35
6 Package and PCB thermal data .................................................... 36
6.1 PowerSSO-16 thermal data ............................................................ 36
7 Package information ..................................................................... 39
7.1 PowerSSO-16 package information ................................................ 39
7.2 PowerSSO-16 packing information ................................................. 41
7.3 PowerSSO-16 marking informat ion ................................................. 43
8 Order c ode s ................................................................................... 44
9 Revision history ............................................................................ 45
2/46 DocID027404 Rev 1
VNQ7140AJ
List of tables
List of tables
Table 1: Pin functions ................................................................................................................................. 5
Table 2: Suggested connections for unused and not connected pins ........................................................ 6
Table 3: Absolute maximum ratings ........................................................................................................... 7
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Power section ............................................................................................................................... 8
Table 6: Switching ....................................................................................................................................... 9
Table 7: Logic inputs ................................................................................................................................. 10
Table 8: Protections .................................................................................................................................. 10
Table 9: MultiSense .................................................................................................................................. 11
Table 10: Truth table ................................................................................................................................. 19
Table 11: MultiSense multiplexer addressing ........................................................................................... 19
Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 28
Table 13: MultiSense pin levels in off-state .............................................................................................. 32
Table 14: PCB properties ......................................................................................................................... 36
Table 15: Thermal parameters ................................................................................................................. 38
Table 16: PowerSSO-16 mechanical data................................................................................................ 39
Table 17: Reel dimensions ....................................................................................................................... 41
Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 42
Table 19: Device summary ....................................................................................................................... 44
Table 20: Document revision history ........................................................................................................ 45
DocID027404 Rev 1 3/46
List of figur es
List of figures
Figure 1: Block diagram .............................................................................................................................. 5
Figure 2: Configuration diagram (top view)................................................................................................. 6
Figure 3: Current and voltage conventions ................................................................................................. 7
Figure 4: IOUT/ISENSE versus IOUT ....................................................................................................... 16
Figure 5: Current sense precision vs. IOUT ............................................................................................. 16
Figure 6: Switching time and Pulse skew ................................................................................................. 17
Figure 7: MultiSense timings (current sense mode) ................................................................................. 17
Figure 8: Multisense timings (chip temperature and VCC sense mode) .................................................. 18
Figure 9: TDSKON .................................................................................................................................... 18
Figure 10: Latch func t ion al ity - behavior in hard short circuit condition (TAMB << TTSD) ...................... 20
Figure 11: Latch func t ion al ity - behavior in hard short circuit condition .................................................... 20
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 21
Figure 13: Standby mode activation ......................................................................................................... 21
Figure 14: Stand b y state di agram ............................................................................................................. 22
Figure 15: OFF-state output current ......................................................................................................... 22
Figure 16: Stand b y curre nt ....................................................................................................................... 22
Figure 17: IGND(ON) vs. Tcase ............................................................................................................... 23
Figure 18: Logic Input hi gh le vel volt age .................................................................................................. 23
Figure 19: Log ic Input lo w level vo ltag e .................................................................................................... 23
Figure 20: High lev el logic input curre nt ................................................................................................... 23
Figure 21: Low level logic input current .................................................................................................... 23
Figure 22: Logic Input h yster es is volt age ................................................................................................. 23
Figure 23: FaultRST Input clamp voltage ................................................................................................. 24
Figure 24: Under vo lta ge shut do wn ........................................................................................................... 24
Figure 25: On-state resistance vs. Tcase ................................................................................................. 24
Figure 26: On-state resistance vs. VCC ................................................................................................... 24
Figure 27: Turn-on volta ge s lope .............................................................................................................. 24
Figure 28: Turn-off voltage slope .............................................................................................................. 24
Figure 29: Won vs. Tcase ......................................................................................................................... 25
Figure 30: Woff vs. Tcase ......................................................................................................................... 25
Figure 31: ILIMH vs. Tcase ....................................................................................................................... 25
Figure 32: OFF-state open-load voltage detection threshold ................................................................... 25
Figure 33: Vsense clamp vs. Tcase .......................................................................................................... 25
Figure 34: Vsense h vs . Tc ase .................................................................................................................. 25
Figure 35: Appl icati on dia gram ................................................................................................................. 27
Figure 36: Simplified internal structure ..................................................................................................... 27
Figure 37: Multi Se nse a nd diagnos t ic – block diagram ............................................................................ 29
Figure 38: MultiSense block diagram ....................................................................................................... 30
Figure 39: Anal ogu e HSD – open-load detect ion in of f -state ................................................................... 31
Figure 40: Open-load / short to VCC condition ......................................................................................... 32
Figure 41: GND voltage shift .................................................................................................................... 33
Figure 42: Maximum turn off current versus inductance .......................................................................... 35
Figure 43: Power S SO-16 o n two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 36
Figure 44: Power S SO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 36
Figure 45: PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition ......................... 37
Figure 46: Power S SO-16 thermal impedance junction ambient single pulse .......................................... 37
Figure 47: Thermal fitting model for PowerSSO-16 .................................................................................. 38
Figure 48: Power S SO-16 package dimensions ........................................................................................ 39
Figure 49: PowerSSO-16 reel 13" ............................................................................................................ 41
Figure 50: Power S SO-16 carrier tape ...................................................................................................... 42
Figure 51: Power S SO-16 schematic drawing of leader and trailer tape .................................................. 42
Figure 52: Power S SO-16 marking information ......................................................................................... 43
4/46 DocID027404 Rev 1
VNQ7140AJ
Block diagram and pin description
1 Block diagram and pin description
Figure 1: Block diagra m
Table 1: Pin functions
Name Function
VCC Battery connection.
OUTPUT0,1,2,3 Power output.
GND Ground connection. Must be reverse battery protected by an external
diode / resistor netw or k.
INPUT0,1,2,3 Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V
CMOS outputs. It controls output switch state.
MultiSense Multiplexed analog sense output pin; it delivers a current proportional to
the selected diagnostic: load current, supply voltage or chip temperature.
SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables
the MultiSense diagnostic pin.
SEL0,1,2
Active high compatible with 3 V and 5 V CMOS outputs pin; they address
the MultiSense multiplexer.
FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches
the output in case of fault; If kept low, sets the outputs in auto-restart
mode.
Channel 3
Channel 2
CH 3
CH 2
Channel 1
Control & Diagnostic
Channel 0
V
CC
V
ON
Limitation
Current
Limitation
V
CC
– OUT
Clamp
Internal supply
CH 1
OUTPUT
0
CH 0
MUX
Current
Sense
0
GND
Undervoltage
shut-down
V
CC
– GND
Clamp
Fault
T
Short to V
CC
Open-Load in OFF
Overtemperature
Power Limitation
T
V
SENSEH
INPUT
0
SEL
0
SEL
2
SEn
Multisense
FaultRST
INPUT
1
OUTPUT
1
V
CC
Gate Driver
INPUT
2
INPUT
3
OUTPUT
2
OUTPUT
3
SEL
1
GAPGCFT00378
DocID027404 Rev 1 5/46
Block diagram and pin description
VNQ7140AJ
Figure 2: Configuration diagram (top view)
Table 2: Suggested connections for unused and not connected pins
Connection / pin MultiSense N.C. Output Input SEn, SELx,
FaultRST
Floating Not allowed X (1) X X X
To ground Through 1 kΩ
resistor X Not allowed Through 15 kΩ
resistor Through 15 kΩ
resistor
Notes:
(1)X: do not care.
1
2
3
4
5
6INPUT2
INPUT0 SEL1
7
8
INPUT1
INPUT3
16
15
14
13
12
11
OUTPUT0
OUTPUT1 SEL2
N.C. 10
9
SEL0
OUTPUT2
OUTPUT3
SEn
MultiSense
FaultRS T
GND
TAB = V
CC
PowerSSO-16
GAPGCFT00379
6/46 DocID027404 Rev 1
VNQ7140AJ
Electrical specification
2 Electrical specification
Figure 3: Current and voltage conventions
V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
2.1 Absolute m a xi m um rat ings
Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability.
Table 3: A bsolut e maximum rat ings
Symbol Parameter Value Unit
VCC DC supply voltage 38 V
-VCC Reverse DC supply voltage 0.3
VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40V; RL = 4 Ω) 40 V
VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V
-IGND DC reverse ground pin current 200 mA
IOUT OUTPUT0,1,2,3 DC output curre nt Internally
limited A
-IOUT Reverse DC output current 4
IIN INPUT0,1,2,3 DC input current
-1 to 10 mA
ISEn SEn DC input current
ISEL SEL0,1,2 DC input current
IFR FaultRST DC input current
VFR FaultRST DC input voltage 7.5 V
V
IN
OUTPUT
0,1,2,3
MultiSense
FaultRST
SE
n
SEL
0,1,2
INPUT0,1,2,3
I
IN
I
SEL
I
SEn
I
FR
I
GND
V
SENSE
V
OUT
V
CC
V
Fn
I
S
I
OUT
I
SENSE
V
CC
V
SEL
V
SEn
V
FR
GAPGCFT00380
DocID027404 Rev 1 7/46
Electrical specification
VNQ7140AJ
Symbol Parameter Value Unit
ISENSE MultiSense pin DC output current
(VGND = VCC and VSENSE < 0 V) 10 mA
MultiSense pin DC output current in reverse (VCC < 0 V) -20
EMAX Maximum switching energy (single pulse)
(TDEMAG = 0.4 ms; Tjstart = 150 °C) 10 mJ
VESD
Electrostatic discharge (JEDEC 22A-114F)
• INPUT0,1,2,3
• MultiSense
• SEn, SEL0,1,2, FaultRST
• OUTPUT0,1,2,3
• VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
Tj Junction operating temperature -40 to 150 °C
Tstg Storage temperat ure -55 to 150
2.2 Thermal da t a
Table 4: Thermal data
Symbol Parameter Typ. value Unit
Rthj-board T hermal resi stan ce jun cti on-board (JEDEC JESD 51-5 / 51-8) (1)(2) 7.7
°C/W
Rthj-amb Thermal resistance jun cti on-ambient (JEDEC JESD 51-5)(1)(3) 61
Rthj-amb Thermal resistance jun cti on-ambient (JEDEC JESD 51-7)(1)(2) 26.8
Notes:
(1)One channel ON.
(2)Device mounted on four-layers 2s2p PCB.
(3)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.
2.3 Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5: Power section
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit
VCC Operating supply voltage
4 13 28
V
VUSD Undervoltage shut dow n
4
VUSDReset
Undervolta ge shut down reset
5
VUSDhyst Undervolta ge shut down
hysteresis
0.3
RON On-state resistance (1)
IOUT = 1 A; Tj = 25°C
140
mΩ IOUT = 1 A; Tj = 150°C
280
IOUT = 1 A; VCC = 4 V; Tj = 25°C
210
8/46 DocID027404 Rev 1
VNQ7140AJ
Electrical specification
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit
Vclamp Clamp voltage IS = 20 mA; Tj = -40°C 38
V
IS = 20 mA; 25°C < Tj < 150°C 41 46 52
ISTBY Supply current in standby at
VCC = 13 V (2)
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1,2 = 0 V; Tj = 25°C 0.5 µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1,2 = 0 V; Tj = 85°C (3) 0.5 µA
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1,2 = 0 V; Tj = 125°C 3 µA
tD_STBY Standby mode blanking time VCC = 13 V;
VIN = VOUT = VFR = VSEL0,1,2 = 0 V;
VSEn = 5 V to 0 V 60 300 550 µs
IS(ON) Supply current VCC = 13 V;
VSEn = VFR = VSEL0,1,2 = 0 V;
VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0 A 10 16 mA
IGND(ON) Control stage curren t
consumption in ON state. All
channels active.
VCC = 13 V; VSEn = 5 V;
VFR = VSEL0,1,2 = 0 V; VIN0,1,2,3 = 5 V;
IOUT0,1,2,3 = 1 A 20 mA
IL(off) Off-state output current at
VCC = 13 V(1)
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C 0 0.01 0.5 µA
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C 0
3
VF Output - VCC diode voltage (1) IOUT = -1 A; Tj = 150°C
0.7 V
Notes:
(1)For each channel.
(2)PowerMOS leakage included.
(3)Parameter specified by design; not subject to production t est.
Table 6: Switchin g
VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified
Symbol Parameter Test conditions Min.
Typ.
Max. Unit
td(on)(1) Turn-on delay time at Tj = 25°C RL = 13 Ω 10 70 120 µs
td(off)(1) Turn-off delay time at Tj = 25°C 10 40 100
(dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25°C RL = 13 Ω 0.1 0.29 0.7 V/µs
(dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25°C 0.1 0.35 0.7
WON Switching energy losses at turn-on (twon) RL = 13 Ω — 0.15 0.2 (2) mJ
WOFF Switching energy losses at turn-off (twoff) RL = 13 Ω — 0.1 0.18(2) mJ
tSKEW(1) Differential Pulse skew (tPHL- tPLH) RL = 13 Ω -90 -40 10 µs
Notes:
(1)See Figure 6: "Switching time and Pulse skew"
(2)Parameter guaranteed by design and characterizati on; not subj ect to product i on test.
DocID027404 Rev 1 9/46
Electrical specification
VNQ7140AJ
Table 7: Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
INPUT0,1,2,3 characteristics
VIL Input low level voltage
0.9 V
IIL Low level input current VIN = 0.9 V 1
µA
VIH Input high level voltage
2.1
V
IIH High level input current VIN = 2.1 V
10 µA
VI(hyst) Input hystere si s voltage
0.2
V
VICL Input clamp voltag e IIN = 1 mA 5.3
7.2 V
IIN = -1 mA
-0.7
FaultRST characteristics
VFRL Input low level voltage
0.9 V
IFRL Low level input current VIN = 0.9 V 1
µA
VFRH Input high level voltage
2.1
V
IFRH High level input current VIN = 2.1 V
10 µA
VFR(hyst) Input hysteresi s volta ge
0.2
V
VFRCL Input clamp voltage IIN = 1 mA 5.3
7.5 V
IIN = -1 mA
-0.7
SEL0,1,2 characteristics (7 V < VCC < 18 V)
VSELL Input low level voltage
0.9 V
ISELL Low level input current VIN = 0.9 V 1
µA
VSELH Input high level voltage
2.1
V
ISELH High level input current VIN = 2.1 V
10 µA
VSEL(hyst) Input hysteresis volta ge
0.2
V
VSELCL Input clamp voltage IIN = 1 mA 5.3
7.2 V
IIN = -1 mA
-0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL Input low level voltage
0.9 V
ISEnL Low level input current VIN = 0.9 V 1
µA
VSEnH Input high level voltage
2.1
V
ISEnH High level input current VIN = 2.1 V
10 µA
VSEn(hyst) Input hysteresis volta ge
0.2
V
VSEnCL Input clamp voltage IIN = 1 mA 5.3
7.2 V
IIN = -1 mA
-0.7
Table 8: Protect ions
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
ILIMH DC short circuit current VCC = 13 V 8 12 16 A
4 V < VCC < 18 V (1)
16
10/46 DocID027404 Rev 1
VNQ7140AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
ILIML Short circuit current
during thermal cycling VCC = 13 V;
TR < Tj < TTSD
4
TTSD Shutdown temperature
150 175 200
°C
TR Reset temperature(1)
TRS + 1 TRS + 7
TRS Thermal reset of fault
diagnostic ind ica tio n VFR = 0 V; VSEn = 5 V 135
THYST Thermal hysteresis
(TTSD - TR)(1)
7
ΔTJ_SD Dynamic temperature Tj = -40°C; VCC = 13 V
60
K
tLATCH_RST(1) Fault reset time for
output unlatch
VFR = 5 V to 0 V;
VSEn = 5 V
• E.g. Ch0
VIN0 = 5 V;
VSEL0,1,2 = 0 V
3 10 20 µs
VDEMAG Turn-off output voltage
clamp
IOUT= 1 A; L = 6 mH;
Tj = -40°C VCC - 38
V
IOUT= 1 A; L = 6 mH;
Tj = 25°C to 150°C VCC - 41 VCC - 46 VCC - 52 V
VON Output volt age drop
limitation IOUT = 0.07 A
20
mV
Notes:
(1)Parameter guaranteed by design and characterizati on; not subj ect to product i on test.
Table 9: MultiSen se
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSENSE_CL MultiS ense clamp
voltage VSEn = 0 V; ISENSE = 1 mA -17
-12 V
VSEn = 0 V; ISENSE = -1 mA
7
Current Sense characteristics
KOL IOUT/ISENSE IOUT = 0.01 A; V SENSE = 0.5 V;
VSEn = 5 V 330
dKcal/Kcal(1)(2) Curr ent sen se ratio
drift at calibration
point
IOUT = 0.01 A to 0.025 A;
Ical = 17.5 mA; VSENSE = 0.5 V;
VSEn = 5 V -30 30 %
KLED IOUT/ISENSE IOUT = 0.025 A; VSENSE = 0.5 V;
VSEn = 5 V 330 580 830
dKLED/KLED(1)(2) Current sen se ratio
drift IOUT = 0.025 A; VSENSE = 0.5 V;
VSEn = 5 V -25
25 %
K0 IOUT/ISENSE IOUT = 0.070 A; VSENSE = 0.5 V;
VSEn = 5 V 375 550 720
dK0/K0(1)(2) Current sense ratio
drift IOUT = 0.070 A; VSENSE = 0.5 V;
VSEn = 5 V -20
20 %
DocID027404 Rev 1 11/46
Electrical specification
VNQ7140AJ
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
K1 IOUT/ISENSE IOUT = 0.15 A; VSENSE = 4 V;
VSEn = 5 V 365 520 675
dK1/K1(1)(2) Current sense ratio
drift IOUT = 0.15 A; VSENSE = 4 V;
VSEn = 5 V -15
15 %
K2 IOUT/ISENSE IOUT = 0.7 A; VSENSE = 4 V;
VSEn = 5 V 380 475 570
dK2/K2(1)(2) Current sense ratio
drift IOUT = 0.7 A; VSENSE = 4 V;
VSEn = 5 V -10
10 %
K3 IOUT/ISENSE IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V 420 470 520
dK3/K3(1)(2) Current sense ratio
drift IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V -5
5 %
ISENSE0 MultiSense l
eakage
current
MultiSense disabled: VSEn = 0 V 0
0.5
µA
MultiSense disabled:
-1 V < VSENSE < 5 V(1) -0.5
0.5
MultiSense enabled: VSEn = 5 V
All channels ON; IOUTX = 0 A;
ChX diagnostic select ed:
• E.g. Ch0:
VIN0,1,2,3 = 5 V; VSEL0 = 0 V;
VSEL1,2 = 0 V; I OUT0 = 0 A;
IOUT1,2,3 = 1 A
0 2
MultiSense enabled: VSEn = 5 V;
ChX OFF; ChX diagnostic selected:
• E.g. Ch0:
VIN0 = 0 V; VIN1,2,3 = 0 V;
VSEL0 = 5V; VSEL1,2 = 0 V;
IOUT1,2,3 = 1 A
0 2
VOUT_MSD(1) Output Voltage for
MultiSense
shutdown
VSEn = 5 V; RSENSE = 2.7 kΩ
• E.g. Ch0:
VIN0 = 5 V; VSEL0,1,2 = 0 V;
IOUT0 = 1 A 5 V
VSENSE_SAT MultiSense
saturation voltage
VCC = 7 V; RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL0,1,2 = 0 V; IOUT0 = 2 A;
Tj = 150°C
5 V
ISENSE_SAT(1) CS saturation
current
VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V;
VSEn = 5 V; VSEL0,1,2 = 0 V;
Tj = 150°C 4 mA
IOUT_SAT(1) Output saturation
current
VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V;
VSEn = 5 V; VSEL0,1,2 = 0 V;
Tj = 150°C 2.2 A
OFF-state diagnostic
VOL OFF-state open-
load voltage
detection threshold
VSEn = 5 V; ChX OFF; ChX
diagnostic se lect ed
• E.g: Ch0
VIN0 = 0 V; VSEL0,1,2 = 0 V
2 3 4 V
12/46 DocID027404 Rev 1
VNQ7140AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
IL(off2) OFF-state output
sink current VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C -100
-15 µA
tDSTKON
OFF-state
diagnostic del ay
time from fallin g
edge of INPUT
(see Figure 9:
"TDSKON")
VSEn = 5 V; ChX ON to OFF
transition;
ChX diagnostic select ed:
• E.g: Ch0
VIN0 = 5 V to 0 V;
VSEL0,1,2 = 0 V; VOUT0 = 4 V;
IOUT0 = 0 A
100 350 700 µs
tD_OL_V
Settling time for
valid OFF-state
open load
diagnostic
indication from
rising edge of SEn
VIN0,1,2,3 = 0 V; VFR = 0 V;
VSEL0,1,2 = 0 V; VOUT0 = 4 V;
VSEn = 0 V to 5 V 60 µs
tD_VOL
OFF-state
diagnostic del ay
time from rising
edge of VOUT
VSEn = 5 V; ChX OFF;
ChX diagnostic select ed:
• E.g: Ch0
VIN0 = 0 V; VSEL0,1,2 = 0 V;
VOUT0 = 0 V to 4 V
5 30 µs
Chip temperature analog feedback
VSENSE_TC
MultiSense output
voltage propor tio nal
to chip temperature
all channels off
VSEn = 5 V; VSEL0 = 0 V;
VSEL1,2 = 5 V; VIN0,1,2,3 = 0 V;
RSENSE = 1 kΩ; Tj = -40°C 2.325 2.41 2.495
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1,2 = 5 V; VIN0,1,2,3 = 0 V;
RSENSE = 1 kΩ; Tj = 25°C 1.985 2.07 2.155
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1,2 = 5 V; VIN0,1,2,3 = 0 V;
RSENSE = 1 kΩ; Tj = 125°C 1.435 1.52 1.605
V
dVSENSE_TC/dT(1)
Temperature
coefficient Tj = -40 °C to 150 °C
-5.5
mV/
K
Transfer function VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
VCC supply voltage analog feedback
VSENSE_VCC
MultiSense output
voltag
e proportio nal
to VCC supply
voltage
VCC = 13 V; VSEn = 5 V;
VIN0,1,2,3 = 0 V; VSEL0,1,2 = 5 V;
RSENSE = 1 kΩ 3.16 3.23 3.3 V
Transfer function (3) VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 10: "Truth table")
VSENSEH MultiSense output
voltage in fault
condition
VCC = 13 V; RSENSE = 1 kΩ
• E.g: Ch0 in open load
VIN0 = 0 V; VSEn = 5 V;
VSEL0,1,2 = 0 V; IOUT0 = 0 A;
VOUT0 = 4 V
5 6.6 V
DocID027404 Rev 1 13/46
Electrical specification
VNQ7140AJ
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISENSEH MultiSense output
cu rrent in fault
condition VCC = 13 V; VSENSE = 5 V 7 20 30 mA
MultiSense ti mings (current sense mode - see Figure 7: "MultiSense timings (current sense
mode)")(4)
tDSENSE1H Current sen se
se ttling time from
rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 13 Ω 60 µs
tDSENSE1L
Current sense
disable delay time
from falling edge of
SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 13 Ω 5 20 µs
tDSENSE2H
Current sense
se ttling time from
rising edge of
INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 13 Ω 100 250 µs
ΔtDSENSE2H
Current sense
se ttling time from
rising edge of IOUT
(dynamic response
to a step change of
IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ; ISENSE = 90 % of
ISENSEMAX; RL = 13 Ω 100 µs
tDSENSE2L
Current sense tur n-
off delay time from
falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 13 Ω 50 250 µs
MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip
temperature and VCC sens e mode)")(4)
tDSENSE3H VSENSE_TC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V; VSEL0 = 0 V;
VSEL1,2 = 5 V; RSENSE = 1 kΩ 60 µs
tDSENSE3L VSENSE_TC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V; VSEL0 = 0 V;
VSEL1,2 = 5 V; RSENSE = 1 kΩ 20 µs
MultiSense timings (VCC volt age sense mode - see Figure 8: "Multisense timings (chip
temperature and VCC sens e mode)")(4)
tDSENSE4H VSENSE_VCC settling
time from risin g
edge of SEn
VSEn = 0 V to 5 V; VSEL0,1,2 = 5 V;
RSENSE = 1 kΩ 60 µs
tDSENSE4L VSENSE_VCC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V; VSEL0,1,2 = 5 V;
RSENSE = 1 kΩ 20 µs
MultiSense timings (multiplexer transition times)(4)
tD_XtoY MultiSense
transition delay
from ChX to ChY
VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V;
VSEL1,2 = 0 V; VSEL0 = 0 V to 5 V;
IOUT0 = 0 A; IOUT1 = 1A;
RSENSE = 1 kΩ 20 µs
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VNQ7140AJ
Electrical specification
7 V < VCC < 18 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit
tD_CStoTC
MultiSense
transition delay
from current sens e
to TC sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1 = 0 V;
VSEL2 = 0 V to 5 V; IOUT0 = 0.5 A;
RSENSE = 1 kΩ 60 µs
tD_TCtoCS
MultiSense
transition delay
fromTC sense to
current sense
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1 = 0 V;
VSEL2 = 5 V to 0 V; IOUT0 = 0.5 A;
RSENSE = 1 kΩ 20 µs
tD_CStoVCC
MultiSense
transition delay
from current sens e
to VCC sense
VIN3 = 5 V; VSEn = 5 V;
VSEL0,1 = 5 V;
VSEL2 = 0 V to 5 V; IOUT3 = 0.5 A;
RSENSE = 1 kΩ 60 µs
tD_VCCtoCS
MultiSense
transition delay
from VCC sense to
current sense to
VIN3 = 5 V; VSEn = 5 V;
VSEL0,1 = 5 V;
VSEL2 = 5 V to 0 V; IOUT3 = 0.5 A;
RSENSE = 1 kΩ 20 µs
tD_TCtoVCC
MultiSense
transition delay
from TC sense to
VCC sense
VCC = 13 V; Tj = 125°C; VSEn = 5 V;
VSEL1,2 = 5 V; VSEL0 = 0 V to 5 V;
RSENSE = 1 kΩ 20 µs
tD_VCCtoTC
MultiSense
transition delay
from VCC sense to
TC sense
VCC = 13 V; Tj = 125°C; VSEn = 5 V;
VSEL1,2 = 5 V; VSEL0 = 5 V to 0 V;
RSENSE = 1 kΩ 20 µs
tD_CStoVSENSEH
MultiSense
transition delay
from stable curre nt
sense on ChX to
VSENSEH on ChY
VIN0 = 5 V; VIN1 = 0 V; VSEn = 5 V;
VSEL1,2 = 0 V; VSEL0 = 0 V to 5 V;
IOUT0 = 1 A; VOUT1 = 4 V;
RSENSE = 1 kΩ 20 µs
Notes:
(1)Parameter specified by design; not subject to production t est.
(2)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
(3)VCC sensing and TC sensing are referred to GND potential.
(4)Transition delays are measured up to +/- 10% of final conditions.
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Electrical specification
VNQ7140AJ
Figure 4: IOUT/ISENSE versus IOUT
Figure 5: Current sense precision vs. IOUT
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Electrical specification
Figure 6: Switching time and Pulse skew
Figure 7: MultiSense timings (current sense mode)
VOUT
t
Vcc
twon
80%Vcc
20% Vcc
twoff
INPUT
td(on)
tpLH tpHL
td(off)
t
dV
OUT
/dt
ON OFF
dV
OUT
/dt
GAPGCFT00797
CurrentSense
IN1
SEn
IOUT1
tDSENSE2H tDSENSE1L tDSENSE2L
tDSENSE1H
SEL0
SEL1 Low
High
Low
High
Low
High
SEL2 Low
High
GAPGCFT00432
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Electrical specification
VNQ7140AJ
Figure 8: Multisense timings (chip temperature and VCC sense mode)
Figure 9: TDSKON
MultiSense
SEn
V
CC
t
DSENSE4H
t
DSENSE4L
t
DSENSE3L
t
DSENSE3H
SEL0
SEL1
Low
High
Low
High
Low
High
V
SENS E
= V
SENSE _VCC
V
SENS E
= V
SENSE _TC
VCC VOLTAGE SENSE MODE CHIP TEMPERATURESENSE MODE
SEL2
Low
High
GAPGCFT00816
T
DSTKON
V
INPU T
V
OUT
MultiSense
V
OUT
> V
OL
GAPG2609141140CFT
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VNQ7140AJ
Electrical specification
Table 10: Truth table
Mode Conditions INX
FR
SEn
SELX OUTX MultiSense Comments
Standby All logic inputs
low L L L L L Hi-Z Low quiescent current
consumption
Normal Nominal load
connected;
Tj < 150°C
L X
See (1)
L See (1)
H L H See (1) Outputs configured for
auto-restart
H H H See (1) Outputs configured for
Latch-off
Overload
Overload or short
to GND causing:
Tj > TTSD or
ΔTj > ΔTj_SD
L X
L See (1)
H L H See (1) Output cycles with
temperature hysteresis
H H L See (1) Output latches-off
Under-voltage VCC < VUSD
(falling) X X X X L
L Hi-Z
Hi-Z
Re-start when
VCC > VUSD +
VUSDhyst (rising)
OFF-state
diagnostics Short to VCC L X See (1) H See (1)
Open-load L X H See (1) External pull-up
Negative
output voltage Inductive loads
turn-off L X See (1) < 0 V See (1)
Notes:
(1)Refer to Table 11: "MultiSense multiplexer addressing"
Table 11: MultiSe nse mult iplexer addressing
SEn
SEL2 SEL1 SEL0 MUXchannel MultiSense output
Nomal mode Overload OFF-state
diag. (1)(2)(3)
Negative
output
L X X X
Hi-Z
H L L L Channel 0
diagnostic ISENSE =
1/K * IOUT0 VSENSE =
VSENSEH VSENSE =
VSENSEH Hi-Z
H L L H Channel 1
diagnostic ISENSE =
1/K * IOUT1 VSENSE =
VSENSEH VSENSE =
VSENSEH Hi-Z
H L H L Channel 2
diagnostic ISENSE =
1/K * IOUT2 VSENSE =
VSENSEH VSENSE =
VSENSEH Hi-Z
H L H H Channel 3
diagnostic ISENSE =
1/K * IOUT3 VSENSE =
VSENSEH VSENSE =
VSENSEH Hi-Z
H H L L TCHIP Sense VSENSE = VSENSE_TC
H H L H VCC Sense VSENSE = VSENSE_VCC
H H H L TCHIP Sense VSENSE = VSENSE_TC
H H H H VCC Sense VSENSE = VSENSE_VCC
Notes:
(1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense
pin delive rs fee db ac k acco rdi ng to OF F -State diagnostic.
(2)Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0
(3)Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH
DocID027404 Rev 1 19/46
Electrical specification
VNQ7140AJ
2.4 Waveforms
Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)
Figure 11: Latch functionality - behavior in hard short circuit condition
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Electrical specification
Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode +
latch off)
Figure 13: Standby mode activation
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Electrical specification
VNQ7140AJ
Figure 14: Standby state diagram
2.5 Electrical characteristics curves
Figure 15: OFF-state output current
Figure 16: Standby current
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Electrical specification
Figure 17: IGND(ON) vs. Tcase
Figure 18: Logic Input high level voltage
Figure 19: Logic Input low level voltage
Figure 20: High level logic input current
Figure 21: Low level logic input current
Figure 22: Logic Input hysteresis voltage
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Electrical specification
VNQ7140AJ
Figure 23: FaultRST Input clamp voltage
Figure 24: Undervoltage shutdown
Figure 25: On-state resistance vs. Tcase
Figure 26: On-state resistance vs. VCC
Figure 27: Turn-on voltage slope
Figure 28: Turn-off voltage slope
0
1
2
3
4
5
6
7
8
-50 -25 0 25 50 75 100125150175
T [°C]
VUSD [V]
GAPGRI00399
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Electrical specification
Figure 29: Won vs. Tcase
Figure 30: Woff vs. Tcase
Figure 31: ILIMH vs. Tcase
Figure 32: OFF-state open-load voltage
detection threshold
Figure 33: Vsense clamp vs. Tcase
Figure 34: Vsenseh vs. Tcase
DocID027404 Rev 1 25/46
Protections
VNQ7140AJ
3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as
soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the
FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis
according to the maximum instantaneous power which can be handled (FaultRST = Low)
or remains off (FaultRST = High). The protection prevents fast thermal transient effects
and, consequently, reduces thermo-mechanical fatigue.
3.2 Thermal s hut dow n
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon
as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well
as the other components of the system (e.g. bonding wires, wiring harness, connectors,
loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or
during load power-up, the output current is clamped to a safety level, ILIMH, by operating the
output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a
certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the
device.
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Application information
4 Application information
Figure 35: Application diagram
4.1 GND protection network against reverse batter y
Figure 36: Simplified internal structure
DocID027404 Rev 1 27/46
Application information
VNQ7140AJ
4.1.1 Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inducti ve load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input thr es hold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12: "ISO 7637-2 -
electrical transient conduction along supply line".
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present
device only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns
automatically to normal operation after the test”.
Table 12: ISO 7637-2 - ele ctr i cal trans i ent cond u ctio n alo ng supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time P ulse durati on and
pulse generator
internal impedance
Level US(1) min max
1 III -112V 500 pulses 0,5 s
2ms, 10Ω
2a III +55V 500 pulses 0,2 s 5 s 50µs, 2Ω
3a IV -220V 1h 90 ms 100 ms 0.1µs, 50Ω
3b IV +150V 1h 90 ms 100 ms 0.1µs, 50Ω
4 (2) IV -7V 1 pulse
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B (3)
40V 5 pulse 1 min
400ms, 2Ω
Notes:
(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
(2)Test pulse from ISO 7637-2:2004(E).
(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
4.3 MCU I/O s prot e ction
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
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Application information
The value of these resistors is a compromise between the leakage current of
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with
the latch-up limit of microcontroller I/Os.
Equation
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculat ion example:
For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4 Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
• Current monitor: current mirror of channel output current
• VCC monitor: voltage propotional to VCC
• TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in MultiSense multiplexer
addressing Table.
Figure 37: MultiSense and diagnostic – block diagra m
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Application information
VNQ7140AJ
4.4.1 Principle of Multisense signal generation
Figure 38: MultiSense block diagram
Current monitor
When current mode is selected in the MultiSense, this output is capable to provide:
• Current mirror proportional to the load current in normal operation, delivering current
proportional to the load according to known ratio named K
• Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation can
be done using simple equations
Current provided by MultiSense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K
Where:
• VSENSE is voltage measurable on RSENSE resistor
• ISENSE is current provided from MultiSense pin in current output mode
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Application information
• IOUT is current flowing through output
• K factor represents the ratio between PowerMOS cells and SenseMOS cells; its
spread includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin
which is switched to a “current limited” voltage source, VSENSEH.
In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH.
The typical behavior in case of overload or hard short circuit is shown in Waveforms
section.
Figure 39: Analogue HSD – open-load detection in off-state
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Application information
VNQ7140AJ
Figure 40: Open -load / short to VCC condition
Table 13: MultiSense pin levels in off-state
Condition Output MultiSense SEn
Open-load
VOUT > VOL Hi-Z L
VSENSEH H
VOUT < VOL Hi-Z L
0 H
Short to VCC VOUT > VOL Hi-Z L
VSENSEH H
Nominal VOUT < VOL Hi-Z L
0 H
4.4.2 TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because a
voltage shift is generated between device GND and the microcontroller input GND
reference.
Figure 41: "GND voltage shift" shows link between VMEASURED and real VSENSE signal.
32/46 DocID027404 Rev 1
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Application information
Figure 41: GND voltage shift
VCC monitor
Battery monitoring channel provides VSENSE = V CC / 4.
Case temperature monitor
Case temperature monitor is capable to provide information about the actual device
temperature. Since a diode is used for temperature sensing, the following equation
describes the link between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C).
4.4.3 Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the de vice off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following
equation:
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Application information
VNQ7140AJ
Equation
R
PU
< V
PU
- 4
I
L(off2)min @ 4V
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Maximum demagnetization energy (VCC = 16 V)
5 Maximum demagnetization energy (VCC = 16 V)
Figure 42: Maximum turn off current versus inductance
Values are generated with R
L
= 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of
every pulse must not exceed the temperature specified above for curves A and B.
0.1
1
10
0.1 1 10 100 1000
I (A)
L (mH)
VNQ7140AJ- Maximumturn off current versus inductance
VNQ7140AJ - Single Pulse
Repetitive pulse Tjstart=100°C
Repetitive pulse Tjstart=125°C
GAPGCFT01304
DocID027404 Rev 1 35/46
Package and PCB thermal data
VNQ7140AJ
6 Package and PCB thermal data
6.1 PowerSSO-16 thermal data
Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 14: PCB properties
Dimension Value
Board finish thickness 1.6 mm +/- 10%
Board dimension 77 mm x 86 mm
Board Material FR4
Copper thickness (top and bottom layers) 0.070 m m
Copper thickness (inner layers) 0.035 m m
Thermal vias separation 1.2 mm
Thermal via diamet er 0.3 mm +/- 0.08 mm
Copper thickness on vias 0. 025 m m
Footprint dimension (top layer) 2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer) Footpr int , 2 cm2 or 8 cm2
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Package and PCB thermal data
Figure 45: PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition
Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse
Equation: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
GAPGCFT01305
40
50
60
70
80
90
100
0 2 4 6 8 10
RTHjamb
RTHjamb
RTHj_amb( C/W)
PCB Cu heatsink area (cm^2)
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
ZTH (°C/W)
Time (s)
Cu=8 cm2
Cu=2 cm2
Cu=foot print
4 Layer
GAPGCFT01306
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Package and PCB thermal data
VNQ7140AJ
Figure 47: Thermal fitting model for PowerSSO-16
The fitting model is a simplified thermal tool and is valid for transient evolutions
where the embedded protections (power limitation or thermal cycling during
thermal shutdown) are not triggered.
Table 15: Thermal par am eters
Area/island (cm2) Footprint 2 8 4L
R1 = R7 = R9 = R11 (°C/W) 4.8
R2 = R8 = R10 = R12 (°C/W) 1.8
R3 (°C/W) 8 8 8 5
R4 (°C/W) 16 6 6 4
R5 (°C/W) 30 20 10 3
R6 (°C/W) 26 20 18 7
C1 = C7 = C9 = C11 (W.s/°C) 0.0002
C2 = C8 = C10 = C12 (W.s/°C) 0.005
C3 (W.s/ ° C) 0.08
C4 (W.s/ ° C) 0.2 0.3 0.3 0.4
C5 (W.s/ ° C) 0.4 1 1 4
C6 (W.s/ ° C) 3 5 7 18
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Package information
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 PowerSSO-16 package information
Figure 48: PowerSSO-16 package dimensions
Table 16: Po werSSO-16 mec h anica l data
Symbol Millimeters
Min. Typ. Max.
Θ 0°
8°
Θ1 0°
Θ2 5°
15°
Θ3 5°
15°
A
1.70
A1 0.00
0.10
A2 1.10
1.60
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Package information
VNQ7140AJ
Symbol Millimeters
Min. Typ. Max.
b 0.20
0.30
b1 0.20 0.25 0.28
c 0.19
0.25
c1 0.19 0.20 0.23
D 4.9 BSC
D1 3.60
4.20
e 0.50 BSC
E 6.00 BSC
E1 3.90 BSC
E2 1.90
2.50
h 0.25
0.50
L 0.40 0.60 0.85
L1 1.00 REF
N 16
R 0.07
R1 0.07
S 0.20
Tolerance of form and position
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.08
eee 0.10
fff 0.10
ggg 0.15
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Package information
7.2 PowerSSO-16 packing inf orm a ti on
Figure 49: PowerSSO-16 reel 13"
Table 17: Reel dimensions
Description Value(1)
Base quantity 2500
Bulk quantity 2500
A (max) 330
B (min) 1.5
C (+0.5, -0.2) 13
D (min) 20.2
N 100
W1 (+2 /-0) 12.4
W2 (max) 18.4
Notes:
(1)All dimensions are in mm.
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Package information
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Figure 50: PowerSSO-16 carrier tape
Table 18: Po werSSO-16 carrier tape dimensions
Description Value(1)
A0 6.50 ± 0.1
B0 5.25 ± 0.1
K0 2.10 ± 0.1
K1 1.80 ± 0.1
F 5.50 ± 0.1
P1 8.00 ± 0.1
W 12.00 ± 0.3
Notes:
(1)All dimensions are in mm.
Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape
0.30 ±0.05 1.55 ±0.05
1.6±0.1
R 0.5
Typical
K
1
K
0
B
0
P
2
2.0 ±0.1
P
0
4.0 ±0.1
P
1
A
0
F
W
1.75 ±0.1
SECTION X - X
SECTION Y - Y
REF 4.18
REF 0.6
REF 0.5
X
X
Y Y
GAPG2204151242CFT
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Package information
7.3 PowerSSO-16 marking information
Figure 52: PowerSSO-16 marking information
Engineering Samples: these samples can be clearly identified by a dedicated
special symbol in the marking of each unit. These samples are intended to be
used for electrical compatibility evaluation only; usage for any other purpose may
be agreed only upon written authorization by ST. ST is not liable for any customer
usage in product ion and/or in reli abili t y qualific at io n trials .
Commercial Samples: fully qualified parts from ST standard production with no
usage restrictions.
GAPG0401151415CFT
1234567 8
Special function digit
&: Engineering sample
<blank>: Commercial sample
PowerSSO-16 TOP VIEW
(not in scale)
Marking area
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Order codes
VNQ7140AJ
8 Order codes
Table 19: Device summary
Package Order codes
Tape and reel
PowerSSO-16 VNQ7140AJTR
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Revision history
9 Revision history
Table 20: Document revision history
Date Revision Changes
25-May-2015 1 Initial release.
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