Z5U Dielectric General Specifications Z5U formulations are "general-purpose" ceramics which are meant primarily for use in limited temperature applications where small size and cost are important. Z5U show wide variations in capacitance under influence of environmental and electrical operating conditions. Despite their capacitance instability, Z5U formulations are very popular because of their small size, low ESL, low ESR and excellent frequency response. These features are particularly important for decoupling application where only a minimum capacitance value is required. PART NUMBER (see page 3 for complete part number explanation) 0805 5 E 104 Z A T 2 A Size (L" x W") Voltage 25V = 3 50V = 5 Dielectric Z5U = E Capacitance Code Capacitance Tolerance Preferred Z = +80% -20% M = 20% Failure Rate A = Not Applicable Terminations T = Plated Ni and Solder Packaging 2 = 7" Reel 4 = 13" Reel Special Code A = Std. Product PERFORMANCE CHARACTERISTICS Capacitance Range Capacitance Tolerances Operating Temperature Range Temperature Characteristic Voltage Ratings Dissipation Factor Insulation Resistance (+25C, RVDC) Dielectric Strength Test Voltage Test Frequency 12 0.01 F to 1.0 F Preferred +80 -20% others available: 20%, +100 -0% +10C to +85C +22% to -56% max. 25 and 50VDC (+85C) 4% max. 10,000 megohms min. or 1000 M - F min., whichever is less 250% of rated voltage for 5 seconds at 50 mamp max. current 0.5 0.2 Vrms 1 KHz Z5U Dielectric Typical Characteristic Curves** Temperature Coefficient Variation of Impedance with Cap Value Impedance vs. Frequency 1206 -Z5U 100.00 10.00 Impedance, % Capacitance +30 +20 +10 0 -10 -20 -30 -40 -50 -60 +10 +25 +30 +35 +40 +45 +50 +55 +65 +85 Temperature C 10,000 pF 1.00 100,000 pF 0.10 0.01 1 100 10 1,000 Frequency, MHz Variation of Impedance with Chip Size Impedance vs. Frequency .33 F - Z5U 1000 0 -10 Z5U 1206 Z5U 1210 Z5U 1812 100 |Z| (ohms) % Capacitance Capacitance vs. Frequency -20 -30 10 1 -40 1KHz 10 KHz 100 KHz 1 MHz 10 MHz 0.1 0.001 Frequency 0.01 0.1 1 10 100 1,000 Variation of Impedance with Ceramic Formulation Impedance vs. Frequency .1F X7R vs. Z5U 0805 nsu ation Resistance vs Temperature 100,000 10000 10,000 X7R 0805 Z5U 0805 1000 1,000 |Z| (ohms) Insulation Resistance (Ohm-Farads) Frequency, MHz 100 0 +20 +30 +40 +50 +60 +70 100 10 1 0.1 +80 Temperature C 0.01 0.001 0.01 0.1 1 10 100 1,000 Frequency, MHz SUMMARY OF CAPACITANCE RANGES VS. CHIP SIZE Style 0603* 0805* 1206* 1210* 1808 1812* 1825* 2225 25V .01F - .047F .01F - .12F .01F - .33F .01F - .56F .01F - .56F .01F - 1.0F .01F - 1.0F .01F - 1.0F 50V .01F - .027F .01F - 0.1F .01F - .33F .01F - .47F .01F - .47F .01F - 1.0F .01F - 1.0F .01F - 1.0F * Standard Sizes ** For additional information on performance changes with operating conditions consult AVX's software SpiCap. 13 Z5U Dielectric Capacitance Range PREFERRED SIZES ARE SHADED SIZE 0603* 0805 1206 1210 Standard Reel Packaging All Paper Paper/Embossed Paper/Embossed Paper/Embossed 1.60 .15 (.063 .006) .81 .15 (.032 .006) .90 (.035) .35 .15 (.014 .006) 2.01 .20 (.079 .008) 1.25 .20 (.049 .008) 1.30 (.051) .50 .25 (.020 .010) 3.20 .20 (.126 .008) 1.60 .20 (.063 .008) 1.50 (.059) .50 .25 (.020 .010) 3.20 .20 (.126 .008) 2.50 .20 (.098 .008) 1.70 (.067) .50 .25 (.020 .010) WVDC 50 25 50 25 L 50 W *Reflow soldering only. 50 .010 .012 .015 .018 .022 .027 .033 .039 .047 .056 .068 .082 .10 .12 .15 .18 .22 .27 .33 .39 .47 .56 .68 .82 1.0 1.5 25 Cap (F) 25 (t) Terminal (T) Max. Thickness T (W) Width MM (in.) MM (in.) MM (in.) MM (in.) (L) Length t = Paper Tape = Embossed Tape NOTES: For low profile chips, see page 19. 14 Z5U Dielectric Capacitance Range PREFERRED SIZES ARE SHADED 1808* 1812* 1825* 2225* All Embossed All Embossed All Embossed All Embossed 04.57 .25 (.180 .010) 2.03 .25 (.080 .010) 1.52 (.060) .64 .39 (.025 .015) 4.50 .30 (.177 .012) 3.20 .20 (.126 .008) 1.70 (.067) .61 .36 (.024 .014) 4.50 .30 (.177 .012) 6.40 .40 (.252 .016) 1.70 (.067) .61 .36 (.024 .014) 5.72 .25 (.225 .010) 6.35 .25 (.250 .010) 1.70 (.067) .64 .39 (.025 .015) (t) Terminal 25 25 50 25 50 25 L 50 W *Reflow soldering only. 50 .010 .012 .015 .018 .022 .027 .033 .039 .047 .056 .068 .082 .10 .12 .15 .18 .22 .27 .33 .39 .47 .56 .68 .82 1.0 1.5 WVDC Cap (F) (T) Max. Thickness T (W) Width MM (in.) MM (in.) MM (in.) MM (in.) (L) Length SIZE Standard Reel Packaging t = Paper Tape = Embossed Tape NOTES: For low profile chips, see page 19. 15 Basic Capacitor Formulas I. Capacitance (farads) English: C = .224 K A TD Metric: C = .0884 K A TD XI. Equivalent Series Resistance (ohms) E.S.R. = (D.F.) (Xc) = (D.F.) / (2 fC) XII. Power Loss (watts) Power Loss = (2 fCV2) (D.F.) XIII. KVA (Kilowatts) KVA = 2 fCV2 x 10 -3 II. Energy stored in capacitors (Joules, watt - sec) E = 12 CV2 XIV. Temperature Characteristic (ppm/C) T.C. = Ct - C25 x 106 C25 (Tt - 25) III. Linear charge of a capacitor (Amperes) dV I=C dt XV. Cap Drift (%) C1 - C2 C.D. = C1 IV. Total Impedance of a capacitor (ohms) Z = RS + (XC - XL ) V. Capacitive Reactance (ohms) 1 xc = 2 fC 2 2 XVI. Reliability of Ceramic Capacitors Vt L0 X Tt Y = Lt Vo To ( ) ( ) VI. Inductive Reactance (ohms) xL = 2 fL XVII. Capacitors in Series (current the same) Any Number: 1 = 1 + 1 --- 1 CT C1 C2 CN C1 C2 Two: CT = C1 + C2 VII. Phase Angles: Ideal Capacitors: Current leads voltage 90 Ideal Inductors: Current lags voltage 90 Ideal Resistors: Current in phase with voltage XVIII. Capacitors in Parallel (voltage the same) CT = C1 + C2 --- + CN VIII. Dissipation Factor (%) D.F.= tan (loss angle) = E.S.R. = (2 fC) (E.S.R.) Xc IX. Power Factor (%) P.F. = Sine (loss angle) = Cos (phase angle) f P.F. = (when less than 10%) = DF XIX. Aging Rate A.R. = % D C/decade of time XX. Decibels db = 20 log V1 V2 X. Quality Factor (dimensionless) Q = Cotan (loss angle) = 1 D.F. METRIC PREFIXES Pico Nano Micro Milli Deci Deca Kilo Mega Giga Tera 2 X 10-12 X 10-9 X 10-6 X 10-3 X 10-1 X 10+1 X 10+3 X 10+6 X 10+9 X 10+12 x 100 SYMBOLS K = Dielectric Constant f = frequency Lt = Test life A = Area L = Inductance Vt = Test voltage TD = Dielectric thickness = Loss angle Vo = Operating voltage V = Voltage f = Phase angle Tt = Test temperature t = time X&Y = exponent effect of voltage and temp. To = Operating temperature Rs = Series Resistance Lo = Operating life How to Order Part Number Explanation EXAMPLE: 08055A101JAT2A 0805 Size (L" x W") 0402 0504 0603 0805 1005 0907 1206 1210 1505 1805 1808 1812 1825 2225 3640 5 A 101 Dielectric C0G (NP0) = A X7R = C X5R = D Z5U = E Y5V = G Voltage 10V = Z 16V = Y 25V = 3 50V = 5 100V = 1 200V = 2 250V = V 500V = 7 600V = C 1000V = A 1500V = S 2000V = G 2500V = W 3000V = H 4000V = J 5000V = K J C D F G J K M Z P A Capacitance Tolerance = .25 pF* = .50 pF* = 1% ( 25 pF) = 2% ( 13 pF) = 5% = 10% = 20% = +80%, -20% = +100%, -0% Capacitance Code (2 significant digits + no. of zeros) Examples: 10 pF = 100 100 pF = 101 1,000 pF = 102 22,000 pF = 223 220,000 pF = 224 1 F = 105 For values below 10 pF, use "R" in place of decimal point, e.g., 9.1 pfd = 9R1. T 2 Terminations Standard: T = Ni and Tin Plated Others: 7 = Plated Ni Gold Plated 1 = Pd/Ag Failure Rate A = Not Applicable A Special** Code A = Standard Product Non-Standard P = Embossed unmarked M = Embossed marked E = Standard packaging marked Low Profile Chips Only Max. Thickness T = .66mm (.026") S = .56mm (.022") R = .46mm (.018") Packaging** Recommended: 2 =7" Reel 4 =13" Reel Others: 7 = Bulk Cassette 9 = Bulk * C&D tolerances for 10 pF values. ** Standard Tape and Reel material depends upon chip size and thickness. See individual part tables for tape material type for each capacitance value. Note: Unmarked product is standard. Marked product is available on special request, please contact AVX. Standard packaging is shown in the individual tables. Non-standard packaging is available on special request, please contact AVX. 3 General Specifications Environmental THERMAL SHOCK MOISTURE RESISTANCE Specification Appearance No visual defects Capacitance Variation C0G (NP0): 2.5% or .25pF, whichever is greater X7R: 7.5% Z5U: 20% Y5V: 20% Q, Tan Delta To meet initial requirement Insulation Resistance C0G (NP0), X7R: To meet initial requirement Z5U, Y5V: Initial Value x 0.1 Dielectric Strength No problem observed Measuring Conditions Step Temperature C Time (minutes) C0G (NP0), X7R: -55 2 1 Z5U: +10 2 30 3 Y5V: -30 2 2 Room Temperature #3 C0G (NP0), X7R: +125 2 3 30 3 Z5U, Y5V: +85 2 4 Room Temperature #3 Repeat for 5 cycles and measure after 48 hours 4 hours (24 hours for C0G (NP0)) at room temperature. Specification Appearance No visual defects Capacitance Variation C0G (NP0): 5% or .5pF, whichever is greater X7R: 10% Z5U: 30% Y5V: 30% Q, Tan Delta C0G (NP0): 30pF........................Q 350 10pF, < 30pF ...........Q 275+5C/2 < 10pF ........................Q 200+10C X7R: Initial requirement + .5% Z5U: Initial requirement + 1% Y5V: Initial requirement + 2% IMMERSION Specification Appearance No visual defects Capacitance Variation C0G (NP0): 2.5% or .25pF, whichever is greater X7R: 7.5% Z5U: 20% Y5V: 20% Q, Tan Delta To meet initial requirement Insulation Resistance C0G (NP0), X7R: To meet initial requirement Z5U, Y5V: Initial Value x 0.1 Dielectric Strength No problem observed Measuring Conditions Step Temperature C Time (minutes) +65 +5/-0 1 15 2 Pure Water 03 2 15 2 NaCl solution Repeat cycle 2 times and wash with water and dry. Store at room temperature for 48 4 hours (24 hours for C0G (NP0)) and measure. 22 Insulation Resistance Initial Value x 0.3 Measuring Conditions Step Temp. C Humidity % Time (hrs) 1 +25->+65 90-98 2.5 2 +65 90-98 3.0 3 +65->+25 80-98 2.5 4 +25->+65 90-98 2.5 5 +65 90-98 3.0 6 +65->+25 80-98 2.5 7 +25 90-98 2.0 7a -10 uncontrolled - 7b +25 90-98 - Repeat 20 cycles (1-7) and store for 48 hours (24 hours for C0G (NP0)) at room temperature before measuring. Steps 7a & 7b are done on any 5 out of first 9 cycles. General Specifications Environmental STEADY STATE HUMIDITY (No Load) Specification Appearance No visual defects Capacitance Variation C0G (NP0): 5% or .5pF, whichever is greater X7R: 10% Z5U: 30% Y5V: 30% Q, Tan Delta C0G (NP0): 30pF......................Q 350 10pF, < 30pF.........Q 275+5C/2 < 10pF ....................Q 200+10C X7R: Initial requirement + .5% Z5U: Initial requirement + 1% Y5V: Initial requirement + 2% Insulation Resistance Initial Value x 0.3 Measuring Conditions Store at 85 5% relative humidity and 85C for 1000 hours, without voltage. Remove from test chamber and stabilize at room temperature and humidity for 48 4 hours (24 2 hours for C0G (NP0)) before measuring. Charge and discharge currents must be less than 50ma. LOAD HUMIDITY Specification Appearance No visual defects Capacitance Variation C0G (NP0): 5% or .5pF, whichever is greater X7R: 10% Z5U: 30% Y5V: 30% Q, Tan Delta C0G (NP0): 30pF .....................Q 350 10pF,< 30pF .........Q 275+5C/2 < 10pF ....................Q 200+10C X7R: Initial requirement + .5% Z5U: Initial requirement + 1% Y5V: Initial requirement + 2% Insulation Resistance C0G (NP0), X7R: To meet initial value x 0.3 Z5U, Y5V: Initial Value x 0.1 Charge devices with rated voltage in test chamber set at 85 5% relative humidity and 85C for 1000 (+48,-0) hours. Remove from test chamber and stabilize at room temperature and humidity for 48 4 hours (24 2 hours for C0G (NP0)) before measuring. Charge and discharge currents must be less than 50ma. LOAD LIFE Specification Appearance No visual defects Capacitance Variation C0G (NP0): 3% or .3pF, whichever is greater X7R: 10% Z5U: 30% Y5V: 30% Q, Tan Delta C0G (NP0): 30pF......................Q 350 10pF, < 30pF.........Q 275+5C/2 < 10pF ....................Q 200+10C X7R: Initial requirement + .5% Z5U: Initial requirement + 1% Y5V: Initial requirement + 2% Insulation Resistance C0G (NP0), X7R: To meet initial value x 0.3 Z5U, Y5V: Initial Value x 0.1 Charge devices with twice rated voltage in test chamber set at +125C 2C for C0G (NP0) and X7R, +85 2C for Z5U, and Y5V for 1000 (+48,-0) hours. Remove from test chamber and stabilize at room temperature for 48 4 hours (24 2 hours for C0G (NP0)) before measuring. Charge and discharge currents must be less than 50ma. 23 General Specifications Mechanical END TERMINATION ADHERENCE Specification No evidence of peeling of end terminal Measuring Conditions After soldering devices to circuit board apply 5N (0.51kg f) for 10 1 seconds, please refer to Figure 1. BEND STRENGTH Speed = 1mm/sec 2mm Deflection R340mm 45mm 5N FORCE 45mm Supports Figure 2. Bend Strength DEVICE UNDER TEST TEST BOARD Figure 1. Terminal Adhesion RESISTANCE TO VIBRATION Specification Appearance: No visual defects Capacitance Within specified tolerance Q, Tan Delta To meet initial requirement Insulation Resistance C0G (NP0), X7R Initial Value x 0.3 Z5U, Y5V Initial Value x 0.1 Measuring Conditions Vibration Frequency 10-2000 Hz Maximum Acceleration 20G Swing Width 1.5mm Test Time X, Y, Z axis for 2 hours each, total 6 hours of test SOLDERABILITY Specification 95% of each termination end should be covered with fresh solder Measuring Conditions Dip device in eutectic solder at 230 5C for 2 .5 seconds 24 Specification Appearance: No visual defects Capacitance Variation C0G (NP0): 5% or .5pF, whichever is larger X7R: 12% Z5U: 30% Y5V: 30% Insulation Resistance C0G (NP0): Initial Value x 0.3 X7R: Initial Value x 0.3 Z5U: Initial Value x 0.1 Y5V: Initial Value x 0.1 Measuring Conditions Please refer to Figure 2 Deflection: 2mm Test Time: 30 seconds RESISTANCE TO SOLDER HEAT Specification Appearance: No serious defects, <25% leaching of either end terminal Capacitance Variation C0G (NP0): 2.5% or 2.5pF, whichever is greater X7R: 7.5% Z5U: 20% Y5V: 20% Q, Tan Delta To meet initial requirement Insulation Resistance To meet initial requirement Dielectric Strength No problem observed Measuring Conditions Dip device in eutectic solder at 260C, for 1 minute. Store at room temperature for 48 hours (24 hours for C0G (NP0)) before measuring electrical parameters. Part sizes larger than 3.20mm x 2.49mm are reheated at 150C for 30 5 seconds before performing test. European Detail Specifications CECC 32 101-801/Chips Standard European Ceramic Chip Capacitors PART NUMBER (example) 0805 5 C 103 Size (L" x W") Voltage 50V = 5 100V = 1 200V = 2 Dielectric 1B CG = A 2R1 = C 2F4 = G Capacitance Code M T T Capacitance Specification Terminations Tolerance CECC32101-801 T = Plated Ni See Dielectrics and Sn C0G, X7R, Y5V 2 A Marking Packaging 2 = 7" Reel 4 = 13" Reel Special Code A = Std. Product RANGE OF APPROVED COMPONENTS Case Size 1BCG Voltage and Capacitance Range 100V Dielectric Type 50V 0603 0805 1206 1210 1808 1812 2220 1B CG 1B CG 1B CG 1B CG 1B CG 1B CG 1B CG 0.47pF - 150pF 0.47pF - 560pF 0.47pF - 3.3nF 0.47pF - 4.7nF 0.47pF - 6.8nF 0.47pF - 15nF 0.47pF - 39nF 0.47pF - 120pF 0.47pF - 560pF 0.47pF - 3.3nF 0.47pF - 4.7nF 0.47pF - 6.8nF 0.47pF - 15nF 0.47pF - 39nF 0.47pF - 100pF 0.47pF - 330pF 0.47pF - 1.5nF 0.47pF - 2.7nF 0.47pF - 4.7nF 0.47pF - 10nF 0.47pF - 15nF 0603 0805 1206 1210 1808 1812 2220 2R1 2R1 2R1 2R1 2R1 2R1 2R1 10pF - 6.8nF 10pF - 33nF 10pF - 100nF 10pF - 150nF 10pF - 270nF 10pF - 470nF 10pF - 1.2F 10pF - 6.8nF 10pF - 18nF 10pF - 68nF 10pF - 100nF 10pF - 180nF 10pF - 330nF 10pF - 680nF 10pF - 1.2nF 10pF - 3.3nF 10pF - 18nF 10pF - 27nF 10pF - 47nF 10pF - 100nF 10pF - 220nF 0805 1206 1210 1808 1812 2220 2F4 2F4 2F4 2F4 2F4 2F4 10pF - 100nF 10pF - 330nF 10pF - 470nF 10pF - 560nF 10pF - 1.8F 10pF - 2.2F 200V 2R1 2F4 31 Packaging of Chip Components Automatic Insertion Packaging TAPE & REEL QUANTITIES All tape and reel specifications are in compliance with RS481. 8mm Paper or Embossed Carrier (1) 12mm 0805, 1005, 1206, 1210 Embossed Only 0504, 0907 Paper Only 0402, 0603 1505, 1805, 1808 1812, 1825 2220, 2225 Qty. per Reel/7" Reel 2,000 or 4,000 (1) 3,000 1,000 Qty. per Reel/13" Reel 10,000 10,000 4,000 Dependent on chip thickness. Low profile chips shown on page 27 are 5,000 per reel for 7" reel. 0402 size chips are 10,000 per 7" reels and are not available on 13" reels. For 3640 size chip contact factory for quantity per reel. REEL DIMENSIONS Tape Size(1) A Max. B* Min. C D* Min. N Min. 8mm 330 (12.992) 1.5 (.059) 13.00.20 (.512.008) 20.2 (.795) W2 Max. W3 8.4 +1.0 -0.0 (.331 +.060 -0.0 ) 14.4 (.567) 7.9 Min. (.311) 10.9 Max. (.429) 12.4 +2.0 -0.0 +.076 ) (.488 -0.0 18.4 (.724) 11.9 Min. (.469) 15.4 Max. (.607) 50 (1.969) 12mm Metric dimensions will govern. English measurements rounded and for reference only. (1) For tape sizes 16mm and 24mm (used with chip size 3640) consult EIA RS-481 latest revision. 32 W1 Embossed Carrier Configuration 8 & 12mm Tape Only 8 & 12mm Embossed Tape Metric Dimensions Will Govern CONSTANT DIMENSIONS Tape Size 8mm and 12mm D0 +0.10 -0.0 +.004 -0.0 8.4 (.059 E ) P0 P2 1.75 0.10 4.0 0.10 2.0 0.05 (.069 .004) (.157 .004) (.079 .002) T Max. T1 G1 G2 0.600 (.024) 0.10 (.004) Max. 0.75 (.030) Min. See Note 3 0.75 (.030) Min. See Note 4 R Min. See Note 2 T2 W A0 B0 K0 VARIABLE DIMENSIONS Tape Size B1 D1 Max. Min. See Note 6 See Note 5 F P1 8mm 4.55 (.179) 1.0 (.039) 3.5 0.05 4.0 0.10 (.138 .002) (.157 .004) 25 (.984) 2.5 Max (.098) 8.0 +0.3 -0.1 (.315 +.012 -.004 ) See Note 1 12mm 8.2 (.323) 1.5 (.059) 5.5 0.05 4.0 0.10 (.217 .002) (.157 .004) 30 (1.181) 6.5 Max. (.256) 12.0 .30 (.472 .012) See Note 1 8mm 1/2 Pitch 4.55 (.179) 1.0 (.039) 3.5 0.05 2.0 0.10 (.138 .002) 0.79 .004 25 (.984) 2.5 Max. (.098) 8.0 +0.3 -0.1 (.315 +.012 -.004 ) See Note 1 12mm Double Pitch 8.2 (.323) 1.5 (.059) 5.5 0.05 8.0 0.10 (.217 .002) (.315 .004) 30 (1.181) 6.5 Max. (.256) 12.0 .30 (.472 .012) See Note 1 NOTES: 1. A0, B0, and K0 are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. The clearance between the end of the terminals or body of the component to the sides and depth of the cavity (A0, B0, and K0) must be within 0.05 mm (.002) min. and 0.50 mm (.020) max. The clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (see sketches C & D). 2. Tape with components shall pass around radius "R" without damage. The minimum trailer length (Note 2 Fig. 3) may require additional length to provide R min. for 12 mm embossed tape for reels with hub diameters approaching N min. (Table 4). 3. G1 dimension is the flat area from the edge of the sprocket hole to either the outward deformation of the carrier tape between the embossed cavities or to the edge of the cavity whichever is less. 4. G2 dimension is the flat area from the edge of the carrier tape opposite the sprocket holes to either the outward deformation of the carrier tape between the embossed cavity or to the edge of the cavity whichever is less. 5. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and hole location shall be applied independent of each other. 6. B1 dimension is a reference dimension for tape feeder clearance only. 33 Paper Carrier Configuration 8 & 12mm Tape Only 8 & 12mm Paper Tape Metric Dimensions Will Govern CONSTANT DIMENSIONS Tape Size 8mm and 12mm D0 1.5 (.059 +0.1 -0.0 +.004 -.000 E ) 1.75 0.10 (.069 .004) P0 P2 4.0 0.10 2.0 0.05 (.157 .004) (.079 .002) T1 G1 G2 R MIN. 0.10 (.004) Max. 0.75 (.030) Min. 0.75 (.030) Min. 25 (.984) See Note 2 VARIABLE DIMENSIONS Tape Size P1 F W A0 B0 T 8mm 4.0 0.10 (.157 .004) 3.5 0.05 (.138 .002) 8.0 +0.3 -0.1 (.315 +.012 -.004 ) See Note 1 See Note 3 12mm 4.0 .010 (.157 .004) 5.5 0.05 (.217 .002) 12.0 0.3 (.472 .012) 8mm 1/2 Pitch 2.0 0.10 (.079 .004) 3.5 0.05 (.138 .002) 8.0 +0.3 -0.1 (.315 +.012 -.004 ) 12mm Double Pitch 8.0 0.10 (.315 .004) 5.5 0.05 (.217 .002) 12.0 0.3 (.472 .012) NOTES: 1. A0, B0, and T are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. The clearance between the ends of the terminals or body of the component to the sides and depth of the cavity (A0, B0, and T) must be within 0.05 mm (.002) min. and 0.50 mm (.020) max. The clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (see sketches A & B). 2. Tape with components shall pass around radius "R" without damage. 3. 1.1 mm (.043) Base Tape and 1.6 mm (.063) Max. for Non-Paper Base Compositions. Bar Code Labeling Standard AVX bar code labeling is available and follows latest version of EIA-556-A. 34 Bulk Case Packaging BENEFITS BULK FEEDER * Easier handling * Smaller packaging volume (1/20 of T/R packaging) * Easier inventory control Case * Flexibility * Recyclable Cassette Gate Shooter CASE DIMENSIONS Shutter Slider 12mm 36mm Mounter Head Expanded Drawing 110mm Chips Attachment Base CASE QUANTITIES Part Size 0402 0603 0805 Qty. (pcs / cassette) 80,000 15,000 10,000 (T=0.6mm) 5,000 (T0.6mm) 35 General Description Basic Construction - A multilayer ceramic (MLC) capacitor is a monolithic block of ceramic containing two sets of offset, interleaved planar electrodes that extend to two opposite surfaces of the ceramic dielectric. This simple Ceramic Layer structure requires a considerable amount of sophistication, both in material and manufacture, to produce it in the quality and quantities needed in today's electronic equipment. Electrode End Terminations Terminated Edge Terminated Edge Formulations - Multilayer ceramic capacitors are available in both Class 1 and Class 2 formulations. Temperature compensating formulation are Class 1 and temperature stable and general application formulations are classified as Class 2. Class 1 - Class 1 capacitors or temperature compensating capacitors are usually made from mixtures of titanates where barium titanate is normally not a major part of the mix. They have predictable temperature coefficients and in general, do not have an aging characteristic. Thus they are the most stable capacitor available. The most popular Class 1 multilayer ceramic capacitors are C0G (NP0) temperature compensating capacitors (negative-positive 0 ppm/C). 36 Margin Electrodes Class 2 - EIA Class 2 capacitors typically are based on the chemistry of barium titanate and provide a wide range of capacitance values and temperature stability. The most commonly used Class 2 dielectrics are X7R and Y5V. The X7R provides intermediate capacitance values which vary only 15% over the temperature range of -55C to 125C. It finds applications where stability over a wide temperature range is required. The Y5V provides the highest capacitance values and is used in applications where limited temperature changes are expected. The capacitance value for Y5V can vary from 22% to -82% over the -30C to 85C temperature range. The Z5U dielectric is between X7R and Y5V in both stability and capacitance range. All Class 2 capacitors vary in capacitance value under the influence of temperature, operating voltage (both AC and DC), and frequency. For additional information on performance changes with operating conditions, consult AVX's software, SpiCap. General Description 0 -2.5 -5 -7.5 -10 25% 50% 75% Percent Rated Volts 100% Figure 4 40 Typical Cap. Change vs. Temperature AVX X7R T.C. 30 20 10 0 12.5 25 37.5 Volts AC at 1.0 KHz 50 Figure 2 Capacitor specifications specify the AC voltage at which to measure (normally 0.5 or 1 VAC) and application of the wrong voltage can cause spurious readings. Figure 3 gives the voltage coefficient of dissipation factor for various AC voltages at 1 kilohertz. Applications of different frequencies will affect the percentage changes versus voltages. D.F. vs. A.C. Measurement Volts AVX X7R T.C. 10.0 Dissipation Factor Percent 2.5 50 Curve 1 - 100 VDC Rated Capacitor 8.0 Curve 2 - 50 VDC Rated Capacitor Curve 3 - 25 VDC Rated Capacitor 6.0 Curve 3 Curve 2 4.0 Curve 1 2.0 0 .5 1.0 1.5 2.0 2.5 AC Measurement Volts at 1.0 KHz Figure 3 The effect of the application of DC voltage is shown in Figure 4. The voltage coefficient is more pronounced for higher K dielectrics. These figures are shown for room temperature conditions. The combination characteristic known as voltage temperature limits which shows the effects of rated voltage over the operating temperature range is shown in Figure 5 for the military BX characteristic. Capacitance Change Percent Capacitance Change Percent Cap. Change vs. A.C. Volts AVX X7R T.C. Cap. Change vs. D.C. Volts AVX X7R T.C. Capacitance Change Percent Effects of Voltage - Variations in voltage have little effect on Class 1 dielectric but does affect the capacitance and dissipation factor of Class 2 dielectrics. The application of DC voltage reduces both the capacitance and dissipation factor while the application of an AC voltage within a reasonable range tends to increase both capacitance and dissipation factor readings. If a high enough AC voltage is applied, eventually it will reduce capacitance just as a DC voltage will. Figure 2 shows the effects of AC voltage. +20 +10 0VDC 0 RVDC -10 -20 -30 -55 -35 -15 +5 +25 +45 +65 +85 +105 +125 Temperature Degrees Centigrade Figure 5 Effects of Time - Class 2 ceramic capacitors change capacitance and dissipation factor with time as well as temperature, voltage and frequency. This change with time is known as aging. Aging is caused by a gradual re-alignment of the crystalline structure of the ceramic and produces an exponential loss in capacitance and decrease in dissipation factor versus time. A typical curve of aging rate for semistable ceramics is shown in Figure 6. If a Class 2 ceramic capacitor that has been sitting on the shelf for a period of time, is heated above its curie point, (125C for 4 hours or 150C for 12 hour will suffice) the part will de-age and return to its initial capacitance and dissipation factor readings. Because the capacitance changes rapidly, immediately after de-aging, the basic capacitance measurements are normally referred to a time period sometime after the de-aging process. Various manufacturers use different time bases but the most popular one is one day or twenty-four hours after "last heat." Change in the aging curve can be caused by the application of voltage and other stresses. The possible changes in capacitance due to de-aging by heating the unit explain why capacitance changes are allowed after test, such as temperature cycling, moisture resistance, etc., in MIL specs. The application of high voltages such as dielectric withstanding voltages also 37 General Description tends to de-age capacitors and is why re-reading of capacitance after 12 or 24 hours is allowed in military specifications after dielectric strength tests have been performed. Typical Curve of Aging Rate X7R Dielectric +1.5 Capacitance Change Percent 0 -1.5 Lo = Lt -3.0 Vt Vo where Lo = operating life Lt = test life Vt = test voltage Vo = operating voltage -4.5 -6.0 -7.5 1 10 100 Characteristic C0G (NP0) X7R Z5U Y5V 1000 10,000 100,000 Hours Max. Aging Rate %/Decade None 2 3 5 Figure 6 Effects of Frequency - Frequency affects capacitance and impedance characteristics of capacitors. This effect is much more pronounced in high dielectric constant ceramic formulation that is low K formulations. AVX's SpiCap software generates impedance, ESR, series inductance, series resonant frequency and capacitance all as functions of frequency, temperature and DC bias for standard chip sizes and styles. It is available free from AVX. 38 Effects of Mechanical Stress - High "K" dielectric ceramic capacitors exhibit some low level piezoelectric reactions under mechanical stress. As a general statement, the piezoelectric output is higher, the higher the dielectric constant of the ceramic. It is desirable to investigate this effect before using high "K" dielectrics as coupling capacitors in extremely low level applications. Reliability - Historically ceramic capacitors have been one of the most reliable types of capacitors in use today. The approximate formula for the reliability of a ceramic capacitor is: X Tt To Y Tt = test temperature and To = operating temperature in C X,Y = see text Historically for ceramic capacitors exponent X has been considered as 3. The exponent Y for temperature effects typically tends to run about 8. A capacitor is a component which is capable of storing electrical energy. It consists of two conductive plates (electrodes) separated by insulating material which is called the dielectric. A typical formula for determining capacitance is: C = .224 KA t C = capacitance (picofarads) K = dielectric constant (Vacuum = 1) A = area in square inches t = separation between the plates in inches (thickness of dielectric) .224 = conversion constant (.0884 for metric system in cm) Capacitance - The standard unit of capacitance is the farad. A capacitor has a capacitance of 1 farad when 1 coulomb charges it to 1 volt. One farad is a very large unit and most capacitors have values in the micro (10-6), nano (10-9) or pico (10-12) farad level. Dielectric Constant - In the formula for capacitance given above the dielectric constant of a vacuum is arbitrarily chosen as the number 1. Dielectric constants of other materials are then compared to the dielectric constant of a vacuum. Dielectric Thickness - Capacitance is indirectly proportional to the separation between electrodes. Lower voltage requirements mean thinner dielectrics and greater capacitance per volume. Area - Capacitance is directly proportional to the area of the electrodes. Since the other variables in the equation are usually set by the performance desired, area is the easiest parameter to modify to obtain a specific capacitance within a material group. General Description Energy Stored - The energy which can be stored in a capacitor is given by the formula: I (Ideal) I (Actual) E = 12CV2 E = energy in joules (watts-sec) V = applied voltage C = capacitance in farads Potential Change - A capacitor is a reactive component which reacts against a change in potential across it. This is shown by the equation for the linear charge of a capacitor: I ideal = C dV dt Loss Angle Phase Angle f V IR s In practice the current leads the voltage by some other phase angle due to the series resistance RS. The complement of this angle is called the loss angle and: where I = Current C = Capacitance dV/dt = Slope of voltage transition across capacitor Thus an infinite current would be required to instantly change the potential across a capacitor. The amount of current a capacitor can "sink" is determined by the above equation. Equivalent Circuit - A capacitor, as a practical device, exhibits not only capacitance but also resistance and inductance. A simplified schematic for the equivalent circuit is: C = Capacitance L = Inductance Rp = Parallel Resistance Rs = Series Resistance Power Factor (P.F.) = Cos f or Sine Dissipation Factor (D.F.) = tan for small values of the tan and sine are essentially equal which has led to the common interchangeability of the two terms in the industry. Equivalent Series Resistance - The term E.S.R. or Equivalent Series Resistance combines all losses both series and parallel in a capacitor at a given frequency so that the equivalent circuit is reduced to a simple R-C series connection. RP E.S.R. L C Reactance - Since the insulation resistance (Rp) is normally very high, the total impedance of a capacitor is: Z= where C RS The watts loss are: Watts loss = (2 fCV2 ) (D.F.) R 2S + (XC - XL )2 Z = Total Impedance Rs = Series Resistance XC = Capacitive Reactance = XL = Inductive Reactance Dissipation Factor - The DF/PF of a capacitor tells what percent of the apparent power input will turn to heat in the capacitor. Dissipation Factor = E.S.R. = (2 fC) (E.S.R.) XC 1 2 fC = 2 fL The variation of a capacitor's impedance with frequency determines its effectiveness in many applications. Phase Angle - Power Factor and Dissipation Factor are often confused since they are both measures of the loss in a capacitor under AC application and are often almost identical in value. In a "perfect" capacitor the current in the capacitor will lead the voltage by 90. Very low values of dissipation factor are expressed as their reciprocal for convenience. These are called the "Q" or Quality factor of capacitors. Parasitic Inductance - The parasitic inductance of capacitors is becoming more and more important in the decoupling of today's high speed digital systems. The relationship between the inductance and the ripple voltage induced on the DC voltage line can be seen from the simple inductance equation: V = L di dt 39 General Description di The dt seen in current microprocessors can be as high as 0.3 A/ns, and up to 10A/ns. At 0.3 A/ns, 100pH of parasitic inductance can cause a voltage spike of 30mV. While this does not sound very drastic, with the Vcc for microprocessors decreasing at the current rate, this can be a fairly large percentage. Another important, often overlooked, reason for knowing the parasitic inductance is the calculation of the resonant frequency. This can be important for high frequency, bypass capacitors, as the resonant point will give the most signal attenuation. The resonant frequency is calculated from the simple equation: 1 fres = 2LC Insulation Resistance - Insulation Resistance is the resistance measured across the terminals of a capacitor and consists principally of the parallel resistance R P shown in the equivalent circuit. As capacitance values and hence the area of dielectric increases, the I.R. decreases and hence the product (C x IR or RC) is often specified in ohm farads or more commonly megohm-microfarads. Leakage current 40 is determined by dividing the rated voltage by IR (Ohm's Law). Dielectric Strength - Dielectric Strength is an expression of the ability of a material to withstand an electrical stress. Although dielectric strength is ordinarily expressed in volts, it is actually dependent on the thickness of the dielectric and thus is also more generically a function of volts/mil. Dielectric Absorption - A capacitor does not discharge instantaneously upon application of a short circuit, but drains gradually after the capacitance proper has been discharged. It is common practice to measure the dielectric absorption by determining the "reappearing voltage" which appears across a capacitor at some point in time after it has been fully discharged under short circuit conditions. Corona - Corona is the ionization of air or other vapors which causes them to conduct current. It is especially prevalent in high voltage units but can occur with low voltages as well where high voltage gradients occur. The energy discharged degrades the performance of the capacitor and can in time cause catastrophic failures. Surface Mounting Guide MLC Chip Capacitors Component Pad Design Component pads should be designed to achieve good solder filets and minimize component movement during reflow soldering. Pad designs are given below for the most common sizes of multilayer ceramic capacitors for both wave and reflow soldering. The basis of these designs is: * Pad width equal to component width. It is permissible to decrease this to as low as 85% of component width but it is not advisable to go below this. * Pad overlap 0.5mm beneath component. * Pad extension 0.5mm beyond components for reflow and 1.0mm for wave soldering. REFLOW SOLDERING D2 D1 D3 D4 D5 Dimensions in millimeters (inches) Case Size 0402 0603 0805 1206 1210 1808 1812 1825 2220 2225 D1 D2 D3 D4 D5 1.70 (0.07) 2.30 (0.09) 3.00 (0.12) 4.00 (0.16) 4.00 (0.16) 5.60 (0.22) 5.60 (0.22) 5.60 (0.22) 6.60 (0.26) 6.60 (0.26) 0.60 (0.02) 0.80 (0.03) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04)) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 0.50 (0.02) 0.70 (0.03) 1.00 (0.04) 2.00 (0.09) 2.00 (0.09) 3.60 (0.14) 3.60 (0.14) 3.60 (0.14) 4.60 (0.18) 4.60 (0.18) 0.60 (0.02) 0.80 (0.03) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 0.50 (0.02) 0.75 (0.03) 1.25 (0.05) 1.60 (0.06) 2.50 (0.10) 2.00 (0.08) 3.00 (0.12) 6.35 (0.25) 5.00 (0.20) 6.35 (0.25) 41 Surface Mounting Guide MLC Chip Capacitors WAVE SOLDERING Case Size 0603 0805 1206 1210 D2 D1 D3 D4 D1 D2 D3 D4 D5 3.10 (0.12) 4.00 (0.15) 5.00 (0.19) 5.00 (0.19) 1.20 (0.05) 1.50 (0.06) 1.50 (0.06) 1.50 (0.06) 0.70 (0.03) 1.00 (0.04) 2.00 (0.09) 2.00 (0.09) 1.20 (0.05) 1.50 (0.06) 1.50 (0.06) 1.50 (0.06) 0.75 (0.03) 1.25 (0.05) 1.60 (0.06) 2.50 (0.10) D5 Dimensions in millimeters (inches) Component Spacing Preheat & Soldering For wave soldering components, must be spaced sufficiently far apart to avoid bridging or shadowing (inability of solder to penetrate properly into small spaces). This is less important for reflow soldering but sufficient space must be allowed to enable rework should it be required. The rate of preheat should not exceed 4C/second to prevent thermal shock. A better maximum figure is about 2C/second. For capacitors size 1206 and below, with a maximum thickness of 1.25mm, it is generally permissible to allow a temperature differential from preheat to soldering of 150C. In all other cases this differential should not exceed 100C. For further specific application or process advice, please consult AVX. 1.5mm (0.06) 1mm (0.04) 1mm (0.04) 42 Cleaning Care should be taken to ensure that the capacitors are thoroughly cleaned of flux residues especially the space beneath the capacitor. Such residues may otherwise become conductive and effectively offer a low resistance bypass to the capacitor. Ultrasonic cleaning is permissible, the recommended conditions being 8 Watts/litre at 20-45 kHz, with a process cycle of 2 minutes vapor rinse, 2 minutes immersion in the ultrasonic solvent bath and finally 2 minutes vapor rinse. Surface Mounting Guide MLC Chip Capacitors APPLICATION NOTES General Good solderability is maintained for at least twelve months, provided the components are stored in their "as received" packaging at less than 40C and 70% RH. Surface mounting chip multilayer ceramic capacitors are designed for soldering to printed circuit boards or other substrates. The construction of the components is such that they will withstand the time/temperature profiles used in both wave and reflow soldering methods. Solderability Handling Terminations to be well soldered after immersion in a 60/40 tin/lead solder bath at 235 5C for 21 seconds. Chip multilayer ceramic capacitors should be handled with care to avoid damage or contamination from perspiration and skin oils. The use of tweezers or vacuum pick ups is strongly recommended for individual components. Bulk handling should ensure that abrasion and mechanical shock are minimized. Taped and reeled components provides the ideal medium for direct presentation to the placement machine. Any mechanical shock should be minimized during handling chip multilayer ceramic capacitors. Storage Leaching Terminations will resist leaching for at least the immersion times and conditions shown below. Termination Type Nickel Barrier Solder Solder Tin/Lead/Silver Temp. C 60/40/0 2605 Immersion Time Seconds 301 Preheat Recommended Soldering Profiles Reflow 300 Natural Cooling Preheat Solder Temp. 250 200 220C to 250C 150 Soldering 100 50 0 1min 10 sec. max 1min (Minimize soldering time) Wave Preheat Natural Cooling 250 Solder Temp. Mildly activated rosin fluxes are preferred. The minimum amount of solder to give a good joint should be used. Excessive solder can lead to damage from the stresses caused by the difference in coefficients of expansion between solder, chip and substrate. AVX terminations are suitable for all wave and reflow soldering systems. If hand soldering cannot be avoided, the preferred technique is the utilization of hot air soldering tools. Cooling 300 200 It is important to avoid the possibility of thermal shock during soldering and carefully controlled preheat is therefore required. The rate of preheat should not exceed 4C/second and a target figure 2C/second is recommended. Although an 80C to 120C temperature differential is preferred, recent developments allow a temperature differential between the component surface and the soldering temperature of 150C (Maximum) for capacitors of 1210 size and below with a maximum thickness of 1.25mm. The user is cautioned that the risk of thermal shock increases as chip size or temperature differential increases. T 230C to 250C 150 100 50 0 1 to 2 min 3 sec. max (Preheat chips before soldering) T/maximum 150C Natural cooling in air is preferred, as this minimizes stresses within the soldered joint. When forced air cooling is used, cooling rate should not exceed 4C/second. Quenching is not recommended but if used, maximum temperature differentials should be observed according to the preheat conditions above. Cleaning Flux residues may be hygroscopic or acidic and must be removed. AVX MLC capacitors are acceptable for use with all of the solvents described in the specifications MIL-STD202 and EIA-RS-198. Alcohol based solvents are acceptable and properly controlled water cleaning systems are also acceptable. Many other solvents have been proven successful, and most solvents that are acceptable to other components on circuit assemblies are equally acceptable for use with ceramic capacitors. 43 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: AVX: 08055E103MAT2A 08055E103ZAT2A 08055E104MAT2A 08055E104ZAT2A 08055E104ZAT4A 08055E473MAT2A 08055E473ZAT2A 12063E334MAT2A 12063E334ZAT2A 12065E103MAT2A 12065E104MAT2A 12065E104ZAT2A 12065E184MAT2A 12065E224MAT2A 12065E224MAT4A 12065E224ZAT2A 12065E274MAT2A 12065E334MAT2A 12065E334ZAT2A 12065E474MAT2A 12105E224MAT2A 12105E224ZAT2A 12105E334MAT2A 12105E334ZAT2A 12105E474MAT2A 12103E334ZAT2A 18125E105MAT2A 18125E105ZAT2A 18125E474MAT2A 06033E103ZAT2A 06033E473MAT2A 08053E104MAT4A 08053E104ZAT2A 08055E683MAT2A 12065E334MAT4A 18255E105MAT2A 18123E105ZAT2A 12105E394MAT2A 06035E103MAT2A 08053E224MAT2A 08055E104MAT4A 12065E473MAT2A 18125E474ZAT2A 12103E684MAT2A 08053E103MAT4A 12105E154MAT2A 12063E104ZAT2A 08055E334MAT2A 12063E104MAT2A 12103E334MAT2A 12105E473MAT2A 06033E103MAT2A 08055E103MAT4A 08053E823MAT2A 08055E333MAT2A 06033E102MAT2A 12105E104MAT4A 06035E223MAT2A 06033E473ZAT2A 06033E333MAT2A 12065E154MAT2A 08055E153MAT4A 12103E684MAT4A 12065E184ZAT2A 18125E102MAT2A 18123E225ZAT2A 18125E105MAT4A 08055E393MAT2A 08055E333MAT4A 06033E223ZAT2A 12065E104ZAT4A 08053E103ZAT2A 06035E223ZAT4A 08055E223MAT2A 12105E474ZAT2A 18255E224MAT2A 12103E224ZAT2A 08053E473MAT2A 05083E104ZAT2A 06035E103ZAT2A 06035E223ZAT2A 12065E103ZAT2A 12105E103MAT2A 12105E474MAT4A 18125E104MAT2A 12105E104ZAT4A 18255E105ZAT2A 12103E474ZAT2A 12065E333MAT2A 18125E105ZAT4A 08053E104MAT2A 08055E153MAT2A 06035E273MAT4A 18085E104ZAT2A 12103E474MAT2A 12065E124MAT2A 18125E334MAT2A 12065E153MAT2A 06033E223ZAT4A 12103E184ZAT2A