DB,DBQ,DGV,DW,ORPWPACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
P0
P1
P2
P3
GND
VCC
SDA
SCL
INT
P7
P6
P5
P4
RGVPACKAGE
(TOP VIEW)
16
6 8
2
10 P7
P5
4
3
1
75
12
11
9
131415
SDA
A0
A1
P6
INT
SCL
P3
GND
P4
A2
P0
P1
P2
RGTPACKAGE
(TOP VIEW)
16
6 8
2
10 P7
P5
4
3
1
75
12
11
9
131415
SDA
A0
A1
P6
INT
SCL
P3
GND
P4
A2
P0
P1
P2
VCC
VCC
PCA9534A
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SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
REMOTE 8-BIT I
2
C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
Check for Samples: PCA9534A
1FEATURES
• Low Standby Current Consumption of • Polarity Inversion Register
1mA Max • Internal Power-On Reset
• I2C to Parallel Port Expander • Power-Up With All Channels Configured as
• Open-Drain Active-Low Interrupt Output Inputs
• Operating Power-Supply Voltage Range of • No Glitch on Power-Up
2.3 V to 5.5 V • Noise Filter on SCL/SDA Inputs
• 5-V Tolerant I/O Ports • Latched Outputs With High-Current Drive
• 400-kHz Fast I2C Bus Maximum Capability for Directly Driving LEDs
• Three Hardware Address Pins Allow Up to • Latch-Up Performance Exceeds 100 mA Per
Eight Devices on the I2C/SMBus JESD 78, Class II
• Allows Up to 16 Devices on the I2C/SMBus • ESD Protection Exceeds JESD 22
When Used in Conjunction with the PCA9534 – 2000-V Human-Body Model (A114-A)
See Table 1 for I2C Expander offerings – 200-V Machine Model (A115-A)
• Input/Output Configuration Register – 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock
(SCL), serial data (SDA)].
The PCA9534A consists of one 8-bit configuration (input or output selection), input port, output port, and polarity
inversion (active high or active low) register. At power on, the I/Os are configured as inputs. However, the system
master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each
input or output is kept in the corresponding input or output register. The polarity of the input port register can be
inverted with the polarity inversion register. All registers can be read by the system master.
The system master can reset the PCA9534A in the event of a timeout or other improper operation by utilizing the
power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine.
The PCA9534A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
input port register state and is used to indicate to the system master that an input state has changed.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9534A can remain a simple slave device.
The device's outputs (latched) have high-current drive capability for directly driving LEDs. It has low current
consumption.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus.
The PCA9534A is pin-to-pin and I2C address compatible with the PCF8574A. However, software changes are
required due to the enhancements in the PCA9534A over the PCF8574A.
The PCA9534A is a low-power version of the PCA9554A. The only difference between the PCA9534A and
PCA9554A is that the PCA9534A eliminates an internal I/O pullup resistor, which dramatically reduces power
consumption in the standby mode when the I/Os are held low.
The PCA9534A and PCA9534 are identical, except for their fixed I2C address. This allows for up to 16 of these
devices (8 of each) on the same I2C bus.
ORDERING INFORMATION
TAPACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGT Reel of 3000 PCA9534ARGTR ZVJ
QFN – RGV Reel of 2500 PCA9534ARGVR PD534A
QSOP – DBQ Reel of 2500 PCA9534ADBQR PDA534A
Tube of 40 PCA9534ADW
SOIC – DW PCA9534A
Reel of 2000 PCA9534ADWR
–40°C to 85°C Reel of 2000 PCA9534ADBR
SSOP – DB PDA534A
Tube of 80 PCA9534ADB
Tube of 90 PCA9534APW
TSSOP – PW PD534A
Reel of 2000 PCA9534APWR
TVSOP – DGV Reel of 2000 PCA9534ADGVR PD534A
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
Table 1. I2C Expander offerings
MAX VCC NO. OF INTERRUPT RESET CONFIGURATION 5-V PUSH-PULL OPEN-DRAIN
I2C
DEVICE COMMENT
FREQUENCY RANGE GPIOs OUTPUT INPUT REGISTERS TOLERANT I/O TYPE I/O TYPE
ADDRESS
Power on reset, tf(fall time) > 100 ms and tr(ramp time) <
TCA6408 400 0100 00x 1.65 to 5.5 8 Yes Yes Yes Yes Yes No 10 ms
Unrestricted power on reset ramp/fall time. Both tf(fall
TCA6408 400 0100 00x 1.65 to 5.5 8 Yes Yes Yes Yes Yes No time) and TRT (ramp time) can be between 0.1 ms and
2000 ms
Power on reset, tf(fall time) > 100 ms and TRT (ramp
TCA6416 400 0100 00x 1.65 to 5.5 16 Yes Yes Yes Yes Yes No time) < 10 ms
Unrestricted power on reset ramp/fall time. Both tf(fall
TCA6416A 400 0100 00x 1.65 to 5.5 16 Yes Yes Yes Yes Yes No time) and TRT (ramp time) can be between 0.1 ms and
2000ms
Power on reset, tf(fall time) > 100 ms and TRT (ramp
TCA6424 400 0100 00x 1.65 to 5.5 24 Yes Yes Yes Yes Yes No time) < 10 ms
TCA9535 400 0100 xxx 1.65 to 5.5 16 Yes No Yes Yes Yes No
TCA9539 400 1110 1xx 1.65 to 5.5 16 Yes Yes Yes Yes Yes No
TCA9555 400 0100 xxx 1.65 to 5.5 16 Yes No Yes Yes Yes No
Yes Yes One open drain output; eight push pull outputs
PCA6107 400 0011 xxx 2.3 to 5.5 8 Yes Yes Yes Yes P1―P7 bits P0 bit
PCA9534 has a different slave address as the PCA9534A,
allowing up to 16 devices '9534 type devices on the same
PCA9534 400 0100 xxx 2.3 to 5.5 8 Yes No Yes Yes Yes No I2C bus
PCA9534A has a different slave address as the PCA9534,
allowing up to 16 devices '9534 type devices on the same
PCA9534A 400 0111 xxx 2.3 to 5.5 8 Yes No Yes Yes Yes No I2C bus
PCA9535 400 0100 xxx 2.3 to 5.5 16 Yes No Yes Yes Yes No
PCA9536 400 1000 001 2.3 to 5.5 4 No No Yes Yes Yes No
PCA9538 400 1110 0xx 2.3 to 5.5 8 Yes Yes Yes Yes Yes No
PCA9539 400 1110 1xx 2.3 to 5.5 16 Yes Yes Yes Yes Yes No
PCA9554 400 0100 xxx 2.3 to 5.5 8 Yes No Yes Yes Yes No
PCA9554A 400 0111 xxx 2.3 to 5.5 8 Yes No Yes Yes Yes No
PCA9555 400 0100 xxx 2.3 to 5.5 16 Yes No Yes Yes Yes No
PCA9557 400 0011 xxx 2.3 to 5.5 8 No Yes Yes Yes Yes Yes
PCA8574 has a different slave address as the PCA8574A,
allowing up to 16 devices '9534 type devices on the same
PCF8574 400 0100 xxx 2.5 to 6.0 8 Yes No No Yes Yes No I2C bus
PCA8574A has a different slave address as the PCA8574,
allowing up to 16 devices '9534 type devices on the same
PCF8574A 400 0111 xxx 2.5 to 6.0 8 Yes No No Yes Yes No I2C bus
PCF8575 400 0100 xxx 2.5 to 5.5 16 Yes No No Yes Yes No
PCF8575C 400 0100 xxx 4.5 to 5.5 16 Yes No No Yes No Yes
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
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14
I/O
Port
Shift
Register 8 Bits
LP Filter
Interrupt
Logic
Input
Filter
15
Power-On
Reset Read Pulse
Write Pulse
2
1
13
16
8
GND
VCC
SDA
SCL
A1
A0
INT
I2C Bus
Control
P7−P0
3
A2
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
Table 2. TERMINAL FUNCTIONS
NO.
QSOP (DBQ),
SOIC (DW), QFN (RGT) NAME DESCRIPTION
SSOP (DB), AND
TSSOP (PW), AND QFN (RGV)
TVSOP (DGV)
1 15 A0 Address input. Connect directly to VCC or ground.
2 16 A1 Address input. Connect directly to VCC or ground.
3 1 A2 Address input. Connect directly to VCC or ground.
4 2 P0 P-port input/output. Push-pull design structure.
5 3 P1 P-port input/output. Push-pull design structure.
6 4 P2 P-port input/output. Push-pull design structure.
7 5 P3 P-port input/output. Push-pull design structure.
8 6 GND Ground
9 7 P4 P-port input/output. Push-pull design structure.
10 8 P5 P-port input/output. Push-pull design structure.
11 9 P6 P-port input/output. Push-pull design structure.
12 10 P7 P-port input/output. Push-pull design structure.
13 11 INT Interrupt output. Connect to VCC through a pullup resistor.
14 12 SCL Serial clock bus. Connect to VCC through a pullup resistor.
15 13 SDA Serial data bus. Connect to VCC through a pullup resistor.
16 14 VCC Supply voltage
LOGIC DIAGRAM (POSITIVE LOGIC)
A. Pin numbers shown are for DB, DBQ, DGV, DW, or PW package.
B. All I/Os are set to inputs at reset.
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Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity
Pulse
Data From
Shift Register
Output Port
Register
Configuration
Register
Input Port
Register
Polarity
Inversion
Register
Polarity
Register Data
Input Port
Register Data
GND
ESD Protection
Diode
P0 to P7
VCC
Output Port
Register Data
Q1
Q2
D
CK
FF
Q
Q
D
CK
FF
Q
Q
D
CK
FF
Q
Q
D
CK
FF
Q
Q
To INT
PCA9534A
www.ti.com
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
SIMPLIFIED SCHEMATIC OF P0 TO P7
A. At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input
voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address byte
is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 2).
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SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Figure 1. Definition of Start and Stop Conditions
Figure 2. Bit Transfer
Figure 3. Acknowledgment on I2C Bus
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0 0 0 0 B1 B000
PCA9534A
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SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
Table 3. Interface Definition
BIT
BYTE 7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C slave address L H H H A2 A1 A0 R/W
Px I/O data bus P7 P6 P5 P4 P3 P2 P1 P0
Device Address
Figure 4 shows the address byte of the PCA9534A.
Figure 4. PCA9534A Address
Table 4. Address Reference
INPUTS I2C BUS SLAVE ADDRESS
A2 A1 A0
L L L 56 (decimal), 38 (hexadecimal)
L L H 57 (decimal), 39 (hexadecimal)
L H L 58 (decimal), 3A (hexadecimal)
L H H 59 (decimal), 3B (hexadecimal)
H L L 60 (decimal), 3C (hexadecimal)
H L H 61 (decimal), 3D (hexadecimal)
H H L 62 (decimal), 3E (hexadecimal)
H H H 63 (decimal), 3F (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte which is
stored in the control register in the PCA9534A. Two bits of this command byte state the operation (read or write)
and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can
be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
Figure 5. Control Register Bits
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SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
Table 5. Command Byte
CONTROL COMMAND POWER-UP
REGISTER BITS REGISTER PROTOCOL
BYTE (HEX) DEFAULT
B1 B0
0 0 0x00 Input Port Read byte xxxx xxxx
0 1 0x01 Output Port Read/write byte 1111 1111
1 0 0x02 Polarity Inversion Read/write byte 0000 0000
1 1 0x03 Configuration Read/write byte 1111 1111
Register Descriptions
The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the
input port register will be accessed next.
Table 6. Register 0 (Input Port Register)
BIT I7 I6 I5 I4 I3 I2 I1 I0
DEFAULT XXXXXXXX
The output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 7. Register 1 (Output Port Register)
BIT O7 O6 O5 O4 O3 O2 O1 O0
DEFAULT 11111111
The polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained.
Table 8. Register 2 (Polarity Inversion Register)
BIT N7 N6 N5 N4 N3 N2 N1 N0
DEFAULT 00000000
The configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 9. Register 3 (Configuration Register)
BIT C7 C6 C5 C4 C3 C2 C1 C0
DEFAULT 11111111
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9534A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9534A registers and
I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and
then back up to the operating voltage for a power-reset cycle.
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SCL
Start Condition
Data 1 Valid
SDA
Write to Port
Data Out
From Port
R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data 11A20 1S 11 A1 A0 0 A 0000000 A A P
tpv
Data to PortCommand ByteSlave Address
Data1/0A20 1S 11 A1 A0 0 A 1000000 A A P
SCL
SDA
Data to
Register
Start Condition R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data to RegisterCommand ByteSlave Address
PCA9534A
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SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to VCC.
Bus Transactions
Data is exchanged between the master and PCA9534A through write and read commands.
Writes
Data is transmitted to the PCA9534A by sending the device address and setting the least-significant bit to a logic
0 (see Figure 4 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte (see Figure 6 and Figure 7). There is no limitation on the
number of data bytes sent in one write transmission.
Figure 6. Write to Output Port Register
<br/>
Figure 7. Write to Configuration or Polarity Inversion Registers
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A20 1S 11 A1 A0 0 A A
Data from Register
Slave Address
Slave Address
R/W
ACK From
Slave
Command Byte
ACK From
Slave
S A20 1 11 A1 A0
R/W
1 A Data A
ACK From
Master
Data
Data from Register NACK From
Master
NA P
Last Byte
ACK From
Slave
SCL
SDA
INT
Start
Condition
R/W
Read From
Port
Data Into
Port
Stop
Condition
ACK From
Master
NACK From
Master
ACK From
Slave
Data From Port
Slave Address Data From Port
1 98765432
A2
01
S1
1A1 A0 1AData 1 Data 4
A NA P
Data 2 Data 3 Data 4
tiv
tph tps
tir
Data 5
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
Reads
The bus master first must send the PCA9534A address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9534A (see Figure 8 and Figure 9). After
a restart, the value of the register defined by the command byte matches the register being accessed when the
restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation
on the number of data bytes received in one read transmission, but when the final byte is received, the bus
master must not acknowledge the data.
Figure 8. Read From Register
<br/>
A. This figure assumes that the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a stop condition.
C. This figure eliminates the command byte transfer, a restart and slave address call between the initial slave address
call and the actual data transfer from the P Port. See Figure 8 for these details.
Figure 9. Read Input Port Register
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SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 6 V
VIInput voltage range(2) –0.5 6 V
VOOutput voltage range(2) –0.5 6 V
IIK Input clamp current VI< 0 –20 mA
IOK Output clamp current VO< 0 –20 mA
IIOK Input/output clamp current VO< 0 or VO> VCC ±20 mA
IOL Continuous output low current VO= 0 to VCC 50 mA
IOH Continuous output high current VO= 0 to VCC –50 mA
Continuous current through GND –250
ICC mA
Continuous current through VCC 160
DB package 82
DBQ package 90
DGV package 86
DW package 46
qJA Package thermal impedance(3) °C/W
N package 67
PW package 88
RGT package TBD
RGV package 51
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VCC Supply voltage 2.3 5.5 V
SCL, SDA 0.7 × VCC 5.5
VIH High-level input voltage V
A2–A0, P7–P0 2 5.5
SCL, SDA –0.5 0.3 × VCC
VIL Low-level input voltage V
A2–A0, P7–P0 –0.5 0.8
IOH High-level output current P7–P0 –10 mA
IOL Low-level output current P7–P0 25 mA
TAOperating free-air temperature –40 85 °C
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VIK Input diode clamp voltage II= –18 mA 2.3 V to 5.5 V –1.2 V
VPOR Power-on reset voltage VI= VCC or GND, IO= 0 VPOR 1.5 1.65 V
2.3 V 1.8
3 V 2.6
IOH = –8 mA 4.5 V 4.1
4.75 V 4.1
VOH P-port high-level output voltage(2) V
2.3 V 1.7
3 V 2.5
IOH = –10 mA 4.5 V 4
4.75 V 4
SDA VOL = 0.4 V 2.3 V to 5.5 V 3 8
2.3 V 8 10
3 V 8 14
VOL = 0.5 V 4.5 V 8 17
4.75 V 8 35
IOL P port(3) mA
2.3 V 10 13
3 V 10 19
VOL = 0.7 V 4.5 V 10 24
4.75 V 10 45
INT VOL = 0.4 V 2.3 V to 5.5 V 3 10
SCL, SDA ±1
IIVI= VCC or GND 2.3 V to 5.5 V mA
A2–A0 ±1
IIH P port VI= VCC 2.3 V to 5.5 V 1 mA
IIL P port VI= GND 2.3 V to 5.5 V –1 mA
5.5 V 104 175
VI= VCC or GND, IO= 0, 3.6 V 50 90
I/O = inputs, fscl = 400 kHz 2.7 V 20 65
Operating mode 5.5 V 60 150
VI= VCC or GND, IO= 0,
ICC 3.6 V 15 40 mA
I/O = inputs, fscl = 100 kHz 2.7 V 8 20
5.5 V 0.25 1
VI= GND, IO= 0,
Standby mode 3.6 V 0.2 0.9
I/O = inputs, fscl = 0 kHz 2.7 V 0.1 0.8
One input at VCC – 0.6 V, 2.3 V to 5.5 V 1.5
Other inputs at VCC or GND
Additional current in standby
ΔICC mA
mode All LED I/Os at VI= 4.3 V, 5.5 V 1
fscl = 0 kHz
CISCL VI= VCC or GND 2.3 V to 5.5 V 4 5 pF
SDA 5.5 6.5
Cio VIO = VCC or GND 2.3 V to 5.5 V pF
P port 8 9.5
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA= 25°C.
(2) The total current sourced by all I/Os must be limited to 85 mA.
(3) Each I/O must be externally limited to a maximum of 25 mA, and the P port (P7–P0) must be limited to a maximum current of 200 mA.
12 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
PCA9534A
www.ti.com
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
I2C INTERFACE TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE FAST MODE
I2C BUS I2C BUS UNIT
MIN MAX MIN MAX
fscl I2C clock frequency 0 100 0 400 kHz
tsch I2C clock high time 4 0.6 ms
tscl I2C clock low time 4.7 1.3 ms
tsp I2C spike time 50 50 ns
tsds I2C serial-data setup time 250 100 ns
tsdh I2C serial-data hold time 0 0 ns
ticr I2C input rise time 1000 20 + 0.1Cb(1) 300 ns
ticf I2C input fall time 300 20 + 0.1Cb(1) 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 300 20 + 0.1Cb(1) 300 ns
tbuf I2C bus free time between stop and start 4.7 1.3 ms
tsts I2C start or repeated start condition setup 4.7 0.6 ms
tsth I2C start or repeated start condition hold 4 0.6 ms
tsps I2C stop condition setup 4 0.6 ms
tvd(data) Valid data time SCL low to SDA output valid 300 50 ns
ACK signal from SCL low to
tvd(ack) Valid data time of ACK condition 0.3 3.45 0.1 0.9 ms
SDA (out) low
CbI2C bus capacitive load 400 400 ns
(1) Cb= total capacitive of one bus in pF
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted) (see Figure 11 and Figure 12)
STANDARD MODE FAST MODE
FROM TO I2C BUS I2C BUS
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX
tiv Interrupt valid time P port INT 4 4 ms
tir Interrupt reset delay time SCL INT 4 4 ms
tpv Output data valid SCL P7–P0 200 200 ns
tps Input data setup time P port SCL 100 100 ns
tph Input data hold time P port SCL 1 1 ms
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): PCA9534A
0
5
10
15
20
25
30
35
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
ICC – Supply Current – nA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
SCL = VCC
0
5
10
15
20
25
30
35
40
45
50
55
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
ICC – Supply Current – µA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
fSCL = 400 kHz
I/Os unloaded
0
50
100
150
200
250
300
350
400
450
500
550
600
0 1 2 3 4 5 6 7 8
Number of I/Os Held Low
ICC – Supply Current – µA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
0
10
20
30
40
50
60
70
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
ICC – Supply Current – µA
fSCL = 400 kHz
I/Os unloaded
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
TYPICAL CHARACTERISTICS
SUPPLY CURRENT QUIESCENT SUPPLY CURRENT
vs vs
TEMPERATURE TEMPERATURE
SUPPLY CURRENT SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE NUMBER OF I/Os HELD LOW
14 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 85°C
0
25
50
75
100
125
150
175
200
225
250
275
300
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
VOL – Output Low Voltage – mV
VCC = 5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
0
5
10
15
20
25
30
35
40
45
50
55
60
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 85°C
PCA9534A
www.ti.com
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
TYPICAL CHARACTERISTICS (continued)
I/O OUTPUT LOW VOLTAGE I/O SINK CURRENT
vs vs
TEMPERATURE OUTPUT LOW VOLTAGE
I/O SINK CURRENT I/O SINK CURRENT
vs vs
OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): PCA9534A
0
5
10
15
20
25
30
35
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 85°C
0
25
50
75
100
125
150
175
200
225
250
275
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
(VCC – VOH) – Output High Voltage – mV
VCC = 5 V, IOL = 10 mA
VCC = 2.5 V, IOL = 10 mA
VCC = 5 V, IOL = 1 mA
VCC = 2.5 V, IOL = 1 mA
0
5
10
15
20
25
30
35
40
45
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
I/O OUTPUT HIGH VOLTAGE I/O SOURCE CURRENT
vs vs
TEMPERATURE OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT I/O SOURCE CURRENT
vs vs
OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE
16 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
0
1
2
3
4
5
6
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
VOH – Output High Voltage – V
IOH = –10 mA
IOH = –8 mA
TA= 25°C
PCA9534A
www.ti.com
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
TYPICAL CHARACTERISTICS (continued)
OUTPUT HIGH VOLTAGE
vs
SUPPLY VOLTAGE
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): PCA9534A
RL = 1 kΩ
VCC
CL = 50 pF
(see Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tPHL
tPLH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
Three Bytes for Complete
Device Programming
SDA LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDA
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Address
Bit 1
Address
Bit 6
BYTE DESCRIPTION
1 I2C address
2, 3 P-port data
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
18 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
A
A
A
A
S 0 1 1 1 A1A2 A0 1 Data 1 1 PData 2
Start
Condition 8 Bits
(One Data Byte)
From Port Data From PortSlave Address R/W
87654321
tir
tir
tsps
tiv
Address Data 1 Data 2
INT
Data
Into
Port
B
B
A
A
PnINT
R/W A
tir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
INT SCL
View B−BView A−A
tiv
RL = 4.7 kΩ
VCC
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
DUT INT
ACK
From Slave ACK
From Slave
PCA9534A
www.ti.com
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): PCA9534A
P0 A 0.7 × VCC
0.3 × VCC
SCL P3
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tpv
(see Note B)
Slave
ACK
Unstable
Data
Last Stable Bit
SDA
Pn
Pn
WRITE MODE (R/W = 0)
P0 A 0.7 × VCC
0.3 × VCC
SCL P3
0.7 × VCC
0.3 × VCC
tps tph
READ MODE (R/W = 1)
DUT
CL = 50 pF
(see Note A)
P-PORT LOAD CONFIGURATION
Pn 2 × VCC
500 W
500 W
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 12. P-Port Load Circuit and Voltage Waveforms
20 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
SDA
SCL
Start
ACK or Read Cycle
tw
tREC
RESET
0.3 y VCC
VCC/2
tRESET
Pn
RL = 1 kΩ
VCC
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
DUT SDA
P-PORT LOAD CONFIGURATION
VCC/2
tRESET
DUT
CL = 50 pF
(see Note A)
Pn 2 × VCC
500 W
500 W
PCA9534A
www.ti.com
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLincludes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, tr/tf≤30 ns.
C. I/Os are configured as inputs.
D. All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): PCA9534A
A2
A1
A0
SDA
SCL
INT
GND
GND
P6
P0
P1
P2
P3
P4
P5
P7
INT
GND
VCC
VCC
(5 V)
VCC 10 kΩ10 kΩ10 kΩ10 kΩ2 kΩ100 kΩ
( 3)X
100 kΩ
4.7 kΩ
Master
Controller
PCA9534A
INT
RESET
Subsystem 2
(e.g., Counter)
Subsystem 3
(e.g., Alarm System)
ALARM
Controlled Device
(e.g., CBT Device)
ENABLE
A
B
Subsystem 1
(e.g., Temperature Sensor)
SCL
SDA
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
APPLICATION INFORMATION
Figure 14 shows an application in which the PCA9534A can be used.
A. Device address is configured as 0111100 for this example.
B. P0, P2, and P3 are configured as outputs.
C. P1, P4, and P5 are configured as inputs.
D. P6 and P7 are not used and must be configured as outputs.
Figure 14. Typical Application
22 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
LED
LEDx
VCC
100 kW
VCC
LED
3.3 V 5 V
LEDx
VCC
VCC
Ramp-Up Re-Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VCC_RT VCC_RT
VCC_FT
VCC_TRR_GND
PCA9534A
www.ti.com
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
Minimizing ICC When the I/O Controls LEDs
When the I/Os are used to control LEDs, they normally are connected to VCC through a resistor as shown in
Figure 14. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The
supply current, ICC, increases as VIN becomes lower than VCC and is specified as ΔICC in Electrical
Characteristics.
For battery-powered applications, it is essential that the voltage of the I/O pins is greater than or equal to VCC
when the LED is off to minimize current consumption. Figure 15 shows a high-value resistor in parallel with the
LED. Figure 16 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain
the I/O VIN at or above VCC and prevents additional supply-current consumption when the LED is off.
Figure 15. High-Value Resistor in Parallel With the LED
Figure 16. Device Supplied by a Lower Voltage
Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9534A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 17 and Figure 18.
Figure 17. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): PCA9534A
VCC
Ramp-Up
Time to Re-Ramp
Time
Ramp-Down
VIN drops below POR levels
VCC_RT
VCC_FT
VCC_TRR_VPOR50
VCC
Time
VCC_GH
VCC_GW
PCA9534A
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
www.ti.com
Figure 18. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 10 specifies the performance of the power-on reset feature for PCA9534A for both types of power-on
reset.
Table 10. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES(1)
PARAMETER MIN TYP MAX UNIT
VCC_FT Fall rate See Figure 17 1 100 ms
VCC_RT Rise rate See Figure 17 0.01 100 ms
VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 17 0.001 ms
VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 18 0.001 ms
Level that VCCP can glitch down to, but not cause a functional
VCC_GH See Figure 19 1.2 V
disruption when VCCX_GW = 1 ms
Glitch width that will not cause a functional disruption when
VCC_GW See Figure 19 ms
VCCX_GH = 0.5 × VCCx
VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V
VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V
(1) TA= –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 19 and Table 10 provide more
information on how to measure these specifications.
Figure 19. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 20 and Table 10 provide more details on this specification.
24 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
VCC
VPOR
VPORF
Time
POR
Time
PCA9534A
www.ti.com
SCPS141F –SEPTEMBER 2006–REVISED JUNE 2010
Figure 20. VPOR
Interrupt Requirements
The expected performance of the interrupt feature is that INT is to be cleared (de-asserted) when the input
register is read or all inputs return to the last read values. INT is also de-asserted when both of the following
occur:
• The last I2C command byte (register pointer) written was 00h. This generally means the last operation with
the device was a read of the input register, but the command byte may have been written with 00h without
ever going on to read the Input register.
• Any other slave device on the I2C bus acknowledges an address byte with the R/W bit set high. This occurs
when reading any other valid device on the bus.
In order to prevent INT from de-asserting when another device is read on the I2C bus, the user needs to change
the command byte to something other than 00 (hex) after a read operation to the device.
Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): PCA9534A
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jun-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9534ADB ACTIVE SSOP DB 16 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCA9534ADBG4 ACTIVE SSOP DB 16 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCA9534ADBR ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCA9534ADBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCA9534ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCA9534ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCA9534ADW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCA9534ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCA9534ADWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCA9534ADWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCA9534APW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCA9534APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
PCA9534APWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCA9534APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
PCA9534ARGTR ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
PCA9534ARGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
PCA9534ARGVR ACTIVE VQFN RGV 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
PACKAGE OPTION ADDENDUM
www.ti.com 24-Jun-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9534ARGVRG4 ACTIVE VQFN RGV 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9534ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
PCA9534ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
PCA9534ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PCA9534APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCA9534ARGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9534ADBR SSOP DB 16 2000 367.0 367.0 38.0
PCA9534ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
PCA9534ADWR SOIC DW 16 2000 367.0 367.0 38.0
PCA9534APWR TSSOP PW 16 2000 367.0 367.0 35.0
PCA9534ARGTR QFN RGT 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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