ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com 14-/12-Bit, 65/125MSPS, Ultralow-Power ADC Check for Samples: ADS4122, ADS4125, ADS4142, ADS4145 FEATURES DESCRIPTION * The ADS412x/4x are lower sampling speed variants of the ADS41xx family of analog-to-digital converters (ADCs). These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications. 1 23 * * * * * * * Ultralow Power with 1.8V Single Supply: - 103mW Total Power at 65MSPS - 153mW Total Power at 125MSPS High Dynamic Performance: - SNR: 72.2dBFS at 170MHz - SFDR: 81dBc at 170MHz Dynamic Power Scaling with Sample Rate Output Interface: - Double Data Rate (DDR) LVDS with Programmable Swing and Strength - Standard Swing: 350mV - Low Swing: 200mV - Default Strength: 100 Termination - 2x Strength: 50 Termination - 1.8V Parallel CMOS Interface Also Supported Programmable Gain up to 6dB for SNR/SFDR Trade-Off DC Offset Correction Supports Low Input Clock Amplitude Down To 200mVPP Package: QFN-48 (7mm x 7mm) The ADS412x/4x have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance. The ADS412x/4x are available in a compact QFN-48 pacakge and are specified over the industrial temperature range (-40C to +85C). ADS412x/ADS414x Family Comparison WITH ANALOG INPUT BUFFERS FAMILY 65MSPS 125MSPS 160MSPS 250MSPS 200MSPS 250MSPS ADS412x 12-Bit Family ADS4122 ADS4125 ADS4126 ADS4129 -- ADS41B29 ADS414x 14-Bit Family ADS4142 ADS4145 ADS4146 ADS4149 -- ADS41B49 9-Bit -- -- -- -- -- ADS58B19 11-Bit -- -- -- -- ADS58B18 -- 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011, Texas Instruments Incorporated ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ADS4122 QFN-48 RGZ ADS4125 ADS4142 ADS4145 (1) (2) QFN-48 QFN-48 QFN-48 RGZ RGZ RGZ ECO PLAN (2) LEAD/BALL FINISH PACKAGE MARKING -40C to +85C GREEN (RoHS, no Sb/Br) Cu/NiPdAu AZ4122 -40C to +85C GREEN (RoHS, no Sb/Br) -40C to +85C GREEN (RoHS, no Sb/Br) -40C to +85C GREEN (RoHS, no Sb/Br) Cu/NiPdAu Cu/NiPdAu Cu/NiPdAu AZ4125 AZ4142 AZ4145 ORDERING NUMBER TRANSPORT MEDIA ADS4122IRGZR Tape and reel ADS4122IRGZT Tape and reel ADS4125IRGZR Tape and reel ADS4125IRGZT Tape and reel ADS4142IRGZR Tape and reel ADS4142IRGZT Tape and reel ADS4145IRGZR Tape and reel ADS4145IRGZT Tape and reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more information. The ADS412x/4x family is pin-compatible to the previous generation ADS6149 family; this architecture enables easy migration. However, there are some important differences between the generations, summarized in Table 1. Table 1. MIGRATING FROM THE ADS6149 FAMILY ADS6149 FAMILY ADS4145 FAMILY PINS Pin 21 is NC (not connected) Pin 21 is NC (not connected) Pin 23 is MODE Pin 23 is RESERVED in the ADS4145 family. It is reserved as a digital control pin for an (as yet) undefined function in the next-generation ADC series. SUPPLY AVDD is 3.3V AVDD is 1.8V DRVDD is 1.8V No change INPUT COMMON-MODE VOLTAGE VCM is 1.5V VCM is 0.95V SERIAL INTERFACE Protocol: 8-bit register address and 8-bit register data No change in protocol New serial register map EXTERNAL REFERENCE MODE Supported Not supported ADS61B49 FAMILY ADS41B29/B49/ADS58B18 FAMILY PINS Pin 21 is NC (not connected) Pin 21 is 3.3V AVDD_BUF (supply for the analog input buffers) Pin 23 is MODE Pin 23 is a digital control pin for the RESERVED function. Pin 23 functions as SNR Boost enable (B18 only). SUPPLY AVDD is 3.3V AVDD is 1.8V, AVDD_BUF is 3.3V DRVDD is 1.8V No change INPUT COMMON-MODE VOLTAGE VCM is 1.5V VCM is 1.7V SERIAL INTERFACE Protocol: 8-bit register address and 8-bit register data No change in protocol New serial register map EXTERNAL REFERENCE MODE Supported 2 Not supported Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VALUE UNIT Supply voltage range, AVDD -0.3 to 2.1 V Supply voltage range, DRVDD -0.3 to 2.1 V Voltage between AGND and DRGND -0.3 to 0.3 V 0 to 2.1 V Voltage between AVDD to DRVDD (when AVDD leads DRVDD) Voltage between DRVDD to AVDD (when DRVDD leads AVDD) INP, INM Voltage applied to input pins CLKP, CLKM (2), DFS, OE 0 to 2.1 V -0.3 to minimum (1.9, AVDD + 0.3) V -0.3 to AVDD + 0.3 V -0.3 to 3.9 V Operating free-air temperature range, TA -40 to +85 C Operating junction temperature range, TJ +125 C RESET, SCLK, SDATA, SEN Storage temperature range, TSTG -65 to +150 C ESD, human body model (HBM) 2 kV (1) (2) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|. This prevents the ESD protection diodes at the clock input pins from turning on. THERMAL INFORMATION ADS4122/25/42/45 THERMAL METRIC (1) RGZ UNITS 48 PINS JA Junction-to-ambient thermal resistance 29 JCtop Junction-to-case (top) thermal resistance n/a JB Junction-to-board thermal resistance 10 JT Junction-to-top characterization parameter 0.3 JB Junction-to-board characterization parameter 9 JCbot Junction-to-case (bottom) thermal resistance 1.1 (1) C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 3 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range, unless otherwise noted. ADS4122/5, ADS4142/5 MIN TYP MAX UNIT SUPPLIES AVDD Analog supply voltage 1.7 1.8 1.9 V DRVDD Digital supply voltage 1.7 1.8 1.9 V ANALOG INPUTS Differential input voltage range (1) 2 VPP VCM 0.05 V (2) 400 MHz Maximum analog input frequency with 1VPP input amplitude (2) 800 MHz Input common-mode voltage Maximum analog input frequency with 2VPP input amplitude CLOCK INPUT Input clock sample rate ADS4122/ADS4142, low-speed mode enabled by default 20 65 MSPS ADS4125/ADS4145, low-speed mode enabled 20 80 MSPS ADS4125/ADS4145, low-speed mode disabled >80 125 MSPS Input clock amplitude differential (VCLKP - VCLKM) Sine wave, ac-coupled 1.5 VPP LVPECL, ac-coupled 0.2 1.6 VPP LVDS, ac-coupled 0.7 VPP LVCMOS, single-ended, ac-coupled 1.8 V Input clock duty cycle Low-speed enabled 40 50 60 % Low-speed disabled 35 50 65 % DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DRGND RLOAD Differential load resistance between the LVDS output pairs (LVDS mode) TA Operating free-air temperature HIGH PERFORMANCE MODES Set the MODE 1 register bits to get best performance across sample clock and input signal frequencies. Register address = 03h, register data = 03h Mode 2 Set the MODE 2 register bit to get best performance at high input signal frequencies greater than 230MHz. Register address = 4Ah, register data = 01h 4 pF 100 +85 C (3) (4) (5) Mode 1 (1) (2) (3) (4) (5) -40 5 With 0dB gain. See the Gain section in the Application Information for relation between input voltage range and gain. See the Theory of Operation section in the Application Information. It is recommended to use these modes to obtain best performance. These modes can be set using the serial interface only. See the Serial Interface section for details on register programming. Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device Configuration section. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS4122/ADS4125 Typical values are at +25C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = -40C to TMAX = +85C, AVDD = 1.8V, and DRVDD = 1.8V. ADS4122 (65MSPS) PARAMETER TEST CONDITIONS MIN TYP Resolution SINAD (signal-to-noise and distortion ratio), LVDS SFDR THD 70.9 70.8 dBFS 70.7 70.6 dBFS 70.1 dBFS IMD Input overload recovery 67 70.2 68 fIN = 300MHz 68.8 69.6 dBFS fIN = 10MHz 70.8 70.7 dBFS fIN = 70MHz 70.8 70.7 dBFS fIN = 100MHz 70.6 70.3 dBFS 69.8 dBFS 66 70.1 67 fIN = 300MHz 68 69 dBFS fIN = 10MHz 86.5 86 dBc fIN = 70MHz 86 86 dBc fIN = 100MHz 87 82 dBc 81 dBc 70 85 71 fIN = 300MHz 72.5 77 dBc fIN = 10MHz 82.5 82 dBc fIN = 70MHz 84 83.5 dBc fIN = 100MHz 84 80.5 dBc 79.5 dBc fIN = 300MHz 72 75.5 dBc fIN = 10MHz 87 87 dBc fIN = 70MHz 88 86 dBc fIN = 100MHz 88 82 dBc 83 69.5 dBc 70 81 69.5 86 71 fIN = 300MHz 72.5 77 dBc fIN = 10MHz 86.5 86 dBc fIN = 70MHz 86 88 dBc fIN = 100MHz 87 85 dBc 81 dBc 70 85 71 fIN = 300MHz 85 82 dBc fIN = 10MHz 96 95 dBc fIN = 70MHz 96 95 dBc fIN = 100MHz 94 95 dBc 91 dBc fIN = 170MHz Two-tone intermodulation distortion Bits fIN = 70MHz fIN = 170MHz Worst spur (other than second and third harmonics) UNIT fIN = 100MHz fIN = 170MHz HD3 12 dBFS fIN = 170MHz HD2 MAX 71 fIN = 170MHz Third-harmonic distortion TYP 71.1 fIN = 170MHz Second-harmonic distortion MIN fIN = 10MHz fIN = 170MHz Total harmonic distortion MAX 12 SNR (signal-to-noise ratio), LVDS Spurious-free dynamic range ADS4125 (125MSPS) 76.5 92 76.5 fIN = 300MHz 88 88 dBc f1 = 100MHz, f2 = 105MHz, each tone at -7dBFS 90 87.5 dBFS Recovery to within 1% (of final value) for 6dB overload with sine-wave input 1 1 Clock cycles > 30 > 30 dB AC power-supply rejection ratio PSRR For 100mVPP signal on AVDD supply, up to 10MHz Effective number of bits ENOB fIN = 170MHz Differential nonlinearity DNL fIN = 170MHz Integrated nonlinearity INL fIN = 170MHz Copyright (c) 2011, Texas Instruments Incorporated 11.2 -0.85 11.2 0.2 1.5 0.3 3.5 -0.85 LSBs 0.2 1.5 LSBs 0.35 3.5 LSBs Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 5 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS4142/ADS4145 Typical values are at +25C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = -40C to TMAX = +85C, AVDD = 1.8V, and DRVDD = 1.8V. ADS4142 (65MSPS) PARAMETER TEST CONDITIONS MIN TYP Resolution SINAD (signal-to-noise and distortion ratio), LVDS SFDR THD 73.5 73.4 dBFS 73.2 73.1 dBFS 72.2 dBFS IMD Input overload recovery 70 71.3 dBFS fIN = 10MHz 73.5 73.2 dBFS fIN = 70MHz 73.3 73 dBFS fIN = 100MHz 73 72.6 dBFS 71.8 dBFS 68 72.3 69 fIN = 300MHz 69.2 70.6 dBFS fIN = 10MHz 87 86 dBc fIN = 70MHz 86.5 85.5 dBc fIN = 100MHz 87 82 dBc 81.5 dBc 71 85 72.5 fIN = 300MHz 72.5 77 dBc fIN = 10MHz 84 83 dBc fIN = 70MHz 84 83.5 dBc fIN = 100MHz 84 81 dBc 80 dBc fIN = 300MHz 72.5 75.5 dBc fIN = 10MHz 88 87 dBc fIN = 70MHz 87 85.5 dBc fIN = 100MHz 88 82 dBc 84 69.5 dBc 71 82.5 70.5 87 72.5 fIN = 300MHz 72.5 77 dBc fIN = 10MHz 87 86 dBc fIN = 70MHz 86.5 87 dBc fIN = 100MHz 87 85 dBc 81.5 dBc 71 85 72.5 fIN = 300MHz 85 84 dBc fIN = 10MHz 96 95 dBc fIN = 70MHz 95 95 dBc fIN = 100MHz 94 95 dBc 91 dBc 77.5 92 78.5 fIN = 300MHz 87 88 dBc f1 = 100MHz, f2 = 105MHz, each tone at -7dBFS 88.5 87.5 dBFS Recovery to within 1% (of final value) for 6dB overload with sine-wave input 1 1 Clock cycles > 30 > 30 dB PSRR For 100mVPP signal on AVDD supply, up to 10MHz Effective number of bits ENOB fIN = 170MHz Differential nonlinearity DNL fIN = 170MHz Integrated nonlinearity INL fIN = 170MHz Submit Documentation Feedback 72.4 70.5 AC power-supply rejection ratio 6 69 fIN = 300MHz fIN = 170MHz Two-tone intermodulation distortion Bits fIN = 70MHz fIN = 170MHz Worst spur (other than second and third harmonics) UNIT fIN = 100MHz fIN = 170MHz HD3 14 dBFS fIN = 170MHz HD2 MAX 73.7 fIN = 170MHz Third-harmonic distortion TYP 73.9 fIN = 170MHz Second-harmonic distortion MIN fIN = 10MHz fIN = 170MHz Total harmonic distortion MAX 14 SNR (signal-to-noise ratio), LVDS Spurious-free dynamic range ADS4145 (125MSPS) 11.5 -0.95 11.3 0.5 1.7 1.5 4.5 -0.95 LSBs 0.5 1.7 LSBs 1.5 4.5 LSBs Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Typical values are at +25C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = -40C to TMAX = +85C, AVDD = 1.8V, and DRVDD = 1.8V. ADS4122/ADS4142 (65MSPS) PARAMETER MIN TYP MAX ADS4125/ADS4145 (125MSPS) MIN TYP MAX UNIT ANALOG INPUTS Differential input voltage range 2.0 2.0 VPP Differential input resistance (at dc); see Figure 102 >1 >1 M 4 4 pF 550 550 MHz A/MSPS Differential input capacitance; see Figure 103 Analog input bandwidth Analog input common-mode current (per input pin) Common-mode output voltage VCM VCM output current capability 0.6 0.6 0.95 0.95 V 4 4 mA DC ACCURACY -15 Offset error Temperature coefficient of offset error 2.5 15 -15 2.5 0.003 Gain error as a result of internal reference inaccuracy alone EGREF Gain error of channel alone EGCHAN Temperature coefficient of EGCHAN -2 15 0.003 2 -2 2 -0.2 -0.2 0.001 0.001 mV mV/C -1 %FS %FS %/C POWER SUPPLY IAVDD Analog supply current 42 IDRVDD (1) Output buffer supply current LVDS interface with 100 external termination Low LVDS swing (200mV) 28.5 IDRVDD Output buffer supply current LVDS interface with 100 external termination Standard LVDS swing (350mV) 40 IDRVDD output buffer supply current (1) (2) CMOS interface (2) 8pF external load capacitance fIN = 2.5MHz 15 Analog power Digital power, LVDS interface, low LVDS swing Digital power CMOS interface (2) 8pF external load capacitance fIN = 2.5MHz 75 35.5 53 48 mA mA 57 mA mA 76 112 mW 52 66.5 mW 27 41.5 mW 10 Standby 105 (2) 62 23 Global power-down (1) 55 15 10 15 130 mW mW The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10pF. In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section in the Application Information). Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 7 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com DIGITAL CHARACTERISTICS Typical values are at +25C, AVDD = 1.8V, DRVDD = 1.8V, and 50% clock duty cycle, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = -40C to TMAX = +85C, AVDD = 1.8V, and DRVDD = 1.8V. ADS4122, ADS4125, ADS4142, ADS4145 PARAMETER TEST CONDITIONS MIN RESET, SCLK, SDATA, and SEN support 1.8V and 3.3V CMOS logic levels 1.3 OE only supports 1.8V CMOS logic levels 1.3 TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE) High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage V 0.4 V V 0.4 V High-level input current: SDATA, SCLK (1) VHIGH = 1.8V 10 A High-level input current: SEN VHIGH = 1.8V 0 A Low-level input current: SDATA, SCLK VLOW = 0V 0 A Low-level input current: SEN VLOW = 0V -10 A DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT) DRVDD - 0.1 High-level output voltage DRVDD Low-level output voltage 0 V 0.1 V DIGITAL OUTPUTS (LVDS INTERFACE: DA0P/M TO DA13P/M, DB0P/M TO DB13P/M, CLKOUTP/M) High-level output voltage (2) VODH Standard swing LVDS 270 +350 430 mV Low-level output voltage (2) VODL Standard swing LVDS -430 -350 -270 mV High-level output voltage (2) VODH Low swing LVDS +200 Low-level output voltage (2) VODL Low swing LVDS -200 Output common-mode voltage VOCM (1) (2) 8 0.85 1.05 mV mV 1.25 V SDATA and SCLK have an internal 180k pull-down resistor. With an external 100 termination. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com PIN CONFIGURATION (LVDS MODE) D10_D11_P D10_D11_M D8_D9_P D8_D9_M D6_D7_P D6_D7_M D4_D5_P D4_D5_M D2_D3_P D2_D3_M D0_D1_P D0_D1_M RGZ PACKAGE(1) QFN-48 (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 NC CLKOUTP 5 32 NC DFS 6 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 AVDD NC 33 RESERVED 34 4 AVDD 3 CLKOUTM NC OVR_SDOUT AVDD DRVDD AVDD 35 AGND 2 AGND DRVDD INP DRGND INM 36 AGND 1 VCM DRGND (1) The PowerPAD is connected to DRGND. Figure 1. ADS412x LVDS Pinout Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 9 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com D8_D9_M D6_D7_P D6_D7_M 45 44 43 42 41 D2_D3_M D8_D9_P 46 D2_D3_P D10_D11_M 47 D4_D5_P D10_D11_P 48 D4_D5_M D12_D13_P D12_D13_M RGZ PACKAGE(2) QFN-48 (TOP VIEW) 40 39 38 37 DRGND 1 36 DRGND NC 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 AVDD 32 6 RESERVED 5 DFS NC CLKOUTP AVDD D0_D1_M AVDD 33 AVDD 4 AGND CLKOUTM INM D0_D1_P AGND DRVDD 34 INP 35 3 VCM 2 AGND DRVDD OVR_SDOUT (2) The PowerPADTM is connected to DRGND. Figure 2. ADS414x LVDS Pinout 10 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com ADS414x, ADS412x Pin Assignments (LVDS Mode) PIN NAME PIN NUMBER # OF PINS FUNCTION AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply DESCRIPTION AGND 9, 12, 14, 17, 19, 25 6 I Analog ground CLKP 10 1 I Differential clock input, positive CLKM 11 1 I Differential clock input, negative INP 15 1 I Differential analog input, positive INM 16 1 I Differential analog input, negative VCM 13 1 O Outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input pins. RESET 30 1 I Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin. RESET has an internal 180k pull-down resistor. SCLK 29 1 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground. This pin has an internal 180k pull-down resistor. SDATA 28 1 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This pin has an internal 180k pull-down resistor. SEN 27 1 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and should be tied to AVDD. This pin has an internal 180k pull-up resistor to AVDD. OE 7 1 I Output buffer enable input, active high; this pin has an internal 180k pull-up resistor to DRVDD. DFS 6 1 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS/CMOS output interface type. See Table 5 for detailed information. RESERVED 23 1 I Digital control pin, reserved for future use CLKOUTP 5 1 O Differential output clock, true CLKOUTM 4 1 O Differential output clock, complement D0_D1_P Refer to Figure 1 and Figure 2 1 O Differential output data D0 and D1 multiplexed, true D0_D1_M Refer to Figure 1 and Figure 2 1 O Differential output data D0 and D1 multiplexed, complement D2_D3_P Refer to Figure 1 and Figure 2 1 O Differential output data D2 and D3 multiplexed, true D2_D3_M Refer to Figure 1 and Figure 2 1 O Differential output data D2 and D3 multiplexed, complement D4_D5_P Refer to Figure 1 and Figure 2 1 O Differential output data D4 and D5 multiplexed, true D4_D5_M Refer to Figure 1 and Figure 2 1 O Differential output data D4 and D5 multiplexed, complement D6_D7_P Refer to Figure 1 and Figure 2 1 O Differential output data D6 and D7 multiplexed, true D6_D7_M Refer to Figure 1 and Figure 2 1 O Differential output data D6 and D7 multiplexed, complement D8_D9_P Refer to Figure 1 and Figure 2 1 O Differential output data D8 and D9 multiplexed, true D8_D9_M Refer to Figure 1 and Figure 2 1 O Differential output data D8 and D9 multiplexed, complement D10_D11_P Refer to Figure 1 and Figure 2 1 O Differential output data D10 and D11 multiplexed, true D10_D11_M Refer to Figure 1 and Figure 2 1 O Differential output data D10 and D11 multiplexed, complement D12_D13_P Refer to Figure 1 and Figure 2 1 O Differential output data D12 and D13 multiplexed, true D12_D13_M Refer to Figure 1 and Figure 2 1 O Differential output data D12 and D13 multiplexed, complement OVR_SDOUT 3 1 O This pin functions as an out-of-range indicator after reset, when register bit READOUT = 0, and functions as a serial register readout pin when READOUT = 1. DRVDD 2, 35 2 I 1.8V digital and output buffer supply DRGND 1, 36, PAD 2 I Digital and output buffer ground NC Refer to Figure 1 and Figure 2 -- -- Copyright (c) 2011, Texas Instruments Incorporated Do not connect Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 11 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com PIN CONFIGURATION (CMOS MODE) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RGZ PACKAGE(3) QFN-48 (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND NC 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 AVDD 32 6 RESERVED 5 DFS AVDD CLKOUT NC NC AVDD 33 AVDD 4 AGND UNUSED AGND NC INP DRVDD 34 INM 35 3 AGND 2 VCM DRVDD OVR_SDOUT (3) The PowerPAD is connected to DRGND. Figure 3. ADS412x CMOS Pinout 12 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 RGZ PACKAGE(4) QFN-48 (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 DRGND 1 36 DRGND NC 31 NC OE 7 30 RESET AVDD 8 29 SCLK AGND 9 28 SDATA CLKP 10 27 SEN CLKM 11 26 AVDD AGND 12 25 AGND 13 14 15 16 17 18 19 20 21 22 23 24 AVDD 32 6 RESERVED 5 DFS AVDD CLKOUT NC D0 AVDD 33 AVDD 4 AGND UNUSED AGND D1 INP DRVDD 34 INM 35 3 AGND 2 VCM DRVDD OVR_SDOUT (4) The PowerPAD is connected to DRGND. Figure 4. ADS414x CMOS Pinout Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 13 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com ADS414x, ADS412x Pin Assignments (CMOS Mode) 14 PIN NAME PIN NUMBER # OF PINS FUNCTION AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply DESCRIPTION AGND 9, 12, 14, 17, 19, 25 6 I Analog ground CLKP 10 1 I Differential clock input, positive CLKM 11 1 I Differential clock input, negative INP 15 1 I Differential analog input, positive INM 16 1 I Differential analog input, negative VCM 13 1 O Outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input pins. RESET 30 1 I Serial interface RESET input. When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface section. When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin. RESET has an internal 180k pull-down resistor. SCLK 29 1 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground. This pin has an internal 180k pull-down resistor. SDATA 28 1 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This pin has an internal 180k pull-down resistor. SEN 27 1 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and should be tied to AVDD. This pin has an internal 180k pull-up resistor to AVDD. OE 7 1 I Output buffer enable input, active high; this pin has an internal 180k pull-up resistor to DRVDD. DFS 6 1 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS/CMOS output interface type. See Table 5 for detailed information. RESERVED 23 1 I Digital control pin, reserved for future use CLKOUT 5 1 O CMOS output clock D0 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D1 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D2 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D3 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D4 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D5 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D6 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D7 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D8 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D9 Refer to Figure 3 and Figure 4 1 O D10 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D11 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D12 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data D13 Refer to Figure 3 and Figure 4 1 O 12-bit/14-bit CMOS output data OVR_SDOUT 3 1 O This pin functions as an out-of-range indicator after reset, when register bit READOUT = 0, and functions as a serial register readout pin when READOUT = 1. 12-bit/14-bit CMOS output data DRVDD 2, 35 2 I 1.8V digital and output buffer supply DRGND 1, 36, PAD 2 I Digital and output buffer ground UNUSED 4 1 -- Unused pin in CMOS mode NC Refer to Figure 3 and Figure 4 -- -- Do not connect Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DDR LVDS Interface DRGND CLKP CLKOUTP CLOCKGEN CLKOUTM CLKM D0_D1_P D0_D1_M D2_D3_P D2_D3_M Low-Latency Mode (Default After Reset) INP INM 12-Bit ADC Sampling Circuit Common Digital Functions D4_D5_P DDR Serializer D4_D5_M D6_D7_P D6_D7_M D8_D9_P D8_D9_M Control Interface Reference VCM D10_D11_P D10_D11_M OVR_SDOUT DFS SEN SDATA SCLK RESET ADS412x OE Figure 5. ADS412x Block Diagram Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 15 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 AVDD www.ti.com AGND DRVDD DDR LVDS Interface DRGND CLKOUTP CLKP CLOCKGEN CLKOUTM CLKM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M Low-Latency Mode (Default After Reset) INP INM 14-Bit ADC Sampling Circuit Common Digital Functions D6_D7_P DDR Serializer D6_D7_M D8_D9_P D8_D9_M D10_D11_P D10_D11_M Control Interface Reference VCM D12_D13_P D12_D13_M OVR_SDOUT DFS SEN SDATA SCLK RESET ADS414x OE Figure 6. ADS414x Block Diagram 16 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TIMING CHARACTERISTICS Dn_Dn + 1_P Logic 0 VODL Logic 1 VODH Dn_Dn + 1_M VOCM GND (1) With external 100 termination. Figure 7. LVDS Output Voltage Levels TIMING REQUIREMENTS: LVDS and CMOS Modes (1) Typical values are at +25C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 125 MSPS, sine wave input clock, CLOAD = 5pF (2), and RLOAD = 100 (3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = -40C to TMAX = +85C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V. PARAMETER tA CONDITIONS Aperture delay Variation of aperture delay tJ MIN TYP MAX UNIT 0.6 0.8 1.2 ns Between two devices at the same temperature and DRVDD supply Aperture jitter Wakeup time ADC latency (4) 100 ps 100 fS rms Time to valid data after coming out of STANDBY mode 5 25 s Time to valid data after coming out of PDN GLOBAL mode 100 500 s Low-latency mode (default after reset) 10 Clock cycles Low-latency mode disabled (gain enabled, offset correction disabled) 16 Clock cycles Low-latency mode disabled (gain and offset correction enabled) 17 Clock cycles DDR LVDS MODE (5) (6) tSU Data setup time (3) (3) tH Data hold time tPDI Clock propagation delay Variation of tPDI (1) (2) (3) (4) (5) (6) (7) Data valid (7) to zero-crossing of CLKOUTP 2.3 3.0 ns Zero-crossing of CLKOUTP to data becoming invalid (7) 0.35 0.60 ns Input clock rising edge cross-over to output clock rising edge cross-over Sampling frequency 125MSPS 3 4.2 Between two devices at the same temperature and DRVDD supply 5.4 0.6 ns ns Timing parameters are ensured by design and characterization but are not production tested. CLOAD is the effective external single-ended load capacitance between each output pin and ground. RLOAD is the differential load resistance between the LVDS output pair. At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. Measurements are done with a transmission line of 100 characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. The LVDS timings are unchanged for low latency disabled and enabled. Data valid refers to a logic high of +100mV and a logic low of -100mV. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 17 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS: LVDS and CMOS Modes(1) (continued) Typical values are at +25C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 125 MSPS, sine wave input clock, CLOAD = 5pF(2), and RLOAD = 100(3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = -40C to TMAX = +85C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V. PARAMETER CONDITIONS MIN TYP MAX UNIT DDR LVDS MODE (continued) LVDS bit clock duty cycle Duty cycle of differential clock, (CLKOUTP - CLKOUTM) Sampling frequency 125MSPS 48 % tRISE, tFALL Data rise time, Data fall time Rise time measured from -100mV to +100mV Fall time measured from +100mV to -100mV Sampling frequency 125MSPS 0.14 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from -100mV to +100mV Fall time measured from +100mV to -100mV Sampling frequency 125MSPS 0.14 ns tOE Output enable (OE) to data delay Time to valid data after OE becomes active 50 PARALLEL CMOS MODE 100 ns (8) Data setup time Data valid (9) to 50% of CLKOUT rising edge 3.1 3.7 ns tHOLD Data hold time 50% of of CLKOUT rising edge to data becoming invalid (9) 3.2 4.0 ns tPDI Clock propagation delay Input clock rising edge cross-over to 50% of output clock rising edge Sampling frequency 125MSPS 4 5.5 Output clock duty cycle Duty cycle of output clock, CLKOUT Sampling frequency 125MSPS 47 % tSETUP 7 ns tRISE, tFALL Data rise time, Data fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD Sampling frequency 125MSPS 0.35 ns tCLKRISE, tCLKFALL Output clock rise time, Output clock fall time Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD Sampling frequency 125MSPS 0.35 ns tOE Output enable (OE) to data delay Time to valid data after OE becomes active 20 (8) (9) 18 40 ns Low latency mode enabled. Data valid refers to a logic high of 1.25V and a logic low of 0.54V. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Table 2. LVDS Timing Across Sampling Frequencies SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) MIN HOLD TIME (ns) TYP MAX MIN TYP 65 5.5 6.5 0.35 0.60 80 4.50 5.20 0.35 0.60 MAX Table 3. CMOS Timing Across Sampling Frequencies (Low Latency Enabled) TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK SAMPLING FREQUENCY (MSPS) MIN TYP 65 6.5 80 5.4 tSETUP (ns) tHOLD (ns) MAX MIN TYP 7.5 6.5 6.0 5.4 tPDI (ns) MAX MIN TYP MAX 7.5 4.0 5.5 7.0 6.0 4.0 5.5 7.0 Table 4. CMOS Timing Across Sampling Frequencies (Low Latency Disabled) TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK SAMPLING FREQUENCY (MSPS) tSETUP (ns) MIN tHOLD (ns) TYP MAX MIN tPDI (ns) TYP MAX MIN TYP MAX 65 6 7 7 8 4.0 5.5 7.0 80 4.8 5.5 5.7 6.5 4.0 5.5 7.0 125 2.5 3.2 3.5 4.3 4.0 5.5 7.0 Sample N N+3 N+2 N+1 N+4 N + 12 N + 11 N + 10 Input Signal tA CLKP Input Clock CLKM CLKOUTM CLKOUTP tPDI tH 10 Clock Cycles DDR LVDS (1) tSU (2) Output Data (DXP, DXM) E O N - 10 E O N-9 E O E N-8 O N-7 O E E O O E N-6 E O N+1 N E O E O N+2 tPDI CLKOUT tSU Parallel CMOS 10 Clock Cycles Output Data N - 10 N-9 N-8 (1) N-7 tH N-1 N N+1 (1) ADC latency in low-latency mode. At higher sampling frequencies, tDPI is greater than one clock cycle which then makes the overall latency = ADC latency + 1. (2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc). Figure 8. Latency Diagram Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 19 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com CLKM Input Clock CLKP tPDI CLKOUTP Output Clock CLKOUTM tSU Output Dn_Dn + 1_P Data Pair Dn_Dn + 1_M tSU tH Dn (1) Dn + 1 tH (1) (1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc. Figure 9. LVDS Mode Timing CLKM Input Clock CLKP tPDI Output Clock CLKOUT tSU Output Data Dn tH Dn (1) CLKM Input Clock CLKP tSTART tDV Output Data Dn Dn (1) Dn = bits D0, D1, D2, etc. Figure 10. CMOS Mode Timing 20 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com DEVICE CONFIGURATION The ADS412x/4x have several modes that can be configured using a serial programming interface, as described in Table 5, Table 6, and Table 7. In addition, the devices have two dedicated parallel pins for quickly configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors). Table 5. DFS: Analog Control Pin VOLTAGE APPLIED ON DFS DESCRIPTION (Data Format/Output Interface) 0, +100mV/-0mV Twos complement/DDR LVDS (3/8) AVDD 100mV Twos complement/parallel CMOS (5/8) AVDD 100mV Offset binary/parallel CMOS AVDD, +0mV/-100mV Offset binary/DDR LVDS Table 6. OE: Digital Control Pin VOLTAGE APPLIED ON OE DESCRIPTION 0 Output data buffers disabled AVDD Output data buffers enabled When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have any alternative functions. Keep SEN tied high and SCLK tied low on the board. Table 7. SDATA: Digital Control Pin VOLTAGE APPLIED ON SDATA DESCRIPTION 0 Normal operation Logic high Device enters standby AVDD (5/8) AVDD 3R (5/8) AVDD GND AVDD 2R (3/8) AVDD 3R (3/8) AVDD To Parallel Pin Figure 11. Simplified Diagram to Configure DFS Pin Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 21 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com SERIAL INTERFACE The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequency from 20MHz down to very low speeds (a few hertz) and also with non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways: 1. Either through hardware reset by applying a high pulse on RESET pin (of width greater than 10ns), as shown in Figure 12; or 2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low. Register Address SDATA A7 A6 A5 A4 A3 Register Data A2 A1 A0 D7 D6 D5 tSCLK D4 tDSU D3 D2 D1 D0 tDH SCLK tSLOADS tSLOADH SEN RESET Figure 12. Serial Interface Timing SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at +25C, minimum and maximum values across the full temperature range: TMIN = -40C to TMAX = +85C, AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted. PARAMETER MIN TYP > DC MAX UNIT 20 MHz fSCLK SCLK frequency (equal to 1/tSCLK) tSLOADS SEN to SCLK setup time 25 ns tSLOADH SCLK to SEN hold time 25 ns tDSU SDATA setup time 25 ns tDH SDATA hold time 25 ns 22 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Serial Register Readout The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially: 1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode and disables any further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of the register at address 0 cannot be read in the register readout mode. 2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read. 3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin. 4. The external controller can latch the contents at the falling edge of SCLK. 5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin. Register Address A[7:0] = 0x00 SDATA 0 0 0 0 0 0 Register Data D[7:0] = 0x01 0 0 0 0 0 0 0 0 0 1 SCLK SEN OVR_SDOUT (1) a) Enable Serial Readout (READOUT = 1) Register Address A[7:0] = 0x43 SDATA A7 A6 A5 A4 A3 A2 Register Data D[7:0] = XX (don't care) A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 0 SCLK SEN OVR_SDOUT (2) b) Read Contents of Register 0x43. This Register Has Been Initialized with 0x40 (device is put into global power-down mode). (1) The OVR_SDOUT pin finctions as OVR (READOUT = 0). (2) The OVR_SDOUT pin finctions as a serial readout (READOUT = 1). Figure 13. Serial Readout Timing Diagram Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 23 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com RESET TIMING CHARACTERISTICS Power Supply AVDD, DRVDD t1 RESET t3 t2 SEN NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET must be permanently tied high. Figure 14. Reset Timing Diagram RESET TIMING REQUIREMENTS Typical values at +25C and minimum and maximum values across the full temperature range: TMIN = -40C to TMAX = +85C, unless otherwise noted. PARAMETER t1 Power-on delay t2 Reset pulse width t3 (1) 24 TEST CONDITIONS MIN Delay from power-up of AVDD and DRVDD to RESET pulse active 1 Pulse width of active RESET signal that resets the serial registers 10 Delay from RESET disable to SEN active 100 TYP MAX UNIT ms ns 1 (1) s ns The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1s, the device could enter the parallel configuration mode briefly and then return back to serial interface mode. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com SERIAL REGISTER MAP Table 8 summarizes the functions supported by the serial interface. Table 8. Serial Interface Register Map (1) (1) REGISTER ADDRESS DEFAULT VALUE AFTER RESET A[7:0] (Hex) D[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0 00 00 0 0 0 0 0 0 RESET READOUT 01 00 0 0 03 00 0 0 0 0 0 HIGH PERF MODE 1 25 00 26 00 0 3D 00 DATA FORMAT 3F 00 40 00 REGISTER DATA LVDS SWING 0 DISABLE GAIN GAIN 0 TEST PATTERNS 0 0 0 0 EN OFFSET CORR 0 0 0 LVDS LVDS DATA CLKOUT STRENGTH STRENGTH 0 0 CUSTOM PATTERN HIGH D[13:6] CUSTOM PATTERN D[5:0] 0 CMOS CLKOUT STRENGTH EN CLKOUT RISE CLKOUT FALL POSN 0 0 DIS LOW LATENCY STBY 0 PDN GLOBAL 0 PDN OBUF 0 0 0 0 0 0 0 0 41 00 LVDS CMOS 42 00 43 00 4A 00 BF 00 CLKOUT RISE POSN 0 CF 00 DF 00 0 0 0 OFFSET CORR TIME CONSTANT LOW SPEED 0 0 EN LVDS SWING OFFSET PEDESTAL FREEZE OFFSET CORR 0 EN CLKOUT FALL 0 0 HIGH PERF MODE 2 0 0 0 0 0 0 Multiple functions in a register can be programmed in a single write operation. DESCRIPTION OF SERIAL REGISTERS For best performance, two special mode register bits must be enabled: HI PERF MODE 1 and HI PERF MODE 2. Register Address 00h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RESET READOUT Bits[7:2] Always write '0' Bit 1 RESET: Software reset applied This bit resets all internal registers to the default values and self-clears to 0 (default = 1). Bit 0 READOUT: Serial readout This bit sets the serial readout of the registers. 0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage indicator. 1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 25 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Register Address 01h (Default = 00h) 7 6 5 4 3 2 LVDS SWING Bits[7:2] (1) 0 0 0 0 LVDS SWING: LVDS swing programmability (1) 000000 = 011011 = 110010 = 010100 = 111110 = 001111 = Bits[1:0] 1 Default LVDS swing; 350mV with external 100 termination LVDS swing increases to 410mV LVDS swing increases to 465mV LVDS swing increases to 570mV LVDS swing decreases to 200mV LVDS swing decreases to 125mV Always write '0' The EN LVDS SWING register bits must be set to enable LVDS swing control. Register Address 03h (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 HI PERF MODE 1 Bits[7:2] Always write '0' Bits[1:0] HI PERF MODE 1: High performance mode 1 00 = Default performance after reset 01 = Do not use 10 = Do not use 11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF MODE 1 bits 26 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Register Address 25h (Default = 00h) 7 6 5 4 GAIN Bits[7:4] 3 2 1 DISABLE GAIN 0 TEST PATTERNS GAIN: Gain programmability These bits set the gain programmability in 0.5dB steps. 0000 0001 0010 0011 0100 0101 0110 Bit 3 = = = = = = = 0dB gain (default after reset) 0.5dB gain 1.0dB gain 1.5dB gain 2.0dB gain 2.5dB gain 3.0dB gain 0111 1000 1001 1010 1011 1100 = = = = = = 3.5dB gain 4.0dB gain 4.5dB gain 5.0dB gain 5.5dB gain 6dB gain DISABLE GAIN: Gain setting This bit sets the gain. 0 = Gain enabled; gain is set by the GAIN bits only if low-latency mode is disabled 1 = Gain disabled Bits[2:0] TEST PATTERNS: Data capture These bits verify data capture. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern In the ADS4122/25, output data D[11:0] is an alternating sequence of 010101010101 and 101010101010. In the ADS4142/45, output data D[13:0] is an alternating sequence of 01010101010101 and 10101010101010. 100 = Outputs digital ramp In ADS4122/25, output data increments by one LSB (12-bit) every fourth clock cycle from code 0 to code 4095 In ADS4142/45, output data increments by one LSB (14-bit) every clock cycle from code 0 to code 16383 101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern) 110 = Unused 111 = Unused Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 27 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Register Address 26h (Default = 00h) 7 6 0 5 0 4 0 3 0 0 2 1 0 0 LVDS CLKOUT STRENGTH LVDS DATA STRENGTH Bits[7:2] Always write '0' Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength This bit determines the external termination to be used with the LVDS output clock buffer. 0 = 100 external termination (default strength) 1 = 50 external termination (2x strength) Bit 0 LVDS DATA STRENGTH: LVDS data buffer strength This bit determines the external termination to be used with all of the LVDS data buffers. 0 = 100 external termination (default strength) 1 = 50 external termination (2x strength) Register Address 3Dh (Default = 00h) 7 6 DATA FORMAT Bits[7:6] 5 4 3 2 1 0 EN OFFSET CORR 0 0 0 0 0 DATA FORMAT: Data format selection These bits selects the data format. 00 = The DFS pin controls data format selection 10 = Twos complement 11 = Offset binary Bit 5 ENABLE OFFSET CORR: Offset correction setting This bit sets the offset correction. 0 = Offset correction disabled 1 = Offset correction enabled Bits[4:0] Always write '0' Register Address 3Fh (Default = 00h) 7 6 5 4 3 2 1 0 CUSTOM PATTERN D13 CUSTOM PATTERN D12 CUSTOM PATTERN D11 CUSTOM PATTERN D10 CUSTOM PATTERN D9 CUSTOM PATTERN D8 CUSTOM PATTERN D7 CUSTOM PATTERN D6 Bits[7:0] CUSTOM PATTERN (1) These bits set the custom pattern. (1) For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM PATTERN D[13:2]. Register Address 40h (Default = 00h) 7 6 5 4 3 2 1 0 CUSTOM PATTERN D5 CUSTOM PATTERN D4 CUSTOM PATTERN D3 CUSTOM PATTERN D2 CUSTOM PATTERN D1 CUSTOM PATTERN D0 0 0 Bits[7:2] CUSTOM PATTERN (1) These bits set the custom pattern. Bits[1:0] (1) 28 Always write '0' For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM PATTERN D[13:2]. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Register Address 41h (Default = 00h) 7 6 LVDS CMOS Bits[7:6] 5 4 CMOS CLKOUT STRENGTH 3 EN CLKOUT RISE 2 1 CLKOUT RISE POSN 0 EN CLKOUT FALL LVDS CMOS: Interface selection These bits select the interface. 00 = The DFS pin controls the selection of either LVDS or CMOS interface 10 = The DFS pin controls the selection of either LVDS or CMOS interface 01 = DDR LVDS interface 11 = Parallel CMOS interface Bits[5:4] CMOS CLKOUT STRENGTH Controls strength of CMOS output clock only. 00 = Maximum strength (recommended and used for specified timings) 01 = Medium strength 10 = Low strength 11 = Very low strength Bit 3 ENABLE CLKOUT RISE 0 = Disables control of output clock rising edge 1 = Enables control of output clock rising edge Bits[2:1] CLKOUT RISE POSN: CLKOUT rise control Controls position of output clock rising edge LVDS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 500ps, hold increases by 500ps 10 = Data transition is aligned with rising edge 11 = Setup reduces by 200ps, hold increases by 200ps CMOS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 100ps, hold increases by 100ps 10 = Setup reduces by 200ps, hold increases by 200ps 11 = Setup reduces by 1.5ns, hold increases by 1.5ns Bit 0 ENABLE CLKOUT FALL 0 = Disables control of output clock fall edge 1 = Enables control of output clock fall edge Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 29 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Register Address 42h (Default = 00h) 7 6 5 CLKOUT FALL CTRL Bits[7:6] 0 4 3 2 1 0 0 DIS LOW LATENCY STBY 0 0 CLKOUT FALL CTRL Controls position of output clock falling edge LVDS interface: 00 = Default position (timings are specified in this condition) 01 = Setup reduces by 400ps, hold increases by 400ps 10 = Data transition is aligned with rising edge 11 = Setup reduces by 200ps, hold increases by 200ps CMOS interface: 00 = Default position (timings are specified in this condition) 01 = Falling edge is advanced by 100ps 10 = Falling edge is advanced by 200ps 11 = Falling edge is advanced by 1.5ns Bits[5:4] Always write '0' Bit 3 DIS LOW LATENCY: Disable low latency This bit disables low-latency mode, 0 = Low-latency mode is enabled. Digital functions such as gain, test patterns and offset correction are disabled 1 = Low-latency mode is disabled. This setting enables the digital functions. See the Digital Functions and Low Latency Mode section. Bit 2 STBY: Standby mode This bit sets the standby mode. 0 = Normal operation 1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time from standby is fast Bits[1:0] 30 Always write '0' Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Register Address 43h (Default = 00h) 7 6 5 4 3 2 1 0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING Bit 0 Always write '0' Bit 6 PDN GLOBAL: Power-down 0 This bit sets the state of operation. 0 = Normal operation 1 = Total power down; the ADC, internal references, and output buffers are powered down; slow wake-up time. Bit 5 Always write '0' Bit 4 PDN OBUF: Power-down output buffer This bit set the output data and clock pins. 0 = Output data and clock pins enabled 1 = Output data and clock pins powered down and put in high- impedance state Bits[3:2] Always write '0' Bits[1:0] EN LVDS SWING: LVDS swing control 00 01 10 11 = = = = LVDS swing control using LVDS SWING register bits is disabled Do not use Do not use LVDS swing control using LVDS SWING register bits is enabled Register Address 4Ah (Default = 00h) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 HI PERF MODE 2 Bits[7:1] Always write '0' Bit[0] HI PERF MODE 2: High performance mode 2 This bit is recommended for high input signal frequencies greater than 230MHz. 0 = Default performance after reset 1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 31 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Register Address BFh (Default = 00h) 7 6 5 4 3 2 OFFSET PEDESTAL Bits[7:2] 1 0 0 0 OFFSET PEDESTAL These bits set the offset pedestal. When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits. Bits[1:0] 32 ADS414x VALUE PEDESTAL 011111 011110 011101 -- 000000 -- 111111 111110 -- 100000 31LSB 30LSB 29LSB -- 0LSB -- -1LSB -2LSB -- -32LSB Always write '0' Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Register Address CFh (Default = 00h) 7 6 FREEZE OFFSET CORR 0 Bit 7 5 4 3 2 OFFSET CORR TIME CONSTANT 1 0 0 0 FREEZE OFFSET CORR This bit sets the freeze offset correction. 0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set) 1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the last estimated value is used for offset correction every clock cycle. See the Offset Correction section. Bit 6 Always write '0' Bits[5:2] OFFSET CORR TIME CONSTANT These bits set the offset correction time constant for the correction loop time constant in number of clock cycles. Bits[1:0] VALUE TIME CONSTANT (Number of Clock Cycles) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1M 2M 4M 8M 16M 32M 64M 128M 256M 512M 1G 2G Always write '0' Register Address DFh (Default = 00h) 7 6 0 0 5 4 LOW SPEED Bits[7:6] Always write '0' Bits[5:4] LOW SPEED: Low-speed mode 3 2 1 0 0 0 0 0 For the ADS4122/42, the low-speed mode is enabled by default after reset. 00, 01, 10, 11 = Do not use For the ADS4125/55 only: 00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for sampling rates greater than 80MSPS. 11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal to 80MSPS. Bits[3:0] Always write '0' Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 33 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 85.1dBc SNR = 71.3dBFS SINAD = 71.1dBFS THD = 83dBc -20 -20 -40 Amplitude (dB) Amplitude (dB) -40 -60 -60 -80 -80 -100 -100 -120 SFDR = 84.3dBc SNR = 70.5dBFS SINAD = 70.3dBFS THD = 82.7dBc 0 5 10 15 20 25 -120 30 32.5 0 20 Frequency (MHz) Figure 16. 25 30 32.5 FFT FOR TWO-TONE INPUT SIGNAL 0 SFDR = 71.9dBc SNR = 69.3dBFS SINAD = 67.7dBFS THD = 71.7dBc -20 Each Tone at -7dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two-Tone IMD = 90.1dBFS SFDR = 97.3dBFS -20 -40 Amplitude (dB) -40 Amplitude (dB) 15 Figure 15. FFT FOR 300MHz INPUT SIGNAL 34 10 Frequency (MHz) 0 -60 -60 -80 -80 -100 -100 -120 5 0 5 10 15 20 25 30 32.5 -120 0 5 10 15 20 Frequency (MHz) Frequency (MHz) Figure 17. Figure 18. Submit Documentation Feedback 25 30 32.5 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR TWO-TONE INPUT SIGNAL SFDR vs INPUT FREQUENCY 0 88 Each Tone at -36dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two-Tone IMD = 99.5dBFS SFDR = 106.9dBFS -20 83 78 SFDR (dBc) Amplitude (dB) -40 -60 73 -80 68 -100 63 -120 0 5 10 15 20 25 58 30 32.5 0 50 100 Frequency (MHz) 150 200 250 300 350 400 Input Frequency (MHz) Figure 19. Figure 20. SNR vs INPUT FREQUENCY SFDR ACROSS GAIN AND INPUT FREQUENCY 71.5 98 High Perf MODE1 Enabled Default 170MHz 220MHz 94 71 300MHz 400MHz 90 70.5 86 SFDR (dBc) SNR (dBFS) 70 69.5 69 82 78 74 70 68.5 66 68 67.5 62 0 50 100 150 200 250 300 350 400 58 0 0.5 1 1.5 2 Input Frequency (MHz) 3 3.5 4 4.5 5 5.5 6 Gain (dB) Figure 21. Copyright (c) 2011, Texas Instruments Incorporated 2.5 Figure 22. Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 35 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone) SINAD ACROSS GAIN AND INPUT FREQUENCY 74 120 72 170MHz 220MHz 71 Input Frequency = 40MHz 300MHz 400MHz SFDR (dBFS) SFDR (dBc) SNR 110 70 73.5 73 100 90 72.5 80 72 70 71.5 60 71 50 70.5 40 70 61 30 69.5 60 20 -45 SFDR (dBc, dBFS) SINAD (dBFS) 68 67 66 65 64 SNR (dBFS) 69 63 62 59 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 -35 -30 -25 -20 -15 -10 -5 0 69 Amplitude (dBFS) 6 Gain (dB) Figure 23. Figure 24. PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone) PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SFDR (dBFS) SFDR (dBc) SNR 110 Input Frequency = 150MHz 73.5 72.5 80 72 70 71.5 60 71 50 70.5 40 70 30 69.5 -40 -35 -30 -25 -20 -15 Amplitude (dBFS) -10 -5 0 69 SFDR (dBc) SFDR (dBc, dBFS) 90 SNR (dBFS) 73 100 20 -45 90 71 86 70.5 82 70 78 69.5 74 0.8 0.85 0.9 Submit Documentation Feedback 0.95 1 1.05 69 1.1 Input Common-Mode Voltage (V) Figure 25. 36 SFDR SNR SNR (dBFS) Input Frequency = 150MHz 71.5 94 74 120 Figure 26. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS TEMPERATURE vs AVDD SUPPLY SNR ACROSS TEMPERATURE vs AVDD SUPPLY 73 100 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 96 92 1.85 1.9 1.95 Input Frequency = 150MHz 72 88 1.85 1.9 1.95 71 84 SNR (dBFS) SFDR (dBc) 1.65 1.7 1.75 1.8 80 76 70 69 72 68 68 64 -15 10 35 60 67 -40 85 -15 Temperature (C) 35 60 85 Figure 27. Figure 28. PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 72 94 Input Frequency = 40MHz 90 71 88 70.5 86 70 84 69.5 1.75 1.8 1.85 DRVDD Supply (V) 1.9 69 1.95 SFDR (dBc) 71.5 1.7 72 87 71 86 70 85 69 84 68 83 67 82 66 81 65 80 64 79 0 0.5 1 1.5 2 2.5 3 63 3.5 Differential Clock Amplitude (VPP) Figure 29. Copyright (c) 2011, Texas Instruments Incorporated SFDR SNR 88 92 82 1.65 73 89 SNR SFDR SNR (dBFS) Input Frequency =150MHz SFDR (dBc) 10 Temperature (C) SNR (dBFS) 60 -40 Figure 30. Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 37 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4122 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR (dBc) 93 Input Frequency = 10MHz 91 71 89 69 87 67 85 65 83 63 81 61 79 59 77 57 0 0.5 1 1.5 2 2.5 Differential Clock Amplitude (VPP) 3 55 3.5 90 71.5 86 71 82 70.5 78 40 45 50 Submit Documentation Feedback 55 60 70 Input Clock Duty Cycle (%) Figure 31. 38 THD SNR 73 THD (dBc) SFDR SNR SNR (dBFS) Input Frequency = 150MHz 72 94 75 95 75 PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE SNR (dBFS) PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE Figure 32. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 86.9dBc SNR = 71.2dBFS SINAD = 71dBFS THD = 83.9dBc -20 -20 -40 Amplitude (dB) Amplitude (dB) -40 -60 -60 -80 -80 -100 -100 -120 SFDR = 82.4dBc SNR = 70.5dBFS SINAD = 70.1dBFS THD = 80.5dBc 0 10 20 30 40 50 -120 60 0 30 40 Frequency (MHz) Figure 33. Figure 34. FFT FOR 300MHz INPUT SIGNAL 50 60 FFT FOR TWO-TONE INPUT SIGNAL 0 SFDR = 79.7dBc SNR = 70dBFS SINAD = 69.5dBFS THD = 78.3dBc -20 Each Tone at -7dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two-Tone IMD = 87.7dBFS SFDR = 96.7dBFS -20 -40 Amplitude (dB) -40 Amplitude (dB) 20 Frequency (MHz) 0 -60 -60 -80 -80 -100 -100 -120 10 0 10 20 30 40 50 60 -120 0 10 20 30 40 Frequency (MHz) Frequency (MHz) Figure 35. Figure 36. Copyright (c) 2011, Texas Instruments Incorporated 50 Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 60 39 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR TWO-TONE INPUT SIGNAL SFDR vs INPUT FREQUENCY 0 90 Each Tone at -36dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two-Tone IMD = 99.4dBFS SFDR = 106.3dBFS -20 85 80 SFDR (dBc) Amplitude (dB) -40 -60 75 -80 70 -100 65 -120 0 10 20 30 40 50 60 60 0 50 100 Frequency (MHz) 150 200 250 300 350 400 Input Frequency (MHz) Figure 37. Figure 38. SNR vs INPUT FREQUENCY SFDR ACROSS GAIN AND INPUT FREQUENCY 71.5 96 High Perf MODE1 Enabled Default 170MHz 220MHz 300MHz 400MHz 92 71 88 70.5 SFDR (dBc) SNR (dBFS) 84 70 80 76 69.5 72 69 68 68.5 0 50 100 150 200 250 300 350 400 64 0 0.5 1 1.5 2 Input Frequency (MHz) Submit Documentation Feedback 3 3.5 4 4.5 5 5.5 6 Gain (dB) Figure 39. 40 2.5 Figure 40. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone) 74 120 72 170MHz 220MHz 71 Input Frequency = 40MHz 300MHz 400MHz SFDR (dBFS) SFDR (dBc) SNR 110 73.5 73 100 SFDR (dBc, dBFS) 70 SINAD (dBFS) 69 68 67 66 65 90 72.5 80 72 70 71.5 60 71 50 70.5 40 70 30 69.5 20 69 SNR (dBFS) SINAD ACROSS GAIN AND INPUT FREQUENCY 64 10 -45 63 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -40 -35 -30 -25 -20 -15 -10 -5 0 68.5 Amplitude (dBFS) 6 Gain (dB) Figure 41. Figure 42. PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone) PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SFDR (dBFS) SFDR (dBc) SNR 110 Input Frequency = 150MHz 73.5 72.5 80 72 70 71.5 60 71 50 70.5 40 70 30 69.5 -40 -35 -30 -25 -20 -15 Amplitude (dBFS) -10 -5 0 69 SFDR (dBc) SFDR (dBc, dBFS) 90 SNR (dBFS) 73 100 20 -45 86 70.5 82 70 78 69.5 74 69 70 0.8 0.85 0.9 0.95 1 1.05 68.5 1.1 Input Common-Mode Voltage (V) Figure 43. Copyright (c) 2011, Texas Instruments Incorporated SFDR SNR SNR (dBFS) Input Frequency = 150MHz 71 90 74 120 Figure 44. Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 41 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS TEMPERATURE vs AVDD SUPPLY SNR ACROSS TEMPERATURE vs AVDD SUPPLY 73 100 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 96 92 1.85 1.9 1.95 Input Frequency = 150MHz 72 88 1.85 1.9 1.95 71 84 SNR (dBFS) SFDR (dBc) 1.65 1.7 1.75 1.8 80 76 70 69 72 68 68 64 -15 10 35 60 67 -40 85 -15 Temperature (C) 60 85 Figure 46. PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 72 Input Frequency = 40MHz 84 71 82 70.5 80 70 78 69.5 1.75 1.8 1.85 DRVDD Supply (V) 1.9 69 1.95 SFDR (dBc) 71.5 1.7 73 87 72 86 71 85 70 84 69 83 68 82 67 81 66 80 65 79 0 0.5 1 1.5 2 2.5 3 64 3.5 Differential Clock Amplitude (VPP) Figure 47. Submit Documentation Feedback SFDR SNR 88 86 76 1.65 74 89 SNR SFDR SNR (dBFS) Input Frequency =150MHz 42 35 Figure 45. 88 SFDR (dBc) 10 Temperature (C) SNR (dBFS) 60 -40 Figure 48. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4125 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 95 Input Frequency = 150MHz SFDR SNR 93 SNR ACROSS INPUT CLOCK DUTY CYCLE 73 73 72 72 91 71 89 70 87 69 85 68 83 67 81 66 79 65 77 64 75 63 Default Low-Speed Mode Enabled 71 SNR (dBFS) SNR (dBFS) SFDR (dBc) 70 69 68 67 66 65 73 0 0.5 1 1.5 2 2.5 3 Differential Clock Amplitude (VPP) 3.5 4 62 64 Input Frequency = 10MHz 63 30 35 40 45 50 55 60 65 70 Input Clock Duty Cycle (%) Figure 49. Copyright (c) 2011, Texas Instruments Incorporated Figure 50. Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 43 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 83.4dBc SNR = 74.3dBFS SINAD = 73.7dBFS THD = 82dBc -20 -20 -40 Amplitude (dB) Amplitude (dB) -40 -60 -60 -80 -80 -100 -100 -120 SFDR = 83dBc SNR = 72.8dBFS SINAD = 72.4dBFS THD = 81.6dBc 0 5 10 15 20 25 -120 30 32.5 0 20 Frequency (MHz) Figure 52. 25 30 32.5 FFT FOR TWO-TONE INPUT SIGNAL 0 SFDR = 70.7dBc SNR = 68.4dBFS SINAD = 66.3dBFS THD = 69.3dBc -20 Each Tone at -7dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two-Tone IMD = 88.7dBFS SFDR = 96.6dBFS -20 -40 Amplitude (dB) -40 Amplitude (dB) 15 Figure 51. FFT FOR 300MHz INPUT SIGNAL 44 10 Frequency (MHz) 0 -60 -60 -80 -80 -100 -100 -120 5 0 5 10 15 20 25 30 32.5 -120 0 5 10 15 20 Frequency (MHz) Frequency (MHz) Figure 53. Figure 54. Submit Documentation Feedback 25 30 32.5 Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR TWO-TONE INPUT SIGNAL SFDR vs INPUT FREQUENCY 0 93 Each Tone at -36dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two-Tone IMD = 99dBFS SFDR = 105.3dBFS -20 88 83 SFDR (dBc) Amplitude (dB) -40 -60 78 73 -80 68 -100 -120 63 0 5 10 15 20 25 58 30 32.5 0 50 100 Frequency (MHz) 250 300 350 Figure 56. SNR vs INPUT FREQUENCY SFDR ACROSS GAIN AND INPUT FREQUENCY 400 98 High Perf MODE1 Enabled Default 73.5 73 90 72.5 86 72 82 71.5 71 74 70 70 66 69.5 62 50 100 150 200 250 300 350 400 58 0 0.5 1 1.5 2 Input Frequency (MHz) 2.5 3 3.5 4 4.5 5 5.5 6 Gain (dB) Figure 57. Copyright (c) 2011, Texas Instruments Incorporated 300MHz 400MHz 78 70.5 0 170MHz 220MHz 94 SFDR (dBc) SNR (dBFS) 200 Figure 55. 74 69 150 Input Frequency (MHz) Figure 58. Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 45 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone) 77 120 73 170MHz 220MHz 72 Input Frequency = 40MHz 300MHz 400MHz SFDR (dBFS) SFDR (dBc) SNR 110 71 76 100 70 SFDR (dBc, dBFS) 69 68 SINAD (dBFS) 76.5 67 66 65 64 63 90 75.5 80 75 70 74.5 60 74 50 73.5 40 73 30 72.5 SNR (dBFS) SINAD ACROSS GAIN AND INPUT FREQUENCY 62 61 20 -70 60 59 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -60 -50 -40 -30 -20 -10 0 72 Amplitude (dBFS) 6 Gain (dB) Figure 59. Figure 60. PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone) PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SFDR (dBFS) SFDR (dBc) SNR 110 Input Frequency = 150MHz 76.5 75.5 80 75 70 74.5 60 74 50 73.5 40 73 30 72.5 -60 -50 -40 -30 Amplitude (dBFS) -20 -10 0 72 SFDR (dBc) SFDR (dBc, dBFS) 90 SNR (dBFS) 76 100 20 -70 86 73.5 82 73 78 72.5 74 72 70 0.8 0.85 0.9 Submit Documentation Feedback 0.95 1 1.05 71.5 1.1 Input Common-Mode Voltage (V) Figure 61. 46 SFDR SNR SNR (dBFS) Input Frequency = 150MHz 74 90 77 120 Figure 62. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS TEMPERATURE vs AVDD SUPPLY SNR ACROSS TEMPERATURE vs AVDD SUPPLY 75 100 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 96 1.85 1.9 1.95 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 74 1.85 1.9 1.95 92 73 SNR (dBFS) SFDR (dBc) 88 84 80 76 72 71 72 70 68 64 -40 -15 10 35 60 69 -40 85 -15 Temperature (C) 35 60 85 Figure 63. Figure 64. PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 74 94 Input Frequency =150MHz Input Frequency = 40MHz SFDR SNR 89 75 88 74 87 73 86 72 85 71 84 70 83 69 73.5 86 72 SNR (dBFS) 72.5 SFDR (dBc) 88 SNR (dBFS) 73 90 71.5 84 82 1.65 76 90 SNR SFDR 92 SFDR (dBc) 10 Temperature (C) 1.7 1.75 1.8 1.85 DRVDD Supply (V) 1.9 71 1.95 82 0 0.5 1 1.5 2.5 3 68 3.5 Differential Clock Amplitude (VPP) Figure 65. Copyright (c) 2011, Texas Instruments Incorporated 2 Figure 66. Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 47 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4142 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. 76 SFDR SNR SFDR (dBc) 89 Input Frequency = 10MHz 72 85 70 83 68 81 66 79 64 77 62 75 60 0.5 1 1.5 2 2.5 3 THD SNR 74 87 0 74.5 94 THD (dBc) Input Frequency = 150MHz SNR (dBFS) 91 73 PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE 58 3.5 90 74 86 73.5 82 73 78 40 45 50 55 60 SNR (dBFS) PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 72.5 Input Clock Duty Cycle (%) Differential Clock Amplitude (VPP) Figure 67. Figure 68. INTEGRAL NONLINEARITY OUTPUT NOISE HISTOGRAM (with Inputs Shorted to VCM) 50 1.5 45 1 40 Code Occurrence (%) 35 INL (LSB) 0.5 0 -0.5 30 25 20 15 10 -1 5 -1.5 0 2048 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) 0 8168 8169 8170 8171 8172 8173 8174 8175 8176 Output Code (LSB) Figure 69. 48 Submit Documentation Feedback Figure 70. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 86dBc SNR = 74dBFS SINAD =73.7dBFS THD = 83.5dBc -20 -20 -40 Amplitude (dB) Amplitude (dB) -40 -60 -60 -80 -80 -100 -100 -120 SFDR = 82.5dBc SNR = 72.8dBFS SINAD = 72.2dBFS THD = 80.1dBc 0 10 20 30 40 50 -120 60 0 30 40 Frequency (MHz) Figure 71. Figure 72. FFT FOR 300MHz INPUT SIGNAL 50 60 FFT FOR TWO-TONE INPUT SIGNAL 0 SFDR = 80dBc SNR = 72dBFS SINAD = 71.3dBFS THD = 78.5dBc -20 Each Tone at -7dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two-Tone IMD = 87.7dBFS SFDR = 97.5dBFS -20 -40 Amplitude (dB) -40 Amplitude (dB) 20 Frequency (MHz) 0 -60 -60 -80 -80 -100 -100 -120 10 0 10 20 30 40 50 60 -120 0 10 20 30 40 Frequency (MHz) Frequency (MHz) Figure 73. Figure 74. Copyright (c) 2011, Texas Instruments Incorporated 50 Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 60 49 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR TWO-TONE INPUT SIGNAL SFDR vs INPUT FREQUENCY 0 90 Each Tone at -36dBFS Amplitude fIN1 = 100MHz fIN2 = 105MHz Two-Tone IMD = 99.2dBFS SFDR = 106.6dBFS -20 85 80 SFDR (dBc) Amplitude (dB) -40 -60 75 -80 70 -100 65 -120 0 10 20 30 40 50 60 60 0 50 100 Frequency (MHz) 150 200 250 Figure 76. SNR vs INPUT FREQUENCY SFDR ACROSS GAIN AND INPUT FREQUENCY 170MHz 220MHz 73.5 92 73 88 72.5 84 SFDR (dBc) SNR (dBFS) 400 96 High Perf MODE1 Enabled Default 72 71.5 76 71 72 70.5 68 0 50 100 150 200 250 300 350 400 64 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Gain (dB) Figure 77. Submit Documentation Feedback 300MHz 400MHz 80 Input Frequency (MHz) 50 350 Figure 75. 74 70 300 Input Frequency (MHz) Figure 78. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone) SINAD ACROSS GAIN AND INPUT FREQUENCY 76.5 120 74 170MHz 220MHz 73 Input Frequency = 40MHz 300MHz 400MHz SFDR (dBFS) SFDR (dBc) SNR 110 76 72 75.5 100 75 80 74.5 70 74 60 73.5 50 73 64 40 72.5 63 30 -70 SFDR (dBc, dBFS) 90 SINAD (dBFS) 70 69 68 67 SNR (dBFS) 71 66 65 62 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 -60 -50 -40 -30 -20 -10 0 72 Amplitude (dBFS) 6 Gain (dB) Figure 79. Figure 80. PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone) PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SFDR (dBFS) SFDR (dBc) SNR 110 Input Frequency = 150MHz 76 75 80 74.5 70 74 60 73.5 50 73 40 72.5 30 72 -60 -50 -40 -30 -20 Amplitude (dBFS) -10 0 71.5 SFDR (dBc) SFDR (dBc, dBFS) 90 SNR (dBFS) 75.5 100 20 -70 86 73.5 82 73 78 72.5 74 72 70 0.8 0.85 0.9 0.95 1 1.05 71.5 1.1 Input Common-Mode Voltage (V) Figure 81. Copyright (c) 2011, Texas Instruments Incorporated SFDR SNR SNR (dBFS) Input Frequency = 150MHz 74 90 76.5 120 Figure 82. Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 51 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS TEMPERATURE vs AVDD SUPPLY SNR ACROSS TEMPERATURE vs AVDD SUPPLY 75 100 Input Frequency = 150MHz 1.65 1.7 1.75 1.8 96 92 1.85 1.9 1.95 Input Frequency = 150MHz 74 88 1.85 1.9 1.95 73 84 SNR (dBFS) SFDR (dBc) 1.65 1.7 1.75 1.8 80 76 72 71 72 68 70 64 -15 10 35 60 69 -40 85 -15 10 Temperature (C) 85 Figure 84. PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 73 Input Frequency = 40MHz 86 72 84 71.5 82 71 80 70.5 1.75 1.8 1.85 DRVDD Supply (V) 1.9 70 1.95 SFDR (dBc) 72.5 1.7 75 88 74 87 73 86 72 85 71 84 70 83 69 82 68 81 67 80 0 0.5 1 1.5 2 2.5 3 3.5 4 66 Differential Clock Amplitude (VPP) Figure 85. Submit Documentation Feedback SFDR SNR 89 88 78 1.65 76 90 SNR SFDR SNR (dBFS) Input Frequency =150MHz SFDR (dBc) 60 Figure 83. 90 52 35 Temperature (C) SNR (dBFS) 60 -40 Figure 86. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: ADS4145 (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE 76 75 89 74 74 86 72 73 83 70 72 80 68 77 66 74 64 71 62 92 SNR (dBFS) SFDR SNR SNR (dBFS) Input Frequency = 150MHz SFDR (dBc) SNR ACROSS INPUT CLOCK DUTY CYCLE Default Low-Speed Mode Enabled 71 70 69 68 67 68 0 0.5 1 1.5 2 2.5 3 3.5 4 60 Input Frequency = 10MHz 66 Differential Clock Amplitude (VPP) 30 35 40 45 50 55 60 65 70 Input Clock Duty Cycle (%) Figure 87. Figure 88. INTEGRAL NONLINEARITY OUTPUT NOISE HISTOGRAM (with Inputs Shorted to VCM) 35 1.5 30 1 Code Occurrence (%) 25 INL (LSB) 0.5 0 -0.5 20 15 10 -1 -1.5 5 0 2048 4096 6144 8192 10240 12288 14336 16384 Output Code (LSB) 0 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179 Output Code (LSB) Figure 89. Copyright (c) 2011, Texas Instruments Incorporated Figure 90. Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 53 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: COMMON At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. CMRR vs FREQUENCY PSRR vs FREQUENCY 0 0 PSRR on AVDD Supply 50mVPP -10 -10 -20 -20 PSRR (dB) CMRR (dB) Input Frequency = 70MHz 50mVPP Signal Superimposed on Input Common-Mode Voltage (0.95V) -30 -30 -40 -40 -50 -50 -60 0 50 100 150 200 250 -60 300 0 10 20 Frequency of Input Common-Mode Signal (MHz) 30 50 60 70 80 90 100 Frequency of Signal on Supply (MHz) Figure 91. Figure 92. POWER vs SAMPLE RATE DRVDD CURRENT vs SAMPLE RATE 70 130 AVDD Power DRVDD Power 200mV Swing DRVDD Power 350mV Swing 120 LVDS, 200mV Swing LVDS, 350mV Swing CMOS, 6pF Load Capacitance CMOS, 8pF Load Capacitance 65 60 110 55 100 50 DRVDD Current (mA) Power (mW) 40 90 80 70 45 40 35 30 25 60 20 50 15 10 40 30 5 5 25 45 65 85 Sampling Frequency (MSPS) 105 125 0 5 25 45 65 85 Sampling Frequency (MSPS) Figure 93. 54 Submit Documentation Feedback 105 125 Figure 94. Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (0dB Gain) 125 120 Sampling Frequency (MSPS) 110 84 84 75 81 87 67 71 78 100 63 90 84 80 87 84 87 70 60 81 75 67 71 78 84 63 84 50 87 84 40 75 84 78 81 30 87 75 84 71 59 63 67 55 20 20 50 100 150 200 250 300 350 400 Input Frequency (MHz) 60 55 65 70 75 80 85 SFDR (dBc) Figure 95. SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain) 125 120 87 84 110 Sampling Frequency (MSPS) 87 87 87 77 90 73 100 81 87 90 69 90 80 84 70 73 77 87 60 87 87 69 81 50 40 81 87 30 87 73 77 65 69 84 61 20 20 50 100 150 200 250 300 350 400 Input Frequency (MHz) 60 65 70 75 80 85 90 SFDR (dBc) Figure 96. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 55 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. ADS414x: SNR ACROSS INPUT AND SAMPLING FREQUENCIES (0dB Gain) 125 120 Sampling Frequency (MSPS) 72.5 73 73.5 110 72 70 71 100 90 80 72 72.5 73 70 73.5 60 71 69 70 50 40 69 72 30 72.5 73.5 68 70 71 69 73 67 68 66 20 20 50 100 150 200 250 300 350 400 Input Frequency (MHz) 66 67 68 69 70 71 73 72 SNR (dBFS) Figure 97. ADS414x: SNR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain) 125 120 67.5 Sampling Frequency (MSPS) 110 67 100 90 80 67 68 70 67.5 66.5 60 50 67 40 66 66.5 67.5 68 30 67 66.5 65.5 66 65 20 20 50 100 150 200 250 300 350 400 67.5 68 Input Frequency (MHz) 64 64.5 65 65.5 66 66.5 67 SNR (dBFS) Figure 98. 56 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) At +25C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, -1dBFS differential analog input, 0dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. ADS412x SNR ACROSS INPUT AND SAMPLING FREQUENCIES (0dB Gain) 125 120 Sampling Frequency (MSPS) 70.5 71 110 70 69.5 100 69 90 80 70 69.5 70.5 71 70 60 68 50 69 40 69.5 30 71 67 68 70 70.5 69 66 67 20 20 50 100 150 200 250 300 350 400 Input Frequency (MHz) 65 66 67 68 69 70 71 SNR (dBFS) Figure 99. ADS412x SNR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain) 125 120 Sampling Frequency (MSPS) 110 66.5 67 100 90 80 67 70 66 66.5 60 50 65.5 40 66 30 67 66 66.5 65 65.5 20 20 50 100 150 200 250 300 350 64.5 64 400 Input Frequency (MHz) 64 64.5 65 65.5 66 66.5 67 SNR (dBFS) Figure 100. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 57 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS412x/4x are lower sampling speed members of the ADS41xx family of ultralow power analog-to-digital converters (ADCs). The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 10 clock cycles. The output is available as 14-bit data or 12-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement format. ANALOG INPUT The analog input consists of a switched-capacitor-based, differential, sample-and-hold architecture. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INP and INM pins must be externally biased around a common-mode voltage of 0.95V, available on the VCM pin. For a full-scale differential input, each input INP and INM pin must swing symmetrically between (VCM + 0.5V) and (VCM - 0.5V), resulting in a 2VPP differential input swing. The input sampling circuit has a high 3dB bandwidth that extends up to 550MHz (measured from the input pins to the sampled voltage). Figure 101 shows an equivalent circuit for the analog input. Sampling Switch LPKG 2nH INP 10W CBOND 1pF RESR 200W 100W INM CPAR2 1pF RESR 200W CSAMP 2pF CPAR1 0.5pF RON 15W 100W CBOND 1pF RON 15W 3pF 3pF LPKG 2nH Sampling Capacitor RCR Filter RON 15W CPAR2 1pF CSAMP 2pF Sampling Capacitor Sampling Switch Figure 101. Analog Input Equivalent Circuit Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This technique improves the common-mode noise immunity and even-order harmonic rejection. A 5 to 15 resistor in series with each input pin is recommended to damp out ringing caused by package parasitics. It is also necessary to present low impedance (less than 50) for the common-mode switching currents. This impedance can be achieved by using two resistors from each input terminated to the common-mode voltage (VCM). Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the glitches caused by the opening and closing of the sampling capacitors. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but also reduces the input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal R-C filter, high input frequency can be supported but now the sampling glitches must be supplied by the external driving circuit. The inductance of the package bond wires limits the ability of the external driving circuit to support the sampling glitches. 58 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com In the ADS412x/4x, the R-C component values have been optimized while supporting high input bandwidth (550MHz). However, in applications where very high input frequency support is not required, filtering of the glitches can be improved further with an external R-C-R filter; see Figure 104 and Figure 105). In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While designing the drive circuit, the ADC impedance must be considered. Figure 102 and Figure 103 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins. Differential Input Resistance (kW) 100.00 10.00 1.00 0.10 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input Frequency (GHz) Figure 102. ADC Analog Input Resistance (RIN) Across Frequency Differential Input Capacitance (pF) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input Frequency (GHz) Figure 103. ADC Analog Input Capacitance (CIN) Across Frequency Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 59 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Driving Circuit Two example driving circuit configurations are shown in Figure 104 and Figure 105--one optimized for low bandwidth (tlow input frequencies) and the other one for high bandwidth to support higher input frequencies. In Figure 104, an external R-C-R filter with 3.3pF is used to help absorb sampling glitches. The R-C-R filter limits the bandwidth of the drive circuit, making it suitable for low input frequencies (up to 250MHz). Transformers such as ADT1-1WT or WBC1-1 can be used up to 250MHz. For higher input frequencies, the R-C-R filter can be dropped. Together with the lower series resistors (5 to 10), this drive circuit provides higher bandwidth to support frequencies up to 500MHz (as shown in Figure 105). A transmission line transformer such as ADTL2-18 can be used. Note that both the drive circuits have been terminated by 50 near the ADC side. The termination is accomplished by a 25 resistor from each input to the 0.95V common-mode (VCM) from the device. This termination allows the analog inputs to be biased around the required common-mode voltage. 10W to 15W T2 3.6nH INP T1 0.1mF 0.1mF 25W 50W RIN 3.3pF 25W CIN 50W INM 1:1 1:1 10W to 15W 3.6nH VCM ADS41xx Figure 104. Drive Circuit with Low Bandwidth (for Low Input Frequencies) 5W to 10W T2 T1 INP 0.1mF 0.1mF 25W RIN CIN 25W INM 1:1 1:1 5W to 10W VCM ADS41xx Figure 105. Drive Circuit with High Bandwidth (for High Input Frequencies) 60 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 104 and Figure 105. The center point of this termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 (for a 50 source impedance). Figure 104 and Figure 105 use 1:1 transformers with a 50 source. As explained in the Drive Circuit Requirements section, this architecture helps to present a low source impedance to absorb sampling glitches. With a 1:4 transformer, the source impedance is 200. The higher source impedance is unable to absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers). In almost all cases, either a bandpass or low-pass filter is needed to obtain the desired dynamic performance, as shown in Figure 106. Such a filter presents low source impedance at the high frequencies corresponding to the sampling glitch and helps avoid the performance loss with the high source impedance. 10W Bandpass or Low-Pass Filter Differential Input Signal 0.1mF INP 100W ADS41xx 100W INM 10W VCM Figure 106. Drive Circuit with 1:4 Transformer Input Common-Mode To ensure a low-noise, common-mode reference, the VCM pin is filtered with a 0.1F low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each ADC input pin sinks a common-mode current of approximately 0.6A per MSPS of clock frequency. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 61 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com CLOCK INPUT The ADS412x/4x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5k resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources. Figure 107 shows an equivalent circuit for the input clock. Clock Buffer LPKG 1nH 20W CLKP CBOND 1pF RESR 100W LPKG 1nH 5kW 2pF 20W CEQ CEQ VCM 5kW CLKM CBOND 1pF RESR 100W NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer. Figure 107. Input Clock Equivalent Circuit A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1F capacitor, as shown in Figure 108. For best performance, the clock inputs must be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 109 shows a differential circuit. CMOS Clock Input 0.1mF 0.1mF CLKP CLKP VCM 0.1mF Differential Sine-Wave, PECL, or LVDS Clock Input 0.1mF CLKM CLKM Figure 108. Single-Ended Clock Driving Circuit 62 Submit Documentation Feedback Figure 109. Differential Clock Driving Circuit Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com DIGITAL FUNCTIONS AND LOW LATENCY MODE The device has several useful digital functions such as test patterns, gain, and offset correction. All of these functions require extra clock cycles for operation and increase the overall latency and power of the device. Alternately, the device has a low-latency mode in which the raw ADC output is routed to the output data pins with a latency of 10 clock cycles. In this mode, the digital functions are bypassed. Figure 110 shows more details of the processing after the ADC. The device is in low-latency mode after reset. In order to use any of the digital functions, the low-latency mode must first be disabled by setting the DIS LOW LATENCY register bit to '1'. After this, the respective register bits must be programmed as described in the following sections and in the Serial Register Map section. Output Interface 14-Bit ADC 14b 14b Digital Functions (Gain, Offset Correction, Test Patterns) DDR LVDS or CMOS DIS LOW LATENCY Pin Figure 110. Digital Processing Block Diagram GAIN FOR SFDR/SNR TRADE-OFF The ADS412x/4x include gain settings that can be used to improve SFDR performance. The gain is programmable from 0dB to 6dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 9. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR. After a reset, the device is in low-latency mode and gain function is disabled. To use gain: * First, disable the low-latency mode (DIS LOW LATENCY = 1). * This setting enables the gain and puts the device in a 0dB gain mode. * For other gain settings, program the GAIN bits. Table 9. Full-Scale Range Across Gains GAIN (dB) TYPE 0 Default after reset 2 1 Programmable 1.78 2 Programmable 1.59 3 Programmable 1.42 4 Programmable 1.26 5 Programmable 1.12 6 Programmable 1.00 Copyright (c) 2011, Texas Instruments Incorporated FULL-SCALE (VPP) Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 63 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com OFFSET CORRECTION The ADS412x/4x has an internal offset corretion algorithm that estimates and corrects dc offset up to 10mV. The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 10. Table 10. Time Constant of Offset Correction Loop (1) OFFSET CORR TIME CONSTANT TIME CONSTANT, TCCLK (Number of Clock Cycles) TIME CONSTANT, TCCLK x 1/fS (sec) (1) 0000 1M 8ms 0001 2M 16ms 0010 4M 33.4ms 0011 8M 67ms 0100 16M 134ms 0101 32M 268ms 0110 64M 537ms 0111 128M 1.08s 1000 256M 2.15s 1001 512M 4.3s 1010 1G 8.6s 1011 2G 17.2s 1100 Reserved -- 1101 Reserved -- 1110 Reserved -- 1111 Reserved -- Sampling frequency, fS = 125MSPS. After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by a default after reset. After a reset, the device is in low-latency mode and offset correction is disabled. To use offset correction: * First, disable the low-latency mode (DIS LOW LATENCY = 1). * Then set EN OFFSET CORR to '1' and program the required time constant. Figure 111 shows the time response of the offset correction algorithm after it is enabled. Output Code (LSB) OFFSET CORRECTION Time Response 8200 8190 8180 8170 8160 8150 8140 8130 8120 8110 8100 8090 8080 8070 8060 8050 8181 Offset of 10 LSBs 8192 Final converged value Offset correction converges to output code of 8192 Offset correction begins -5 5 15 25 35 45 55 65 75 85 95 105 Time (ms) Figure 111. Time Response of Offset Correction 64 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com POWER DOWN The ADS412x/4x has three power-down modes: power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down, resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100s. To enter the global power-down mode, set the PDN GLOBAL register bit. Standby In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up time of 5s. The total power dissipation in standby mode is approximately 130mW at 125MSPS. To enter the standby mode, set the STBY register bit. Output Buffer Disable The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast, approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin. Input Clock Stop In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The power dissipation is approximately 80mW. POWER-SUPPLY SEQUENCE During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the device. Externally, they can be driven from separate supplies or from a single supply. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 65 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com DIGITAL OUTPUT INFORMATION The ADS412x/4x provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the data. Output Interface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the LVDS CMOS serial interface register bit or using the DFS pin. DDR LVDS Outputs In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as shown in Figure 112 and Figure 113. Pins Pins CLKOUTP Output Clock CLKOUTP CLKOUTM Output Clock CLKOUTM D0_D1_P Data Bits D0, D1 D0_D1_P Data Bits D0, D1 D0_D1_M LVDS Buffers LVDS Buffers D0_D1_M D2_D3_P Data Bits D2, D3 D2_D3_M D2_D3_P Data Bits D2, D3 D2_D3_M D4_D5_P 12-Bit ADC Data Data Bits D4, D5 D4_D5_M D4_D5_P Data Bits D4, D5 14-Bit ADC Data D4_D5_M D6_D7_P Data Bits D6, D7 D6_D7_P Data Bits D6, D7 D6_D7_M D6_D7_M D8_D9_P Data Bits D8, D9 D8_D9_P Data Bits D8, D9 D8_D9_M D8_D9_M D10_D11_P D10_D11_P Data Bits D10, D11 Data Bits D10, D11 D10_D11_M D10_D11_M ADS412x D12_D13_P Data Bits D12, D13 Figure 112. ADS412x LVDS Data Outputs D12_D13_M ADS414x Figure 113. ADS414x LVDS Data Outputs 66 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits, as shown in Figure 114. CLKOUTP CLKOUTM D0_D1_P, D0_D1_M D0 D1 D0 D1 D2_D3_P, D2_D3_M D2 D3 D2 D3 D4_D5_P, D4_D5_M D4 D5 D4 D5 D6_D7_P, D6_D7_M D6 D7 D6 D7 D8_D9_P, D8_D9_M D8 D9 D8 D9 D10_D11_P, D10_D11_M D10 D11 D10 D11 D12_D13_P, D12_D13_M D12 D13 D12 D13 Sample N Sample N + 1 Figure 114. DDR LVDS Interface Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 67 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 115. After reset, the buffer presents an output impedance of 100 to match with the external 100 termination. The VDIFF voltage is nominally 350mV, resulting in an output swing of 350mV with 100 external termination. The VDIFF voltage is programmable using the LVDS SWING register bits from 125mV to 570mV. Additionally, a mode exists to double the strength of the LVDS buffer to support 50 differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100 termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively. The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity. VDIFF High Low OUTP External 100W Load OUTM 1.1V ROUT VDIFF Low High NOTE: Use the default buffer strength to match 100 external termination (ROUT = 100). To match with a 50 external termination, set the LVDS STRENGTH bit (ROUT = 50). Figure 115. LVDS Buffer Equivalent Circuit 68 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Parallel CMOS Interface In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 116 depicts the CMOS output interface. Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window. It is recommended to use short traces (one to two inches or 2,54cm to 5,08cm) terminated with less than 5pF load capacitance, as shown in Figure 117. Pins OVR CLKOUT CMOS Output Buffers D0 D1 D2 D3 1/4 1/4 14-Bit ADC Data D11 D12 D13 ADS414x Figure 116. CMOS Output Interface Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 69 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Use External Clock Buffer (> 200MSPS) Input Clock Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CMOS Output Buffers D0 D1 D2 CLKIN D0_In D1_In D2_In 14-Bit ADC Data D12 D13 D12_In D13_In ADS414x Use short traces between ADC output and receiver pins (1 to 2 inches). Figure 117. Using the CMOS Data Outputs CMOS Interface Power Dissipation With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. Digital Current as a Result of CMOS Output Switching = CL x DRVDD x (N x fAVG) where: CL = load capacitance, N x FAVG = average number of output bits switching. (1) Figure 94 details the current across sampling frequencies at 2 MHz analog input frequency. 70 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Input Over-Voltage Indication (OVR Pin) The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS). For a positive overload, the D[13:0] output data bits are 3FFFh in offset binary output format and 1FFFh in twos complement output format. For a negative input overload, the output code is 0000h in offset binary output format and 2000h in twos complement output format. Output Data Format Two output data formats are supported: twos complement and offset binary. Each mode can be selected using the DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. BOARD DESIGN CONSIDERATIONS Grounding A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout and grounding. Supply Decoupling Because the ADS412x/4x already include internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply pins. Exposed Pad In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com). Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 71 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth - The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay - The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel). Aperture Uncertainty (Jitter) - The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle - The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle. Maximum Conversion Rate - The maximum sampling rate at which specified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate - The minimum sampling rate at which the ADC functions. Differential Nonlinearity (DNL) - An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs. Integral Nonlinearity (INL) - The INL is the deviation of the ADC transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Gain Error - Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as EGREF and EGCHAN. To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN. For example, if ETOTAL = 0.5%, the full-scale input varies from (1 - 0.5/100) x FSideal to (1 + 0.5/100) x FSideal. Offset Error - The offset error is the difference, given in number of LSBs, between the ADC actual average idle channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts. Temperature Drift - The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX - TMIN. Signal-to-Noise Ratio - SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first nine harmonics. SNR = 10Log10 PS PN (2) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Signal-to-Noise and Distortion (SINAD) - SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. SINAD = 10Log10 PS PN + PD (3) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. 72 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 ADS4122, ADS4125 ADS4142, ADS4145 SBAS520A - FEBRUARY 2011 - REVISED MARCH 2011 www.ti.com Effective Number of Bits (ENOB) - ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (4) Total Harmonic Distortion (THD) - THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (5) THD is typically given in units of dBc (dB to carrier). Spurious-Free Dynamic Range (SFDR) - The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion - IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 - f2 or 2f2 - f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. DC Power-Supply Rejection Ratio (DC PSRR) - DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The dc PSRR is typically given in units of mV/V. AC Power-Supply Rejection Ratio (AC PSRR) - AC PSRR is the measure of rejection of variations in the supply voltage by the ADC. If VSUP is the change in supply voltage and VOUT is the resultant change of the ADC output code (referred to the input), then: DVOUT PSRR = 20Log 10 (Expressed in dBc) DVSUP (6) Voltage Overload Recovery - The number of clock cycles taken to recover to less than 1% error after an overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and negative overload. The deviation of the first few samples after the overload (from the expected values) is noted. Common-Mode Rejection Ratio (CMRR) - CMRR is the measure of rejection of variation in the analog input common-mode by the ADC. If VCM_IN is the change in the common-mode voltage of the input pins and VOUT is the resulting change of the ADC output code (referred to the input), then: DVOUT CMRR = 20Log10 (Expressed in dBc) DVCM (7) Crosstalk (only for multi-channel ADCs) - This is a measure of the internal coupling of a signal from an adjacent channel into the channel of interest. It is specified separately for coupling from the immediate neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel input. It is typically expressed in dBc. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS4122 ADS4125 ADS4142 ADS4145 73 PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS4122IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS4122IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS4125IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS4125IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS4142IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS4142IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS4145IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS4145IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS4145IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (3) 26-Mar-2011 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Apr-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS4122IRGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4122IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4125IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4125IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4142IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4142IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4145IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS4145IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Apr-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS4122IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS4122IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS4125IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS4125IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS4142IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS4142IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS4145IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS4145IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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