Important notice
Dear Customer,
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1. General description
The 74HC30-Q100; 74HCT30-Q100 is an 8-input NAND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC30-Q100: CMOS level
For 74HCT30-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
74HC30-Q100; 74HCT30-Q100
8-input NAND gate
Rev. 1 — 30 January 2013 Product data sheet
Table 1. Ordering information
Type number Package
Temp erature range Name Description Version
74HC30D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74HCT30D-Q100
74HC30PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT30PW-Q100
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 2 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna488
A
Y
1
8
B
2C
3D
4E
5F
6G
11 H
12
8
&
mna489
1
2
3
4
5
6
11
12
Fig 3. Logic diagra m
B
A
C
D
F
E
G
H
mna490
Y
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 3 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration SO1 4 an d TSSO P1 4
+&4
+&74
$ 9
&&
% QF
& +
' *
( QF
) QF
*1' <
DDD





Table 2. Pin description
Symbol Pin Description
A 1 data input
B 2 data input
C 3 data input
D 4 data input
E 5 data input
F 6 data input
GND 7 ground (0 V)
Y 8 data output
n.c. 9 not connected
n.c. 10 not connected
G 11 dat a i nput
H 12 d ata input
n.c. 13 not connected
VCC 14 supply voltage
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 4 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
Table 3. Function table[1]
Input Output
A B C D E F G H Y
LXXXXXXXH
XLXXXXXXH
XXLXXXXXH
XXXLXXXXH
XXXXLXXXH
XXXXXLXXH
XXXXXXLXH
XXXXXXXLH
HHHHHHHHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V [1] -20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput curren t 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
SO14 and TSSOP14
packages [2] - 500 mW
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 5 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC30-Q100 74HCT30-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 62 5 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - n s /V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC30-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V --2.0- 20 - 40A
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 6 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
10. Dynamic characteristics
CIinput
capacitance -3.5- - - - -pF
74HCT30-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0 .8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =5.5V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =5.5V --2.0- 20 - 40A
ICC additional
supply current per input pin;
VI=V
CC 2.4 V; IO=0A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
- 60 216 - 275 - 294 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynam ic characteristics
GND = 0 V; CL= 50 pF; for test circuit see Figure 6.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
74HC30-Q100
tpd propagation delay A, B, C, D, E, F, G, H to Y;
see Figure 5 [1]
VCC = 2.0 V - 41 130 165 195 ns
VCC = 4.5 V - 15 26 33 39 ns
VCC = 5.0 V; CL=15pF - 12 - - - ns
VCC = 6.0 V - 12 22 28 33 ns
tttransition time see Figure 5 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 7 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+ (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
CPD power dissipation
capacitance per package; VI=GNDtoV
CC [3] -15- - -pF
74HCT30-Q100
tpd propagation delay A, B, C, D, E, F, G, H to Y;
see Figure 5 [1]
VCC = 4.5 V - 16 28 35 42 ns
VCC = 5.0 V; CL=15pF - 12 - - - ns
tttransition time VCC = 4.5 V; see Figure 5 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance per package;
VI=GNDtoV
CC 1.5 V [3] -15- - -pF
Table 7. Dynam ic characteristics …continued
GND = 0 V; CL= 50 pF; for test circuit see Figure 6.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Input to output propagation delays
001aal792
VOL
VOH
GND
VM
tPHL tPLH
tTHL tTLH
VM
VX
VY
nY output
A, B, C, D,
E, F, G, H
input
VI
Table 8. Measurement points
Type Input Output
VMVMVXVY
74HC30-Q100 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT30-Q100 1.3 V 1.3 V 0.1VCC 0.9VCC
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 8 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
Test data is given in Table 9.
Definitions for test circuit:
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
CL= load capacitance including jig and probe capacitance.
Fig 6. Test circuit for measuring switching times
001aah768
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 % VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC30-Q100 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT30-Q100 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 9 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
12. Package outline
Fig 7. Package outline SOT108-1 (SO14)
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 10 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
Fig 8. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 11 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
MIL Military
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT30_Q100 v.1 20130130 Product data sheet - -
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 12 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
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Limited warr a nty and liability — Information in this document is believed to
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representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — T his NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
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Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
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Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
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NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
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Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
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products are sold subject to the general terms and conditions of commercial
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applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Pro duction This document contains the product specification.
74HC_HCT30_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 30 January 2013 13 of 14
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
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Translations — A non-English (translated) version of a document is for
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between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC30-Q100; 74HCT30-Q100
8-input NAND gate
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 January 2013
Document identifier: 74HC_ HCT30_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14