BUK9225-55A
TrenchMOS™ logic level FET
Rev. 01 — 17 April 2001 Product specification
c
c
M3D300
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™1 technology, featuring very low on-state resistance.
Product availability:
BUK9225-55A in SOT428 (D-PAK).
2. Features
■TrenchMOS™ technology
■Q101 compliant
■175 °C rated
■Logic level compatible.
3. Applications
■Automotive and general purpose power switching:
◆12 V and 24 V loads
◆Motors, lamps and solenoids.
4. Pinning information
1. TrenchMOS is a trademark of Royal Philips Electronics.
Table 1: Pinning - SOT428 (D-PAK), simplified outline and symbol
Pin Description Simplified outline Symbol
1 gate (g)
SOT428 (D-PAK)
2 drain (d)
3 source (s)
mb mounting base;
connected to
drain (d)
MBK091
Top view
13
mb
2
s
d
g
MBB076
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 2 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
5. Quick reference data
6. Limiting values
[1] IDM is limited by chip, not package.
Table 2: Quick reference data
Symbol Parameter Conditions Typ Max Unit
VDS drain-source voltage (DC) −55 V
IDdrain current (DC) Tmb =25°C; VGS =5V −43 A
Ptot total power dissipation Tmb =25°C−94 W
Tjjunction temperature −175 °C
RDSon drain-source on-state resistance Tj=25°C; VGS =5V; I
D= 25 A 21 25 mΩ
Tj=25°C; VGS = 4.5 V; ID= 25 A −27 mΩ
Tj=25°C; VGS = 10 V; ID= 25 A 19 22 mΩ
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage (DC) −55 V
VDGR drain-gate voltage (DC) RGS =20kΩ−55 V
VGS gate-source voltage (DC) −±15 V
IDdrain current (DC) Tmb =25°C; VGS =5V;
Figure 2 and 3−43 A
Tmb = 100 °C; VGS =5V;Figure 2 −30 A
IDM peak drain current Tmb =25°C; pulsed; tp≤10 µs;
Figure 3 [1] −173 A
Ptot total power dissipation Tmb =25°C; Figure 1 −94 W
Tstg storage temperature −55 +175 °C
Tjoperating junction temperature −55 +175 °C
Source-drain diode
IDR reverse drain current (DC) Tmb =25°C−43 A
IDRM pulsed reverse drain current Tmb =25°C; pulsed; tp≤10 µs−173 A
Avalanche ruggedness
WDSS non-repetitive avalanche energy unclamped inductive load; ID=43A;
VDS ≤55 V; VGS =5V; R
GS =50Ω;
starting Tj=25°C
−123 mJ
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 3 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
VGS ≥4.5 V
Fig 1. Normalized total power dissipation as a
function of mounting base temperature. Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
Tmb =25°C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
03aa16
0
20
40
60
80
100
120
0 50 100 150 200
T
mb
(
o
C)
P
der
(%)
03aa24
0
20
40
60
80
100
120
0 25 50 75 100 125 150 175 200
Ider
(%)
Tmb (oC)
Pder Ptot
Ptot 25 C
°
()
---------------------- 100%×=
Ider ID
ID25C
°
()
-------------------100%×=
03ne70
1
10
10
2
10
3
1 10 10
2
VDS (V)
ID
(A)
D.C.
100 ms
10 ms
RDSon = VDS / ID
1 ms
tp = 10 us
100 us
tp
tp
T
P
t
T
δ =
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 4 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
7. Thermal characteristics
7.1 Transient thermal impedance
Table 4: Thermal characteristics
Symbol Parameter Conditions Value Unit
Rth(j-a) thermal resistance from junction to ambient 71.4 K/W
Rth(j-mb) thermal resistance from junction to mounting
base Figure 4 1.6 K/W
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
03ne71
Single Shot
0.2
0.1
0.05
0.02
10
-2
10
-1
1
10
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
1
tp (s)
Zth(j-mb)
(K/W)
δ = 0.5
tp
tp
T
P
t
T
δ =
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 5 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
8. Characteristics
Table 5: Characteristics
T
j
=25
°
C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
voltage ID= 0.25 mA; VGS =0V
Tj=25°C55−−V
Tj=−55 °C50−−V
VGS(th) gate-source threshold voltage ID= 1 mA; VDS =V
GS;
Figure 9
Tj=25°C 1 1.5 2 V
Tj= 175 °C 0.5 −−V
Tj=−55 °C−−2.3 V
IDSS drain-source leakage current VDS = 55 V; VGS =0V
Tj=25°C−0.05 10 µA
Tj= 175 °C−−500 µA
IGSS gate-source leakage current VGS =±10 V; VDS =0V −2 100 nA
RDSon drain-source on-state
resistance VGS =5V; I
D=25A;
Figure 7 and 8
Tj=25°C−21 25 mΩ
Tj= 175 °C−−50 mΩ
VGS = 4.5 V; ID=25A; −−27 mΩ
VGS =10V; I
D=25 A; −19 22 mΩ
Dynamic characteristics
Ciss input capacitance VGS =0V; V
DS =25V;
f = 1 MHz; Figure 12 −1360 1724 pF
Coss output capacitance −240 287 pF
Crss reverse transfer capacitance −160 222 pF
td(on) turn-on delay time VDD = 30 V; RL= 1.2 Ω;
VGS =5V; R
G=10Ω;−17 −ns
trrise time −104 −ns
td(off) turn-off delay time −82 −ns
tffall time −80 −ns
Ldinternal drain inductance measured from drain to
centre of die −2.5 −nH
Lsinternal source inductance measured from source lead
to source bond pad −7.5 −nH
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 6 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
Source-drain diode
VSD source-drain (diode forward)
voltage IS= 15 A; VGS =0V;
Figure 15 −0.85 1.2 V
trr reverse recovery time IS=20A;dI
S/dt = −100 A/µs
VGS =−10 V; VDS =30V −50 −ns
Qrrecovered charge −85 −nC
Table 5: Characteristics
…continued
T
j
=25
°
C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
Tj=25°CT
j=25°C; ID=25A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values. Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values.
Tj=25°C
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values. Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
03na05
0
20
40
60
80
100
120
140
160
180
0246810
VDS (V)
ID
(A)
2.2
3
4
5
6
7
10
8
VGS (V) = 9
03na03
10
15
20
25
30
35
40
45
246810
VGS (V)
RDSon
(mΩ)
03na06
10
15
20
25
30
35
40
45
50
10 30 50 70 90
ID (A)
RDSon
(mΩ)
5
4
3.8
3.6
3.4
3.2
3VGS (V)=
03ne89
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
-60 -20 20 60 100 140 180
Tj (oC)
a
aRDSon
RDSon 25 C
°
()
----------------------------
=
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 7 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
ID= 1 mA; VDS =V
GS Tj=25°C; VDS =V
GS
Fig 9. Gate-source threshold voltage as a function of
junction temperature. Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
Tj=25°C; VDS =25V V
GS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values. Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
03aa33
0
0.5
1
1.5
2
2.5
-60 0 60 120 180
T
j
(
o
C)
V
GS(th)
(V)
03aa36
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
0 0.5 1 1.5 2 2.5 3
V
GS
(V)
I
D
(A)
maxtypmin
03na04
0
5
10
15
20
25
30
35
40
0 20406080
ID (A)
gfs
(S)
03na09
0
500
1000
1500
2000
2500
3000
3500
4000
10-2 10-1
1 10
102
VDS (V)
C
(pF)
Ciss
Coss
Crss
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 8 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
VDS =25V T
j=25°C; ID=25A
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values. Fig 14. Gate-source voltage as a function of turn-on
gate charge; typical values.
VGS =0V
Fig 15. Reverse diode current as a function of reverse diode voltage; typical values.
03na00
0
20
40
60
80
100
0246
VGS (V)
ID
(A)
Tj = 25 oC
Tj = 175 oC
03na02
0
1
2
3
4
5
6
0 10203040
QG (nC)
VGS
(V)
VDD = 44 V
VDD= 14 V
03na01
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
VSD (V)
IS
(A)
Tj = 175 oCTj = 25 oC
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 9 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
9. Package outline
Fig 16. SOT428 (D-PAK).
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT428 TO-252 SC-63 98-04-07
99-09-13
0 10 20 mm
scale
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped) SOT428
E
b2D1
wAM
bc
b1
L1
L
13
2
D
E1
HE
L2
Note
1. Measured from heatsink back to lead.
e1
e
AA2
A
A1
y
seating plane
mounting
base
A1(1) D
max.
bD1
max. E
max. HE
max. wy
max.
A2b2
b1
max. cE1
min. ee
1L1
min. L2
L
A
max.
UNIT
DIMENSIONS (mm are the original dimensions)
0.2 0.2
mm 2.38
2.22 0.65
0.45 0.89
0.71
0.89
0.71 1.1
0.9 5.36
5.26 0.4
0.2 6.22
5.98 4.81
4.45 2.285 4.57 10.4
9.6 0.5 0.7
0.5
6.73
6.47 4.0 2.95
2.55
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 10 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
10. Revision history
Table 6: Revision history
Rev Date CPCN Description
01 20010417 - Product specification; initial version.
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 11 of 13
9397 750 08134 © Philips Electronics N.V. 2001 All rights reserved.
11. Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
12. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
13. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Data sheet status[1] Product status[2] Definition
Objective data Development This datasheet contains data from theobjectivespecification forproduct development.Philips Semiconductors
reserves the right to change the specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.
Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to
make changes at any time in order to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change Notification (CPCN) procedure
SNW-SQ-650A.
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 17 April 2001 12 of 13
9397 750 08134 © Philips Electronics N.V. 2001. All rights reserved.
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(SCA72)
© Philips Electronics N.V. 2001. Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
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intellectual property rights.
Date of release: 17 April 2001 Document order number: 9397 750 08134
Contents
Philips Semiconductors BUK9225-55A
TrenchMOS™ logic level FET
1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
7 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
7.1 Transient thermal impedance. . . . . . . . . . . . . . 4
8 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
10 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
11 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 11
12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
