Micropower, Dual-Channel Digital Isolators
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Ultralow power operation
3.3 V operation
5.6 μA per channel quiescent current, refresh enabled
0.3 μA per channel quiescent current, refresh disabled
148 μA/Mbps per channel typical dynamic current
2.5 V operation
3.1 μA per channel quiescent current, refresh enabled
0.1 μA per channel quiescent current, refresh disabled
116 μA/Mbps per channel typical dynamic current
Small, 20-lead SSOP package and small 8-lead SOIC package
Bidirectional communication
Up to 2 Mbps data rate nonreturn to zero (NRZ)
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/μs
Safety and Regulatory Approvals
UL 1577 component recognition program
3750 V rms for 1 minute per UL 1577 (20-lead SSOP)
3000 V rms for 1 minute per UL 1577 (8-lead SOIC)
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 849 V peak (20-lead SSOP)
VIORM = 560 V peak (8-lead SOIC)
APPLICATIONS
General-purpose, low power, multichannel isolation
1 MHz low power serial peripheral interface (SPI)
4 mA to 20 mA loop process control
GENERAL DESCRIPTION
The ADuM1240/ADuM1241/ADuM1245/ADuM12461 are
micropower, 2-channel, digital isolators based on the Analog
Devices, Inc., iCoupler® technology. Combining high speed,
complementary metal oxide semiconductor (CMOS) and
monolithic air core transformer technologies, these isolation
components provide outstanding performance characteristics
superior to the alternatives, such as optocoupler devices.
The 20-lead SSOP version of the ADuM1240/ADuM1241/
ADuM1245/ADuM1246 allows control of the internal refresh
functions. As shown in Figure 3, in standard operating mode,
when ENx = 0 (internal refresh enabled), the current per channel is
less than 10 μA.
When ENx = 1 (internal refresh disabled), the current per
channel drops to less than 1 μA.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
NIC
NIC
V
IA/VOA
VIB
EN1
NIC
VDD2
GND2
NIC
NIC
VOA/VIA
VOB
EN2
NIC
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
NIC
GND1
NIC
GND2
9
10
12
11
ADuM124x
11925-002
Figure 1. 20-Lead SSOP Package Functional Block Diagram
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
/V
OA
V
IB
V
DD2
V
OA
/V
IA
V
OB
1
2
3
4
8
7
6
5
GND
2
ADuM124x
11925-102
Figure 2. 8-Lead SOIC Package Functional Block Diagram
The ADuM1240/ADuM1241/ADuM1245/ADuM1246 are
packaged in either a 20-lead SSOP for 3.75 kV reinforced
isolation or an 8-lead SOIC for 3 kV basic isolation. The devices
meet regulatory requirements, such as UL and CSA standards.
In addition to the space saving package options, the ADuM1240/
ADuM1241/ADuM1245/ADuM1246 operate with supplies as
low as 2.25 V. All models provide low, pulse width distortion at
<8 ns. In addition, every model has an input glitch filter to
protect against extraneous noise disturbances.
0.1
1
10
100
1000
0.1 1 10 100 1000 10000
TYPIC
A
L TOTAL SUPPLY CURRENT
PER CHANN EL (µA)
DATA RATE (kbps)
EN
x
= 1
EN
x
= 0
11925-001
Figure 3. Typical Total Supply Current (IDD1 + IDD2) per Channel (VDDx =
3.3 V) as a Function of Data Rate
1 Protected by U.S. Patents 5,952,849, 6,873,065, 7,075,329, 6,262,600. Other patents pending.
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics3.3 V Operation ............................ 3
Electrical Characteristics2.5 V Operation ............................ 4
Electrical Characteristics—VDD1 = 3.3 V, VDD2 = 2.5 V
Operation ....................................................................................... 6
Electrical Characteristics—VDD1 = 2.5 V, VDD2 = 3.3 V
Operation ....................................................................................... 6
Package Characteristics ............................................................... 7
Regulatory Information ............................................................... 7
Insulation and Safety Related Specifications ............................ 8
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics ............................................................ 8
Recommended Operating Conditions ...................................... 9
Absolute Maximum Ratings ..................................................... 10
Continuous Working Voltage ................................................... 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Truth Tables................................................................................. 13
Typical Performance Characteristics ........................................... 14
Applications Information .............................................................. 17
PCB Layout ................................................................................. 17
Propagation Delay Related Parameters ................................... 17
DC Correctness and Low Power Operation ........................... 17
Magnetic Field Immunity.......................................................... 18
Power Consumption .................................................................. 19
Insulation Lifetime ..................................................................... 19
Packaging and Ordering Information .......Error! Bookmark not
defined.
Outline Dimensions ................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
9/2016—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Regulatory Information Section and Table 12 ......... 7
3/2014Rev. 0 to Rev. A
Added 8-lead SOIC Package ............................................. Universal
Changes to Features Section, General Description Section, and
Figure 3 .............................................................................................. 1
Deleted Product Highlights Section............................................... 1
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Table 12 .......................................................................... 7
Changes to Table 13 .......................................................................... 8
Added Table 14; Renumbered Sequentially .................................. 8
Changed Case Temperature to Ambient Temperature,
Figure 4 Caption ............................................................................... 9
Added Figure 5................................................................................ 11
Changes to Table 19 ....................................................................... 11
Added Figure 7................................................................................ 12
Changes to Table 20 ....................................................................... 12
Changes to Table 22 and Table 23 ....................................................... 13
Changes to PCB Layout Section ............................................................. 17
Added Figure 28 ......................................................................................... 17
Changes to Recommended Input Voltage for Low Power
Operation Section........................................................................... 18
Added Figure 35, Outline Dimensions ........................................ 20
Changes to Ordering Guide .......................................................... 21
12/2013Revision 0: Initial Version
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 3.6 V, and 40°C TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 1.
Parameter Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
2
Mbps
Within pulse width distortion (PWD) limit
Propagation Delay tPHL, tPLH 80 180 ns 50% input to 50% output
Change vs. Temperature 200 ps/°C
Minimum Pulse Width PW 500 ns Within PWD limit
Pulse Width Distortion PWD 8 ns |tPLH − tPHL|
Propagation Delay Skew1 tPSK 10 ns
Channel Matching
Codirectional tPSKCD 10 ns
Opposing Direction tPSKOD 15 ns
1 tPSK is the magnitude of the worst case difference in tPHL and tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY CURRENT 2 Mbps, no load
ADuM1240/ADuM1245 IDD1 366 600 µA
IDD2 246 375 µA
ADuM1241/ADuM1246 IDD1 306 450 µA
IDD2 306 450 µA
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Threshold
Logic High VIH 0.7 VDDx1 V
Logic Low VIL 0.3 VDDx1 V
Output Voltages
Logic High VOH VDDx1 − 0.1 3.3 V IOUTx = −20 µA, VIx = VIxH
VDDx1 − 0.4 3.1 V IOUTx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOUTx = 20 µA, VIx = VIxL
0.2 0.4 V IOUTx = 4 mA, VIx = VIxL
Input Current per Channel II −1 +0.01 +1 µA 0 V VIx VDDx1
Input Switching Thresholds
Positive Threshold Voltage VT+ 1.8 V
Negative Going Threshold VT− 1.2 V
Input Hysteresis ΔVT 0.6 V
Undervoltage Lockout, VDD1 or VDD2 UVLO 1.5 V
Supply Current per Channel
Quiescent Current
Input Supply IDDI (Q) 4.8 10 µA ENX low
Output Supply IDDO (Q) 0.8 6 µA ENX low
Input (Refresh Off ) IDDI (Q) 0.12 µA ENX high
Output (Refresh Off) IDDO (Q) 0.13 µA ENX high
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 4 of 24
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Dynamic Supply Current
Input IDDI (D) 88 µA/Mbps
Output IDDO (D) 60 µA/Mbps
AC SPECIFICATIONS
Output Rise Time/Fall Time tR/tF 2 ns 10% to 90%
Common-Mode Transient Immunity2 |CM| 25 40 kV/µs VIx = VDDx1, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
f
r
14
kbps
1 VDDx = VDD1 or VDD2.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and
falling common-mode voltage edges.
ELECTRICAL CHARACTERISTICS2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum and maximum specifications apply over the entire
recommended operation range of 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD22.75 V, and 40°C TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate 2 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 112 180 ns 50% input to 50% output
Change vs. Temperature 280 ps/°C
Pulse Width Distortion PWD 12 ns |tPLH − tPHL|
Minimum Pulse Width PW 500 ns Within PWD limit
Propagation Delay Skew1 tPSK 10 ns
Channel Matching
Codirectional tPSKCD 10 ns
Opposing Direction tPSKOD 30 ns
1 tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 5.
Parameter Symbol
Min
Typ
Max
Unit Test Conditions/Comments
SUPPLY CURRENT 2 Mbps, no load
ADuM1240/ADuM1245 IDD1 312 400 µA
IDD2 168 250 µA
ADuM1241/ADuM1246 IDD1 240 375 µA
I
DD2
240
375
µA
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 5 of 24
Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Threshold
Logic High VIH 0.7 VDDx1 V
Logic Low VIL 0.3 VDDx1 V
Output Voltages
Logic High VOH VDDx1 − 0.1 2.5 V IOx = −20 µA, VIx = VIxH
VDDx1 0.4 2.35 V IOx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.1 0.4 V IOx = 4 mA, VIx = VIxL
Input Current per Channel
I
I
−1
+0.01
+1
µA
0 V
V
Ix
V
DDx1
Input Switching Thresholds
Positive Threshold Voltage VT+ 1.5 V
Negative Going Threshold VT− 1.0 V
Input Hysteresis ΔVT 0.5 V
Undervoltage Lockout, VDD1 or VDD2 UVLO 1.5 V
Supply Current per Channel
Quiescent Current
Input Supply IDDI (Q) 2.6 3.75 µA ENX low
Output Supply IDDO (Q) 0.5 3.75 µA ENX low
Input (Refresh Off ) IDDI (Q) 0.05 µA ENX high
Output (Refresh Off) IDDO (Q) 0.05 µA ENX high
Dynamic Supply Current
Input IDDI (D) 76 µA/Mbps
Output IDDO (D) 41 µA/Mbps
AC SPECIFICATIONS
Output Rise Time/Fall Time tR/tF 2 ns 10% to 90%
Common-Mode Transient Immunity2 |CM| 25 40 kV/µs VIx = VDDx1, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 14 kbps
1 VDDx = VDD1 or VDD2.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and
falling common-mode voltage edges.
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 6 of 24
ELECTRICAL CHARACTERISTICS—VDD1 = 3.3 V, VDD2 = 2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V, and VDD2 = 2.5 V. Minimum and maximum specifications apply over the entire
recommended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 2.25 V ≤ VDD22.75 V, and 40°C TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
For dc specifications and ac specifications, see Table 3 for parameters related to Side 1 operation, and see Table 6 for parameters related to
Side 2 operation.
Table 7.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate 2 Mbps Within PWD limit
Propagation Delay
Side 1 to Side 2 tPHL, tPLH 84 180 ns 50% input to 50% output
Side 2 to Side 1 tPHL, tPLH 120 180 ns 50% input to 50% output
Change vs. Temperature 280 ps/°C
Pulse Width Distortion PWD 12 ns |tPLHtPHL|
Pulse Width PW 500 ns Within PWD limit
Propagation Delay Skew1 tPSK 10 ns
Channel Matching
Codirectional
t
PSKCD
10
ns
Opposing Direction
t
PSKOD
60
ns
1 tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT 2 Mbps, no load
ADuM1240/ADuM1245 IDD1 366 500 µA
IDD2 168 375 µA
ADuM1241/ADuM1246 IDD1 306 400 µA
IDD2 240 375 µA
ELECTRICAL CHARACTERISTICS—VDD1 = 2.5 V, VDD2 = 3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 2.5 V, and VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range of 2.25 V ≤ VDD1 ≤ 2.75 V, 3.0 V ≤ VDD2 3.6 V, and 40°C TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
For dc specifications and ac specifications, see Table 6 for parameters related to Side 1 operation, and see Table 3 for parameters related to
Side 2 operation.
Table 9.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate
2
Mbps
Within PWD limit
Propagation Delay
Side 1 to Side 2
t
PHL
, t
PLH
120
180
ns
50% input to 50% output
Side 2 to Side 1
t
PHL
, t
PLH
84
180
ns
50% input to 50% output
Change vs. Temperature
200
ps/°C
Pulse Width Distortion
PWD
12
ns
|t
PLH
− t
PHL
|
Pulse Width
PW
500
ns
Within PWD limit
Propagation Delay Skew1
t
PSK
10
ns
Channel Matching
Codirectional
t
PSKCD
10
ns
Opposing Direction
t
PSKOD
60
ns
1 tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 7 of 24
Table 10.
Parameter Symbol
Min
Typ
Max
Unit Test Conditions/Comments
SUPPLY CURRENT 2 Mbps, no load
ADuM1240/ADuM1245 IDD1 306 500 µA
IDD2 248 375 µA
ADuM1241/ADuM1246 IDD1 240 375 µA
IDD2 306 450 µA
PACKAGE CHARACTERISTICS
Table 11.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 RI-O 1013
Capacitance (Input to Output)1 CI-O 2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction to Ambient Thermal Resistance θJA 85 °C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 18 and the Absolute Maximum Ratings section for recommended maximum working voltages for specific cross isolation
waveforms and insulation levels.
Table 12.
UL CSA VDE
Recognized under 1577 component
recognition program1
Approved under CSA Component Acceptance Notice 5A Certified according to DIN V VDE V
0884-10 (VDE V 0884-10): 2006-122
Single protection, 8-lead SOIC package,
3000 V rms isolation voltage
8-lead SOIC package, basic insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (565 V peak) maximum working
voltage
8-lead SOIC package, reinforced
insulation, 560 VPEAK
Single protection, 20-lead SSOP package,
3750 V rms isolation voltage
20-lead SSOP package, basic insulation per CSA 60950-1-03
and IEC 60950-1, 530 V rms (700 V peak) maximum working
voltage
20-lead SSOP package, reinforced
insulation, 849 VPEAK
20-lead SSOP package, reinforced insulation per CSA
60950-1-03 and IEC 60950-1, 265 V rms (374 V peak)
maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL1577, each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second
(current leakage detection limit = 5 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥1050 V peak for
1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 8 of 24
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 13.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage
(8-Lead SOIC)
3000
V rms
1 minute duration
Rated Dielectric Insulation Voltage
(20-Lead SSOP)
3750 V rms 1 minute duration
Minimum External Tracking and Air Gap,
8-Lead SOIC (Creepage and Clearance)
L(I02) 4 mm min Measured from input terminals to output terminals,
shortest distance path along package body
Minimum Clearance in the Plane of the
Printed Circuit Board, 8-Lead SOIC (PCB
Clearance)
L(I01) 4.5 mm min Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Minimum Clearance in the Plane of the
Printed Circuit Board, 20-Lead SSOP
(PCB Clearance)
L(I01) 5.1 mm min Measured from input terminals to output terminals,
shortest distance path along package body
Minimum Clearance in the Plane of the
Printed Circuit Board, 20-Lead SSOP
(PCB Clearance)
L(I02) 5.1 mm min Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Minimum Internal Gap (Internal
Clearance)
0.017 mm min Insulation distance through insulation
Tracking Resistance (Comparative
Tracking Index)
CTI >400 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.
Table 14. 8-Lead SOIC (R-8)
Parameter Symbol Test Conditions/Comments Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage 150 V rms I to IV
For Rated Mains Voltage 300 V rms I to III
For Rated Mains Voltage 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage
V
IORM
560
V
PEAK
Input to Output Test Voltage, Method b1 Vpd(m) VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = one second, partial discharge < 5 pC
1050 VPEAK
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1 Vpd(m) VIORM × 1.5 = Vpd(m), tini = 60 seconds, tm = 10 seconds,
partial discharge < 5 pC
840 VPEAK
After Input and/or Safety Test Subgroup 2
and Subgroup 3
V
pd(m)
V
IORM
× 1.2 = V
pd(m)
, t
ini
= 60 seconds, t
m
= 10 seconds,
partial discharge < 5 pC
672
V
PEAK
Highest Allowable Overvoltage VIOTM 3500 VPEAK
Surge Isolation Voltage VIOSM VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time 4000 VPEAK
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 4)
Case Temperature TS 150 °C
Total Power Dissipation at 25°C IS1 1.64 W
Insulation Resistance at TS RS VIO = 500 V >109
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 9 of 24
Table 15. 20-Lead SSOP (RS-20)
Parameter Symbol Test Conditions/Comments Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage 150 V rms I to IV
For Rated Mains Voltage 300 V rms I to III
For Rated Mains Voltage 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 849 VPEAK
Input to Output Test Voltage, Method b1 Vpd(m) VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = one second, partial discharge < 5 pC
1592 VPEAK
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1 Vpd(m) VIORM × 1.5 = Vpd(m), tini =60 seconds,
tm = 10 seconds, partial discharge < 5 pC
1273 VPEAK
After Input and/or Safety Test Subgroup 2 and
Subgroup 3
Vpd(m) VIORM × 1.2 = Vpd(m), tini = 60 seconds,
tm = 10 seconds, partial discharge < 5 pC
1018 VPEAK
Highest Allowable Overvoltage VIOTM 5335 VPEAK
Surge Isolation Voltage
V
IOSM
V
PEAK
= 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
6000
V
PEAK
Safety Limiting Values Maximum value allowed in the event of a
failure (see Figure 4)
Case Temperature TS 150 °C
Side 1 I
DD1
Current
I
S1
2.5
W
Insulation Resistance at TS RS VIO = 500 V >109
0
0.5
1.0
1.5
2.0
2.5
3.0
050 100 150 200
SAFE LIMITING POWER (W)
AMBIENT TEMPERATURE (°C)
11925-003
Figure 4. Thermal Derating Curve, Dependent on Safety Limiting Values with
Ambient Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 16.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +125 °C
Supply Voltages1 VDD1, VDD2 2.25 3.6 V
Input Signal Rise and Fall Times 1.0 ms
1 See the DC Correctness and Low Power Operation section for more
information.
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 10 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 17.
Parameter Rating
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature
(TA) Range
−40°C to +125°C
Supply Voltages (VDD1, VDD2) −0.5 V to +5 V
Input Voltages (VIA, VIB ) −0.5 V to VDDI + 0.5 V
Output Voltages (VOA, VOB) −0.5 V to VDD2 + 0.5 V
Average Output Current per Pin1
Side 1 (IO1) −10 mA to +10 mA
Side 2 (IO2) −10 mA to +10 mA
Common-Mode Transients2 −100 kV/μs to +100 kV/μs
1 See Figure 4 for maximum rated current values for various temperatures.
2 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings can cause
latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
CONTINUOUS WORKING VOLTAGE
Table 18. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC Voltage
Bipolar Waveform 565 V peak 50-year minimum
lifetime
Unipolar Waveform 1131 V peak 50-year minimum
lifetime
DC Voltage 1131 V peak 50-year minimum
lifetime
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 11 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
VIA 2
VIB 3
GND14
VDD2
8
7
6
GND2
5
VOA
VOB
ADuM1240/
ADuM1245
TOP VI EW
(Not to Scale)
11925-104
Figure 5. ADuM1240/ADuM1245 8-Lead SOIC (R-8) Pin Configuration
V
DD1 1
GND
12
NIC
3
NIC
4
V
DD2
NIC = NOT INT ERNALLY CONNECTED.
20
GND
2
19
NIC
18
NIC
17
V
IA 5
V
OA
16
V
IB 6
V
OB
15
EN
17
EN
2
14
NIC
8
NIC
13
NIC
9
NIC
12
GND
110
GND
2
11
ADuM1240/
ADuM1245
TOP VIEW
(No t to S cale)
11925-004
Figure 6. ADuM1240/ADuM1245 20-Lead SSOP (RS-20) Pin Configuration
Table 19. ADuM1240/ADuM1245 8-Lead SOIC (R-8) and 20-Lead SSOP (RS-20) Pin Function Descriptions1
8-Lead
SOIC
Pin No.2
20-Lead
SSOP
Pin No. Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range
of 0.01 μF to 0.1 μF between VDD1 and GND1.
N/A 2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and
connecting both to GND1 is recommended.
N/A 3 NIC Not Internally Connected. Leave this pin floating.
N/A 4 NIC Not Internally Connected. Leave this pin floating.
2 5 VIA Logic Input A.
3 6 VIB Logic Input B.
N/A 7 EN1 Refresh and Watchdog Enable 1. In the 20-lead SSOP package, connecting Pin 7 to GND1 enables
the input/output refresh and watchdog functionality for Side 1, supporting standard iCoupler
operation. Tying Pin 7 to VDD1 disables the refresh and watchdog functionality for the lowest power
operation. See the DC Correctness and Low Power Operation section for a description of this mode.
EN1 and EN2 must be set to the same logic state.
N/A 8 NIC Not Internally Connected. Leave this pin floating.
N/A 9 NIC Not Internally Connected. Leave this pin floating.
4 10 GND1 Ground 1. Ground reference for Isolator Side 1. In the 20-lead SSOP package, Pin 2 and Pin 10 are
internally connected, and connecting both to GND1 is recommended.
5 11 GND2 Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are
internally connected, and connecting both to GND2 is recommended.
N/A 12 NIC Not Internally Connected. Leave this pin floating.
N/A 13 NIC Not Internally Connected. Leave this pin floating.
N/A 14 EN2 Refresh and Watchdog Enable 2. In the 20-lead SSOP package, connecting Pin 14 to GND2 enables
the input/output refresh and watchdog functionality for Side 2, supporting standard iCoupler
operation. Tying Pin 14 to VDD2 disables the refresh and watchdog functionality for lowest power
operation. See the DC Correctness and Low Power Operation section for a description of this mode.
EN1 and EN2 must be set to the same logic state.
6 15 VOB Logic Output B.
7 16 VOA Logic Output A.
N/A 17 NIC Not Internally Connected. Leave this pin floating.
N/A 18 NIC Not Internally Connected. Leave this pin floating.
N/A 19 GND2 Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are
internally connected, and connecting both to GND2 is recommended.
8 20 VDD2 Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range
of 0.01 μF to 0.1 μF between VDD2 and GND2.
1 Reference AN-1109 for specific layout guidelines.
2 N/A means not applicable.
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 12 of 24
V
DD1 1
V
OA 2
V
IB 3
GND
14
V
DD2
8
7
6
GND
2
5
V
IA
V
OB
ADuM1241/
ADuM1246
TOP VIEW
(No t t o Scal e)
11925-105
Figure 7. ADuM1241/ADuM1246 8-Lead SOIC (R-8) Pin Configuration
V
DD1 1
GND
12
NIC
3
NIC
4
V
DD2
NIC = NOT INT E RNALLY CONNECTED.
20
GND
2
19
NIC
18
NIC
17
V
OA 5
V
IA
16
V
IB 6
V
OB
15
EN
17
EN
2
14
NIC
8
NIC
13
NIC
9
NIC
12
GND
110
GND
2
11
ADuM1241/
ADuM1246
TOP VIEW
(No t t o Scal e)
11925-005
Figure 8. ADuM1241/ADuM1246 20-Lead SSOP (RS-20) Pin Configuration
Table 20. ADuM1241/ADuM1246 8-Lead SOIC (R-8) and 20-Lead SSOP (RS-20) Pin Function Descriptions1
8-Lead
SOIC
Pin No.2
20-Lead
SSOP
Pin No. Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range
of 0.01 µF to 0.1 µF between VDD1 and GND1.
N/A 2 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and
connecting both to GND1 is recommended.
N/A 3 NIC Not Internally Connected. Leave this pin floating.
N/A
4
NIC
Not Internally Connected. Leave this pin floating.
2 5 VOA Logic Output A.
3 6 VIB Logic Input B.
N/A 7 EN1 Refresh and Watchdog Enable 1. In the 20-lead SSOP package, connecting Pin 7 to GND1 enables
the input/output refresh and watchdog functionality for Side 1, supporting standard iCoupler
operation. Tying Pin 7 to VDD1 disables the refresh and watchdog functionality for the lowest power
operation. See the DC Correctness and Low Power Operation section for a description of this mode.
EN1 and EN2 must be set to the same logic state.
N/A 8 NIC Not Internally Connected. Leave this pin floating.
N/A 9 NIC Not Internally Connected. Leave this pin floating.
4 10 GND1 Ground 1. Ground reference for Isolator Side 1. In the 20-lead SSOP package, Pin 2 and Pin 10 are
internally connected, and connecting both to GND1 is recommended.
5 11 GND2 Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are
internally connected, and connecting both to GND2 is recommended.
N/A 12 NIC Not Internally Connected. Leave this pin floating.
N/A 13 NIC Not Internally Connected. Leave this pin floating.
N/A 14 EN2 Refresh and Watchdog Enable 2. In the 20-lead SSOP package, connecting Pin 14 to GND2 enables
the input/output refresh and watchdog functionality for Side 2, supporting standard iCoupler
operation. Tying Pin 14 to VDD2 disables the refresh and watchdog functionality for lowest power
operation. See the DC Correctness and Low Power Operation section for a description of this mode.
EN1 and EN2 must be set to the same logic state.
6 15 VOB Logic Output B.
7 16 VIA Logic Input A.
N/A 17 NIC Not Internally Connected. Leave this pin floating.
N/A 18 NIC Not Internally Connected. Leave this pin floating.
N/A 19 GND2 Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are
internally connected, and connecting both to GND2 is recommended.
8 20 VDD2 Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range
of 0.01 µF to 0.1 µF between VDD2 and GND2.
1 Reference AN-1109 for specific layout guidelines.
2 N/A means not applicable.
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 13 of 24
TRUTH TABLES
Table 22 provides the truth table (positive logic) for the
ADuM1240 and the ADuM1241, and Table 23 provides the
truth table (positive logic) for the ADuM1245 and the
ADuM1246. For a description of the abbreviations used in the
truth tables, see Table 21.
Table 21. Truth Table Abbreviations
Letter Description
H High level
L Low level
Rising data transition
Falling data transition
X Irrelevant
QO Level of VOX prior to levels being established
Z High impedance
Table 22. ADuM1240/ADuM1241 Truth Table (Positive Logic)1, 2, 3
VIx Input VDDI State VDDO State
ENx
State VOx Output Description
H Powered Powered L H Normal operation; data is high and refresh is enabled.
L Powered Powered L L Normal operation; data is low and refresh is enabled.
X Unpowered Powered L H Input unpowered. Outputs are in the default high state. Outputs return to
the input state within 150 µs of VDDI power restoration. See the pin function
descriptions (Table 19 and Table 20) for details.
X Unpowered Powered H QO Input unpowered. Outputs are static at the level that was last sent from
the input or at the power-up level. See the pin function descriptions (Table 19
and Table 20) for details.
Powered Powered H H Output is high after propagation delay, refresh is disabled.
Powered Powered H L Output is low after propagation delay, refresh is disabled.
X Powered Unpowered X Z Output unpowered. Output pins are in high impedance state. Outputs
return to the input state within 150 µs of VDDO power restoration. See the
pin function descriptions (Table 19 and Table 20) for details.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
2 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D).
3 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
Table 23. ADuM1245/ADuM1246 Truth Table (Positive Logic)1, 2, 3
VIx Input VDDI State VDDO State ENx State VOx Output Description
H Powered Powered L H Normal operation; data is high and refresh is enabled.
L Powered Powered L L Normal operation; data is low and refresh is enabled.
X Unpowered Powered L L Input unpowered. Outputs are in the default low state. Outputs
return to the input state within 150 µs of VDDI power restoration. See
the pin function descriptions (Table 19 and Table 20) for details.
X Unpowered Powered H QO Input unpowered. Outputs are static at the level that was last sent
from the input or at the power-up level. See the pin function
descriptions (Table 19 and Table 20) for details.
Powered Powered H H Output is high, refresh is disabled.
Powered Powered H L Output is low, refresh is disabled.
X Powered Unpowered X Z Output unpowered. Output pins are in high impedance state.
Outputs return to input state within 150 µs of VDDO power restoration.
See the pin function descriptions (Table 19 and Table 20) for details.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
2 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D).
3 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 14 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
0
50
100
150
200
250
300
350
0500 1000 1500 2000
CURRENT CO NS UM P TI ON PE R INPUT ( µA)
DATA RATE (kbps)
V
DDx
INPUT CURRENT
0
5
10
15
020 40
11925-006
Figure 9. Current Consumption per Input vs. Data Rate for 2.5 V,
ENx = Low Operation
0
10
20
30
40
50
60
70
80
90
0500 1000 1500 2000
CURRENT CO NS UM P TI ON PE R O UTPUT A)
DATA RATE (kbps)
V
DDx
OUTPUT CURRE NT
0
2
4
020 40
11925-007
Figure 10. Current Consumption per Output vs. Data Rate for 2.5 V,
ENx = Low Operation
0
50
100
150
200
250
300
350
400
0500 1000 1500 2000
CURRENT CO NS UM P TI ON PE R INPUT (µA)
DATA RATE (kbps)
V
DDx
INPUT CURRENT
0
5
10
15
020 40
11925-008
Figure 11. Current Consumption per Input vs. Data Rate for 3.3 V,
ENx = Low Operation
0
20
40
60
80
100
120
140
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER OUT P UT A)
DATA RATE (kbps)
V
DDx
OUTPUT CURRE NT
0
2
4
020 40
11925-009
Figure 12. Current Consumption per Output vs. Data Rate for 3.3 V,
ENx = Low Operation
0
20
40
60
80
100
120
140
160
0500 1000 1500 2000
CURRENT CO NS UM P TI ON PE R I NP UTA)
DATA RATE (kbps)
VDDx INP UT CURRENT
0
0.5
1.0
0 5 10
11925-010
Figure 13. Current Consumption per Input vs. Data Rate for 2.5 V,
ENx = High Operation
0
10
20
30
40
50
60
70
80
90
0500 1000 1500 2000
CURRENT CO NS UM P TI ON PE R O UTPUT A)
DATA RATE (kbps)
VDDx OUTPUT CURRENT
0
0.5
1.0
0 5 10
11925-011
Figure 14. Current Consumption per Output vs. Data Rate for 2.5 V,
ENx = High Operation
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 15 of 24
0
20
60
40
100
80
120
140
160
180
200
0 500 1000 1500 2000
CURRENT CONSUMPTION PER INP UT A)
DATA RATE (kbps)
V
DDx
INP UT CURRE NT
0
0.5
1.0
0510
11925-012
Figure 15. Current Consumption per Input vs. Data Rate for VDDx = 3.3 V,
ENx = High Operation
0
20
40
60
80
100
120
140
0 500 1000 1500 2000
CURRENT CO NS U M PTIO N P ER O U TPUTA)
DATA RATE (kbps)
VDDx OUTPUT CURRENT
0
0.5
1.0
0510
11925-013
Figure 16. Current Consumption per Output vs. Data Rate for VDDx = 3.3 V,
ENx = High Operation
0
100
200
300
400
500
600
01234
I
DDx
CURRENT (µA)
DATA INPUT VOLTAGE (V)
FALLING
RISING
11925-014
Figure 17. Typical IDDx Current per Input vs. Data Input Voltage for
VDDx = 3.3 V
0
50
100
150
200
250
300
0 0.5 1.0 1.5 2.0 2.5 3.0
I
DDx
CURRENT (µA)
DATA INPUT VOLTAGE (V)
FALLING
RISING
11925-015
Figure 18. IDDx Current per Input vs. Data Input Voltage for VDDx = 2.5 V
0
1
2
3
4
5
6
7
8
9
10
–40 –20 0 20 40 60 80 100 120 140
SUPP LY CURRENT PER CHANNEL (µA)
TEMPERATURE (°C)
OUTPUT
INPUT
11925-016
Figure 19. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 2.5 V, Data Rate = 100 kbps
0
1
2
3
4
5
6
7
8
9
10
–40 –20 0 20 40 60 80 100 120 140
SUPPLY CURRENT PER CHANN
E
L (µ A )
TEMPERATURE (°C)
OUTPUT
INPUT
11925-017
Figure 20. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 3.3 V, Data Rate = 100 kbps
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 16 of 24
0
10
20
30
40
50
60
70
80
90
100
–40 –20 0 20 40 60 80 100 120 140
SUPPLY CURREN
T
PER CHANNEL
(
µA)
TEMPERATURE (°C)
OUTPUT
INPUT
11925-018
Figure 21. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDX = 2.5 V, Data Rate = 1000 kbps
0
10
20
30
40
50
60
70
80
90
100
–40 –20 0 20 40 60 80 100 120 140
SUPPLY CURRENT PER CHANNEL (µ A)
TEMPERATURE (°C)
OUTPUT
INPUT
11925-019
Figure 22. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDX = 3.3 V, Data Rate = 1000 kbps
0
20
40
60
80
100
120
140
–40 20 0 20 40 60 80 100 120 140
PROPAG
A
TION DEL
A
Y (ns)
TEMPERAT URE (°C)
V
DDx
= 2.5V
V
DDx
= 3.3V
11925-020
Figure 23. Typical Propagation Delay vs. Temperature for
VDDx = 3.3 V or VDDx = 2.5 V
0
20
40
60
80
100
120
2.0 2.5 3.0 3.5 4.0
GLITCH FILTER WIDT H (ns )
TRAN S MITT ER V
DDx
(V)
11925-021
Figure 24. Typical Glitch Filter Operation Threshold
0
20
40
60
80
100
120
140
–40 –20 0 20 40 60 80 100 120 140
REFRESH PERIOD (µs)
TEMPERATURE (°C)
V
DDx
= 2.5V
V
DDx
= 3.3V
11925-022
Figure 25. Typical Refresh Period vs. Temperature for
3.3 V and 2.5 V Operation
0
20
40
60
80
100
120
2.0 2.5 3.0 3.5 4.0
REFRESH PERIOD (µs)
V
DDx
VOLTAGE (V)
11925-023
Figure 26. Typical Refresh Period vs. VDDx Voltage
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 17 of 24
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM1240/ADuM1241/ADuM1245/ADuM1246 digital
isolators require no external interface circuitry for the logic
interfaces. Power supply bypassing is strongly recommended at
both the input and output supply pins: VDD1 and VDD2 (see
Figure 27). Maintain the capacitor value between 0.01 μF and
0.1 μF and for best results, ensure that the total lead length
between both ends of the capacitor and the input power supply
does not exceed 20 mm.
With proper PCB design choices, these digital isolators readily
meet CISPR 22 Class A (and FCC Class A) emissions standards,
as well as the more stringent CISPR 22 Class B (and FCC Class B)
standards in an unshielded environment. Refer to AN-1109 for
PCB related electromagnetic interference (EMI) mitigation
techniques, including board layout and stack up issues.
V
DD1
GND
1
NIC
NIC
V
IA/
V
OA
V
IB
EN
1
NIC
NIC = NO T INT E RNALL Y CO NNE C T E D.
V
DD2
GND
2
NIC
NIC
V
OA/
V
IA
V
OB
EN
2
NIC
NIC
GND
1
NIC
GND
2
11925-024
Figure 27. Recommended PCB Layout, 20-Lead SSOP (RS-20)
V
DD1
V
IA/
V
OA
V
IB
V
DD2
V
OA/
V
IA
V
OB
GND
1
GND
2
11925-124
Figure 28. Recommended PCB Layout, 8-Lead SOIC (R-8)
For applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this equal capacitive coupling of pins can
cause voltage differentials between pins exceeding the absolute
maximum ratings of the device, thereby leading to latch-up or
permanent damage.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input to
output propagation delay time for a high to low transition can
differ from the propagation delay time of a low to high transition.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
tPLH tPHL
50%
50%
11925-025
Figure 29. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values, and an indication of how
accurately the timing of the input signal is preserved.
Channel to channel matching refers to the maximum amount
the propagation delay differs between channels within a single
component of the ADuM1240/ADuM1241/ADuM1245/
ADuM1246.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM1240/
ADuM1241/ADuM1245/ADuM1246 components operating
under the same conditions.
DC CORRECTNESS AND LOW POWER OPERATION
Standard Operating Mode
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. When
refresh and watchdog functions are enabled, by pulling EN1 and
EN2 low, in the absence of logic transitions at the input for more
than ~140 μs, a periodic set of refresh pulses, indicative of the
correct input state, is sent to ensure dc correctness at the output. If
the decoder receives no internal pulses of more than approximately
200 μs, the device assumes that the input side is unpowered or
nonfunctional, in which case, the isolator watchdog circuit
forces the output to a default state. The default state is either high,
as in the ADuM1240 and ADuM1241 versions, or low, as in the
ADuM1245 and ADuM1246 versions.
Low Power Operating Mode
For the lowest power consumption, disable the refresh and
watchdog functions of the ADuM1240/ADuM1241/ADuM1245/
ADuM1246 by pulling EN1 and EN2 to logic high. These control
pins must be set to the same value on each side of the component
for proper operation.
In this mode, the current consumption of the chip drops to the
microampere range. However, be careful when using this mode,
because dc correctness is no longer guaranteed at startup. For
example, if the following sequence of events occurs:
1. Power is applied to Side 1.
2. A high level is asserted on the VIA input.
3. Power is applied to Side 2.
The high on VIA is not automatically transferred to the Side 2
VOA, and there can be a level mismatch that is not corrected until a
transition occurs at VIA. When power is stable on each side, and a
transition occurs on the input of the channel, the input and output
state of that channel is correctly matched. This contingency can
be resolved in several ways, such as sending dummy data, or
toggling refresh on for a short period to force synchronization after
turn on.
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 18 of 24
Recommended Input Voltage for Low Power Operation
The ADuM1240/ADuM1241/ADuM1245/ADuM1246
implement Schmitt trigger input buffers so that the devices
operate cleanly in low data rate, or in noisy environments. Schmitt
triggers allow a small amount of shoot through current when the
input voltage is not approximate to either VDDx or GNDx levels.
Shoot through is possible because the two transistors are both
slightly on when input voltages are in the middle of the supply
range. For many digital devices, this leakage is not a large portion
of the total supply current and cannot be noticed; however, in the
ultralow power
ADuM1240/ADuM1241/ADuM1245/ADuM1246, this leakage
can be larger than the total operating current of the device and
must not be ignored.
To achieve optimum power consumption with the ADuM1240/
ADuM1241/ADuM1245/ADuM1246, always drive the inputs as
near to VDDx or GNDx levels as possible. Figure 17 and Figure 18
illustrate the shoot through leakage of an input; therefore, whereas
the logic thresholds of the input are standard CMOS levels,
optimum power performance is achieved when the input logic
levels are driven within 0.5 V of either VDDx or GNDx levels.
MAGNETIC FIELD IMMUNITY
The limitation on the magnetic field immunity of the device is
set by the condition in which, induced voltage in the transformer
receiving coil is sufficiently large, to either falsely set or reset the
decoder. The following analysis defines such conditions. The
ADuM1240 is examined in a 3 V operating condition, because it
represents the typical mode of operation for these products.
The pulses at the transformer output have an amplitude greater
than 1.5 V. The decoder has a sensing threshold of about 1.0 V,
therefore establishing a 0.5 V margin in which induced voltages
are tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)∑πrn2; n = 1, 2, …, N
where:
β is the magnetic flux density.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1240, and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 30.
1000
1k 100M10k
MAXIMUM ALLOWABLE MAGNETIC FLUX (kgauss)
100k 1M 10M
MAG NE TIC FI E LD FRE QUENCY ( Hz )
100
10
1
0.1
0.01
0.001
11925-026
Figure 30. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maxi-
mum allowable magnetic field of 0.5 kgauss induces a voltage of
0.25 V at the receiving coil. This is about 50% of the sensing
threshold and does not cause a faulty output transition. If such
an event occurs, with the worst case polarity, during a transmitted
pulse, it would reduce the received pulse from >1.0 V to 0.75 V.
This is still higher than the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances away from the ADuM1240
transformers. Figure 31 expresses these allowable current magni-
tudes as a function of frequency for selected distances. The
ADuM1240 is very insensitive to external fields. Only extremely
large, high frequency currents, very close to the component,
could potentially be a concern. For the 1 MHz example noted,
the user would have to place a 1.2 kA current 5 mm away from
the ADuM1240 to affect component operation.
1000
1k 100M10k
MAXIMUM ALLOWABLE CURRENT (kA)
100k 1M 10M
MAG NE TIC FI E LD FRE QUENCY ( Hz )
100
10
1
0.1
0.01
DISTANCE = 1m
DISTANCE = 100mm
DISTANCE = 5mm
11925-027
Figure 31. Maximum Allowable Current for
Various Currents to ADuM1240 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces could induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Avoid PCB structures that form loops.
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 19 of 24
POWER CONSUMPTION
The supply current with refresh enabled at a given channel of
the ADuM1240/ADuM1241/ADuM1245/ADuM1246 isolators,
is a function of the supply voltage, the data rate of the channel,
and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2f fr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
IDDI (D) and IDDO (D) are the input and output dynamic supply
currents per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in units of Mbps.
fr is the input stage refresh rate (Mbps) = 1/Tr (µs).
IDDI (Q) and IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 9 through
Figure 16 show per channel supply currents as a function of
data rate for an unloaded output condition.
INSULATION LIFETIME
All insulation structures eventually degrade, when subjected to
voltage stress for a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. In addition to the testing
performed by the regulatory agencies, Analog Devices carries
out an extensive set of evaluations to determine the lifetime of
the insulation structure within the
ADuM1240/ADuM1241/ADuM1245/ADuM1246.
Analog Devices performs accelerated life testing using voltage levels
higher than the rated continuous working voltage. Acceleration
factors for several operating conditions are determined. These
factors allow calculation of the time to failure at the actual working
voltage.
The values shown in Table 18 summarize the peak voltage for 50
years of service life for a bipolar ac operating condition, and the
maximum CSA/VDE approved working voltages. In many cases,
the approved working voltage is higher than 50-year service life
voltage. Operation at these high working voltages can lead to
shortened insulation life, in some cases.
The insulation lifetime of the ADuM1240/ADuM1241/
ADuM1245/ADuM1246 depends on the voltage waveform type
imposed across the isolation barrier. The iCoupler insulation
structure degrades at different rates, depending on whether the
waveform is bipolar ac, unipolar ac, or dc. Figure 19, Figure 20,
and Figure 21 illustrate these different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime, under the ac bipolar condition,
determines the Analog Devices recommended maximum
working voltage.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages, while still achieving a 50-year service life. The working
voltages listed in Table 18 can be applied while maintaining the 50-
year minimum lifetime, provided the voltages conform to either the
unipolar ac or dc voltage case. Treat any cross-insulation voltage
waveform that does not conform to Figure 33 or Figure 34 as a
bipolar ac waveform, and limit peak voltage to the 50-year lifetime
voltage value listed in Table 18.
Note that the voltage presented in Figure 33 is shown as sinusoidal
for illustration purposes only. It represents any voltage waveform
varying between 0 V and some limiting value. The limiting value
can be positive or negative, but the voltage must not cross 0 V.
0V
RATED P E AK V OL TAGE
11925-028
Figure 32. Bipolar AC Waveform
0V
RATE D PE AK V OL TAGE
11925-029
Figure 33. Unipolar AC Waveform
0V
RATED P E AK V OL TAGE
11925-030
Figure 34. DC Waveform
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 20 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARENOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40(0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80(0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51(0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 35. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDE C S TANDARDS MO-150- AE
060106-A
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 M IN
0.65 BSC
2.00 M AX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
Figure 36. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 21 of 24
ORDERING GUIDE
Model1, 2
No.
of Inputs,
VDD1 Side
No.
of Inputs,
VDD2 Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 3.3 V
Output
Default
State
Temperature
Range
Package
Description
Package
Option
ADuM1240ARZ 2 0 2 180 High −40°C to +125°C 8-Lead SOIC_N R-8
ADuM1240ARZ-RL7
2
0
2
180
High
−40°C to +125°C
8-Lead SOIC_N
R-8
ADuM1240ARSZ 2 0 2 180 High −40°C to +125°C 20-Lead SSOP RS-20
ADuM1240ARSZ-RL7 2 0 2 180 High −40°C to +125°C 20-Lead SSOP RS-20
ADuM1241ARZ 1 1 2 180 High −40°C to +125°C 8-Lead SOIC_N R-8
ADuM1241ARZ-RL7 1 1 2 180 High −40°C to +125°C 8-Lead SOIC_N R-8
ADuM1241ARSZ
1
1
2
180
High
−40°C to +125°C
20-Lead SSOP
RS-20
ADuM1241ARSZ-RL7 1 1 2 180 High −40°C to +125°C 20-Lead SSOP RS-20
ADuM1245ARZ 2 0 2 180 Low −40°C to +125°C 8-Lead SOIC_N R-8
ADuM1245ARZ-RL7 2 0 2 180 Low −40°C to +125°C 8-Lead SOIC_N R-8
ADuM1245ARSZ 2 0 2 180 Low −40°C to +125°C 20-Lead SSOP RS-20
ADuM1245ARSZ-RL7 2 0 2 180 Low −40°C to +125°C 20-Lead SSOP RS-20
ADuM1246ARZ 1 1 2 180 Low −40°C to +125°C 8-Lead SOIC_N R-8
ADuM1246ARZ-RL7 1 1 2 180 Low −40°C to +125°C 8-Lead SOIC_N R-8
ADuM1246ARSZ 1 1 2 180 Low −40°C to +125°C 20-Lead SSOP RS-20
ADuM1246ARSZ-RL7 1 1 2 180 Low −40°C to +125°C 20-Lead SSOP RS-20
1 Z = RoHS Compliant Part.
2 Tape and reel is available. The addition of the -RL7 suffix indicates that the product is shipped on 7” tape and reel.
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 22 of 24
NOTES
Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246
Rev. B | Page 23 of 24
NOTES
ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet
Rev. B | Page 24 of 24
NOTES
©20132016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11925-0-9/16(B)