STM32G070RBT6 - STMICROELECTRONICS

This is information on a product in full production.

March 2020 DS12766 Rev 2 1/93

STM32G070CB/KB/RB

Arm® Cortex®-M0+ 32-bit MCU, 128 KB Flash, 36 KB RAM,

4x USART, timers, ADC, comm. I/Fs, 2.0-3.6V

Datasheet - production data

Features

Core: Arm® 32-bit Cortex®-M0+ CPU,

frequency up to 64 MHz

-40°C to 85°C operating temperature

Memories

– 128 Kbytes of Flash memory with

protection

– 36 Kbytes of SRAM (32 Kbytes with HW

parity check)

CRC calculation unit

Reset and power management

– Voltage range: 2.0 V to 3.6 V

– Power-on/Power-down reset (POR/PDR)

– Low-power modes:

Sleep, Stop, Standby

–V

BAT supply for RTC and backup registers

Clock management

– 4 to 48 MHz crystal oscillator

– 32 kHz crystal oscillator with calibration

– Internal 16 MHz RC with PLL option

– Internal 32 kHz RC oscillator (±5 %)

Up to 59 fast I/Os

– All mappable on external interrupt vectors

– Multiple 5 V-tolerant I/Os

7-channel DMA controller with flexible mapping

12-bit, 0.4 µs ADC (up to 16 ext. channels)

– Up to 16-bit with hardware oversampling

– Conversion range: 0 to 3.6V

11 timers: 16-bit for advanced motor control,

five 16-bit general-purpose, two basic 16-bit,

two watchdogs, SysTick timer

Calendar RTC with alarm and periodic wakeup

from Stop/Standby

Communication interfaces

–Two I

2C-bus interfaces supporting Fast-

mode Plus (1 Mbit/s) with extra current

sink, one supporting SMBus/PMBus and

wakeup from Stop mode

– Four USARTs with master/slave

synchronous SPI; two supporting ISO7816

interface, LIN, IrDA capability, auto baud

rate detection and wakeup feature

– Two SPIs (32 Mbit/s) with 4- to 16-bit

programmable bitframe, one multiplexed

with I2S interface

Development support: serial wire debug (SWD)

All packages ECOPACK 2 compliant

LQFP64 10

10 mm

LQFP48 7

7mm

LQFP32 7

7mm

www.st.com

Contents STM32G070CB/KB/RB
2/93 DS12766 Rev 2
Contents
Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1 Arm® Cortex®-M0+ core with MPU   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
3 Embedded Flash memory   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
5 Boot modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
6 Cyclic redundancy check calculation unit (CRC)  . . . . . . . . . . . . . . . . . . .  14
7 Power supply management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
7.1 Power supply schemes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2 Power supply supervisor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3 Voltage regulator  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.4 Low-power modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5 Reset mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.6 VBAT operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
9 Clocks and startup  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . .  19
11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . .  19
12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
13 Interrupts and events  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20
13.2 Extended interrupt/event controller (EXTI)   . . . . . . . . . . . . . . . . . . . . . . 21
14 Analog-to-digital converter (ADC)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
14.2 Internal voltage reference (VREFINT)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
14.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
15 Timers and watchdogs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
15.1 Advanced-control timer (TIM1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.2 General-purpose timers (TIM3, 14, 15, 16, 17)  . . . . . . . . . . . . . . . . . . . 23

DS12766 Rev 2 3/93
STM32G070CB/KB/RB Contents
4
15.3 Basic timers (TIM6 and TIM7)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15.4 Independent watchdog (IWDG)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15.5 System window watchdog (WWDG)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15.6 SysTick timer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16 Real-time clock (RTC), tamper (TAMP) and backup registers  . . . . . . . . .  25
17 Inter-integrated circuit interface (I2C)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
18 Universal synchronous/asynchronous receiver transmitter (USART)   . . .  26
19 Serial peripheral interface (SPI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
20 Development support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
20.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 29
Electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1 Parameter conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40
1.1 Minimum and maximum values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.2 Typical values   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.3 Typical curves   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.4 Loading capacitor   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.5 Pin input voltage   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.6 Power supply scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.7 Current consumption measurement   . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42
3 Operating conditions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  43
3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Operating conditions at power-up / power-down  . . . . . . . . . . . . . . . . . . 43
3.3 Embedded reset and power control block characteristics  . . . . . . . . . . . 43
3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5 Supply current characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.8 Internal clock source characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.10 Flash memory characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.12 Electrical sensitivity characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Contents STM32G070CB/KB/RB
4/93 DS12766 Rev 2
3.13 I/O current injection characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.14 I/O port characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.15 NRST input characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.16 Analog switch booster  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 67
3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.19 VBAT monitoring characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.20 Timer characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.21 Characteristics of communication interfaces  . . . . . . . . . . . . . . . . . . . . . 73
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  81
1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  81
2 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  84
3 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  87
4 Thermal characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  90
4.1 Reference document  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Ordering information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

DS12766 Rev 2 5/93
STM32G070CB/KB/RB List of tables
6
List of tables
Table 1. STM32G070CB/KB/RB family device features and peripheral counts . . . . . . . . . . . . . . . . 10
Table 2. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 13
Table 3. Interconnect of STM32G070CB/KB/RB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Internal voltage reference calibration values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. USART implementation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. SPI/I2S implementation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Terms and symbols used in Table 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. Port A alternate function mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. Port B alternate function mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. Port C alternate function mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. Port D alternate function mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 18. Current characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. General operating conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 21. Operating conditions at power-up / power-down  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 24. Current consumption in Run and Low-power run modes
 at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 28. Current consumption in Standby mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 29. Current consumption in VBAT mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 30. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 32. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 33. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 34. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 35. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 36. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 37. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 38. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 39. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 40. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 41. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 42. EMS characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 43. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 44. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 45. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 46. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 47. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

List of tables STM32G070CB/KB/RB
6/93 DS12766 Rev 2
Table 48. Output voltage characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 49. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 50. NRST pin characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 51. Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 52. ADC characteristics    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 53. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 54. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 55. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 56. VBAT monitoring characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 57. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 58. TIMx characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 59. IWDG min/max timeout period at 32 kHz LSI clock  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 60. Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 61. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 62. SPI characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 63. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 64. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 65. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 66. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 67. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 68. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 69. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

DS12766 Rev 2 7/93
STM32G070CB/KB/RB List of figures
7
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. STM32G070RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4. STM32G070CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. STM32G070KxT LQFP32 pinout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9. Current consumption measurement scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 10. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. High-speed external clock source AC timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 12. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 13. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 14. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 15. I/O input characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 16. I/O AC characteristics definition(1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 17. Recommended NRST pin protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 18. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. Typical connection diagram using the ADC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 20. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 21. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 22. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 23. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 24. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 25. LQFP64 package outline  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 26. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 27. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 28. LQFP48 package outline  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 29. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 30. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 31. LQFP32 package outline  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 32. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 33. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Introduction STM32G070CB/KB/RB

8/93 DS12766 Rev 2

1 Introduction

This document provides information on STM32G070CB/KB/RB microcontrollers, such as

description, functional overview, pin assignment and definition, electrical characteristics,

packaging, and ordering codes.

Information on memory mapping and control registers is object of reference manual.

Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS12766 Rev 2 9/93

STM32G070CB/KB/RB Description

2 Description

The STM32G070CB/KB/RB mainstream microcontrollers are based on high-performance

Arm® Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high

level of integration, they are suitable for a wide range of applications in consumer, industrial

and appliance domains and ready for the Internet of Things (IoT) solutions.

The devices incorporate a memory protection unit (MPU), high-speed embedded memories

(128 Kbytes of Flash program memory with read protection, write protection, and 36 Kbytes

of SRAM), DMA and an extensive range of system functions, enhanced I/Os and

peripherals. The devices offer standard communication interfaces (two I2Cs, two SPIs / one

I2S, and four USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, a low-power

RTC, an advanced control PWM timer, five general-purpose 16-bit timers, two basic timers,

two watchdog timers, and a SysTick timer.

The devices operate within ambient temperatures from -40 to 85°C. They can operate with

supply voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with a

comprehensive set of power-saving modes allows the design of low-power applications.

VBAT direct battery input allows keeping RTC and backup registers powered.

The devices come in packages with 32 to 64 pins.

Description STM32G070CB/KB/RB

10/93 DS12766 Rev 2

Table 1. STM32G070CB/KB/RB family device features and peripheral counts

Peripheral STM32G070KB STM32G070CB STM32G070RB

Flash memory (Kbyte) 128

SRAM (Kbyte) 32 (with parity) or 36 (without parity)

Timers

Advanced control 1 (16-bit)

General-purpose 5 (16-bit)

Basic 2 (16-bit)

SysTick 1

Watchdog 2

Comm.

interfaces

SPI [I2S](1) 2 [1]

I2C2

USART 4

RTC Yes

RNG(2) No

AES(2) No

Tamp er pin s 2

GPIOs 29 43 59

Wakeup pins 4 4 5

12-bit ADC channels 11 ext.

+ 2 int.

14 ext.

+ 3 int.

16 ext.

+ 3 int.

Max. CPU frequency 64 MHz

Operating voltage 2.0 - 3.6 V

Operating temperature Ambient: -40 to 85 °C

Junction: -40 to 105 °C

Number of pins 32 48 64

1. The numbers in brackets denote the count of SPI interfaces configurable as I2S interface.

2. RNG: Random number generator, AES: Advanced Encryption Standard

DS12766 Rev 2 11/93

STM32G070CB/KB/RB Description

Figure 1. Block diagram

MSv42183V1

USART3/4

USART1/2

TIMER 16/17

Power domain of analog blocks : VBAT

6 channels

BRK, ETR input as AF

System and

peripheral

clocks

PA[15:0]

PB[15:0]

PC[15:0]

PF4,3,1,0

59 AF

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS as AF

SWCLK

SWDIO

as AF

16x IN

OSC_IN

OSC_OUT

VBAT

OSC32_IN

OSC32_OUT

RTC_OUT

RTC_REFIN

RTC_TS

MOSI, MISO,

SCK, NSS,

as AF

HSI16

LSI

PLLPCLK

IR_OUT as AF

1 channel as AF

4 ch., ETR as AF

CPU

CORTEX-M0+

max

= 64 MHz

SWD

NVIC

EXTI

SPI1/I2S

SPI2

AHB-to-APB

RCC

Reset & clock control

I/F

XTAL OSC

4-48 MHz

IWDG

SRAM

36 KB

I/F

ADC

RTC, TAMP

Backup regs

I/F

RC 16 MHz

RC 32 kHz

PLL

decoder

XTAL32 kHz

Bus matrix

I/F

VDD

2 channels as AF

RX, TX,CTS, RTS,

CK as AF

RX, TX,CTS, RTS,

CK as AF

TIM6

TIM7

Port D

Port C

Port B

Port A

VDDA

SUPPLY

SUPERVISION

POWER

VCORE

POR

Reset

Int

VDD/VDDA

VSS/VSSA

NRST

POR/PDR

Voltage

regulator

USART3 & 4

USART1 & 2

TIM16 & 17

TIM15

TIM14

TIM3

TIM1

GPIOs

IOPORT

HSE

PLLRCLK

LSE

T sensor

TAMP_IN

APB

AHB

CRC

VREF+

SCL, SDA as AF

SCL, SDA, SMBA,

SMBUS as AF I2C1

I2C2

DBGMCU

WWDG

PWRCTRL

SYSCFG

DMA

DMAMUX

Port F

PD[9:0]

VDDA

VDDIO1

Low-voltage

detector

VDD

Parity

Flash memory

128 KB

VDDIO1

Functional overview STM32G070CB/KB/RB

12/93 DS12766 Rev 2

3 Functional overview

3.1 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of

embedded applications. It offers significant benefits to developers, including:

a simple architecture, easy to learn and program

ultra-low power, energy-efficient operation

excellent code density

deterministic, high-performance interrupt handling

upward compatibility with Cortex-M processor family

platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a

2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy

efficiency through a small but powerful instruction set and extensively optimized design,

providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern

32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to embedded Arm core, the STM32G070CB/KB/RB devices are compatible with Arm

tools and software.

The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)

described in Section 3.13.1.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded Flash memory

STM32G070CB/KB/RB devices feature 128 Kbytes of embedded Flash memory available

for storing code and data.

DS12766 Rev 2 13/93

STM32G070CB/KB/RB Functional overview

Flexible protections can be configured thanks to option bytes:

Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is

selected

– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in

RAM and bootloader selection are disabled. This selection is irreversible.

Write protection (WRP): the protected area is protected against erasing and

programming. Two areas per bank can be selected, with 2-Kbyte granularity.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

single error detection and correction

double error detection

readout of the ECC fail address from the ECC register

3.4 Embedded SRAM

STM32G070CB/KB/RB devices have 32 Kbytes of embedded SRAM with parity. Hardware

parity check allows memory data errors to be detected, which contributes to increasing

functional safety of applications.

When the parity protection is not required because the application is not safety-critical, the

parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

Table 2. Access status versus readout protection level and execution modes

Area Protection

level

User execution Debug, boot from RAM or boot

from system memory (loader)

Read Write Erase Read Write Erase

User

memory

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

System

memory

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

Option

bytes

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

Backup

registers

1YesYesN/A

(1)

1. Erased upon RDP change from Level 1 to Level 0.

No No N/A(1)

2 Yes Yes N/A N/A N/A N/A

Functional overview STM32G070CB/KB/RB

14/93 DS12766 Rev 2

3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot

options:

boot from User Flash memory

boot from System memory

boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be enabled through the boot selector

option bit. The boot loader is located in System memory. It manages the Flash memory

reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I2C-

bus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or

PB12/PB13/PB14/PB15.

3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link

time and stored at a given memory location.

3.7 Power supply management

3.7.1 Power supply schemes

The STM32G070CB/KB/RB devices require a 2.0 V to 3.6 V operating supply voltage (VDD).

Several different power supplies are provided to specific peripherals:

VDD = 2.0 to 3.6 V

VDD is the external power supply for the internal regulator and the system analog such

as reset, power management and internal clocks. It is provided externally through

VDD/VDDA pin.

VDDA = 2.0 V to 3.6 V

VDDA is the analog power supply for the A/D converter. VDDA voltage level is identical to

VDD voltage as it is provided externally through VDD/VDDA pin.

VDDIO1 = VDD

VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage

as it is provided externally through VDD/VDDA pin.

VBAT = 1.55 V to 3.6 V. VBAT is the power supply (through a power switch) for RTC,

TAMP, low-speed external 32.768 kHz oscillator and backup registers when VDD is not

present. VBAT is provided externally through VBAT pin. When this pin is not available

on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.

VREF+ is the analog peripheral input reference voltage. When VDDA < 2 V, VREF+ must

be equal to VDDA. When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. It can be

grounded when the analog peripherals using VREF+ are not active.

DS12766 Rev 2 15/93

STM32G070CB/KB/RB Functional overview

VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is

internally connected with VDD, and the internal voltage reference buffer must be kept

disabled (refer to datasheets for package pinout description).

VCORE

An embedded linear voltage regulator is used to supply the VCORE internal digital

power. VCORE is the power supply for digital peripherals, SRAM and Flash memory.

The Flash memory is also supplied with VDD.

Figure 2. Power supply overview

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power

modes and ensuring proper operation upon power-on and power-down. It maintains the

device in reset when the supply voltage is below VPOR/PDR threshold, without the need for

an external reset circuit.

3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator

(LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power

sleep and Stop modes.

In Standby mode, both regulators are powered down and their outputs set in high-

impedance state, such as to bring their current consumption close to zero.

MSv47920V1

VDDA domain

RTC domain

A/D converter

Standby circuitry

(Wakeup, IWDG)

Voltage

regulator

Core

SRAM

Digital

peripherals

Low-voltage

detector

LSE crystal 32.768 kHz osc

BKP registers

RCC BDCR register

RTC and TAMP

I/O ring

VCORE domain

Temp. sensor

Reset block

PLL, HSI

Flash memory

VDDIO1

VREF+

VDD domain

VCORE

VSS/VSSA

VDD/VDDA

VBAT

VDDA

VREF+

VSSA

VSS

VDD

VDDIO1 domain

Functional overview STM32G070CB/KB/RB

16/93 DS12766 Rev 2

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

Low-power run mode

This mode is achieved with VCORE supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the VCORE domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down VCORE

domain. The low-power regulator is switched off. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

DS12766 Rev 2 17/93

STM32G070CB/KB/RB Functional overview

3.7.6 VBAT operation

The VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and

backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for

example, an external battery or an external supercapacitor. Two anti-tamper detection pins

are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of

RTC domain powering between VDD and voltage from VBAT pin to ensure that the supply

voltage of the RTC domain (VBAT) remains within valid operating conditions. If both voltages

are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the VDD voltage is

within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the VDD is not within a valid range.

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop

modes.

Table 3. Interconnect of STM32G070CB/KB/RB peripherals

Interconnect source Interconnect

destination Interconnect action

Run

Low-power run

Sleep

Low-power sleep

Stop

TIMx

TIMx Timer synchronization or chaining Y Y -

ADCx Conversion triggers Y Y -

DMA Memory-to-memory transfer trigger Y Y -

ADCx TIM1 Timer triggered by analog watchdog Y Y -

RTC TIM16 Timer input channel from RTC events Y Y -

All clocks sources (internal

and external) TIM14,16,17 Clock source used as input channel for

RC measurement and trimming YY -

CSS

RAM (parity error)

Flash memory (ECC error)

TIM1,15,16,17 Timer break Y Y -

Functional overview STM32G070CB/KB/RB

18/93 DS12766 Rev 2

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness. It features:

Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode

for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an

external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

Peripheral clock sources: several peripherals (I2S, USARTs, I2Cs, ADC) have their

own clock independent of the system clock.

Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE

CPU (hard fault) TIM1,15,16,17 Timer break Y - -

GPIO

TIMx External trigger Y Y -

ADC Conversion external trigger Y Y -

Table 3. Interconnect of STM32G070CB/KB/RB peripherals (continued)

Interconnect source Interconnect

destination Interconnect action

Run

Low-power run

Sleep

Low-power sleep

Stop

DS12766 Rev 2 19/93

STM32G070CB/KB/RB Functional overview

clock failure can also be detected and generate an interrupt. The CCS feature can be

enabled by software.

Clock output:

–MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

–LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 64 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such

as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with

single-AHB architecture.

With 7 channels, it performs data transfers between memory-mapped peripherals and/or

memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more

peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

Single-AHB master

Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-

peripheral data transfers

Access, as source and destination, to on-chip memory-mapped devices such as Flash

memory, SRAM, and AHB and APB peripherals

All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a

peripheral, or with a software trigger in memory-to-memory transfers. This

configuration is done by software.

– Priority between the requests is programmable by software (four levels per

channel: very high, high, medium, low) and by hardware in case of equality (such

as request to channel 1 has priority over request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word),

emulating packing and unpacking. Source and destination addresses must be

aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer

management

Functional overview STM32G070CB/KB/RB

20/93 DS12766 Rev 2

– Programmable number of data to be transferred: 0 to 216 - 1

Generation of an interrupt request per channel. Each interrupt request originates from

any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the

peripherals and the DMA controller. Each channel selects a unique DMA request line,

unconditionally or synchronously with events from its DMAMUX synchronization inputs.

DMAMUX may also be used as a DMA request generator from programmable events on its

input trigger signals.

3.13 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called

exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)

and an extended interrupt/event controller (EXTI) are the assets contributing to handling the

exceptions. Exceptions include core-internal events such as, for example, a division by zero

and, core-external events such as logical level changes on physical lines. Exceptions result

in interrupting the program flow, executing an interrupt service routine (ISR) then resuming

the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon

program interrupt and unstacked upon program resume, by hardware. This avoids context

stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving

time, code and power. The ability to abandon and restart load-multiple and store-multiple

operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It

handles physical line events associated with a non-maskable interrupt (NMI) and maskable

interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between

interrupt events and start of corresponding interrupt service routines (ISRs). The ISR

vectors are listed in a vector table, stored in the NVIC at a base address. The vector

address of an ISR to execute is hardware-built from the vector table base address and the

ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring

just before is waiting for being served, the later-arriving higher-priority interrupt event is

served first. Another optimization is called tail-chaining. Upon a return from a higher-priority

ISR then start of a pending lower-priority ISR, the unnecessary processor context

unstacking and stacking is skipped. This reduces latency and contributes to power

efficiency.

DS12766 Rev 2 21/93

STM32G070CB/KB/RB Functional overview

Features of the NVIC:

Low-latency interrupt processing

4 priority levels

Handling of a non-maskable interrupt (NMI)

Handling of 32 maskable interrupt lines

Handling of 10 Cortex-M0+ exceptions

Later-arriving higher-priority interrupt processed first

Tail-chaining

Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and

allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising,

and falling edge detector capability. Any GPIO and a few peripheral signals can be

connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which allows the

software to identify the origin of the processor's wake-up from Stop mode or, to identify the

GPIO and the edge event having caused an interrupt.

3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32G070CB/KB/RB

devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC

has up to 16 external channels and 3 internal channels (temperature sensor, voltage

reference, VBAT monitoring). It performs conversions in single-shot or scan mode. In scan

mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling

rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that

the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole VDD supply

range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to

16 bits (refer to AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all scanned channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to

the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

Functional overview STM32G070CB/KB/RB

22/93 DS12766 Rev 2

3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor

output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall

accuracy of the temperature measurement. As the offset of the temperature sensor may

vary from part to part due to process variation, the uncalibrated internal temperature sensor

is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factory-

calibrated by ST. The resulting calibration data are stored in the part’s engineering bytes,

accessible in read-only mode.

3.14.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the

ADC. VREFINT is internally connected to an ADC input. The VREFINT voltage is individually

precisely measured for each part by ST during production test and stored in the part’s

engineering bytes. It is accessible in read-only mode.

3.14.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage

using an internal ADC input. As the VBAT voltage may be higher than VDDA and thus outside

the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a

consequence, the converted digital value is one third the VBAT voltage.

3.15 Timers and watchdogs

The device includes an advanced-control timer, five general-purpose timers, two basic

timers, two low-power timers, two watchdog timers and a SysTick timer. Table 6 compares

features of the advanced-control, general-purpose and basic timers.

Table 4. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS ADC raw data acquired at a

temperature of 30 °C (± 5 °C),

VDDA = VREF+ = 3.0 V (± 10 mV)

0x1FFF 75A8 - 0x1FFF 75A9

Table 5. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT

Raw data acquired at a

temperature of 30 °C (± 5 °C),

VDDA = VREF+ = 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

DS12766 Rev 2 23/93

STM32G070CB/KB/RB Functional overview

3.15.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6

channels. It has complementary PWM outputs with programmable inserted dead-times. It

can also be seen as a complete general-purpose timer. The four independent channels can

be used for:

input capture

output compare

PWM output (edge or center-aligned modes) with full modulation capability (0-100%)

one-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled, so as to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.15.2) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event

chaining.

3.15.2 General-purpose timers (TIM3, 14, 15, 16, 17)

There are five synchronizable general-purpose timers embedded in the device (refer to

Table 6 for comparison). Each general-purpose timer can be used to generate PWM outputs

or act as a simple timebase.

TIM3

This is a full-featured general-purpose timer with 16-bit auto-reload up/downcounter

and 16-bit prescaler.

It has four independent channels for input capture/output compare, PWM or one-pulse

mode output. It can operate in combination with other general-purpose timers via the

Timer Link feature for synchronization or event chaining. It can generate independent

Table 6. Timer feature comparison

Timer type Timer Counter

resolution

Counter

type

Maximum

operating

frequency

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Comple-

mentary

outputs

Advanced-

control TIM1 16-bit Up, down,

up/down 64 MHz Integer from

1 to 216 Yes 4 3

General-

purpose

TIM3 16-bit Up, down,

up/down 64 MHz Integer from

1 to 216 Yes 4 -

TIM14 16-bit Up 64 MHz Integer from

1 to 216 No 1 -

TIM15 16-bit Up 64 MHz Integer from

1 to 216 Yes 2 1

TIM16

TIM17 16-bit Up 64 MHz Integer from

1 to 216 Yes 1 1

Basic TIM6

TIM7 16-bit Up 64 MHz Integer from

1 to 216 Yes - -

Functional overview STM32G070CB/KB/RB

24/93 DS12766 Rev 2

DMA request and support quadrature encoders. Its counter can be frozen in debug

mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one

channel for input capture/output compare, PWM output or one-pulse mode output. Its

counter can be frozen in debug mode.

TIM15, TIM16, TIM17

These are general-purpose timers featuring:

– 16-bit auto-reload upcounter and 16-bit prescaler

– 2 channels and 1 complementary channel for TIM15

– 1 channel and 1 complementary channel for TIM16 and TIM17

All channels can be used for input capture/output compare, PWM or one-pulse mode

output. The timers can operate together via the Timer Link feature for synchronization

or event chaining. They can generate independent DMA request. Their counters can

be frozen in debug mode.

3.15.3 Basic timers (TIM6 and TIM7)

3.15.4 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with

user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).

Independent of the main clock, it can operate in Stop and Standby modes. It can be used

either as a watchdog to reset the device when a problem occurs, or as a free-running timer

for application timeout management. It is hardware- or software-configurable through the

option bytes. Its counter can be frozen in debug mode.

3.15.5 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked by the

system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug

mode.

3.15.6 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard

down counter.

Features of SysTick timer:

24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source

These timers can be used as generic 16-bit timebases.

DS12766 Rev 2 25/93

STM32G070CB/KB/RB Functional overview

3.16 Real-time clock (RTC), tamper (TAMP) and backup registers

The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of

the silicon die.

The ways of powering the RTC domain are described in Section 3.7.6.

The RTC is an independent BCD timer/counter.

Features of the RTC:

Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format

Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

Programmable alarm

On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with

a master clock

Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be

used to improve the calendar precision

Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy

Two anti-tamper detection pins with programmable filter

Timestamp feature to save a calendar snapshot, triggered by an event on the

timestamp pin or a tamper event, or by switching to VBAT mode

17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable

resolution and period

Multiple clock sources and references:

– A 32.768 kHz external crystal (LSE)

– An external resonator or oscillator (LSE)

– The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

– The high-speed external clock (HSE) divided by 32

When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When

clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt

and wake the device up from the low-power modes.

The backup registers allow keeping 20 bytes of user application data in the event of VDD

failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by

the system reset, power reset, and upon the device’s wakeup from Standby mode.

3.17 Inter-integrated circuit interface (I2C)

The device embeds two I2C peripherals. Refer to Table 7 for the features.

The I2C-bus interface handles communication between the microcontroller and the serial

I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.

Functional overview STM32G070CB/KB/RB

26/93 DS12766 Rev 2

Features of the I2C peripheral:

I2C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Clock stretching

SMBus specification rev 3.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK

control

– Command and data acknowledge control

– Address resolution protocol (ARP) support

– Host and Device support

– SMBus alert

– Timeouts and idle condition detection

PMBus rev 1.3 standard compatibility

Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent of the PCLK reprogramming

Wakeup from Stop mode on address match

Programmable analog and digital noise filters

1-byte buffer with DMA capability

3.18 Universal synchronous/asynchronous receiver transmitter

(USART)

The device embeds universal synchronous/asynchronous receivers/transmitters (USART1,

USART2, USART3, USART4) that communicate at speeds of up to 8 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals,

multiprocessor communication mode, master synchronous communication and single-wire

Table 7. I2C implementation

I2C features(1)

1. X: supported

I2C1 I2C2

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os X X

Programmable analog and digital noise filters X X

SMBus/PMBus hardware support X -

Independent clock X -

Wakeup from Stop mode on address match X -

DS12766 Rev 2 27/93

STM32G070CB/KB/RB Functional overview

half-duplex communication mode. Some can also support SmartCard communication (ISO

7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have

a clock domain independent of the CPU clock, which allows them to wake up the MCU from

Stop mode. The wakeup events from Stop mode are programmable and can be:

start bit detection

any received data frame

a specific programmed data frame

All USART interfaces can be served by the DMA controller.

3.19 Serial peripheral interface (SPI)

The device contains two SPIs running at up to 32 Mbits/s in master and slave modes. It

supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight

master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI

peripherals support NSS pulse mode, TI mode and hardware CRC calculation.

The SPI peripherals can be served by the DMA controller.

The I2S interface mode of the SPI peripheral (if supported, see the following table) supports

four different audio standards can operate as master or slave, in half-duplex communication

mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data

resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to

192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master

mode, it can output a clock for an external audio component at 256 times the sampling

frequency.

Table 8. USART implementation

USART modes/features(1)

1. X: supported

USART1

USART2

USART3

USART4

Hardware flow control for modem X X

Continuous communication using DMA X X

Multiprocessor communication X X

Synchronous mode X X

Smartcard mode X -

Single-wire half-duplex communication X X

IrDA SIR ENDEC block X -

LIN mode X -

Dual clock domain and wakeup from Stop mode X -

Receiver timeout interrupt X -

Modbus communication X -

Auto baud rate detection X -

Driver Enable X X

Functional overview STM32G070CB/KB/RB

28/93 DS12766 Rev 2

3.20 Development support

3.20.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to

the MCU.

Table 9. SPI/I2S implementation

SPI features(1)

1. X = supported.

SPI1 SPI2

Hardware CRC calculation X X

Rx/Tx FIFO X X

NSS pulse mode X X

I2S mode X -

TI mode X X

DS12766 Rev 2 29/93

STM32G070CB/KB/RB Pinouts, pin description and alternate functions

4 Pinouts, pin description and alternate functions

Figure 3. STM32G070RxT LQFP64 pinout

Figure 4. STM32G070CxT LQFP48 pinout

MSv47927V1

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

PB12

PC11

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

NRST

PF0-OSC_IN

PF1-OSC_OUT

PC0

PC1

PC2

PC3

PC8

PA15

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PD9

PD8

PC7

PC6

PA9

PA8

PB15

PB14

PB13

PC9

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PC10

Top view

LQFP64

MSv47928V1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

PB12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

NRST

PF0-OSC_IN

PF1-OSC_OUT

PA0

PA1

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC7

PC6

PA9

PA8

PB15

PB14

PB13

PA15

PD0

PD1

PD2

PD3

PB3

PB4

PB5

PB6

PB7

PB8

PB9

Top view

LQFP48

Pinouts, pin description and alternate functions STM32G070CB/KB/RB

30/93 DS12766 Rev 2

Figure 5. STM32G070KxT LQFP32 pinout

MSv47929V1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

NRST

PA0

PA1

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC6

PA9

PA8

PB2

PA14-BOOT0

PA15

PB3

PB4

PB5

PB6

PB7

PB8

Top view

LQFP32

Table 10. Terms and symbols used in Table 11

Column Symbol Definition

Pin name Terminal name corresponds to its by-default function at reset, unless otherwise specified in

parenthesis under the pin name.

Pin type

S Supply pin

I Input only pin

I/O Input / output pin

I/O structure

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

RST Bidirectional reset pin with embedded weak pull-up resistor

Options for TT or FT I/Os

_f I/O, Fm+ capable

_a I/O, with analog switch function

_c I/O, with specific electrical characteristics

_d I/O, with specific electrical characteristics

Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.

functions

Alternate

functions Functions selected through GPIOx_AFR registers

Additional

functions Functions directly selected/enabled through peripheral registers

DS12766 Rev 2 31/93

STM32G070CB/KB/RB Pinouts, pin description and alternate functions

Table 11. Pin assignment and description

Pin Number

Pin name

(function

upon reset)

Pin type

I/O structure

Note

Alternate

functions

Additional

functions

LQFP32

LQFP48

LQFP64

--1 PC11 I/OFT - USART3_RX, USART4_RX,

TIM1_CH4 -

- - 2 PC12 I/O FT - TIM14_CH1 -

-13 PC13 I/OFT(1)(2) TIM1_BKIN TAMP_IN1,RTC_TS,

RTC_OUT1,WKUP2

-24

PC14-

OSC32_IN

(PC14)

I/O FT (1)(2) TIM1_BKIN2 OSC32_IN

2--

PC14-

OSC32_IN

(PC14)

I/O FT (1)(2) TIM1_BKIN2 OSC32_IN,OSC_IN

335

PC15-

OSC32_OUT

(PC15)

I/O FT (1)(2) OSC32_EN, OSC_EN,

TIM15_BKIN OSC32_OUT

- 4 6 VBAT S - - - -

-57 VREF+ S - - - -

4 6 8 VDD/VDDA S - - - -

5 7 9 VSS/VSSA S - - - -

-810

PF0-OSC_IN

(PF0) I/O FT - TIM14_CH1 OSC_IN

-911

PF1-

OSC_OUT

(PF1)

I/O FT - OSC_EN, TIM15_CH1N OSC_OUT

6 10 12 NRST I/O FT - - NRST

--13 PC0 I/OFT - - -

- - 14 PC1 I/O FT - TIM15_CH1- -

- - 15 PC2 I/O FT - SPI2_MISO, TIM15_CH2 -

- - 16 PC3 I/O FT - SPI2_MOSI -

71117 PA0 I/OFT_a - SPI2_SCK, USART2_CTS,

USART4_TX

ADC_IN0,

TAMP_IN2,WKUP1

Pinouts, pin description and alternate functions STM32G070CB/KB/RB

32/93 DS12766 Rev 2

81218 PA1 I/OFT_a -

SPI1_SCK/I2S1_CK,

USART2_RTS_DE_CK,

USART4_RX, TIM15_CH1N,

I2C1_SMBA, EVENTOUT

ADC_IN1

91319 PA2 I/OFT_a - SPI1_MOSI/I2S1_SD,

USART2_TX, TIM15_CH1

ADC_IN2,

WKUP4,LSCO

10 14 20 PA3 I/O FT_a - SPI2_MISO, USART2_RX,

TIM15_CH2, EVENTOUT ADC_IN3

-1521 PA4 I/OTT_a -

SPI1_NSS/I2S1_WS,

SPI2_MOSI, TIM14_CH1,

EVENTOUT

ADC_IN4, RTC_OUT2

11 - - PA4 I/O TT_a -

SPI1_NSS/I2S1_WS,

SPI2_MOSI, TIM14_CH1,

EVENTOUT

ADC_IN4, TAMP_IN1,

RTC_TS,

RTC_OUT1,WKUP2

12 16 22 PA5 I/O TT_a - SPI1_SCK/I2S1_CK,

USART3_TX, EVENTOUT ADC_IN5

13 17 23 PA6 I/O FT_a -

SPI1_MISO/I2S1_MCK,

TIM3_CH1, TIM1_BKIN,

USART3_CTS, TIM16_CH1

ADC_IN6

14 18 24 PA7 I/O FT_a -

SPI1_MOSI/I2S1_SD,

TIM3_CH2, TIM1_CH1N,

TIM14_CH1, TIM17_CH1

ADC_IN7

- - 25 PC4 I/O FT_a - USART3_TX, USART1_TX ADC_IN17

- - 26 PC5 I/O FT_a - USART3_RX, USART1_RX ADC_IN18, WKUP5

15 19 27 PB0 I/O FT_a (3)

SPI1_NSS/I2S1_WS,

TIM3_CH3, TIM1_CH2N,

USART3_RX

ADC_IN8

16 20 28 PB1 I/O FT_a -

TIM14_CH1, TIM3_CH4,

TIM1_CH3N,

USART3_RTS_DE_CK,

EVENTOUT

ADC_IN9

17 21 29 PB2 I/O FT_a - SPI2_MISO, USART3_TX,

EVENTOUT ADC_IN10

- 22 30 PB10 I/O FT_fa - USART3_TX, SPI2_SCK,

I2C2_SCL ADC_IN11

Table 11. Pin assignment and description (continued)

Pin Number

Pin name

(function

upon reset)

Pin type

I/O structure

Note

Alternate

functions

Additional

functions

LQFP32

LQFP48

LQFP64

DS12766 Rev 2 33/93

STM32G070CB/KB/RB Pinouts, pin description and alternate functions

-2331 PB11 I/OFT_fa - SPI2_MOSI, USART3_RX,

I2C2_SDA ADC_IN15

- 24 32 PB12 I/O FT_a - SPI2_NSS, TIM1_BKIN,

TIM15_BKIN, EVENTOUT ADC_IN16

- 25 33 PB13 I/O FT_f -

SPI2_SCK, TIM1_CH1N,

USART3_CTS, TIM15_CH1N,

I2C2_SCL, EVENTOUT

- 26 34 PB14 I/O FT_f -

SPI2_MISO, TIM1_CH2N,

USART3_RTS_DE_CK,

TIM15_CH1, I2C2_SDA,

EVENTOUT

- 27 35 PB15 I/O FT_c (3)

SPI2_MOSI, TIM1_CH3N,

TIM15_CH1N, TIM15_CH2,

EVENTOUT

RTC_REFIN

18 28 36 PA8 I/O FT_c (3) MCO, SPI2_NSS, TIM1_CH1,

EVENTOUT -

19 29 37 PA9 I/O FT_fd (3)

MCO, USART1_TX, TIM1_CH2,

SPI2_MISO, TIM15_BKIN,

I2C1_SCL, EVENTOUT

20 30 38 PC6 I/O FT (3) TIM3_CH1 -

- 31 39 PC7 I/O FT - TIM3_CH2 -

--40 PD8 I/OFT - USART3_TX,

SPI1_SCK/I2S1_CK -

--41 PD9 I/OFT -

USART3_RX,

SPI1_NSS/I2S1_WS,

TIM1_BKIN2

21 32 42 PA10 I/O FT_fd (3)

SPI2_MOSI, USART1_RX,

TIM1_CH3, TIM17_BKIN,

I2C1_SDA, EVENTOUT

22 33 43 PA11

[PA9](4) I/O FT_f (3)

SPI1_MISO/I2S1_MCK,

USART1_CTS, TIM1_CH4,

TIM1_BKIN2, I2C2_SCL

23 34 44 PA12

[PA10](4) I/O FT_f (3)

SPI1_MOSI/I2S1_SD,

USART1_RTS_DE_CK,

TIM1_ETR, I2S_CKIN,

I2C2_SDA

Table 11. Pin assignment and description (continued)

Pin Number

Pin name

(function

upon reset)

Pin type

I/O structure

Note

Alternate

functions

Additional

functions

LQFP32

LQFP48

LQFP64

Pinouts, pin description and alternate functions STM32G070CB/KB/RB

34/93 DS12766 Rev 2

24 35 45 PA13 I/O FT (5) SWDIO, IR_OUT, EVENTOUT -

25 36 46 PA14-BOOT0 I/O FT (5) SWCLK, USART2_TX,

EVENTOUT BOOT0

26 37 47 PA15 I/O FT -

SPI1_NSS/I2S1_WS,

USART2_RX,

USART4_RTS_DE_CK,

USART3_RTS_DE_CK,

EVENTOUT

- - 48 PC8 I/O FT - TIM3_CH3, TIM1_CH1 -

--49 PC9 I/OFT - I2S_CKIN, TIM3_CH4,

TIM1_CH2 -

-3850 PD0 I/OFT_c (3) EVENTOUT, SPI2_NSS,

TIM16_CH1 -

-3951 PD1 I/OFT_d (3) EVENTOUT, SPI2_SCK,

TIM17_CH1 -

-4052 PD2 I/OFT_c (3) USART3_RTS_DE_CK,

TIM3_ETR, TIM1_CH1N -

-4153 PD3 I/OFT_d (3) USART2_CTS, SPI2_MISO,

TIM1_CH2N -

--54 PD4 I/OFT - USART2_RTS_DE_CK,

SPI2_MOSI, TIM1_CH3N -

--55 PD5 I/OFT -

USART2_TX,

SPI1_MISO/I2S1_MCK,

TIM1_BKIN

--56 PD6 I/OFT - USART2_RX,

SPI1_MOSI/I2S1_SD -

27 42 57 PB3 I/O FT_a -

SPI1_SCK/I2S1_CK, TIM1_CH2,

USART1_RTS_DE_CK,

EVENTOUT

28 43 58 PB4 I/O FT_a -

SPI1_MISO/I2S1_MCK,

TIM3_CH1, USART1_CTS,

TIM17_BKIN, EVENTOUT

29 44 59 PB5 I/O FT -

SPI1_MOSI/I2S1_SD,

TIM3_CH2, TIM16_BKIN,

I2C1_SMBA

WKUP6

Table 11. Pin assignment and description (continued)

Pin Number

Pin name

(function

upon reset)

Pin type

I/O structure

Note

Alternate

functions

Additional

functions

LQFP32

LQFP48

LQFP64

DS12766 Rev 2 35/93

STM32G070CB/KB/RB Pinouts, pin description and alternate functions

30 45 60 PB6 I/O FT_fa -

USART1_TX, TIM1_CH3,

TIM16_CH1N, SPI2_MISO,

I2C1_SCL, EVENTOUT

31 46 61 PB7 I/O FT_fa -

USART1_RX, SPI2_MOSI,

TIM17_CH1N, USART4_CTS,

I2C1_SDA, EVENTOUT

32 47 62 PB8 I/O FT_f -

SPI2_SCK, TIM16_CH1,

USART3_TX, TIM15_BKIN,

I2C1_SCL, EVENTOUT

14863 PB9 I/OFT_f -

IR_OUT, TIM17_CH1,

USART3_RX, SPI2_NSS,

I2C1_SDA, EVENTOUT

- - 64 PC10 I/O FT - USART3_TX, USART4_TX,

TIM1_CH3 -

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of

current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (for example to drive a LED).

2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the

content of the RTC registers as they are not reset by the system reset. For details on how to manage these GPIOs,

refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.

3. Upon reset, a pull-down resistor might be present on PA8, PD0, or PD2, depending on the voltage level on PB0,

PA9, PC6, PA10, PD1, and PD3. In order to disable this resistor, strobe the UCPDx_STROBE bit of the

SYSCFG_CFGR1 register during start-up sequence.

4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.

5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the

internal pull-down on PA14 pin are activated.

Table 11. Pin assignment and description (continued)

Pin Number

Pin name

(function

upon reset)

Pin type

I/O structure

Note

Alternate

functions

Additional

functions

LQFP32

LQFP48

LQFP64

STM32G070CB/KB/RB

36/93 DS12766 Rev 2

Table 12. Port A alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PA0 SPI2_SCK USART2_CTS - - USART4_TX - - -

PA1 SPI1_SCK/

I2S1_CK

USART2_RTS

_DE_CK - - USART4_RX TIM15_CH1N I2C1_SMBA EVENTOUT

PA2 SPI1_MOSI/

I2S1_SD USART2_TX - - - TIM15_CH1 - -

PA3 SPI2_MISO USART2_RX - - - TIM15_CH2 - EVENTOUT

PA4 SPI1_NSS/

I2S1_WS SPI2_MOSI - - TIM14_CH1 - - EVENTOUT

PA5 SPI1_SCK/

I2S1_CK - - - USART3_TX - - EVENTOUT

PA6 SPI1_MISO/

I2S1_MCK TIM3_CH1 TIM1_BKIN - USART3_CTS TIM16_CH1 - -

PA7 SPI1_MOSI/

I2S1_SD TIM3_CH2 TIM1_CH1N -TIM14_CH1 TIM17_CH1 - -

PA8 MCO SPI2_NSS TIM1_CH1 - - - - EVENTOUT

PA9 MCO USART1_TX TIM1_CH2 - SPI2_MISO TIM15_BKIN I2C1_SCL EVENTOUT

PA10 SPI2_MOSI USART1_RX TIM1_CH3 - - TIM17_BKIN I2C1_SDA EVENTOUT

PA11 SPI1_MISO/

I2S1_MCK USART1_CTS TIM1_CH4 - - TIM1_BKIN2 I2C2_SCL -

PA12 SPI1_MOSI/

I2S1_SD

USART1_RTS

_DE_CK TIM1_ETR - - I2S_CKIN I2C2_SDA -

PA13SWDIOIR_OUT-----EVENTOUT

PA14SWCLKUSART2_TX-----EVENTOUT

PA15 SPI1_NSS/

I2S1_WS USART2_RX - - USART4_RTS

_DE_CK

USART3_RTS

_DE_CK -EVENTOUT

STM32G070CB/KB/RB

DS12766 Rev 2 37/93

Table 13. Port B alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PB0 SPI1_NSS/

I2S1_WS TIM3_CH3 TIM1_CH2N - USART3_RX - - -

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N - USART3_RTS

_DE_CK - - EVENTOUT

PB2 - SPI2_MISO - - USART3_TX - - EVENTOUT

PB3 SPI1_SCK/

I2S1_CK TIM1_CH2 - - USART1_RTS

_DE_CK - - EVENTOUT

PB4 SPI1_MISO/

I2S1_MCK TIM3_CH1 - - USART1_CTS TIM17_BKIN - EVENTOUT

PB5 SPI1_MOSI/

I2S1_SD TIM3_CH2 TIM16_BKIN - - - I2C1_SMBA -

PB6 USART1_TX TIM1_CH3 TIM16_CH1N - SPI2_MISO - I2C1_SCL EVENTOUT

PB7 USART1_RX SPI2_MOSI TIM17_CH1N - USART4_CTS - I2C1_SDA EVENTOUT

PB8 - SPI2_SCK TIM16_CH1 - USART3_TX TIM15_BKIN I2C1_SCL EVENTOUT

PB9 IR_OUT - TIM17_CH1 - USART3_RX SPI2_NSS I2C1_SDA EVENTOUT

PB10 - - - - USART3_TX SPI2_SCK I2C2_SCL -

PB11 SPI2_MOSI - - - USART3_RX - I2C2_SDA -

PB12 SPI2_NSS - TIM1_BKIN - - TIM15_BKIN - EVENTOUT

PB13 SPI2_SCK - TIM1_CH1N - USART3_CTS TIM15_CH1N I2C2_SCL EVENTOUT

PB14 SPI2_MISO - TIM1_CH2N - USART3_RTS

_DE_CK TIM15_CH1 I2C2_SDA EVENTOUT

PB15 SPI2_MOSI - TIM1_CH3N - TIM15_CH1N TIM15_CH2 - EVENTOUT

STM32G070CB/KB/RB

38/93 DS12766 Rev 2

Table 14. Port C alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PC0--------

PC1 - - TIM15_CH1 - - - - -

PC2 - SPI2_MISO TIM15_CH2 - - - - -

PC3-SPI2_MOSI------

PC4 USART3_TX USART1_TX - - - - - -

PC5 USART3_RX USART1_RX - - - - - -

PC6-TIM3_CH1------

PC7-TIM3_CH2------

PC8 - TIM3_CH3 TIM1_CH1 - - - - -

PC9 I2S_CKIN TIM3_CH4 TIM1_CH2 - - - - -

PC10 USART3_TX USART4_TX TIM1_CH3 - - - - -

PC11 USART3_RX USART4_RX TIM1_CH4 - - - - -

PC12 - - TIM14_CH1 - - - - -

PC13 - - TIM1_BKIN - - - - -

PC14 - - TIM1_BKIN2 - - - - -

PC15 OSC32_EN OSC_EN TIM15_BKIN - - - - -

STM32G070CB/KB/RB

DS12766 Rev 2 39/93

Table 15. Port D alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PD0 EVENTOUT SPI2_NSS TIM16_CH1 - - - - -

PD1 EVENTOUT SPI2_SCK TIM17_CH1 - - - - -

PD2 USART3_RTS

_DE_CK TIM3_ETR TIM1_CH1N - - - - -

PD3 USART2_CTS SPI2_MISO TIM1_CH2N - - - - -

PD4 USART2_RTS

_DE_CK SPI2_MOSI TIM1_CH3N - - - - -

PD5 USART2_TX SPI1_MISO/

I2S1_MCK TIM1_BKIN - - - - -

PD6 USART2_RX SPI1_MOSI/

I2S1_SD ------

PD8 USART3_TX SPI1_SCK/

I2S1_CK ------

PD9 USART3_RX SPI1_NSS/

I2S1_WS TIM1_BKIN2-----

Table 16. Port F alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PF0 - - TIM14_CH1 - - - - -

PF1 OSC_EN - TIM15_CH1N - - - - -

Electrical characteristics STM32G070CB/KB/RB

40/93 DS12766 Rev 2

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

Parameter values defined at temperatures or in temperature ranges out of the ordering

information scope are to be ignored.

Packages used for characterizing certain electrical parameters may differ from the

commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They

are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 6.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 7.

Figure 6. Pin loading conditions Figure 7. Pin input voltage

MCU pin

C = 50 pF

MCU pin

DS12766 Rev 2 41/93

STM32G070CB/KB/RB Electrical characteristics

5.1.6 Power supply scheme

Figure 8. Power supply scheme

Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering

ceramic capacitors as shown above. These capacitors must be placed as close as possible

to, or below, the appropriate pins on the underside of the PCB to ensure the good

functionality of the device.

5.1.7 Current consumption measurement

Figure 9. Current consumption measurement scheme

MSv47984V1

VDD

Backup circuitry

(LSE, RTC and

backup registers)

Kernel logic

(CPU, digital and

memories)

Level shifter

logic

OUT

Regulator

GPIOs

1.55 V to 3.6 V

1 x 100 nF

+ 1 x 4.7 μF

VDD/VDDA

VBAT

VCORE

Power

switch

VDDIO1

ADC

VREF+

VREF-

VSS/VSSA

VREF

100 nF

VSS

VSSA

VDDA

VDD

VREF+

MSv47901V1

IDDVBAT

VBAT

IDD

VDD

(VDDA)

VBAT

VDD/VDDA

Electrical characteristics STM32G070CB/KB/RB

42/93 DS12766 Rev 2

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 17, Table 18 and Table 19

may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these conditions is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

All voltages are defined with respect to VSS.

Table 17. Voltage characteristics

Symbol Ratings Min Max Unit

VDD External supply voltage - 0.3 4.0

VBAT External supply voltage on VBAT pin - 0.3 4.0

VREF+ External voltage on VREF+ pin - 0.3 Min(VDD + 0.4, 4.0)

VIN(1)

Input voltage on FT_xx pins except FT_c - 0.3 VDD + 4.0(2)

Input voltage on FT_c pins - 0.3 5.5

Input voltage on any other pin - 0.3 4.0

1. Refer to Table 18 for the maximum allowed injected current values.

2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

Table 18. Current characteristics

Symbol Ratings Max Unit

IVDD/VDDA Current into VDD/VDDA power pin (source)(1) 100

IVSS/VSSA Current out of VSS/VSSA ground pin (sink)(1) 100

IIO(PIN)

Output current sunk by any I/O and control pin except FT_f 15

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 15

∑IIO(PIN)

Total output current sunk by sum of all I/Os and control pins 80

Total output current sourced by sum of all I/Os and control pins80

IINJ(PIN)(2) Injected current on a FT_xx pin -5 / NA(3)

Injected current on a TT_a pin(4) -5 / 0

∑|IINJ(PIN)|Total injected current (sum of all I/Os and control pins)(5) 25

1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power

supplies, in the permitted range.

2. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be

exceeded. Refer also to Table 17: Voltage characteristics for the maximum allowed input voltage values.

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum

value.

4. On these I/Os, any current injection disturbs the analog performances of the device.

5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative

injected currents (instantaneous values).

DS12766 Rev 2 43/93

STM32G070CB/KB/RB Electrical characteristics

5.3 Operating conditions

5.3.1 General operating conditions

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 21 are derived from tests performed under the ambient

temperature condition summarized in Table 20.

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 22 are derived from tests performed under the ambient

temperature conditions summarized in Table 20.

Table 19. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJMaximum junction temperature 150 °C

Table 20. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 64

MHz

fPCLK Internal APB clock frequency - 0 64

VDD/DDA Supply voltage - 2.0(1) 3.6 V

VBAT Backup operating voltage - 1.55 3.6 V

VIN I/O input voltage - -0.3 Min(VDD + 3.6, 5.5)(2) V

TAAmbient temperature(3) - -40 85 °C

TJ Junction temperature - -40 105 °C

1. When RESET is released functionality is guaranteed down to VPDR min.

2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.

3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided

that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.4: Thermal characteristics.

Table 21. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

tVDD V

DD slew rate

VDD rising - ∞

µs/V

VDD falling 10 ∞

Electrical characteristics STM32G070CB/KB/RB

44/93 DS12766 Rev 2

5.3.4 Embedded voltage reference

The parameters given in Table 23 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 20: General operating

conditions.

Table 22. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

tRSTTEMPO(2) POR temporization when VDD crosses VPOR VDD rising - 250 400 μs

VPOR(2) Power-on reset threshold - 2.06 2.10 2.14 V

VPDR(2) Power-down reset threshold - 1.96 2.00 2.04 V

Vhyst_POR_PDR Hysteresis of VPOR and VPDR

Hysteresis in

continuous

mode

-20-

Hysteresis in

other mode -30-

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

Table 23. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage -40°C < TJ < 105°C 1.182 1.212 1.232 V

tS_vrefint (1) ADC sampling time when reading

the internal reference voltage -4

(2) --µs

tstart_vrefint

Start time of reference voltage

buffer when ADC is enable --812

(2) µs

IDD(VREFINTBUF)

VREFINT buffer consumption from

VDD when converted by ADC - - 12.5 20(2) µA

∆VREFINT

Internal reference voltage spread

over the temperature range VDD = 3 V - 5 7.5(2) mV

TCoeff_vrefint Temperature coefficient - - 30 50(2) ppm/°C

ACoeff Long term stability 1000 hours, T = 25 °C - 300 1000(2) ppm

VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V

VREFINT_DIV1 1/4 reference voltage

24 25 26

VREFINT

VREFINT_DIV2 1/2 reference voltage 49 50 51

VREFINT_DIV3 3/4 reference voltage 74 75 76

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

DS12766 Rev 2 45/93

STM32G070CB/KB/RB Electrical characteristics

Figure 10. VREFINT vs. temperature

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 9: Current consumption

measurement scheme.

Typical and maximum current consumption

The MCU is placed under the following conditions:

All I/O pins are in analog input mode

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted with the minimum wait states number,

depending on the fHCLK frequency (refer to the table “Number of wait states according

to CPU clock (HCLK) frequency” available in the RM0454 reference manual).

When the peripherals are enabled fPCLK = fHCLK

For Flash memory and shared peripherals fPCLK = fHCLK = fHCLKS

Unless otherwise stated, values given in Table 24 through Table 30 are derived from tests

performed under ambient temperature and supply voltage conditions summarized in

Table 20: General operating conditions.

MSv40169V1

1.185

1.19

1.195

1.2

1.205

1.21

1.215

1.22

1.225

1.23

1.235

-40 -20 0 20 40 60 80 100 120

°C

Mean Min Max

Electrical characteristics STM32G070CB/KB/RB

46/93 DS12766 Rev 2

Table 24. Current consumption in Run and Low-power run modes

at different die temperatures

Symbol Parameter

Conditions Typ Max(1)

Unit

General fHCLK Fetch

from(2) 25°C 85°C 25°C 85°C

IDD(Run)

Supply

current in Run

mode

Range 1;

PLL enabled;

fHCLK = fHSI bypass

(≤16 MHz), 

fHCLK = fPLLRCLK

(>16 MHz);

(3)

64 MHz

Flash

memory

6.9 7.0 8.0 8.4

56 MHz 6.1 6.3 7.1 7.6

48 MHz 5.5 5.6 6.2 6.8

32 MHz 3.9 4.0 4.8 5.2

24 MHz 3.1 3.2 3.7 4.3

16 MHz 2.0 2.1 2.5 3.0

64 MHz

SRAM

6.6 6.8 7.6 7.9

56 MHz 5.8 6.1 6.7 7.0

48 MHz 5.2 5.3 6.0 6.2

32 MHz 3.6 3.7 4.2 4.6

24 MHz 2.9 3.0 3.4 3.7

16 MHz 1.9 1.9 2.3 2.5

Range 2;

PLL enabled;

fHCLK = fHSI bypass

(≤16 MHz), 

fHCLK = fPLLRCLK

(>16 MHz);

(3)

16 MHz

Flash

memory

1.5 1.7 2.0 2.4

8 MHz 0.9 1.0 1.4 1.6

2 MHz 0.3 0.3 0.6 1.0

16 MHz

SRAM

1.5 1.5 1.9 2.2

8 MHz 0.8 0.9 1.3 1.4

4 MHz 0.4 0.6 0.8 1.1

2 MHz 0.3 0.3 0.6 1.0

IDD(LPRun)

Supply

current in

Low-power

run mode

PLL disabled;

fHCLK = fHSE bypass

(> 32 kHz),

fHCLK = fLSE bypass

(= 32 kHz);

(3)

2 MHz

Flash

memory

242 281 636 954

µA

1 MHz 116 171 606 924

500 kHz 74 116 558 840

125 kHz 29 73 540 624

32 kHz 19 62 450 570

2 MHz

SRAM

219 254 582 840

1 MHz 105 154 516 792

500 kHz 67 105 438 750

125 kHz 26 65 402 528

32 kHz 17 61 390 426

1. Based on characterization results, not tested in production.

2. Prefetch and cache enabled when fetching from Flash

3. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled, cache enabled,

prefetch disabled for code and data fetch from Flash and enabled from SRAM

DS12766 Rev 2 47/93

STM32G070CB/KB/RB Electrical characteristics

Table 25. Current consumption in Sleep and Low-power sleep modes

Symbol Parameter

Conditions Typ Max(1)

Unit

General Voltage

scaling fHCLK 25°C 85°C 25°C 85°C

IDD(Sleep)

Supply

current in

Sleep mode

Flash memory enabled;

fHCLK = fHSE bypass

(≤16 MHz; PLL disabled), 

fHCLK = fPLLRCLK

(>16 MHz; PLL enabled);

All peripherals disabled

Range 1

64 MHz 2.0 2.1 2.2 2.5

56 MHz 1.8 1.9 2.0 2.3

48 MHz 1.5 1.7 1.9 2.0

32 MHz 1.1 1.2 1.4 1.6

24 MHz 0.9 1.0 1.2 1.3

16 MHz 0.6 0.7 0.7 0.8

Range 2

16 MHz 0.4 0.6 0.6 0.7

8 MHz 0.3 0.3 0.4 0.6

2 MHz 0.1 0.2 0.2 0.5

IDD(LPSleep)

Supply

current in

Low-power

sleep mode

Flash memory disabled;

PLL disabled;

fHCLK = fHSE bypass (> 32 kHz),

fHCLK = fLSE bypass (= 32 kHz);

All peripherals disabled

2 MHz 65 108 180 432

µA

1 MHz 36 83 156 396

500 kHz 27 70 150 300

125 kHz 17 61 132 282

32 kHz 15 58 132 270

1. Based on characterization results, not tested in production.

Table 26. Current consumption in Stop 0 mode

Symbol Parameter

Conditions Typ Max(1)

Unit

VDD 25 °C 85 °C 25 °C 85 °C

IDD(Stop 0)

Supply current

in Stop 0

mode

2.4 V 110 160 150 264

µA3 V 110 160 150 288

3.6 V 116 165 156 300

1. Based on characterization results, not tested in production.

Table 27. Current consumption in Stop 1 mode

Symbol Parameter

Conditions(1) Typ Max(2)

Unit

RTC VDD 25 °C 85 °C 25 °C 85 °C

IDD(Stop 1)

Supply current

in Stop 1 mode

Disabled

2.4 V 3.6 35 12 144

µA

3 V 3.7 36 18 162

3.6 V 4.2 36 22 168

Enabled

(clocked by

LSE bypass)

2.4 V 4.1 35 13 144

3 V 4.4 36 19 168

3.6 V 4.8 37 24 174

Electrical characteristics STM32G070CB/KB/RB

48/93 DS12766 Rev 2

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is

externally held low. The value of this current consumption can be simply computed by using

the pull-up/pull-down resistors values given in Table 47: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to

estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate

voltage level is externally applied. This current consumption is caused by the input Schmitt

trigger circuits used to discriminate the input value. Unless this specific configuration is

required by the application, this supply current consumption can be avoided by configuring

these I/Os in analog mode. This is notably the case of ADC input pins which should be

configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to

floating pins, they must either be configured in analog mode, or forced internally to a definite

digital value. This can be done either by using pull-up/down resistors or by configuring the

pins in output mode.

1. Flash memory not powered.

2. Based on characterization results, not tested in production.

Table 28. Current consumption in Standby mode

Symbol Parameter

Conditions Typ Max(1)

Unit

General VDD 25 °C 85 °C 25 °C 85 °C

IDD(Standby)

Supply current in

Standby mode

RTC disabled

2.4 V 1.0 2.2 2.7 14

µA

3.0 V 1.2 2.6 3.5 17

3.6 V 1.4 3.2 4.1 19

RTC enabled,

clocked by LSI

2.4 V 1.5 2.8 3.5 17

3.0 V 1.8 3.3 4.6 21

3.6 V 2.2 4.1 6.4 25

1. Based on characterization results, not tested in production.

Table 29. Current consumption in VBAT mode

Symbol Parameter

Conditions Typ

Unit

RTC VBAT 25 °C 85 °C

IDD_VBAT

Supply current in

VBAT mode

Enabled, clocked by

LSE bypass at

32.768 kHz

2.4 V 286 391

3.0 V 402 523

3.6 V 556 721

Enabled, clocked by

LSE crystal at

32.768 kHz

2.4 V 407 528

3.0 V 517 660

3.6 V 660 897

DS12766 Rev 2 49/93

STM32G070CB/KB/RB Electrical characteristics

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 30: Current consumption of peripherals, the I/Os used by an application also

contribute to the current consumption. When an I/O pin switches, it uses the current from

the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive

load (internal or external) connected to the pin:

where

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load

VDDIO1 is the I/O supply voltage

fSW is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed

frequency.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU

is placed under the following conditions:

All I/O pins are in Analog mode

The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

Ambient operating temperature and supply voltage conditions summarized in Table 17:

Voltage characteristics

The power consumption of the digital part of the on-chip peripherals is given in the

following table. The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

ISW VDDIO1 fSW C=

Table 30. Current consumption of peripherals

Peripheral Bus

Consumption in µA/MHz

Range 1 Range 2 Low-power run

and sleep

IOPORT Bus IOPORT 1.0 0.7 0.5

GPIOA IOPORT 3.4 2.8 3.0

GPIOB IOPORT 3.1 2.6 2.5

GPIOC IOPORT 2.9 2.5 3.0

GPIOD IOPORT 1.8 1.5 1.5

GPIOF IOPORT 0.7 0.6 1.0

Bus matrix AHB 3.2 2.2 2.8

All AHB Peripherals AHB 15.0 12.5 14.0

Electrical characteristics STM32G070CB/KB/RB

50/93 DS12766 Rev 2

5.3.6 Wakeup time from low-power modes and voltage scaling

transition times

The wakeup times given in Table 31 are the latency between the event and the execution of

the first user instruction.

DMA1/DMAMUX AHB 4.7 3.8 4.5

CRC AHB 0.5 0.4 0.5

FLASH AHB 4.1 3.5 4.0

All APB peripherals APB 46.5 47.5 48.0

AHB to APB bridge(1) APB 0.2 0.2 0.1

PWR APB 0.4 0.3 0.5

SYSCFG APB 0.4 0.4 0.3

WWDG APB 0.4 0.3 0.5

TIM1 APB 7.3 6.1 6.5

TIM3 APB 3.6 3.0 2.5

TIM6 APB 0.7 0.6 0.5

TIM7 APB 0.7 0.7 1.0

TIM14 APB 1.5 1.2 1.5

TIM15 APB 4.0 3.3 3.0

TIM16 APB 2.3 2.0 2.0

TIM17 APB 0.7 0.7 0.5

I2C1 APB 3.8 3.1 3.5

I2C2 APB 0.7 0.6 1.0

SPI2 APB 1.5 1.2 1.0

USART1 APB 7.2 6.0 6.5

USART2 APB 7.2 6.0 6.0

USART3 APB 2.0 1.7 2.0

USART4 APB 2.0 1.7 2.0

ADC APB 2.0 1.7 2.0

1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.

Table 30. Current consumption of peripherals (continued)

Peripheral Bus

Consumption in µA/MHz

Range 1 Range 2 Low-power run

and sleep

DS12766 Rev 2 51/93

STM32G070CB/KB/RB Electrical characteristics

Table 31. Low-power mode wakeup times(1)

Symbol Parameter Conditions Typ Max Unit

tWUSLEEP

Wakeup time from

Sleep to Run

mode

-1111

CPU

cycles

tWULPSLEEP

Wakeup time from

Low-power sleep

mode

Transiting to Low-power-run-mode execution in Flash

memory not powered in Low-power sleep mode;

HCLK = HSI16 / 8 = 2 MHz

11 14

tWUSTOP0

Wakeup time from

Stop 0

Transiting to Run-mode execution in Flash memory not

powered in Stop 0 mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1 or Range 2

5.6 6

µs

Transiting to Run-mode execution in SRAM or in Flash

memory powered in Stop 0 mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1 or Range 2

22.4

tWUSTOP1

Wakeup time from

Stop 1

Transiting to Run-mode execution in Flash memory not

powered in Stop 1 mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1 or Range 2

9.0 11.2

µs

Transiting to Run-mode execution in SRAM or in Flash

memory powered in Stop 1 mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1 or Range 2

57.5

Transiting to Low-power-run-mode execution in Flash

memory not powered in Stop 1 mode;

HCLK = HSI16/8 = 2 MHz;

Regulator in low-power mode (LPR = 1 in PWR_CR1)

22 25.3

Transiting to Low-power-run-mode execution in SRAM or

in Flash memory powered in Stop 1 mode;

HCLK = HSI16 / 8 = 2 MHz;

Regulator in low-power mode (LPR = 1 in PWR_CR1)

18 23.5

tWUSTBY

Wakeup time from

Standby mode

Transiting to Run mode;

HCLK = HSI16 = 16 MHz;

Regulator in Range 1

14.5 30 µs

tWULPRUN

Wakeup time from

Low-power run

mode(2)

Transiting to Run mode;

HSISYS = HSI16/8 = 2 MHz 57µs

1. Based on characterization results, not tested in production.

2. Time until REGLPF flag is cleared in PWR_SR2.

Electrical characteristics STM32G070CB/KB/RB

52/93 DS12766 Rev 2

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14. See

Figure 11 for recommended clock input waveform.

Figure 11. High-speed external clock source AC timing diagram

Table 32. Regulator mode transition times(1)

Symbol Parameter Conditions Typ Max Unit

tVOST

Transition times between regulator

Range 1 and Range 2(2) HSISYS = HSI16 20 40 µs

1. Based on characterization results, not tested in production.

2. Time until VOSF flag is cleared in PWR_SR2.

Table 33. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSE_ext User external clock source frequency

Voltage scaling

Range 1 -848

MHz

Voltage scaling

Range 2 -826

VHSEH OSC_IN input pin high level voltage - 0.7 VDDIO1 -V

DDIO1 V

VHSEL OSC_IN input pin low level voltage - VSS -0.3 V

DDIO1

tw(HSEH)

tw(HSEL)

OSC_IN high or low time

Voltage scaling

Range 1 7- -

Voltage scaling

Range 2 18 - -

1. Guaranteed by design.

MS19214V2

VHSEH

tf(HSE)

90%

10%

THSE

tr(HSE)

VHSEL

tw(HSEH)

tw(HSEL)

DS12766 Rev 2 53/93

STM32G070CB/KB/RB Electrical characteristics

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14. See

Figure 12 for recommended clock input waveform.

Figure 12. Low-speed external clock source AC timing diagram

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on design

simulation results obtained with typical external components specified in Table 35. In the

application, the resonator and the load capacitors have to be placed as close as possible to

the oscillator pins in order to minimize output distortion and startup stabilization time. Refer

to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Table 34. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIO1 -V

DDIO1 V

VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIO1

tw(LSEH)

tw(LSEL)

OSC32_IN high or low time - 250 - - ns

1. Guaranteed by design.

MS19215V2

VLSEH

tf(LSE)

90%

10%

TLSE

tr(LSE)

VLSEL

tw(LSEH)

tw(LSEL)

Table 35. HSE oscillator characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 8 48 MHz

RFFeedback resistor - - 200 - kΩ

Electrical characteristics STM32G070CB/KB/RB

54/93 DS12766 Rev 2

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 13). CL1 and CL2 are usually the

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing

CL1 and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

IDD(HSE) HSE current consumption

During startup(3) --5.5

VDD = 3 V, 

Rm = 30 Ω, 

CL = 10 pF@8 MHz

-0.44-

VDD = 3 V, 

Rm = 45 Ω, 

CL = 10 pF@8 MHz

-0.45-

VDD = 3 V, 

Rm = 30 Ω, 

CL = 5 pF@48 MHz

-0.68-

VDD = 3 V, 

Rm = 30 Ω,

CL = 10 pF@48 MHz

-0.94-

VDD = 3 V, 

Rm = 30 Ω, 

CL = 20 pF@48 MHz

-1.77-

Maximum critical crystal

transconductance Startup - - 1.5 mA/V

tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time

4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is

reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Table 35. HSE oscillator characteristics(1) (continued)

Symbol Parameter Conditions(2) Min Typ Max Unit

DS12766 Rev 2 55/93

STM32G070CB/KB/RB Electrical characteristics

Figure 13. Typical application with an 8 MHz crystal

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator

oscillator. All the information given in this paragraph are based on design simulation results

obtained with typical external components specified in Table 36. In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

MS19876V1

(1)

OSC_IN

OSC_OUT

Bias

controlled

gain

fHSE

REXT

8 MHz

resonator

Resonator with integrated

capacitors

CL1

CL2

Table 36. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

IDD(LSE) LSE current consumption

LSEDRV[1:0] = 00 

Low drive capability -250-

LSEDRV[1:0] = 01 

Medium low drive capability -315-

LSEDRV[1:0] = 10 

Medium high drive capability -500-

LSEDRV[1:0] = 11 

High drive capability -630-

Gmcritmax

Maximum critical crystal

LSEDRV[1:0] = 00

Low drive capability --0.5

µA/V

LSEDRV[1:0] = 01

Medium low drive capability - - 0.75

LSEDRV[1:0] = 10

Medium high drive capability --1.7

LSEDRV[1:0] = 11

High drive capability --2.7

tSU(LSE)(3) Startup time VDD is stabilized - 2 - s

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

Electrical characteristics STM32G070CB/KB/RB

56/93 DS12766 Rev 2

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 14. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden

to add one.

5.3.8 Internal clock source characteristics

The parameters given in Table 37 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 20: General operating

conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

MS30253V2

OSC32_IN

OSC32_OUT

Drive

programmable

amplifier

fLSE

32.768 kHz

resonator

Resonator with integrated

capacitors

CL1

CL2

Table 37. HSI16 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

∆Temp(HSI16)

HSI16 oscillator frequency drift over

temperature

TA= 0 to 85 °C -1 - 1 %

TA= -40 to 85 °C -2 - 1.5 %

∆VDD(HSI16)

HSI16 oscillator frequency drift over

VDD

VDD=VDD(min) to 3.6 V -0.1 - 0.05 %

TRIM HSI16 frequency user trimming step

From code 127 to 128 -8 -6 -4

From code 63 to 64

From code 191 to 192 -5.8 -3.8 -1.8

For all other code

increments 0.2 0.3 0.4

DHSI16(2) Duty Cycle - 45 - 55 %

tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2 μs

DS12766 Rev 2 57/93

STM32G070CB/KB/RB Electrical characteristics

Low-speed internal (LSI) RC oscillator

5.3.9 PLL characteristics

The parameters given in Table 39 are derived from tests performed under temperature and

VDD supply voltage conditions summarized in Table 20: General operating conditions.

tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5 μs

IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA

1. Based on characterization results, not tested in production.

2. Guaranteed by design.

Table 37. HSI16 oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Table 38. LSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fLSI LSI frequency

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96

kHz

VDD = VDD(min) to 3.6 V, TA = -40 to

85 °C 29.5 - 34

tSU(LSI)(2) LSI oscillator start-up time - - 80 130 μs

tSTAB(LSI)(2) LSI oscillator stabilization time 5% of final frequency - 125 180 μs

IDD(LSI)(2) LSI oscillator power

consumption - - 110 180 nA

1. Based on characterization results, not tested in production.

2. Guaranteed by design.

Table 39. PLL characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fPLL_IN PLL input clock frequency(2) -2.66-16MHz

DPLL_IN PLL input clock duty cycle - 45 - 55 %

fPLL_P_OUT PLL multiplier output clock P

Voltage scaling Range 1 3.09 - 122

MHz

Voltage scaling Range 2 3.09 - 40

fPLL_R_OUT PLL multiplier output clock R

Voltage scaling Range 1 12 - 64

MHz

Voltage scaling Range 2 12 - 16

fVCO_OUT PLL VCO output

Voltage scaling Range 1 96 - 344

MHz

Voltage scaling Range 2 96 - 128

tLOCK PLL lock time - - 15 40 μs

Jitter

RMS cycle-to-cycle jitter

System clock 56 MHz

-50-

±ps

RMS period jitter - 40 -

Electrical characteristics STM32G070CB/KB/RB

58/93 DS12766 Rev 2

5.3.10 Flash memory characteristics

IDD(PLL)

PLL power consumption

on VDD(1)

VCO freq = 96 MHz - 200 260

μAVCO freq = 192 MHz - 300 380

VCO freq = 344 MHz - 520 650

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between the two PLLs.

Table 39. PLL characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Table 40. Flash memory characteristics(1)

Symbol Parameter Conditions Typ Max Unit

tprog 64-bit programming time - 85 125 µs

tprog_row Row (32 double word) programming time

Normal programming 2.7 4.6

Fast programming 1.7 2.8

tprog_page Page (2 Kbyte) programming time

Normal programming 21.8 36.6

Fast programming 13.7 22.4

tERASE Page (2 Kbyte) erase time - 22.0 40.0

tprog_bank Bank (128 Kbyte(2)) programming time

Normal programming 1.4 2.4

Fast programming 0.9 1.4

tME Mass erase time - 22.1 40.1 ms

IDD(FlashA) Average consumption from VDD

Programming 3 -

mAPage erase 3 -

Mass erase 3 -

IDD(FlashP) Maximum current (peak)

Programming, 2 µs peak

duration 7-

Erase, 41 µs peak duration 7 -

1. Guaranteed by design.

2. Values provided also apply to devices with less Flash memory than one 128 Kbyte bank

Table 41. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1)

1. Guaranteed by characterization results.

Unit

NEND Endurance TA = -40 to +85 °C 1 kcycles

tRET Data retention 1 kcycle(2) at TA = 85 °C

2. Cycling performed over the whole temperature range.

15 Years

DS12766 Rev 2 59/93

STM32G070CB/KB/RB Electrical characteristics

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

the device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and

VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 42. They are based on the EMS levels and classes

defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

corrupted program counter

unexpected reset

critical data corruption (for example control registers)

Table 42. EMS characteristics

Symbol Parameter Conditions Level/

Class

VFESD

Voltage limits to be applied on any I/O pin to

induce a functional disturbance

VDD = 3.3 V, TA = +25 °C, 

fHCLK = 64 MHz, LQFP64,

conforming to IEC 61000-4-2

VEFTB

Fast transient voltage burst limits to be applied

through 100 pF on VDD and VSS pins to induce a

functional disturbance

VDD = 3.3 V, TA = +25 °C, 

fHCLK = 64 MHz, LQFP64,

conforming to IEC 61000-4-4

Electrical characteristics STM32G070CB/KB/RB

60/93 DS12766 Rev 2

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

5.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the ANSI/JEDEC standard.

Table 43. EMI characteristics

Symbol Parameter Conditions Monitored

frequency band

Max vs.

[fHSE/fHCLK]Unit

8 MHz / 64 MHz

SEMI Peak level

VDD = 3.6 V, TA = 25 °C,

LQFP64 package

compliant with IEC 61967-2

0.1 MHz to 30 MHz 7

dBµV

30 MHz to 130 MHz -1

130 MHz to 1 GHz 8

1 GHz to 2 GHz 7

EMI level 2.5 -

Table 44. ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum

value(1) Unit

VESD(HBM)

Electrostatic discharge voltage

(human body model)

TA = +25 °C, conforming to

ANSI/ESDA/JEDEC JS-001 2 2000

VESD(CDM)

Electrostatic discharge voltage

(charge device model)

TA = +25 °C, conforming to

ANSI/ESDA/JEDEC JS-002 C2a 500

1. Based on characterization results, not tested in production.

DS12766 Rev 2 61/93

STM32G070CB/KB/RB Electrical characteristics

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

A supply overvoltage is applied to each power supply pin.

A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

5.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDDIO1 (for standard, 3.3 V-capable I/O pins) should be avoided during normal

product operation. However, in order to give an indication of the robustness of the

microcontroller in cases when abnormal injection accidentally happens, susceptibility tests

are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter: ADC error above a certain limit

(higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional

limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or

oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced

leakage current is caused by positive injection.

Table 45. Electrical sensitivity

Symbol Parameter Conditions Class

LU Static latch-up class TA = +85 °C conforming to JESD78 II Level A

Table 46. I/O current injection susceptibility(1)

Symbol Description

Functional susceptibility

Unit

Negative

injection

Positive

injection

IINJ

Injected current on

All except PA4, PA5, PA6, PB0,

PB3, and PC0 -5 N/A mA

PA4, PA5 -5 0 mA

PA6, PB0, PB3, and PC0 0 N/A mA

1. Based on characterization results, not tested in production.

Electrical characteristics STM32G070CB/KB/RB

62/93 DS12766 Rev 2

5.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 47 are derived from tests

performed under the conditions summarized in Table 20: General operating conditions. All

I/Os are designed as CMOS- and TTL-compliant.

Table 47. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(1) I/O input low level

voltage

All

except

FT_c

VDD(min) < VDDIO1 < 3.6 V - -

0.3 x VDDIO1

(2)

0.39 x VDDIO1

- 0.06 (3)

FT_c

VDDIO1 < 2.7 V - - 0.3 x VDDIO1

VDD(min) < VDDIO1 < 2.7 V - - 0.25 x VDDIO1

VIH(1) I/O input high level

voltage

All

except

FT_c

VDD(min) < VDDIO1 < 3.6 V

0.7 x VDDIO1(

2) --

V0.49 x VDDIO1

+ 0.26(3) --

FT_c VDD(min) < VDDIO1 < 3.6 V 0.7 x VDDIO1 -5

Vhys(3) I/O input hysteresis

TT_xx,

FT_xx,

NRST

VDD(min) < VDDIO1 < 3.6 V - 200 - mV

Ilkg

Input leakage

current(3)

FT_xx

except

FT_c

and

FT_d

0 < VIN ≤ VDDIO1 --±70

VDDIO1 ≤ VIN ≤ VDDIO1+1 V - - 600(4)

VDDIO1 +1 V < VIN ≤

5.5 V(3) - - 150(4)

FT_c

0 < VIN ≤ VDDIO1 - - 2000

VDDIO1 < VIN ≤ 5 V - - 3000(4)

FT_d

0 < VIN ≤ VDDIO1 - - 4500

VDDIO1 < VIN ≤ 5.5 V - - 9000(4)

TT_a

0 < VIN ≤ VDDIO1 --±150

VDDIO1 < VIN ≤

VDDIO1 + 0.3 V - - 2000(4)

RPU

Weak pull-up

equivalent resistor

(5)

VIN = VSS 25 40 55 kΩ

RPD

Weak pull-down

equivalent resistor(5) VIN = VDDIO1 25 40 55 kΩ

CIO I/O pin capacitance - - 5 - pF

1. Refer to Figure 15: I/O input characteristics.

2. Tested in production.

3. Guaranteed by design.

DS12766 Rev 2 63/93

STM32G070CB/KB/RB Electrical characteristics

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters, as shown

in Figure 15.

Figure 15. I/O input characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±6 mA, and up to

±15 mA with relaxed VOL/VOH.

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 5.2:

The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum

consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating

IVDD (see Table 17: Voltage characteristics).

The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of

the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 17:

Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:

ITotal_Ileak_max = 10 µA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

MSv47926V1

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

0.5

1.5

2.5

Minimum required

logic level 1 zone

Minimum required

logic level 0 zone

IHmin

= 0.7 V

DDIO

(CMOS standard requirement)

VILmax = 0.3 VDDIO (CMOS standard requirement)

Undefined input range

IHmin

= 0.49 V

DDIO

+ 0.26

VILmax = 0.39 VDDIO - 0.06

VIN (V)

VDDIO (V)

TTL standard requirement

Device characteristics

Test thresholds

Electrical characteristics STM32G070CB/KB/RB
64/93 DS12766 Rev 2
Table 20: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT 
unless otherwise specified).
          
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 16 and 
Table 49, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under 
the ambient temperature and supply voltage conditions summarized in Table 20: General 
operating conditions.
          
Table 48. Output voltage characteristics(1) 
Symbol Parameter Conditions Min Max Unit
VOL Output low level voltage for an I/O pin CMOS port(2) 
|IIO| = 2 mA for FT_c I/Os
      = 6 mA for other I/Os
VDDIO1 ≥ 2.7 V
-0.4
V
VOH Output high level voltage for an I/O pin VDDIO1 - 0.4 -
VOL(3) Output low level voltage for an I/O pin TTL port(2) 
|IIO| = 2 mA for FT_c I/Os
      = 6 mA for other I/Os
VDDIO1 ≥ 2.7 V
-0.4
VOH(3) Output high level voltage for an I/O pin 2.4 -
VOL(3) Output low level voltage for an I/O pin All I/Os except FT_c
|IIO| = 15 mA
VDDIO1 ≥ 2.7 V
-1.3
VOH(3) Output high level voltage for an I/O pin VDDIO1 - 1.3 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 1 mA for FT_c I/Os
      = 3 mA for other I/Os
-0.4
VOH(3) Output high level voltage for an I/O pin VDDIO1 - 0.45 -
VOLFM+
(3)
Output low level voltage for an FT I/O 
pin in FM+ mode (FT I/O with _f option)
|IIO| = 20 mA
VDDIO1 ≥ 2.7 V -0.4
|IIO| = 9 mA - 0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17: 
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always 
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
Table 49. I/O AC characteristics(1)(2) 
Speed Symbol Parameter Conditions Min Max Unit
00
Fmax Maximum frequency
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 2
MHz
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 0.35
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 3
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 0.45
Tr/Tf Output rise and fall time
C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 100
ns
C=50 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 225
C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 75
C=10 pF, 2.0 V ≤ VDDIO1 ≤ 2.7 V - 150

DS12766 Rev 2 65/93

STM32G070CB/KB/RB Electrical characteristics

Fmax Maximum frequency

C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 10

MHz

C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 2

C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 15

C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 2.5

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 30

C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 60

C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 15

C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30

Fmax Maximum frequency

C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 30

MHz

C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 15

C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 60

C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30

Tr/Tf Output rise and fall time

C=50 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 11

C=50 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 22

C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 4

C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 8

Fmax Maximum frequency

C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 60

MHz

C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 30

C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 80(3)

C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 40

Tr/Tf Output rise and fall time

C=30 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 5.5

C=30 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 11

C=10 pF, 2.7 V ≤ VDDIO1 ≤ 3.6 V - 2.5

C=10 pF, 1.6 V ≤ VDDIO1 ≤ 2.7 V - 5

Fm+ Fmax Maximum frequency C=50 pF, 1.6 V ≤ VDDIO1 ≤ 3.6 V -1MHz

Tf Output fall time(4) -5ns

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0454 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

4. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.

Table 49. I/O AC characteristics(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit

Electrical characteristics STM32G070CB/KB/RB

66/93 DS12766 Rev 2

Figure 16. I/O AC characteristics definition(1)

1. Refer to Table 49: I/O AC characteristics.

5.3.15 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent 

pull-up resistor, RPU.

Unless otherwise specified, the parameters given in the following table are derived from

tests performed under the ambient temperature and supply voltage conditions summarized

in Table 20: General operating conditions.

MS32132V2

10%

50%

90% 10%

50%

90%

Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)

when loaded by the specified capacitance.

r(IO)out

tf(IO)out

Table 50. NRST pin characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST)

NRST input low level

voltage - - - 0.3 x VDDIO1

VIH(NRST)

NRST input high level

voltage - 0.7 x VDDIO1 --

Vhys(NRST)

NRST Schmitt trigger

voltage hysteresis --200-mV

RPU

Weak pull-up

equivalent resistor(2) VIN = VSS 25 40 55 kΩ

VF(NRST) NRST input filtered

pulse ---70ns

VNF(NRST)

NRST input not filtered

pulse 2.0 V ≤ VDD ≤ 3.6 V 350 - - ns

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimal (~10% order).

DS12766 Rev 2 67/93

STM32G070CB/KB/RB Electrical characteristics

Figure 17. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 50: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.16 Analog switch booster

5.3.17 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 52 are preliminary values derived

from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage

conditions summarized in Table 20: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

MS19878V3

RPU

VDD

Internal reset

External

reset circuit(1)

NRST(2)

Filter

0.1 μF

Table 51. Analog switch booster characteristics(1)

1. Guaranteed by design.

Symbol Parameter Min Typ Max Unit

VDD Supply voltage VDD(min) - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs

Booster consumption for

VDD ≤ 2.7 V --500

Booster consumption for

2.7 V ≤ VDD ≤ 3.6 V --900

Table 52. ADC characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit

VDDA Analog supply voltage - 2.0 - 3.6 V

VREF+ Positive reference

voltage

-2-V

DDA V

fADC ADC clock frequency

Range 1 0.14 - 35

MHz

Range 2 0.14 - 16

Electrical characteristics STM32G070CB/KB/RB

68/93 DS12766 Rev 2

fsSampling rate

12 bits - - 2.50

MSps

10 bits - - 2.92

8 bits - - 3.50

6 bits - - 4.38

fTRIG

External trigger

frequency

fADC = 35 MHz; 12 bits - - 2.33

MHz

12 bits - - fADC/15

VAIN (3) Conversion voltage

range -V

SSA -V

REF+ V

RAIN

External input

impedance ---50kΩ

CADC

Internal sample and

hold capacitor --5-pF

tSTAB ADC power-up time - 2 Conversion

cycle

tCAL Calibration time

fADC = 35 MHz 2.35 µs

-821/f

ADC

tLATR

Trigger conversion

latency

CKMODE = 00 2 - 3 1/fADC

CKMODE = 01 6.5

1/fPCLK

CKMODE = 10 12.5

CKMODE = 11 3.5

tsSampling time fADC = 35 MHz

0.043 - 4.59 µs

1.5 - 160.5 1/fADC

tADCVREG_STUP

ADC voltage regulator

start-up time ---20

µs

tCONV

Total conversion time

(including sampling

time)

fADC = 35 MHz

Resolution = 12 bits 0.40 - 4.95 µs

Resolution = 12 bits

ts + 12.5 cycles for successive

approximation

= 14 to 173

1/fADC

tIDLE

Laps of time allowed

between two

conversions without

rearm

- - - 100 µs

IDDA(ADC)

ADC consumption

from VDDA

fs = 2.5 MSps - 410 -

µAfs = 1 MSps - 164 -

fs = 10 kSps - 17 -

Table 52. ADC characteristics(1) (continued)

Symbol Parameter Conditions(2) Min Typ Max Unit

DS12766 Rev 2 69/93

STM32G070CB/KB/RB Electrical characteristics

IDDV(ADC)

ADC consumption

from VREF+

fs = 2.5 MSps - 65 -

µAfs = 1 MSps - 26 -

fs = 10 kSps - 0.26 -

1. Guaranteed by design

2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and

disabled when VDDA ≥ 2.4 V.

3. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate

functions for further details.

Table 52. ADC characteristics(1) (continued)

Symbol Parameter Conditions(2) Min Typ Max Unit

Table 53. Maximum ADC RAIN .

Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz

[ns]

Max. RAIN(1)(2)

(Ω)

12 bits

1.5 43 50

3.5 100 680

7.5 214 2200

12.5 357 4700

19.5 557 8200

39.5 1129 15000

79.5 2271 33000

160.5 4586 50000

10 bits

1.5 43 68

3.5 100 820

7.5 214 3300

12.5 357 5600

19.5 557 10000

39.5 1129 22000

79.5 2271 39000

160.5 4586 50000

8 bits

1.5 43 82

3.5 100 1500

7.5 214 3900

12.5 357 6800

19.5 557 12000

39.5 1129 27000

79.5 2271 50000

160.5 4586 50000

Electrical characteristics STM32G070CB/KB/RB

70/93 DS12766 Rev 2

6 bits

1.5 43 390

3.5 100 2200

7.5 214 5600

12.5 357 10000

19.5 557 15000

39.5 1129 33000

79.5 2271 50000

160.5 4586 50000

1. Guaranteed by design.

2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and

disabled when VDDA ≥ 2.4 V.

Table 53. Maximum ADC RAIN . (continued)

Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz

[ns]

Max. RAIN(1)(2)

(Ω)

Table 54. ADC accuracy(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Tota l

unadjusted

error

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

-36.5LSB

EO Offset error

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

-1.54.5LSB

EG Gain error

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

-35LSB

ED Differential

linearity error

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

-1.21.5LSB

EL Integral linearity

error

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

-2.53LSB

ENOB Effective

number of bits

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

9.6 10.2 - bit

SINAD

Signal-to-noise

and distortion

ratio

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

59.5 63 - dB

SNR Signal-to-noise

ratio

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

60 64 - dB

THD Total harmonic

distortion

VDDA=VREF+ < 3.6 V;

fADC = 35 MHz; fs ≤ 2.5 MSps;

TA = entire range

--74-70dB

DS12766 Rev 2 71/93

STM32G070CB/KB/RB Electrical characteristics

Figure 18. ADC accuracy characteristics

Figure 19. Typical connection diagram using the ADC

1. Refer to Table 52: ADC characteristics for the values of RAIN and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (refer to Table 47: I/O static characteristics for the value of the pad capacitance). A high

Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

3. Refer to Table 47: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 8: Power supply scheme.

The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as

possible to the chip.

1. Based on characterization results, not tested in production.

2. ADC DC accuracy values are measured after internal calibration.

3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion

of signal on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins

susceptible to receive negative current.

4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V

and disabled when VDDA ≥ 2.4 V.

MSv19880V3

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End point correlation line

4095

4094

4093

02 345 6

1 7 4093 4094 4095

1 LSB ideal

(1)

(3)

(2)

Code

(VAIN / VREF+)*4095

ETtotal unadjusted error: maximum deviation

between the actual and ideal transfer curves.

EGgain error: deviation between the last ideal

transition and the last actual one.

EDdifferential linearity error: maximum deviation

between actual steps and the ideal ones.

ELintegral linearity error: maximum deviation between

any actual transition and the end point correlation line.

EOoffset error: maximum deviation between the

first actual transition and the first ideal one.

MS33900V5

Sample and hold ADC converter

12-bit

converter

Cparasitic

(2) Ilkg

(3)

VTCADC

VDDA

RAIN

(1)

VAIN

AINx RADC

Electrical characteristics STM32G070CB/KB/RB

72/93 DS12766 Rev 2

5.3.18 Temperature sensor characteristics

5.3.19 VBAT monitoring characteristics

5.3.20 Timer characteristics

The parameters given in the following tables are guaranteed by design. Refer to

Section 5.3.14: I/O port characteristics for details on the input/output alternate function

characteristics (output compare, input capture, external clock, PWM output).

Table 55. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VTS linearity with temperature - ±1 ±2 °C

Avg_Slope(2) Average slope 2.3 2.5 2.7 mV/°C

V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V

tSTART(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode(4) -815µs

tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs

tS_temp(1) ADC sampling time when reading the temperature 5 - - µs

IDD(TS)(1) Temperature sensor consumption from VDD, when

selected by ADC -4.77 µA

1. Guaranteed by design.

2. Based on characterization results, not tested in production.

3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.

4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

Table 56. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT -39-kΩ

Q Ratio on VBAT measurement - 3 - -

Er(1) Error on Q -10 - 10 %

tS_vbat(1) ADC sampling time when reading the VBAT 12 - - µs

1. Guaranteed by design.

Table 57. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

RBC

Battery

charging

resistor

VBRS = 0 - 5 -

kΩ

VBRS = 1 - 1.5 -

DS12766 Rev 2 73/93

STM32G070CB/KB/RB Electrical characteristics

5.3.21 Characteristics of communication interfaces

I2C-bus interface characteristics

The I2C-bus interface meets timing requirements of the I2C-bus specification and user

manual rev. 03 for:

Standard-mode (Sm): with a bit rate up to 100 kbit/s

Fast-mode (Fm): with a bit rate up to 400 kbit/s

Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The timings are guaranteed by design as long as the I2C peripheral is properly configured

(refer to the reference manual RM0454) and when the I2CCLK frequency is greater than the

minimum shown in the following table.

Table 58. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

tres(TIM) Timer resolution time

-1-t

TIMxCLK

fTIMxCLK = 64 MHz 15.625 - ns

fEXT

Timer external clock frequency

on CH1 to CH4

-0f

TIMxCLK/2

MHz

fTIMxCLK = 64 MHz 0 40

ResTIM Timer resolution TIMx - 16 bit

tCOUNTER 16-bit counter clock period

- 1 65536 tTIMxCLK

fTIMxCLK = 64 MHz 0.015625 1024 µs

tMAX_COUNT

Maximum possible count with

32-bit counter

- - 65536 × 65536 tTIMxCLK

fTIMxCLK = 64 MHz - 67.10 s

1. TIMx, is used as a general term in which x stands for 1,, 3, 4, 5, 6, 7, 8, 15, 16 or 17.

Table 59. IWDG min/max timeout period at 32 kHz LSI clock(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF Unit

/4 0 0.125 512

/8 1 0.250 1024

/16 2 0.500 2048

/32 3 1.0 4096

/64 4 2.0 8192

/128 5 4.0 16384

/256 6 or 7 8.0 32768

1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an

uncertainty of one RC period.

Electrical characteristics STM32G070CB/KB/RB

74/93 DS12766 Rev 2

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins

support Fm+ low-level output current maximum requirement. Refer to Section 5.3.14: I/O

port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its

characteristics:

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Table 6 2 for SPI are derived from tests

performed under the ambient temperature, fPCLKx frequency and supply voltage conditions

summarized in Table 20: General operating conditions. The additional general conditions

are:

OSPEEDRy[1:0] set to 11 (output speed)

capacitive load C = 30 pF

measurement points at CMOS levels: 0.5 x VDD

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 60. Minimum I2CCLK frequency

Symbol Parameter Condition Typ Unit

fI2CCLK(min)

Minimum I2CCLK

frequency for correct

operation of I2C

peripheral

Standard-mode 2

MHz

Fast-mode

Analog filter enabled

DNF = 0

Analog filter disabled

DNF = 1

Fast-mode Plus

Analog filter enabled

DNF = 0

Analog filter disabled

DNF = 1

Table 61. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

tAF

Limiting duration of spikes suppressed

by the filter(2) 50 260 ns

1. Based on characterization results, not tested in production.

2. Spikes shorter than the limiting duration are suppressed.

DS12766 Rev 2 75/93

STM32G070CB/KB/RB Electrical characteristics

Table 62. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

VDD(min) < VDD < 3.6 V

Range 1

MHz

Master transmitter

VDD(min) < VDD < 3.6 V

Range 1

Slave receiver

VDD(min) < VDD < 3.6 V

Range 1

Slave transmitter/full duplex

2.7 < VDD < 3.6 V

Range 1

Slave transmitter/full duplex

VDD(min) < VDD < 3.6 V

Range 1

VDD(min) < VDD < 3.6 V

Range 2 8

tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4 ₓ TPCLK --ns

th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2 ₓ TPCLK --ns

tw(SCKH) SCK high time Master mode TPCLK

- 1.5 TPCLK

TPCLK

+ 1.5 ns

tw(SCKL) SCK low time Master mode TPCLK

- 1.5 TPCLK

TPCLK

+ 1.5 ns

tsu(MI)

Master data input setup

time -1--ns

tsu(SI)

Slave data input setup

time -1--ns

th(MI)

Master data input hold

time -5--ns

th(SI)

Slave data input hold

time -1--ns

ta(SO) Data output access time Slave mode 9 - 34 ns

tdis(SO) Data output disable time Slave mode 9 - 16 ns

tv(SO)

Slave data output valid

time

2.7 < VDD < 3.6 V

Range 1 -914

VDD(min) < VDD < 3.6 V

Range 1 -921

VDD(min) < VDD < 3.6 V

Voltage Range 2 -1124

tv(MO)

Master data output valid

time --35ns

Electrical characteristics STM32G070CB/KB/RB

76/93 DS12766 Rev 2

Figure 20. SPI timing diagram - slave mode and CPHA = 0

Figure 21. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

th(SO)

Slave data output hold

time -5--ns

th(MO)

Master data output hold

time -1--ns

1. Based on characterization results, not tested in production.

Table 62. SPI characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

MSv41658V1

NSS input

CPHA=0

CPOL=0

SCK input

CPHA=0

CPOL=1

MISO output

MOSI input

tsu(SI)

th(SI)

tw(SCKL)

tw(SCKH)

tc(SCK)

tr(SCK)

th(NSS)

tdis(SO)

tsu(NSS)

ta(SO) tv(SO)

Next bits IN

Last bit OUT

First bit IN

First bit OUT Next bits OUT

th(SO) tf(SCK)

Last bit IN

MSv41659V1

NSS input

CPHA=1

CPOL=0

SCK input

CPHA=1

CPOL=1

MISO output

MOSI input

tsu(SI) th(SI)

tw(SCKL)

tw(SCKH)

tsu(NSS)

tc(SCK)

ta(SO) tv(SO)

First bit OUT Next bits OUT

Next bits IN

Last bit OUT

th(SO) tr(SCK)

tf(SCK) th(NSS)

tdis(SO)

First bit IN Last bit IN

DS12766 Rev 2 77/93

STM32G070CB/KB/RB Electrical characteristics

Figure 22. SPI timing diagram - master mode

1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

ai14136c

SCK Output

CPHA= 0

MOSI

OUTPUT

MISO

INP UT

CPHA= 0

LSB OUT

LSB IN

CPOL=0

CPOL=1

B IT1 OUT

NSS input

tc(SCK)

tw(SCKH)

tw(SCKL)

tr(SCK)

tf(SCK)

th(MI)

High

SCK Output

CPHA=1

CPOL=0

CPOL=1

tsu(MI)

tv(MO) th(MO)

MSB IN BIT6 IN

MSB OUT

Table 63. I2S characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S main clock output

fMCK= 256 x Fs; (Fs = audio sampling

frequency)

Fsmin = 8 kHz; Fsmax = 192 kHz;

2.048 49.152 MHz

fCK I2S clock frequency

Master data - 64xFs

MHz

Slave data - 64xFs

DCK

I2S clock frequency duty

cycle Slave receiver 30 70 %

Electrical characteristics STM32G070CB/KB/RB

78/93 DS12766 Rev 2

Figure 23. I2S slave timing diagram (Philips protocol)

1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

tv(WS) WS valid time Master mode - 8

th(WS) WS hold time Master mode 2 -

tsu(WS) WS setup time Slave mode 4 -

th(WS) WS hold time Slave mode 2 -

tsu(SD_MR) Data input setup time

Master receiver 4 -

tsu(SD_SR) Slave receiver 5 -

th(SD_MR) Data input hold time

Master receiver 4.5 -

th(SD_SR) Slave receiver 2 -

tv(SD_ST)

Data output valid time -

slave transmitter

after enable edge; 2.7 < VDD < 3.6V

after enable edge;

VDD(min) < VDD < 3.6V 23

tv(SD_MT)

Data output valid time -

master transmitter after enable edge - 5.5

th(SD_ST)

Data output hold time -

slave transmitter after enable edge 8 -

th(SD_MT)

Data output hold time -

master transmitter after enable edge 1 -

1. Based on characterization results, not tested in production.

Table 63. I2S characteristics(1) (continued)

Symbol Parameter Conditions Min Max Unit

MSv39721V1

CK Input

CPOL = 0

CPOL = 1

tc(CK)

WS input

SDtransmit

SDreceive

tw(CKH) tw(CKL)

tsu(WS) tv(SD_ST) th(SD_ST)

th(WS)

tsu(SD_SR) th(SD_SR)

MSB receive Bitn receive LSB receive

MSB transmit Bitn transmit

LSB receive(2)

LSB transmit(2)

DS12766 Rev 2 79/93

STM32G070CB/KB/RB Electrical characteristics

Figure 24. I2S master timing diagram (Philips protocol)

1. Based on characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

USART characteristics

Unless otherwise specified, the parameters given in Table 64 for USART are derived from

tests performed under the ambient temperature, fPCLKx frequency and supply voltage

conditions summarized in Table 20: General operating conditions. The additional general

conditions are:

OSPEEDRy[1:0] set to 10 (output speed)

capacitive load C = 30 pF

measurement points at CMOS levels: 0.5 x VDD

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, CK, TX, and RX for USART).

MSv39720V1

CK output

CPOL = 0

CPOL = 1

tc(CK)

WS output

SDreceive

SDtransmit

tw(CKH)

tw(CKL)

tsu(SD_MR)

tv(SD_MT) th(SD_MT)

th(WS)

th(SD_MR)

MSB receive Bitn receive LSB receive

MSB transmit Bitn transmit LSB transmit

tf(CK) tr(CK)

tv(WS)

LSB receive(2)

LSB transmit(2)

10%

90%

Table 64. USART characteristics

Symbol Parameter Conditions Min Typ Max Unit

fCK USART clock frequency

Master mode - - 8

MHz

Slave mode - - 21

Electrical characteristics STM32G070CB/KB/RB

80/93 DS12766 Rev 2

tsu(NSS) NSS setup time Slave mode tker + 2 - -

th(NSS) NSS hold time Slave mode 2 - -

tw(CKH) CK high time

Master mode 1 / fCK / 2

- 1 1 / fCK / 2 1 / fCK / 2

+ 1

tw(CKL) CK low time

tsu(RX) Data input setup time

Master mode tker + 2 - -

Slave mode 4 - -

th(RX) Data input hold time

Master mode 1 - -

Slave mode 0.5 - -

tv(TX) Data output valid time

Master mode - 0.5 1

Slave mode - 10 19

th(TX) Data output hold time

Master mode 0 - -

Slave mode 7 - -

Table 64. USART characteristics

Symbol Parameter Conditions Min Typ Max Unit

DS12766 Rev 2 81/93

STM32G070CB/KB/RB Package information

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

6.1 LQFP64 package information

LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.

Figure 25. LQFP64 package outline

1. Drawing is not to scale.

Table 65. LQFP64 package mechanical data

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

5W_ME_V3

SEATING PLANE

ccc C

IDENTIFICATION

PIN 1

116

GAUGE PLANE

0.25 mm

Package information STM32G070CB/KB/RB

82/93 DS12766 Rev 2

Figure 26. Recommended footprint for LQFP64 package

1. Dimensions are expressed in millimeters.

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 - 0.200 0.0035 - 0.0079

D - 12.000 - - 0.4724 -

D1 - 10.000 - - 0.3937 -

D3 - 7.500 - - 0.2953 -

E - 12.000 - - 0.4724 -

E1 - 10.000 - - 0.3937 -

E3 - 7.500 - - 0.2953 -

e - 0.500 - - 0.0197 -

K 0°3.5°7° 0°3.5°7°

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

ccc - - 0.080 - - 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 65. LQFP64 package mechanical data (continued)

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

64 17

116

1.2

0.3

10.3

12.7

10.3

0.5

7.8

12.7

ai14909c

DS12766 Rev 2 83/93

STM32G070CB/KB/RB Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 27. LQFP64 package marking example

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

MSv42184V2

Product identification (1)

Pin 1 identifier

Revision code

Date code

STM32G070

RBT6

YWW

Package information STM32G070CB/KB/RB

84/93 DS12766 Rev 2

6.2 LQFP48 package information

LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.

Figure 28. LQFP48 package outline

1. Drawing is not to scale.

Table 66. LQFP48 mechanical data

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 - 0.200 0.0035 - 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 - 5.500 - - 0.2165 -

5B_ME_V2

PIN 1

IDENTIFICATION

ccc C

0.25 mm

GAUGE PLANE

SEATING

PLANE

DS12766 Rev 2 85/93

STM32G070CB/KB/RB Package information

Figure 29. Recommended footprint for LQFP48 package

1. Dimensions are expressed in millimeters.

E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 - 5.500 - - 0.2165 -

e - 0.500 - - 0.0197 -

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

k 0°3.5°7° 0°3.5°7°

ccc - - 0.080 - - 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 66. LQFP48 mechanical data (continued)

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

9.70 5.80 7.30

0.20

7.30

1.20

5.80

9.70

0.30

1.20

0.50

ai14911d

1348

Package information STM32G070CB/KB/RB

86/93 DS12766 Rev 2

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 30. LQFP48 package marking example

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

STM32G070

MSv42185V1

CBT6

YWW

Product identification (1)

Revision code

Date code

Pin 1 identifier

DS12766 Rev 2 87/93

STM32G070CB/KB/RB Package information

6.3 LQFP32 package information

LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.

Figure 31. LQFP32 package outline

1. Drawing is not to scale.

Table 67. LQFP32 mechanical data

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

GAUGE PLANE

0.25 mm

SEATING

PLANE

PIN 1

IDENTIFICATION

ccc C

5V_ME_V2

Package information STM32G070CB/KB/RB

88/93 DS12766 Rev 2

Figure 32. Recommended footprint for LQFP32 package

1. Dimensions are expressed in millimeters.

b 0.300 0.370 0.450 0.0118 0.0146 0.0177

c 0.090 - 0.200 0.0035 - 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 - 5.600 - - 0.2205 -

E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 - 5.600 - - 0.2205 -

e - 0.800 - - 0.0315 -

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

k 0°3.5°7° 0°3.5°7°

ccc - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 67. LQFP32 mechanical data (continued)

Symbol

millimeters inches(1)

Min Typ Max Min Typ Max

5V_FP_V2

9.70

7.30

1.20

0.30

0.50

1.20

6.10

9.70

0.80

6.10

DS12766 Rev 2 89/93

STM32G070CB/KB/RB Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 33. LQFP32 package marking example

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

STM32

MSv42186V2

G070KBT6

Product identification (1)

Revision code

Pin 1 identifier

YWW

Date code

STM32G070CB/KB/RB

90/93 DS12766 Rev 2

6.4 Thermal characteristics

The operating junction temperature TJ must never exceed the maximum given in

The maximum junction temperature in °C that the device can reach if respecting the

operating conditions, is:

TJ(max) = TA(max) + PD(max) x ΘJA

where:

TA(max) is the maximum operating ambient temperature in °C,

ΘJA is the package junction-to-ambient thermal resistance, in °C/W,

PD = PINT + PI/O,

–P

INT is power dissipation contribution from product of IDD and VDD

–P

I/O is power dissipation contribution from output ports where:

PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH),

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high

level in the application.

6.4.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (still air). Available from www.jedec.org.

Table 20: General operating conditions.

Table 68. Package thermal characteristics

Symbol Parameter Package Value Unit

ΘJA

Thermal resistance

junction-ambient

LQFP64 10 × 10 mm 65

°C/WLQFP48 7 × 7 mm 75

LQFP32 7 × 7 mm 76

DS12766 Rev 2 91/93

STM32G070CB/KB/RB Ordering information

7 Ordering information

For a list of available options (memory, package, and so on) or for further information on any

aspect of this device, please contact your nearest ST sales office.

Example STM32 G 070 K B T 6 xyy

Device family

STM32 = Arm® based 32-bit microcontroller

Product type

G = general-purpose

Device subfamily

070 = STM32G070

Pin count

K = 32

C = 48

R = 64

Flash memory size

B = 128 Kbytes

Package type

T = LQFP

Temperature range

6 = -40 to 85°C (105°C junction)

Options

˽TR = tape and reel packing

˽˽˽ = tray packing

other = 3-character ID incl. custom Flash code and packing information

Revision history STM32G070CB/KB/RB
92/93 DS12766 Rev 2
8  Revision history
          
          
Table 69. Document revision history 
Date Revision Changes
28-Nov-2018 1 Initial release.
11-Mar-2020 2
Cover page updated;
Section 2: Description updated;
Section 3.7.1: Power supply schemes: corrected 
minimum VDD and VDDA values;
Section 3.14.1: Temperature sensor: “engineering 
bytes” replaced “System memory”;
Section 3.17: Inter-integrated circuit interface (I2C): 
SMBus and PMBus feature points;
Section 3.18: Universal synchronous/asynchronous 
receiver transmitter (USART): max. speed corrected;
Table 11: Note 3 inserted and note 4 modified;
Table 17 updated;
Table 18: Note 2 removed;
Table 20: Redefined VIN;
Table 27 Typical current consumption in Run and Low-
power run modes removed;
depending on code executed
Table 45: LU class modified from “II” to “II Level A”;
Table 48: I/O current condition for relaxed VOL/VOH 
corrected from 18 mA to 15 mA; section Output driving 
current corrected accordingly;
Table 52: major update;
Section 3.12: DMA request multiplexer (DMAMUX) 
added;
Figures with package marking examples corrected.

DS12766 Rev 2 93/93

STM32G070CB/KB/RB

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