0.1 1 10 1k 10k
FREQUENCY (Hz)
1
10
100
100
VOLTAGE NOISE (nV/
Hz)
VS = 2.5V, 3.3V, 5V
VCM = 0.5V
VCM = 2.5V
0.1 1 10 1k 10k
FREQUENCY (Hz)
1
10
100
100
CURRENT NOISE (pA/
Hz)
VS = 2.5V, 3.3V, 5V
VCM = 0.5V
VCM = 2.5V
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
2.9 nV/sqrt(Hz) Low Noise, Precision, RRIO Amplifier
Check for Samples: LMP7731
1FEATURES DESCRIPTION
The LMP7731 is a single, low noise, rail-to-rail input
23(Typical Values, TA= 25°C, VS= 5V) and output, low voltage amplifier. The LMP7731 is
• Input Voltage Noise part of the LMP™ precision amplifier family and is
– f = 3 Hz 3.3 nV/√Hz ideal for precision and low noise applications with low
voltage requirements.
– f = 1 kHz 2.9 nV/√Hz
• CMRR 130 dB This operational amplifier offers low voltage noise of
2.9 nV/√Hz with a 1/f corner of only 3 Hz. The
• Open Loop Gain 130 dB LMP7731 has bipolar input stages with a bias current
• GBW 22 MHz of only 1.5 nA. This low input bias current,
• Slew Rate 2.4 V/µs complemented by the very low level of voltage noise,
makes the LMP7731 an excellent choice for
• THD @ f = 10 kHz, AV= +1, RL=2kΩ0.001% photometry applications.
• Supply Current per Channel 2.2 mA The LMP7731 provides a wide GBW of 22 MHz while
• Supply Voltage Range 1.8V to 5.5V consuming only 2 mA of current. This high gain
• Operating Temperature Range −40°C to 125°C bandwidth along with the high open loop gain of 130
• Input Bias Current ±1.5 nA dB enables accurate signal conditioning in
applications with high closed loop gain requirements.
• RRIO The LMP7731 has a supply voltage range of 1.8V to
APPLICATIONS 5.5V, making it an ideal choice for battery operated
portable applications.
• Gas Analysis Instruments The LMP7731 is offered in the space saving 5-Pin
• Photometric Instrumentation SOT-23 and 8-Pin SOIC packages.
• Medical Instrumentation Typical Performance Characteristics
Input Voltage Noise Input Current Noise
vs. vs.
Frequency Frequency
Figure 1. Figure 2.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2LMP is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
ESD Tolerance (3) Human Body Model Inputs pins only 2000V
All other pins 2000V
Machine Model 200V
Charge Device Model 1000V
VIN Differential ±2V
Supply Voltage (VS= V+– V−) 6.0V
Storage Temperature Range −65°C to 150°C
Junction Temperature (4) +150°C max
Soldering Information Infrared or Convection (20 sec) 235°C
Wave Soldering Lead Temp. (10 sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings (1)
Temperature Range −40°C to 125°C
Supply Voltage (VS= V+– V–) 1.8V to 5.5V
Package Thermal Resistance (θJA) 5-Pin SOT-23 265°C/W
8-Pin SOIC 190°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
2.5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 2.5V, V−= 0V, VCM = V+/2, RL>10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
±500
VCM = 2.0V ±9 ±600
Input Offset Voltage
VOS μV
(4) ±500
VCM = 0.5V ±9 ±600
VCM = 2.0V ±0.5 ±5.5
Input Offset Voltage Temperature
TCVOS μV/°C
Drift VCM = 0.5V ±0.2 ±5.5
±30
VCM = 2.0V ±1 ±45
IBInput Bias Current nA
±50
VCM = 0.5V ±12 ±75
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA. Absolute maximum Ratings indicate junction temperature limits beyond which the
device maybe permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing, statistical analysis or design.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Ambient production test is performed at 25°C with a variance of ±3°C.
2Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
2.5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 2.5V, V−= 0V, VCM = V+/2, RL>10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
±50
VCM = 2.0V ±1 ±75
IOS Input Offset Current nA
±60
VCM = 0.5V ±11 ±80
TCIOS Input Offset Current Drift VCM = 0.5V and VCM = 2.0V 0.0474 nA/°C
0.15V ≤VCM ≤0.7V 101 120
0.23V ≤VCM ≤0.7V 89
CMRR Common Mode Rejection Ratio dB
1.5V ≤VCM ≤2.35V 105 129
1.5V ≤VCM ≤2.27V 99
111
2.5V ≤V+≤5V 129
105
PSRR Power Supply Rejection Ratio dB
1.8V ≤V+≤5.5V 117
CMVR Common Mode Voltage Range Large Signal CMRR ≥80 dB 0 2.5 V
RL= 10 kΩto V+/2 112 130
VOUT = 0.5V to 2.0V 104
AVOL Open Loop Voltage Gain dB
RL= 2 kΩto V+/2 109 119
VOUT = 0.5V to 2.0V 90
50
RL= 10 kΩto V+/2 4 75
Output Voltage Swing High 50
RL= 2 kΩto V+/2 13 75 mV from
VOUT either rail
50
RL= 10 kΩto V+/2 6 75
Output Voltage Swing Low 50
RL= 2 kΩto V+/2 9 75
Sourcing, VOUT = V+/2 22 31
VIN (diff) = 100 mV 12
IOUT Output Current mA
Sinking, VOUT = V+/2 15 44
VIN (diff) = −100 mV 10
2.7
VCM = 2.0V 2.0 3.4
Supply Current
ISmA
(Per Channel) 3.1
VCM = 0.5V 2.3 3.9
AV= +1, CL= 10 pF, RL= 10 kΩto
SR Slew Rate V+/2, 2.4 V/μs
VO= 2 VPP
GBW Gain Bandwidth CL= 20 pF, RL= 10 kΩto V+/2 21 MHz
GMGain Margin CL= 20 pF, RL= 10 kΩto V+/2 14 dB
ΦMPhase Margin CL= 20 pF, RL= 10 kΩto V+/2 60 deg
Differential Mode 38 kΩ
RIN Input Resistance Common Mode 151 MΩ
THD+N Total Harmonic Distortion + Noise AV= 1, f = 1 kHz, Amplitude = 1V 0.002 %
f = 1 kHz, VCM = 2.0V 3
Input Referred Voltage Noise nV/√Hz
Density
enf = 1 kHz, VCM = 0.5V 3
Input Voltage Noise 0.1 Hz to 10 Hz 75 nVPP
f = 1 kHz, VCM = 2.0V 1.1
Input Referred Current Noise
inpA/√Hz
Density f = 1 kHz, VCM = 0.5V 2.3
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMP7731
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
3.3V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3.3V, V−= 0V, VCM = V+/2, RL> 10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
±500
VCM = 2.5V ±6 ±600
Input Offset Voltage
VOS μV
(4) ±500
VCM = 0.5V ±6 ±600
VCM = 2.5V ±0.5 ±5.5
Input Offset Voltage Temperature
TCVOS μV/°C
Drift VCM = 0.5V ±0.2 ±5.5
±30
VCM = 2.5V ±1.5 ±45
IBInput Bias Current nA
±50
VCM = 0.5V ±13 ±77
±50
VCM = 2.5V ±1 ±70
IOS Input Offset Current nA
±60
VCM = 0.5V ±11 ±80
TCIOS Input Offset Current Drift VCM = 0.5V and VCM = 2.5V 0.048 nA/°C
0.15V ≤VCM ≤0.7V 101 120
0.23V ≤VCM ≤0.7V 89
CMRR Common Mode Rejection Ratio dB
1.5V ≤VCM ≤3.15V 105 130
1.5V ≤VCM ≤3.07V 99
111
2.5V ≤V+≤5.0V 129
105
PSRR Power Supply Rejection Ratio dB
1.8V ≤V+≤5.5V 117
CMVR Common Mode Voltage Range Large Signal CMRR ≥80 dB 0 3.3 V
RL= 10 kΩto V+/2 112 130
VOUT = 0.5V to 2.8V 104
AVOL Open Loop Voltage Gain dB
RL= 2 kΩto V+/2 110 119
VOUT = 0.5V to 2.8V 92
50
RL= 10 kΩto V+/2 5 75
Output Voltage Swing High 50
RL= 2 kΩto V+/2 14 75 mV from
VOUT either rail
50
RL= 10 kΩto V+/2 9 75
Output Voltage Swing Low 50
RL= 2 kΩto V+/2 13 75
Sourcing, VOUT = V+/2 28 45
VIN (diff) = 100 mV 22
IOUT Output Current mA
Sinking, VOUT = V+/2 25 48
VIN (diff) = -100 mV 20
2.8
VCM = 2.5V 2.1 3.5
Supply Current
ISmA
(Per Channel) 3.2
VCM = 0.5V 2.4 4.0
AV= +1, CL= 10 pF, RL= 10 kΩto
SR Slew Rate V+/2, 2.4 V/μs
VOUT = 2 VPP
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA. Absolute maximum Ratings indicate junction temperature limits beyond which the
device maybe permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing, statistical analysis or design.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Ambient production test is performed at 25°C with a variance of ±3°C.
4Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
3.3V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 3.3V, V−= 0V, VCM = V+/2, RL> 10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
GBW Gain Bandwidth CL= 20 pF, RL= 10 kΩto V+/2 22 MHz
GMGain Margin CL= 20 pF, RL= 10 kΩto V+/2 14 dB
ΦMPhase Margin CL= 20 pF, RL= 10 kΩto V+/2 62 deg
Differential Mode 38 kΩ
RIN Input Resistance Common Mode 151 MΩ
THD+N Total Harmonic Distortion + Noise AV= 1, f = 1 kHz, Amplitude = 1V, 0.002 %
f = 1 kHz, VCM = 2.5V 2.9
Input Referred Voltage Noise nV/√Hz
Density
enf = 1 kHz, VCM = 0.5V 2.9
Input Voltage Noise 0.1 Hz to 10 Hz 65 nVPP
f = 1 kHz, VCM = 2.5V 1.1
Input Referred Current Noise
inpA/√Hz
Density f = 1 kHz, VCM = 0.5V 2.1
5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−= 0V, VCM = V+/2, RL> 10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
±500
VCM = 4.5V ±6 ±600
Input Offset Voltage
VOS μV
(4) ±500
VCM = 0.5V ±6 ±600
VCM = 4.5V ±0.5 ±5.5
Input Offset Voltage Temperature
TCVOS μV/°C
Drift VCM = 0.5V ±0.2 ±5.5
±30
VCM = 4.5V ±1.5 ±50
IBInput Bias Current nA
±50
VCM = 0.5V ±14 ±85
±50
VCM = 4.5V ±1 ±70
IOS Input Offset Current nA
±65
VCM = 0.5V ±11 ±80
TCIOS Input Offset Current Drift VCM = 0.5V and VCM = 4.5V 0.0482 nA/°C
0.15V ≤VCM ≤0.7V 101 120
0.23V ≤VCM ≤0.7V 89
CMRR Common Mode Rejection Ratio dB
1.5V ≤VCM ≤4.85V 105 130
1.5V ≤VCM ≤4.77V 99
111
2.5V ≤V+≤5V 129
105
PSRR Power Supply Rejection Ratio dB
1.8V ≤V+≤5.5V 117
CMVR Common Mode Voltage Range Large Signal CMRR ≥80 dB 0 5 V
RL= 10 kΩto V+/2 112 130
VOUT = 0.5V to 4.5V 104
AVOL Open Loop Voltage Gain dB
RL= 2 kΩto V+/2 110 119
VOUT = 0.5V to 4.5V 94
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA. Absolute maximum Ratings indicate junction temperature limits beyond which the
device maybe permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing, statistical analysis or design.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Ambient production test is performed at 25°C with a variance of ±3°C.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMP7731
V+
1
2
3
45
6
7
8
N/C
-IN
+IN
V-
OUT
N/C
N/C
+
-
OUT
V-
+IN
V+
-IN
+-
1
2
3
5
4
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= 5V, V−= 0V, VCM = V+/2, RL> 10 kΩto V+/2. Boldface
limits apply at the temperature extremes.
Parameter Test Conditions Min (2) Typ (3) Max (2) Units
50
RL= 10 kΩto V+/2 8 75
Output Voltage Swing High 50
RL= 2 kΩto V+/2 24 75 mV from
VOUT either rail
50
RL= 10 kΩto V+/2 9 75
Output Voltage Swing Low 50
RL= 2 kΩto V+/2 23 75
Sourcing, VOUT = V+/2 33 47
VIN (diff) = 100 mV 27
IOUT Output Current mA
Sinking, VOUT = V+/2 30 49
VIN (diff) = -100 mV 25
3.0
VCM = 4.5V 2.2 3.7
Supply Current
ISmA
(Per Channel) 3.4
VCM = 0.5V 2.5 4.2
AV= +1, CL= 10 pF, RL= 10 kΩto
SR Slew Rate V+/2, 2.4 V/μs
VOUT = 2 VPP
GBW Gain Bandwidth CL= 20 pF, RL= 10 kΩto V+/2 22 MHz
GMGain Margin CL= 20 pF, RL= 10 kΩto V+/2 12 dB
ΦMPhase Margin CL= 20 pF, RL= 10 kΩto V+/2 65 deg
Differential Mode 38 kΩ
RIN Input Resistance Common Mode 151 MΩ
THD+N Total Harmonic Distortion + Noise AV= 1, f = 1 kHz, Amplitude = 1V 0.001 %
f = 1 kHz, VCM = 4.5V 2.9
Input Referred Voltage Noise nV/√Hz
Density
enf = 1 kHz, VCM = 0.5V 2.9
Input Voltage Noise 0.1 Hz to 10 Hz 78 nVPP
f = 1 kHz, VCM = 4.5V 1.1
Input Referred Current Noise
inpA/√Hz
Density f = 1 kHz, VCM = 0.5V 2.2
Connection Diagrams
Figure 3. 5-Pin SOT-23 Figure 4. 8-Pin SOIC
Top View Top View
6Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
-50 -40 -30 -20 -10 0 10 20 30 40 50
0
2
4
6
8
10
PERCENTAGE (%)
VOS (PV)
VS = 2.5V, 3.3V
VCM = 0.5V
TCVOS (PV/°C)
-1.5 -1 -0.5 0 0.5
0
5
10
15
20
25
PERCENTAGE (%)
VS = 2.5V
VCM = 0.5V
-40°C dTA d25°C
-50 -40 -30 -20 -10 0 10 20 30 40 50
0
2
4
6
8
10
PERCENTAGE (%)
VOS (PV)
VS = 3.3V, 5V
VCM = VS -0.5V
-0.5 0 0.5 1 1.5
0
2
4
6
8
10
12
14
16
PERCENTAGE (%)
TCVOS (PV/°C)
VS = 3.3V, 5V
VCM = VS -0.5V
-40°C dTA d25°C
-50 -40 -30 -20 -10 0 10 20 30 40 50
0
2
4
6
8
10
PERCENTAGE (%)
VOS (PV)
VS = 2.5V
VCM = 2V
-0.5 0 0.5 1 1.5
0
2
4
6
8
10
12
14
16
PERCENTAGE (%)
TCVOS (PV/°C)
VS = 2.5V
VCM = 2V
-40°C dTA d25°C
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
Typical Performance Characteristics
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Offset Voltage Distribution TCVOS Distribution
Figure 5. Figure 6.
Offset Voltage Distribution TCVOS Distribution
Figure 7. Figure 8.
Offset Voltage Distribution TCVOS Distribution
Figure 9. Figure 10.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LMP7731
0
10 1k 100k 10M
FREQUENCY (Hz)
-140
-100
-60
PSRR (dB)
1M10k
100
-20
-40
-80
-120
-PSRR
+PSRR
VS = 2.5V
VS = 3.3V
VS = 5V
VS = 5V
160
100 10k 10M
FREQUENCY (Hz)
0
60
CMRR (dB)
1M
100k
1k
120
100
40
20
80
140 VS = 2.5V, 3.3V, 5V
-40
TEMPERATURE (°C)
-40
-20
0
20
40
60
120100806040200-20
VS = 2.5V, 3.3V, 5V
VCM = VS - 0.5V
VOS (PV)
5 TYPICAL PARTS
-40
TEMPERATURE (°C)
-5
0
5
10
15
20
120100806040200-20
VS = 2.5V, 3.3V, 5V
VCM = 0.5V
VOS (PV)
5 TYPICAL PARTS
TCVOS (PV/°C)
-1.5 -1 -0.5 0 0.5
0
5
10
15
20
25
PERCENTAGE (%)
VS = 3.3V, 5V
VCM = 0.5V
-40°C dTA d125°C
-40 -30 -20 -10 0 10 20 30 40
VOS (PV)
0
2
4
6
8
10
12
14
PERCENTAGE (%)
VS = 5V
VCM = 0.5V
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Offset Voltage Distribution TCVOS Distribution
Figure 11. Figure 12.
Offset Voltage
vs.
Temperature Offset Voltage vs. Temperature
Figure 13. Figure 14.
CMRR
vs.
PSRR vs. Frequency Frequency
Figure 15. Figure 16.
8Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
050 100 150 200 250 300
TIME (s)
0
0.2
0.4
0.6
0.8
1
OFFSET VOLTAGE DRIFT (PV)
VS = 5V
RL = 2 k:
1.5 2 2.5 3 3.5 4 4.5 5 5.5
2
3.4
SLEW RATE (V/Ps)
SUPPLY VOLTAGE (V)
2.2
2.4
2.6
2.8
3
3.2 RISING EDGE
FALLING EDGE
AV = +1
VIN = 1 VPP
RL = 10 k:
CL = 10 pF
0 0.5 1 1.5 2 2.5 3 3.3
-75
-50
-25
0
25
50
100
VOS (PV)
VCM (V)
75
125°C
85°C
25°C
-40°C
VS = 3.3V
0 1 2 3 4 5
-75
-50
-25
0
25
50
75
100
VOS (PV)
VCM (V)
125°C
85°C
25°C
-40°C
VS = 5V
0 0.5 1 1.5 2 2.5
-75
-50
-25
0
25
50
75
100
VOS (PV)
VCM (V)
125°C
85°C
25°C
-40°C
VS = 2.5V
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
-25
-20
-15
-10
-5
0
5
OFFSET VOLTAGE (PV)
25°C
-40°C
125°C
85°C
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Offset Voltage Offset Voltage
vs. vs.
Supply Voltage VCM
Figure 17. Figure 18.
Offset Voltage Offset Voltage
vs. vs.
VCM VCM
Figure 19. Figure 20.
Slew Rate
vs.
Input Offset Voltage Time Drift Supply Voltage
Figure 21. Figure 22.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LMP7731
0 0.5 1 1.5 2 2.5
-100
-80
-60
-40
-20
0
20
40
60
80
100
INPUT BIAS CURRENT (nA)
VCM (V)
VS = 2.5V
85°C
125°C
25°C
-40°C
0 0.5 1 1.5 2 2.5 3 3.5
-100
-80
-60
-40
-20
0
20
40
60
80
100
INPUT BIAS CURRENT (nA)
VCM (V)
125°C
85°C
25°C
VS = 3.3V
-40°C
0 5 10 15 20 25 30
-800
-600
-400
-200
0
200
400
600
800
1000
VOUT FROM RAIL (mV)
OUTPUT CURRENT (mA)
SOURCE
SINK
VS = 2.5V
VS = 2.5V, 3.3V, 5V
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Time Domain Voltage Noise Time Domain Voltage Noise
Figure 23. Figure 24.
Output Voltage
vs.
Time Domain Voltage Noise Output Current
Figure 25. Figure 26.
Input Bias Current Input Bias Current
vs. vs.
VCM VCM
Figure 27. Figure 28.
10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
VOUT (VPP)
0.1 1 10
0.0001
0.001
0.01
0.1
1
THD+N (%)
VS = 2.5V
VS = 3.3V
VS = 5V
RL = 100 k:
CL = 10 pF
f = 1 kHz
10 100 1k 10k 100k
FREQUENCY (Hz)
0.0001
0.001
0.01
0.1
1
THD+N (%)
VS = 5V
VS = 3.3V
VS = 2.5V
RL = 100 k:
CL = 10 pF
VO = VS -1V
1k 100k 100M
FREQUENCY (Hz)
-40
0
40
100
GAIN (dB)
10M
1M
10k
80
20
-20
60
-90
0
90
225
180
45
-45
135
PHASE (°)
GAIN
PHASE
VS = 2.5V, CL = 100 pF,
RL = 10 k:
VS = 5V, CL = 20 pF,
RL = 2 k:
VS = 2.5V, 3.3V, 5V
CL = 20 pF, 50 pF, 100 pF
RL = 2 k:, 10 k:
1k 100k 100M
-40
0
40
100
GAIN (dB)
10M
1M
10k
80
20
-20
60
FREQUENCY (Hz)
VS = 5V
RL = 10 k:
CL = 20 pF
GAIN
PHASE
-90
0
90
225
180
45
-45
135
PHASE (°)
-40°C
25°C
85°C
125°C
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
-100
-80
-60
-40
-20
0
20
40
60
80
100
INPUT BIAS CURRENT (nA)
VCM (V)
VS = 5V
25°C
85°C
125°C
-40°C
1k 100k 100M
FREQUENCY (Hz)
-40
0
40
100
GAIN (dB)
10M
1M
10k
80
20
-20
60
-90
0
90
225
180
45
-45
135
PHASE (°)
GAIN
PHASE
VS = 2.5V, TA = 25°C
VS = 5V, TA = -40°C
VS = 2.5V, 3.3V, 5V
RL = 10 k:
TA = -40°C, 25°C, 85°C, 125°C
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Input Bias Current
vs.
VCM Open Loop Frequency Response Over Temperature
Figure 29. Figure 30.
Open Loop Frequency Response Open Loop Frequency Response
Figure 31. Figure 32.
THD+N THD+N
vs. vs.
Frequency Output Voltage
Figure 33. Figure 34.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LMP7731
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
0
5
10
15
20
25
30
35
40
VOUT FROM RAIL (mV)
125°C
85°C
25°C
-40°C
RL = 2 k:
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
1.5
2
2.5
3
3.5
SUPPLY CURRENT (mA)
125°C
85°C
25°C -40°C
1 V/DIV
10 Ps/DIV
VS = 5V
VIN = 400 mVPP
f = 10 kHz
AV = +10
RL = 10 k:
CL = 10 pF
200 mV/DIV
10 Ps/DIV
VS = 5V
VIN = 100 mVPP
f = 10 kHz
AV = +10
RL = 10 k:
CL = 10 pF
20 mV/DIV
10 Ps/DIV
VS = 5V
VIN = 100 mVPP
f = 10 kHz
AV = +1
RL = 10 k:
CL = 10 pF
500 mV/DIV
10 Ps/DIV
VS = 5V
VIN = 2 VPP
f = 10 kHz
AV = +1
RL = 10 k:
CL = 10 pF
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Large Signal Step Response Small Signal Step Response
Figure 35. Figure 36.
Large Signal Step Response Small Signal Step Response
Figure 37. Figure 38.
Supply Current Output Swing High
vs. vs.
Supply Voltage Supply Voltage
Figure 39. Figure 40.
12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
10
20
30
40
50
60
ISOURCE (mA)
25°C
85°C
125°C
-40°C
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
0
5
10
15
20
25
30
35
40
VOUT FROM RAIL (mV)
125°C
85°C
25°C -40°C
RL = 2 k:
1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
10
20
30
40
50
60
ISINK (mA)
25°C
85°C 125°C
-40°C
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise noted: TA= 25°C, RL> 10 kΩ, VCM = VS/2.
Output Swing Low
vs.
Supply Voltage Sinking Current vs, Supply Voltage
Figure 41. Figure 42.
Sourcing Current
vs.
Supply Voltage
Figure 43.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMP7731
V+
R1
R2
IN+
IN-
I1
INPUT STAGE
IBIAS CANCELLATION CIRCUIT
Q1 Q2
V+
RC1RC2
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
APPLICATION INFORMATION
LMP7731
The LMP7731 is a single, low noise, rail-to-rail input and output, and low voltage amplifier.
The low input voltage noise of only 2.9 nV/√Hz with a 1/f corner at 3 Hz makes the LMP7731 ideal for sensor
applications where DC accuracy is of importance.
The LMP7731 has a high gain bandwidth of 22 MHz. This wide bandwidth enables use of the amplifier at higher
gain settings while retaining usable bandwidth for the application. This is particularly beneficial when system
designers need to use sensors with very limited output voltage range as it allows larger gains in one stage which
in turn increases the signal to noise ratio.
The LMP7731 has proprietary input bias cancellation circuitry on the input stages. This allows the LMP7731 to
have only about 1.5 nA bias current with a bipolar input stage. This low input bias current, paired with the
inherent lower input voltage noise of bipolar input stages makes the LMP7731 an excellent choice for precision
applications. The combination of low input bias current, and low input voltage noise enables the user to achieve
unprecedented accuracy and higher signal integrity.
Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical
support and extensive characterization data are available for sensitive applications or applications with a
constrained error budget.
The LMP7731 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC packages. These small packages are
ideal solutions for area constrained PC boards and portable electronics.
INPUT BIAS CURRENT CANCELLATION
The LMP7731 has proprietary input bias current cancellation circuitry on their input stages.
The LMP7731 has rail-to-rail input. This is achieved by having two input stages in parallel. Figure 44 shows only
one of the input stages as the circuitry is symmetrical for both stages.
Figure 44 shows that as the common mode voltage gets closer to one of the extreme ends, current I1
significantly increases. This increased current shows as an increase in voltage drop across resistor R1equal to
I1*R1on IN+of the amplifier. This voltage contributes to the offset voltage of the amplifier. When common mode
voltage is in the mid-range, the transistors are operating in the linear region and I1is significantly small. The
voltage drop due to I1across R1can be ignored as it is orders of magnitude smaller than the amplifier's input
offset voltage.
As the common mode voltage gets closer to one of the rails, the offset voltage generated due to I1increases and
becomes comparable to the amplifiers offset voltage.
Figure 44. Input Bias Current Cancellation
14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
-
+
LMP7731
-
+
LMP7731
0.1 PF
100 k:
10:
2 k:
4.7 PF
24.3 k:
100 k:
0.1 PF
4.3 k:
2.2 PF
22 PF
110 k:
SCOPE
x 1
RIN = 1M
VOLTAGE GAIN = 50,000
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
INPUT VOLTAGE NOISE MEASUREMENT
The LMP7731 has very low input voltage noise. The peak-to-peak input voltage noise of the LMP7731 can be
measured using the test circuit shown in Figure 45
Figure 45. 0.1 Hz to 10 Hz Noise Test Circuit
The frequency response of this noise test circuit at the 0.1 Hz corner is defined by only one zero. The test time
for the 0.1 Hz to 10 Hz noise measurement using this configuration should not exceed 10 seconds, as this time
limit acts as an additional zero to reduce or eliminate the noise contributions of noise from frequencies below 0.1
Hz.
Figure 46 shows typical peak-to-peak noise for the LMP7731 measured with the circuit in Figure 45 for the
LMP7731.
Figure 46. 0.1 Hz to 10 Hz Input Voltage Noise
Measuring the very low peak-to-peak noise performance of the LMP7731, requires special testing attention. In
order to achieve accurate results, the device should be warmed up for at least five minutes. This is so that the
input offset voltage of the op amp settles to a value. During this warm up period, the offset can typically change
by a few µV because the chip temperature increases by about 30°C. If the 10 seconds of the measurement is
selected to include this warm up time, some of this temperature change might show up as the measured noise.
Figure 47 shows the start-up drift of five typical LMP7731 units.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMP7731
ESD R1
IN+
ESD
R2ESD
IN-
ESD
V+
V-V-
V+
050 100 150 200 250 300
TIME (s)
0
0.2
0.4
0.6
0.8
1
OFFSET VOLTAGE DRIFT (PV)
VS = 5V
RL = 2 k:
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
Figure 47. Start-Up Input Offset Voltage Drift
During the peak-to-peak noise measurement, the LMP7731 must be shielded. This prevents offset variations due
to airflow. Offset can vary by a few nV due to this airflow and that can invalidate measurements of input voltage
noise with a magnitude which is in the same range. For similar reasons, sudden motions must also be restricted
in the vicinity of the test area. The feed-through which results from this motion could increase the observed noise
value which in turn would invalidate the measurement.
DIODES BETWEEN THE INPUTS
The LMP7731 has a set of anti-parallel diodes between the input pins as shown in Figure 48. These diodes are
present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input
voltage that is allowed on the input pins. A differential signal larger than the voltage needed to turn on the diodes
might cause damage to the diodes. The differential voltage between the input pins should be limited to ±3 diode
drops or the input current needs to be limited to ±20 mA.
Figure 48. Anti-Parallel Diodes between Inputs
DRIVING AN ADC
Analog to Digital Converters, ADCs, usually have a sampling capacitor on their input. When the ADC's input is
directly connected to the output of the amplifier a charging current flows from the amplifier to the ADC. This
charging current causes a momentary glitch that can take some time to settle. There are different ways to
minimize this effect. One way is to slow down the sampling rate. This method gives the amplifier sufficient time to
stabilize its output. Another way to minimize the glitch caused by the switch capacitor is to have an external
capacitor connected to the input of the ADC. This capacitor is chosen so that its value is much larger than the
internal switching capacitor and it will hence provide the voltage needed to quickly and smoothly charge the
16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
ADC
SENSOR INPUT
NETWORK
FEEDBACK
NETWORK
V-
V+
SENSOR INPUT
NETWORK
FEEDBACK
NETWORK
V-
ADC
(a)
(b)
RISO
C
V+
LMP7731
www.ti.com
SNOSAT6E –JULY 2007–REVISED MARCH 2013
ADC's sampling capacitor. Since this large capacitor will be loading the output of the amplifier as well, an
isolation resistor is needed between the output of the amplifier and this capacitor. The isolation resistor, RISO,
separates the additional load capacitance from the output of the amplifier and will also form a low-pass filter and
can be designed to provide noise reduction as well as anti-aliasing. The drawback to having RISO is that it
reduces signal swing since there is some voltage drop across it.
Figure 49 (a) shows the ADC directly connected to the amplifier. To minimize the glitch in this setting, a slower
sample rate needs to be used. Figure 49 (b) shows RISO and an external capacitor used to minimize the glitch.
Figure 49. Driving an ADC
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMP7731
LMP7731
SNOSAT6E –JULY 2007–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 17
18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMP7731
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LMP7731MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP77
31MA
LMP7731MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM LMP77
31MA
LMP7731MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AY3A
LMP7731MFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AY3A
LMP7731MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AY3A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMP7731MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMP7731MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP7731MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMP7731MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMP7731MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMP7731MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMP7731MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0
LMP7731MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
