NXP Semiconductors Data Sheet: Product Preview Document Number S32K1XX Rev. 4, 06/2017 S32K1XX S32K1xx Data Sheet Caution * S32K148, S32K142, S32K146, and S32K116 specific information is preliminary until these devices are qualified. Key Features * Operating characteristics - Voltage range: 2.7 V to 5.5 V - Ambient temperature range: -40 C to 105 C for HSRUN, -40 C to 125 C for RUN * ARMTM Cortex-M4F/M0+ core, 32-bit CPU - Supports up to 112 MHz frequency (HSRUN) with 1.25 Dhrystone MIPS per MHz - ARM Core based on the ARMv7 Architecture and Thumb(R)-2 ISA - Integrated Digital Signal Processor (DSP) - Configurable Nested Vectored Interrupt Controller (NVIC) - Single Precision Floating Point Unit (FPU) * Clock interfaces - 4 - 40 MHz fast external oscillator (SOSC) - 48 MHz Fast Internal RC oscillator (FIRC) - 8 MHz Slow Internal RC oscillator (SIRC) - 128 kHz Low Power Oscillator (LPO) - Up to 112 MHz (HSRUN) System Phased Lock Loop (SPLL) - Up to 50 MHz DC external square wave input clock - Real Time Counter (RTC) * Power management - Low-power ARM Cortex-M4F/M0+ core with excellent energy efficiency - Power Management Controller (PMC) with multiple power modes: HSRUN, Run, Stop, VLPR, and VLPS - Supports peripheral specific clock gating. Only specific peripherals remain working in low power modes. * Memory and memory interfaces - Up to 2 MB program flash memory with ECC - 64 KB FlexNVM for data flash memory with ECC and EEPROM emulation - Up to 256 KB SRAM with ECC - Up to 4 KB of FlexRAM for use as SRAM or EEPROM emulation - Up to 4 KB Code cache to minimize performance impact of memory access latencies - QuadSPI with HyperBusTM support * Mixed-signal analog - Up to two 12-bit Analog-to-Digital Converter (ADC) with up to 32 channel analog inputs per module - One Analog Comparator (CMP) with internal 8-bit Digital to Analog Converter (DAC) * Debug functionality - Serial Wire JTAG Debug Port (SWJ-DP) combines - Debug Watchpoint and Trace (DWT) - Instrumentation Trace Macrocell (ITM) - Test Port Interface Unit (TPIU) - Flash Patch and Breakpoint (FPB) Unit * Human-machine interface (HMI) - Up to 156 GPIO pins with interrupt functionality - Non-Maskable Interrupt (NMI) * Communications interfaces - Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART) modules with DMA support and low power availability - Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability - Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability - Up to three FlexCAN modules (with optional CANFD support) - FlexIO module for flexible and high performance serial interfaces This document contains information on a product under development. NXP reserves the right to change or discontinue this product without notice. Preliminary * Reliability, safety and security - HW Security Engine (CSEc) - Internal watchdog (WDOG) - External Watchdog monitor (EWM) module - Error-Correcting Code (ECC) on flash and SRAM memories - Cyclic Redundancy Check (CRC) module - 128-bit Unique Identification (ID) number - System Memory Protection Unit (System MPU) * Timing and control - Up eight independent 16-bit FlexTimers (FTM) module, offering up to 64 standard channels (IC/OC/PWM) - One 16-bit Low Power Timer (LPTMR) with flexible wake up control - Two Programmable Delay Blocks (PDB) with flexible trigger system - One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels - 32-bit Real Time Counter (RTC) * I/O and package - 32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, MAPBGA-100, 144-pin LQFP, 176-pin LQFP package options * 16 channel DMA with up to 63 request sources using DMAMUX S32K1xx Data Sheet, Rev. 4, 06/2017 2 Preliminary NXP Semiconductors Table of Contents 1 Block diagram.................................................................................... 4 2 Feature comparison............................................................................ 5 3 Ordering parts.....................................................................................7 4 6.2.5 6.3 Memory and memory interfaces................................................27 6.3.1 specifications................................................................27 3.2 Ordering information ................................................................ 8 6.3.1.1 General............................................................................................... 9 Flash timing specifications -- commands................................................ 27 6.3.1.2 4.2 Voltage and current operating requirements..............................10 6.3.2 4.3 Thermal operating characteristics..............................................11 Reliability specifications..........................29 QuadSPI AC specifications..........................................30 6.4 Analog modules......................................................................... 34 4.4 Power and ground pins.............................................................. 12 6.4.1 ADC electrical specifications...................................... 34 4.5 LVR, LVD and POR operating requirements............................13 6.4.1.1 12-bit ADC operating conditions............. 34 4.6 Power mode transition operating behaviors.............................. 14 6.4.1.2 12-bit ADC electrical characteristics....... 36 4.7 Power consumption................................................................... 15 4.7.1 6.4.2 Modes configuration.................................................... 18 CMP with 8-bit DAC electrical specifications............ 37 6.5 Communication modules........................................................... 41 4.8 ESD handling ratings.................................................................18 6.5.1 LPUART electrical specifications............................... 41 4.9 EMC radiated emissions operating behaviors........................... 18 6.5.2 LPSPI electrical specifications.................................... 41 I/O parameters....................................................................................18 6.5.3 LPI2C electrical specifications.................................... 48 5.1 AC electrical characteristics...................................................... 18 6.5.4 FlexCAN electical specifications.................................49 5.2 General AC specifications......................................................... 19 6.5.5 SAI electrical specifications........................................ 49 5.3 DC electrical specifications at 3.3 V Range.............................. 19 6.5.6 Ethernet AC specifications.......................................... 51 5.4 DC electrical specifications at 5.0 V Range.............................. 20 6.5.7 Clockout frequency......................................................54 5.5 AC electrical specifications at 3.3 V range .............................. 21 6 Flash memory module (FTFC) electrical 3.1 Determining valid orderable parts ............................................ 7 4.1 Absolute maximum ratings........................................................9 5 SPLL electrical specifications .....................................27 6.6 Debug modules.......................................................................... 54 5.6 AC electrical specifications at 5 V range ................................. 22 6.6.1 SWD electrical specofications .................................... 54 5.7 Standard input pin capacitance.................................................. 22 6.6.2 Trace electrical specifications......................................56 5.8 Device clock specifications....................................................... 22 6.6.3 JTAG electrical specifications..................................... 57 Peripheral operating requirements and behaviors.............................. 23 7 Thermal attributes.............................................................................. 60 6.1 System modules......................................................................... 23 7.1 Description.................................................................................60 6.2 Clock interface modules............................................................ 23 7.2 Thermal characteristics..............................................................60 6.2.1 External System Oscillator electrical specifications....23 6.2.2 External System Oscillator frequency specifications . 25 6.2.3 System Clock Generation (SCG) specifications.......... 26 6.2.3.1 8 Dimensions.........................................................................................65 8.1 Obtaining package dimensions ................................................. 65 Slow internal RC oscillator (SIRC) 9 Pinouts................................................................................................66 9.1 Package pinouts and signal descriptions....................................66 electrical specifications ........................... 26 6.2.4 temperature................................................................................ 64 Fast internal RC Oscillator (FIRC) electrical specifications............................ 26 6.2.3.2 7.3 General notes for specifications at maximum junction 10 Revision History.................................................................................66 Low Power Oscillator (LPO) electrical specifications ......................................................................................27 S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 3 Block diagram 1 Block diagram Following figures show superset high level architecture block diagrams of S32K14x series and S32K11x series respectively. Other devices within the family have a subset of the features. See Feature comparison for chip specific values. Async Trace port JTAG & Serial Wire ARM Cortex M4F Core MCM TPIU PPB SWJ-DP NVIC AWIC ITM AHB-AP FPU FPB DSP DWT Clock generation System ICODE DCODE DMA MUX LMEM Main SRAM2 Upper region EIM LMEM controller Lower region System MPU1 Mux LPO 128 kHz eDMA FIRC 48 MHz SIRC 8 MHz SOSC 4-40 MHz 8-40 MHz SPLL TCD 512B Code Cache ENET S1 System MPU1 M3 M2 M1 M0 S2 Crossbar switch (AXBS-Lite) S3 S0 System MPU1 Mux System MPU1 QuadSPI GPIO Flash memory controller Peripheral bus controller WDOG ERM LPI2C 12-bit ADC EWM CMP 8-bit DAC LPUART CRC TRGMUX LPSPI FlexIO Low Power Timer FlexCAN FlexTimer PDB RTC LPIT FlexRAM/ SRAM LPIT QSPI Code flash memory CSEc SAI 1: On this device, NXP's system MPU implements the safety mechanisms to prevent masters from accessing restricted memory regions. This system MPU provides memory protection at the level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned different access rights to each protected memory region. The ARM M4 core version in this family does not integrate the ARM Core MPU, which would concurrently monitor only core-initiated memory accesses. In this document, the term MPU refers to NXP's system MPU. 2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces" chapter of the S32K14x Series Reference Manual. Data flash memory Device architectural IP on all S32K devices Key: Peripherals present on all S32K devices Peripherals present on selected S32K devices (see the "Feature Comparison" section in the RM) Figure 1. High-level architecture diagram for the S32K14x family S32K1xx Data Sheet, Rev. 4, 06/2017 4 Preliminary NXP Semiconductors Feature comparison IO PORT ARM Cortex M0+ Clock generation IO PORT Serial Wire SW-DP NVIC AHB-AP SIRC 8 MHz LPO 128 kHz AWIC SOSC FIRC 48 MHz 4-40 MHz DMA MUX Unified Bus PPB BPU MTB+DWT eDMA AHBLite AHBLite M2 M0 Crossbar switch (AXBS-Lite) S0 S2 S1 System MPU1 System MPU1 EIM Flash memory controller SRAM2 FlexRAM/ SRAM2 Code flash memory Peripheral bus controller Data flash memory WDOG ERM LPI2C 12-bit ADC FlexIO Low Power Timer LPIT CSEc CMP 8-bit DAC CMU CRC LPUART TRGMUX FlexCAN LPSPI 1: On this device, NXP's system MPU implements the safety mechanisms to prevent masters from accessing restricted memory regions. This system MPU provides memory protection at the level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned different access rights to each protected memory region. The ARM M0+ core version in this family does not integrate the ARM Core MPU, which would concurrently monitor only core-initiated memory accesses. In this document, the term MPU refers to NXP's system MPU. 2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces" chapter of the S32K1xx Series Reference Manual. PDB FlexTimer GPIO RTC LPIT Device architectural IP on all S32K devices Key: Peripherals present on all S32K devices Peripherals present on selected S32K devices (see the "Feature Comparison" section in the RM) Figure 2. High-level architecture diagram for the S32K11x family 2 Feature comparison The following figure summarizes the memory and package options for the S32K product series and demonstrates where this device fits within the overall series. All devices which share a common package are pin-to-pin compatible. S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 5 Feature comparison S32K14x S32K11x K116 Parameter K118 K142 K146 K144 ARM(R) CortexTM-M0+ Core 48 MHz Frequency K148 ARM(R) CortexTM-M4F up to 112 MHz (HSRUN) IEEE-754 FPU HW security module (CSEc)1 1x 1x capable up to ASIL-B capable up to ASIL-B up to 48 MHz up to 112 MHz (HSRUN) 1x 1x CRC module ISO 26262 Peripheral speed System Crossbar DMA EWM Memory protection unit FIRC CMU Watchdog Low power modes HSRUN mode up to 58 up to 43 Number of I/Os up to 89 up to 128 2.7 - 5.5 V Single supply voltage up to 156 2.7 - 5.5 V Operating temperature (Ta) Temperature ambient -40 to +85C / +105C / +125C Flash 128 KB -40 to +85C / +105C / +125C 256 KB 256 KB 512 KB 25 KB 32 KB 64 KB 1 MB 2 MB2 128 KB 256 KB Error correction code (ECC) Memory System RAM (including FlexRAM and MTB) 17 KB FlexRAM (also available as system RAM) 2 KB 4 KB 4 KB Cache 4 KB (up to 512 KB D-Flash as a part of 2 MB Flash)3 4 KB (up to 64 KB D-Flash) 2 KB (up to 32 KB D-Flash) EEPROM emulated by FlexRAM1 QuadSPI incl. HyperBusTM External memory interface Analog Timer Low power interrupt timer 1x 1x 2x (16) FlexTimer (16-bit counter) 8 channels 4x (32) 1x 1x Real time counter (RTC) 1x 1x Programmable delay block (PDB) 1x Low power timer (LPTMR) 6x (48) 8x (64) 2x Trigger mux (TRGMUX) 1x (43) 1x (45) 1x (64) 1x (73) 1x (81) 12-bit SAR ADC (1 MSPS each) 1x (14) 1x (16) 2x (16) 2x (24) 2x (32) Comparator with 8-bit DAC 1x 1x 1x Communication 100 Mbit IEEE-1588 ethernet MAC 2x Serial audio interface (AC97, TDM, I2S) Low power UART/LIN 2x (Supports LIN protocol versions 1.3, 2.0, 2.1, and SAE J2602) 1x Low power SPI Other IDEs FlexIO (8 pins configurable as UART, SPI, I2C, I2S) Packages 2x 3x 1x 1x (1x with FD) FlexCAN (CAN-FD ISO/CD 11898-1) Ecosystem (IDE, compiler, debugger) 2x 3x 1x Low power I2C Debug & trace 2x 2x (1x with FD) 1x 3x (2x with FD) 3x (3x with FD) 1x SWD, MTB (1 KB), JTAG4 NXP S32 Design Studio (GCC) + SDK, IAR, GHS, COSMIC, Lauterbach, iSystems QFN-32 LQFP-48 2x 3x (1x with FD) LQFP-48 LQFP-64 SWD, JTAG (ITM, SWV, SWO) SWD, JTAG (ITM, SWV, SWO), ETM NXP S32 Design Studio (GCC) + SDK, IAR, GHS, COSMIC, Lauterbach, iSystems LQFP-64 MAPBGA-100 LQFP-64 MAPBGA-100 LQFP-64 LQFP-144 LQFP-100 LQFP-100 LQFP-100 LQFP-176 MAPBGA-100 LQFP-144 LEGEND: Not implemented Available on the device 1 No FTFC commands, including CSE commands (CSEc parts) are available when chip is in VLPR or HSRUN mode. 2 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash. 3 Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details. 4 Only for BSR Figure 3. S32K1xx product series comparison S32K1xx Data Sheet, Rev. 4, 06/2017 6 Preliminary NXP Semiconductors Ordering parts 3 Ordering parts 3.1 Determining valid orderable parts To determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search. Additionally see the attachment S32K_Part_Numbers.xlsx . NOTE Not all part number combinations exist S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 7 Ordering parts 3.2 Ordering information F/P S32 K 1 0 0 X Y F0 M LC R Product status Product type/brand Product line Series/Family (including generation) Core platform/ Performance Memory size Ordering option 1: Letter Ordering option 2: Letter Fab and Mask rev. letter Temperature Package Tape and Reel Product status P: Prototype F: Qualified ordering P/N Product type/brand S32: Automotive 32-bit MCU Product line K: ARM Cortex MCUs M: MagniV/Mixed Signal Series/Family 1: 1st product series 2: 2nd product series Core platform/Performance 1: ARM Cortex M0+ 4: ARM Cortex M4F Memory size 2 4 M0+ 32 K 64 K M4F 256 K 512 K 6 8 128 K 256 K 1M 2M Ordering option X: Speed B: 48 MHz without DMA (only for S32K11x) L: 48 MHz with DMA (only for S32K11x) M: 64 MHz H: 80 MHz U: 112 MHz Y: Optional feature N: No/None R: Max. RAM F: CAN-FD and FlexIO including max. RAM S: Security including max. RAM A: CAN-FD, FlexIO, and Security including max. RAM E: Ethernet and audio including max. RAM J: CAN FD, FlexIO, Security, Ethernet and audio including max. RAM Fab and Mask rev. letter Fx: ATMC Tx: GF XX: Flex # Temperature C: -40C to 85C V: -40C to 105C M: -40C to 125C Package Pins LQFP 32 LC 48 LF LQFP -EP QFN BGA - FM - KF FT - - - LH KH 100 LL - - 144 LQ - - - - - 64 176 LU - MH Tape and Reel T: Trays and Tubes R: Tape and Reel x0: 1st fab revision x1: 2nd fab revision Figure 4. Ordering information S32K1xx Data Sheet, Rev. 4, 06/2017 8 Preliminary NXP Semiconductors General 4 General 4.1 Absolute maximum ratings NOTE Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table for specific conditions. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. All the limits defined in the datasheet specification must be honored together and any volilation to any one or more will not gaurantee desired operation. Table 1. Absolute maximum ratings Symbol 2 Conditions1 Parameter Min Max 3 Unit V VDD 2.7 V - 5. 5V input supply voltage -- -0.3 5.8 VREFH 3.3 V / 5.0 V ADC high reference voltage -- -0.3 5.8 3 V IINJPAD_DC_ABS4 Continuous DC input current (positive / negative) that can be injected into an I/O pin -- -3 +3 mA Continuous DC Voltage on any I/O pin with respect to VSS -- -0.8 5.85 V Sum of absolute value of injected currents on all the pins (Continuous DC limit) -- -- 30 mA VIN_DC IINJSUM_DC_ABS Tramp6 Supply ramp rate -- 0.5 V/min 500 V/ms -- TA7 Ambient temperature -- -40 125 C TSTG Storage temperature -- -55 165 C -- 8 VIN_TRANSIENT Transient overshoot voltage allowed on I/O pin beyond VIN_DC limit -- 6.8 V 1. All voltages are referred to VSS unless otherwise specified. 2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details. 3. 60 s lifetime - No restrictions i.e. The part can switch. 4. 5. 6. 7. 10 hours lifetime - Device in reset i.e. The part cannot switch. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible. While respecting the maximum current injection limit Limit applies to both maximum absolute maximum ramp rate and typical operating conditions. TJ (Junction temperature)=135 C. Assumes TA=125 C for RUN mode S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 9 General TJ (Junction temperature)=125 C. Assumes TA=105 C for HSRUN mode * Assumes maximum JA for 2s2p board. See Thermal characteristics 8. 60 seconds lifetime; device in reset (no outputs enabled/toggling) 4.2 Voltage and current operating requirements NOTE Full functionality/specifications cannot be guaranteed when voltage drops below 2.7 V. Table 2. Voltage and current operating requirements 1 Symbol 2 VDD VDD_OFF VDDA VDD - VDDA Description Min. Max. Unit Notes Supply voltage 2.73 5.5 V 4 0 0.1 V 2.7 5.5 V - 0.1 0.1 V Voltage allowed to be developed on VDD pin when it is not powered from any external power supply source. Analog supply voltage VDD-to-VDDA differential voltage VREFH ADC reference voltage high 2.7 VDDA + 0.1 V VREFL ADC reference voltage low -0.1 0.1 V VODPU Open drain pullup voltage level VDD VDD V IINJPAD_DC_OP7 Continuous DC input current (positive / negative) that can be injected into an I/O pin -3 +3 mA IINJSUM_DC_OP Continuous total DC input current that can be injected across all I/O pins such that there's no degradation in accuracy of analog modules: ADC and ACMP (See section Analog Modules) -- 30 mA 4 5 6 1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 C and typical silicon process unless otherwise stated. 2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details. 3. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes. 4. VDD and VDDA must be shorted to a common source on PCB. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference supply design for SAR ADC. 5. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V 6. Open drain outputs must be pulled to VDD. 7. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible. S32K1xx Data Sheet, Rev. 4, 06/2017 10 Preliminary NXP Semiconductors General 4.3 Thermal operating characteristics Table 3. Thermal operating characteristics for 64 LQFP, 100 LQFP, and 100 MAP-BGA packages. Symbol TA C-Grade Part TJ C-Grade Part TA V-Grade Part TJ V-Grade Part TA M-Grade Part TJ M-Grade Part Parameter Value Ambient temperature under bias Junction temperature under bias Ambient temperature under bias Junction temperature under bias Ambient temperature under bias Junction temperature under bias Unit Min. Typ. Max. -40 -- 851 -- 1051 -- 1051 -- 1251 -- 1252 -- 1352 -40 -40 -40 -40 -40 1. Values mentioned are measured at 112 MHz in HSRUN mode. 2. Values mentioned are measured at 80 MHz in RUN mode. S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 11 General 4.4 Power and ground pins VSS CREF VREFL / VSSA/VSS VDD 100 LQFP Package VREFH VREFL VSS VDD VSSA/VSS VSS VREFH C DEC 64 LQFP Package VDDA C DEC CREF VDD C DEC C DEC VDDA C DEC VDD VDD C DEC VSS VDD C DEC C DEC C DEC VREFL VSSA/VSS VDD VDD C DEC C DEC VSS VDD VSS VSS VSS VSS C DEC 176 LQFP Package VREFH C DEC VSS VDD VSS VDD VDD VDD CDEC VSS VDD VSS VSS VDD VDD CREF VSS DEC VDD C VREFL VSSA/VSS 144 LQFP Package C DEC VSS VDDA C DEC VREFH VDD C DEC VSS CREF DEC C C DEC VSS C DEC VDD VDDA C DEC VDD C DEC C DEC Figure 5. Pinout decoupling Table 4. Supplies decoupling capacitors 1, 2 Symbol Description Min. 3 Typ. Max. Unit CREF, 4, 5 ADC reference high decoupling capacitance 70 100 -- nF CDEC5, 6, 7 Recommended decoupling capacitance 70 100 -- nF 1. VDD and VDDA must be shorted to a common source on PCB. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference supply design for SAR ADC. All VSS pins should be connected to common ground at the PCB level. 2. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type). 3. Minimum recommendation is after considering component aging and tolerance. 4. For improved performance, it is recommended to use 10 F, 0.1 F and 1 nF capacitors in parallel. 5. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins. 6. Contact your local Field Applications Engineer for details on best analog routing practices. 7. The filtering used for decoupling the device supplies must comply with the following best practices rules: * The protection/decoupling capacitors must be on the path of the trace connected to that component. S32K1xx Data Sheet, Rev. 4, 06/2017 12 Preliminary NXP Semiconductors General VREFH VREFL VSSA VDD VDDA * No trace exceeding 1 mm from the protection to the trace or to the ground. * The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm). * The ground of the protection is connected as short as possible to the ground plane under the integrated circuit. VOSC = 3.3 V nominal FIRC SIRC SPLL SOSC ADC CMP VCORE = 1.2 V/1.4 V nominal VFlash = 3.6 V nominal PMC LV SOG GPIO VSS Flash Pads System RAM TCD RAM I/D Cache EEE RAM *Note: VSSA and VSS are shorted at package level Figure 6. Power diagram 4.5 LVR, LVD and POR operating requirements Table 5. VDD supply LVR, LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Rising and falling VDD POR detect voltage 1.1 1.6 2.0 V VLVR LVR falling threshold (RUN, HSRUN, and STOP modes) 2.50 2.58 2.7 V -- 45 -- mV 1.97 2.22 2.44 V VLVR_HYST VLVR_LP LVR hysteresis LVR falling threshold (VLPS/VLPR modes) Notes 1 Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 13 General Table 5. VDD supply LVR, LVD and POR operating requirements (continued) Symbol VLVD VLVD_HYST VLVW VLVW_HYST VBG Description Min. Typ. Max. Unit Falling low-voltage detect threshold 2.8 2.875 3 V LVD hysteresis -- 50 -- mV 4.19 4.305 4.5 V -- 75 -- mV 0.97 1.00 1.03 V Falling low-voltage warning threshold LVW hysteresis Bandgap voltage reference Notes 1 1 1. Rising threshold is the sum of falling threshold and hysteresis voltage. 4.6 Power mode transition operating behaviors All specifications in the following table assume this clock configuration: * RUN Mode: * Clock source: FIRC * SYS_CLK/CORE_CLK = 48 MHz * BUS_CLK = 48 MHz * FLASH_CLK = 24 MHz * HSRUN Mode: * Clock source: SPLL * SYS_CLK/CORE_CLK = 112 MHz * BUS_CLK = 56 MHz * FLASH_CLK = 28 MHz * VLPR Mode: * Clock source: SIRC * SYS_CLK/CORE_CLK = 4 MHz * BUS_CLK = 4 MHz * FLASH_CLK = 1 MHz * STOP1/STOP2 Mode: * Clock source: FIRC * SYS_CLK/CORE_CLK = 48 MHz * BUS_CLK = 48 MHz * FLASH_CLK = 24 MHz * VLPS Mode: All clock sources disabled. Table 6. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 2.7 V to execution of the first instruction across the operating temperature range of the chip. Min. Typ. Max. Unit -- 325 -- s Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 14 Preliminary NXP Semiconductors General Table 6. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit VLPS RUN 8 -- 17 s STOP1 RUN 0.07 0.075 0.08 s STOP2 RUN 0.07 0.075 0.08 s VLPR RUN 19 -- 26 s VLPR VLPS 5.75 6.25 6.5 s VLPS VLPR 26.5 27.25 27.75 s RUN Compute operation 0.35 0.38 0.4 s HSRUN Compute operation 0.3 0.31 0.35 s RUN STOP1 0.35 0.38 0.4 s RUN STOP2 0.2 0.23 0.25 s RUN VLPS 0.35 0.38 0.4 s RUN VLPR 4.4 4.7 5 s VLPS Asynchronous DMA Wakeup 105 110 125 s STOP1 Asynchronous DMA Wakeup 1 1.1 1.3 s STOP2 Asynchronous DMA Wakeup 1 1.1 1.3 s Pin reset Code execution -- 214 -- s NOTE HSRUN should only be used when frequencies in excess of 80 MHz are required. When using 80 MHz and below, RUN mode is the recommended operating mode. 4.7 Power consumption The following table shows the power consumption targets for the device in various mode of operations. S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 15 S32K142 NXP Semiconductors S32K144 Idd/MH z (A/ MHz)5 Peripherals enabled HSRUN@112 MHz (mA) 4 Peripherals disabled Peripherals enabled TBD RUN@80 MHz (mA) Peripherals disabled TBD Peripherals enabled 12 Peripherals disabled 7 RUN@64 MHz (mA) 25 Typ 26 38 105 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD 125 Max TBD TBD TBD TBD TBD TBD TBD 40 TBD 25 Typ 26 38 7 12 TBD TBD 105 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD 125 Max TBD TBD TBD TBD TBD TBD TBD 42 TBD 25 Typ 29 42 10 15 TBD TBD 105 Typ TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD 125 Max TBD TBD TBD TBD TBD 25 Typ 29.8 39.1 1.48 7 1.9 1.9 2.5 RUN@48 MHz (mA) Peripherals enabled STOP2 (mA) Peripherals disabled Peripherals disabled Peripherals enabled Peripherals disabled 6 S32K118 1.9 STOP1 (mA) Peripherals enabled Ambient Temperature (C) S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary S32K116 VLPR (mA) VLPS (A)2, 3 General 16 Table 7. Power consumption (Typicals unless stated otherwise) 1 2.5 2.5 1.50 NA TBD NA TBD TBD TBD TBD TBD TBD 48 57 65 75 TBD TBD TBD TBD TBD 85 90 TBD TBD TBD TBD 60 65 7.7 19.7 26.9 30.2 39.6 Table continues on the next page... NA TBD 25.1 33.3 NA 43.3 TBD 55.6 378 Ambient Temperature (C) NXP Semiconductors Table 7. Power consumption (Typicals unless stated otherwise) 1 (continued) 85 S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary S32K1487, 8 RUN@48 MHz (mA) RUN@64 MHz (mA) RUN@80 MHz (mA) HSRUN@112 MHz (mA) 4 Idd/MH z (A/ MHz)5 159 1.72 1.85 7.2 8.1 20.4 27.1 26.1 33.5 30.5 40 43.9 56.1 381 Max 359 384 2.60 2.65 8.3 9.2 21.9 28.5 27.8 34.4 32.9 41.5 45.5 57.5 411 Typ 256 273 1.80 2.10 7.8 8.5 20.6 27.4 26.6 33.8 31.2 40.5 44.8 57.1 390 Max 850 900 2.65 2.70 10.3 10.6 22.7 30 28.3 36.5 33.4 43.3 47.9 61.3 418 125 Max 1960 1998 3.18 3.25 12.2 13 25.3 32.7 35 39.8 37.1 46.5 NA NA 464 25 Typ 40 55 5 6 15 20 TBD TBD TBD TBD TBD TBD TBD TBD TBD 105 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 95 110 TBD 125 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 70 80 NA NA TBD 25 Typ 40 60 15 20 TBD TBD TBD TBD TBD TBD TBD TBD TBD 105 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 120 125 TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 100 110 NA NA TBD 5 6 Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. This is an average based on the use case described in the Comparator section, whereby the analog sampling is taking place periodically, with a mechanism to only enable the DAC as required. The numbers quoted assumes that only a single ANLCMP is active and the others are disabled Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation. HSRUN mode must not be used at 125C. Max ambient temperature for HSRUN mode is 105C. Values mentioned are measured at 25 at RUN@80 MHz with peripherals disabled. With PMC_REGSC[CLKBIASDIS] set to 1. See Reference Manual for details. Above S32K148 data is preliminary targets only The S32K148 data points assume that ENET/QuadSPI/SAI etc. are active. If the same configuration is selected as per the S32K144, then the two devices will have very similar IDD. 17 General 3. 4. 5. 6. 7. 8. STOP2 (mA) 150 125 1. 2. STOP1 (mA) Typ 105 S32K146 VLPR (mA) VLPS (A)2, 3 I/O parameters 4.7.1 Modes configuration Attached S32K1xx_Power_Modes _Configuration.xlsx details the modes used in gathering the power consumption data stated in the above table Table 7. For full functionality refer to table: Module operation in available low power modes of the Reference Manual. 4.8 ESD handling ratings Symbol Description VHBM Electrostatic discharge voltage, human body model VCDM Electrostatic discharge voltage, charged-device model ILAT Min. Max. Unit Notes - 4000 4000 V 1 2 All pins except the corner pins - 500 500 V Corner pins only - 750 750 V Latch-up current at ambient temperature of 125 C - 100 100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4.9 EMC radiated emissions operating behaviors EMC measurements to IC-level IEC standards are available from NXP on request. 5 I/O parameters 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. S32K1xx Data Sheet, Rev. 4, 06/2017 18 Preliminary NXP Semiconductors I/O parameters Figure 7. Input signal measurement reference 5.2 General AC specifications These general purpose specifications apply to all signals configured for GPIO, UART, and timers. Table 8. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) -- Synchronous path 1.5 -- Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, passive filter disabled) -- Asynchronous path 50 -- ns 3 WFRST RESET input filtered pulse -- 100 ns 4 WFRST RESET input not filtered pulse 100 -- ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater of synchronous and asynchronous timing must be met. 3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized. 4. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. 5.3 DC electrical specifications at 3.3 V Range Table 9. DC electrical specifications at 3.3 V Range Symbol Parameter Value Unit Notes Min. Typ. Max. 2.7 3.3 4 V 1 VDD I/O Supply Voltage Vih Input Buffer High Voltage 0.7 x VDD -- VDD + 0.3 V 2 Vil Input Buffer Low Voltage VSS - 0.3 -- 0.3 x VDD V 3 Input Buffer Hysteresis 0.06 x VDD -- -- V Ioh_Standard I/O current source capability measured when pad = (VDDE - 0.8 V) 3.5 -- -- mA Vhys Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 19 I/O parameters Table 9. DC electrical specifications at 3.3 V Range (continued) Symbol Parameter Value Unit Notes Min. Typ. Max. I/O current sink capability measured when pad = 0.8 V 3 -- -- mA Ioh_Strong I/O current source capability measured when pad = (VDDE - 0.8 V) 14 -- -- mA 4 Iol_Strong I/O current sink capability measured when pad = 0.8 V 12 -- -- mA 5 Output high current total for all ports -- -- 100 mA Iol_Standard IOHT IIN Input leakage current (per pin) for full temperature range at VDD = 3.3 V All pins other than high drive port pins High drive port pins 7 6 0.005 0.5 A 0.010 0.5 A RPU Internal pullup resistors 20 60 k 8 RPD Internal pulldown resistors 20 60 k 9 1. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes. 2. For reset pads, same Vih levels are applicable 3. For reset pads, same Vil levels are applicable 4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard value given above. 5. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_Standard value given above. 6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only. For details refer to S32K144_IO_Signal_Description_Input_Multiplexing.xlsx attached with the Reference Manual. 7. When using ENET and SAI on S32K148, the overall device limits associated with high drive pin configurations must be respected i.e. On 144-pin LQFP the general purpose pins: PTA10, PTD0, and PTE4 must be set to low drive. 8. Measured at input V = VSS 9. Measured at input V = VDD 5.4 DC electrical specifications at 5.0 V Range Table 10. DC electrical specifications at 5.0 V Range Symbol Parameter Value Unit Min. Typ. Max. 4 -- 5.5 V Notes VDD I/O Supply Voltage Vih Input Buffer High Voltage 0.65 x VDD -- VDD + 0.3 V 1 Vil Input Buffer Low Voltage VSS - 0.3 -- 0.35 x VDD V 2 Input Buffer Hysteresis 0.06 x VDD -- -- V Ioh_Standard I/O current source capability measured when pad = (VDDE - 0.8 V) Vhys 5 -- -- mA Iol_Standard I/O current sink capability measured when pad = 0.8 V 5 -- -- mA Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 20 Preliminary NXP Semiconductors I/O parameters Table 10. DC electrical specifications at 5.0 V Range (continued) Symbol Parameter Value Min. Typ. Max. Unit Notes Ioh_Strong I/O current source capability measured when pad = VDDE - 0.8 V 20 -- -- mA 3, 4 Iol_Strong I/O current sink capability measured when pad = 0.8 V 20 -- -- mA 4, 5 IOHT Output high current total for all ports -- -- 100 mA IIN Input leakage current (per pin) for full temperature range at VDD = 5.5 V 6 All pins other than high drive port pins 0.005 0.5 A High drive port pins 0.010 0.5 A RPU Internal pullup resistors 20 50 k 7 RPD Internal pulldown resistors 20 50 k 8 1. For reset pads, same Vih levels are applicable 2. For reset pads, same Vil levels are applicable 3. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard value given above. 4. The strong pad I/O pin is capable of switching a 50 pF load at up to 40 MHz. 5. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_Standard value given above. 6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only. For details refer to SK3K144_IO_Signal_Description_Input_Multiplexing.xlsx attached with the Reference Manual. 7. Measured at input V = VSS 8. Measured at input V = VDD 5.5 AC electrical specifications at 3.3 V range Table 11. AC electrical specifications at 3.3 V Range Symbol Standard Strong DSE NA 0 1 Rise time (nS) 1 Fall time (nS) 1 Capacitance (pF) 2 Min. Max. Min. Max. 4.6 14.5 3.9 15.7 25 7.2 23.7 6.2 26.2 50 24.0 75.4 20.8 88.4 200 4.6 14.5 3.9 15.7 25 7.2 23.7 6.2 26.2 50 24.0 75.4 20.8 88.4 200 2.0 5.8 1.8 6.1 25 2.8 8.0 2.6 8.3 50 7.0 20.7 6.0 22.4 200 1. For reference only. Run simulations with the IBIS model and your custom board for accurate results. 2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections. S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 21 I/O parameters 5.6 AC electrical specifications at 5 V range Table 12. AC electrical specifications at 5 V Range Symbol Standard Strong DSE NA 0 1 Rise time (nS)1 Fall time (nS) 1 Min. Max . Min. Max. 3.2 9.4 3.6 10.7 Capacitance (pF) 2 25 5.4 15.7 5.1 17.4 50 18.5 52.6 17.6 59.7 200 4.0 9.4 3.6 10.7 25 5.8 15.7 5.1 17.4 50 18.1 52.6 17.6 59.7 200 1.6 4.6 1.5 5.0 25 2.2 5.7 2.2 5.8 50 5.6 14.6 5.0 15.4 200 1. For reference only. Run simulations with the IBIS model and your custom board for accurate results. 2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections. 5.7 Standard input pin capacitance Table 13. Standard input pin capacitance Symbol CIN_D Description Input capacitance: digital pins Min. Max. Unit -- 7 pF NOTE Please refer to External System Oscillator electrical specifications for EXTAL/XTAL pins. 5.8 Device clock specifications Table 14. Device clock specifications 1 Symbol Description High Speed run Min. Max. Unit mode2 fSYS System and core clock -- 112 MHz fBUS Bus clock -- 56 MHz Flash clock -- 28 MHz fFLASH Normal run mode (S32K11x series) Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 22 Preliminary NXP Semiconductors Peripheral operating requirements and behaviors Table 14. Device clock specifications 1 (continued) Symbol Description Max. Unit fSYS System and core clock -- 48 MHz fBUS Bus clock -- 24 MHz -- 24 MHz fFLASH Flash clock Normal run mode (S32K14x series) 3 fSYS System and core clock -- 80 MHz fBUS Bus clock -- 40 MHz -- 26.67 MHz fFLASH Flash clock VLPR 1. 2. 3. 4. Min. mode4 fSYS System and core clock -- 4 MHz fBUS Bus clock -- 4 MHz fFLASH Flash clock -- 1 MHz fERCLK External reference clock -- 16 MHz Refer to the section Feature comparison for the availability of modes and other specifications. Only available on some devices. See section Feature comparison. With SPLL as system clock source. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. 6 Peripheral operating requirements and behaviors 6.1 System modules There are no electrical specifications necessary for the device's system modules. 6.2 Clock interface modules 6.2.1 External System Oscillator electrical specifications S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 23 Clock interface modules Single input comparator (EXTAL WAVE) ref_clk Mux Differential input comparator (HG/LP mode) Peak detector LP mode Driver (HG/LP mode) Pull down resistor (OFF) ESD PAD 280 ohms ESD PAD 40 ohms XTAL pin EXTAL pin Series resistor for current limitation 1M ohms Feedback Resistor Crystal or resonator C1 C2 Figure 8. Oscillator connections scheme Table 15. External System Oscillator electrical specifications Symbol Description Min. Typ. Max. Unit gmXOSC Crystal oscillator transconductance 4-8 MHz 2.2 -- 13.7 mA/V 8-40 MHz 16 -- 47 mA/V VIL Input low voltage -- EXTAL pin in external clock mode VIH Input high voltage -- EXTAL pin in external clock mode C1 Notes VSS -- 0.35 * VDD V 0.7 * VDD -- VDD V EXTAL load capacitance -- -- -- 1 C2 XTAL load capacitance -- -- -- 1 RF Feedback resistor 2 Low-gain mode (HGO=0) -- -- -- M Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 24 Preliminary NXP Semiconductors Clock interface modules Table 15. External System Oscillator electrical specifications (continued) Symbol Description Min. Typ. Max. Unit -- 1 -- M Low-gain mode (HGO=0) -- 0 -- k High-gain mode (HGO=1) -- 0 -- k High-gain mode (HGO=1) RS Notes Series resistor Vpp Peak-to-peak amplitude of oscillation (oscillator mode) 3 Low-gain mode (HGO=0) -- 1.0 -- V High-gain mode (HGO=1) -- 3.3 -- V 1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as: gm_crit = 4 * ESR * (2F)2 * (C0 + CL)2 where: * * * * * * * gmXOSC is the transconductance of the internal oscillator circuit ESR is the equivalent series resistance of the external crystal F is the external crystal oscillation frequency C0 is the shunt capacitance of the external crystal CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)] Cs is stray or parasitic capacitance on the pin due to any PCB traces C1, C2 external load capacitances on EXTAL and XTAL pins See manufacture datasheet for external crystal component values * When low-gain is selected, internal RF will be selected and external RF should not be attached. * When high-gain is selected, external RF (1 M Ohm) needs to be connected for proper operation of the crystal. For external resistor, up to 5% tolerance is allowed. 3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 2. 6.2.2 External System Oscillator frequency specifications Table 16. External System Oscillator frequency specifications Symbol Min. Typ. Max. Unit Oscillator crystal or resonator frequency 4 -- 40 MHz fec_extal Input clock frequency (external clock mode) -- -- 50 MHz tdc_extal Input clock duty cycle (external clock mode) 40 50 60 % 8 MHz low-gain mode (HGO=0) -- 1.5 -- ms 8 MHz high-gain mode (HGO=1) -- 2.5 -- 40 MHz low-gain mode (HGO=0) -- 2 -- 40 MHz high-gain mode (HGO=1) -- 2 -- fosc_hi tcst Description Notes Crystal Start-up Time 1 1. Proper PC board layout procedures must be followed to achieve specifications. S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 25 System Clock Generation (SCG) specifications 6.2.3 System Clock Generation (SCG) specifications 6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications Table 17. Fast internal RC Oscillator electrical specifications Parameter1 Symbol Value Unit Min. Typ. Max. FIRC target frequency -- 48 -- MHz F Frequency deviation across process, voltage, and temperature < 105C -- 0.5 1 %FFIRC F125 Frequency deviation across process, voltage, and temperature < 125C -- 0.5 1.1 %FFIRC TStartup Startup time 3.4 5 s2 TJIT, 3 Cycle-to-Cycle jitter -- 250 500 ps Long term jitter over 1000 cycles -- 0.04 0.1 %FFIRC FFIRC 3 TJIT 1. With FIRC regulator enable 2. Startup time is defined as the time between clock enablement and clock availability for system use. 3. FIRC as system clock NOTE Fast internal RC Oscillator is compliant with CAN and LIN standards. 6.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications Table 18. Slow internal RC oscillator (SIRC) electrical specifications Symbol Parameter Value Unit Min. Typ. Max. SIRC target frequency -- 8 -- MHz F Frequency deviation across process, voltage, and temperature < 105C -- -- 3 %FSIRC F125 Frequency deviation across process, voltage, and temperature < 125C -- -- 3.3 %FSIRC TStartup Startup time -- 9 12.5 s1 FSIRC 1. Startup time is defined as the time between clock enablement and clock availability for system use. S32K1xx Data Sheet, Rev. 4, 06/2017 26 Preliminary NXP Semiconductors Memory and memory interfaces 6.2.4 Low Power Oscillator (LPO) electrical specifications Table 19. Low Power Oscillator (LPO) electrical specifications Symbol Parameter FLPO Internal low power oscillator frequency Tstartup Startup Time Min. Typ. Max. Unit 113 128 139 kHz -- -- 20 s 6.2.5 SPLL electrical specifications Table 20. SPLL electrical specifications Symbol Parameter 1 2 FSPLL_REF FSPLL_Input Min. Typ. Max. Unit PLL Reference Frequency Range 8 -- 16 MHz PLL Input Frequency 8 -- 40 MHz FVCO_CLK VCO output frequency 180 -- 320 MHz FSPLL_CLK PLL output frequency 90 -- 160 MHz JCYC_SPLL PLL Period Jitter (RMS)3 -- 120 -- ps -- 75 -- ps at FVCO_CLK 180 MHz -- 1350 -- ps at FVCO_CLK 320 MHz -- 600 -- ps 4.47 -- 5.97 % at FVCO_CLK 180 MHz at FVCO_CLK 320 MHz JACC_SPLL DUNL TSPLL_LOCK PLL accumulated jitter over 1s Lock exit frequency tolerance Lock detector detection (RMS)3 time4 -- -- 10-6 150 x + 1075(1/FSPLL_REF) s 1. FSPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG register of Reference Manual. 2. FSPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input source could be derived from a crystal oscillator or some other external square wave clock source using OSC bypass mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual. 3. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary 4. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use. 6.3 Memory and memory interfaces 6.3.1 Flash memory module (FTFC) electrical specifications This section describes the electrical characteristics of the flash memory module. S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 27 Memory and memory interfaces 6.3.1.1 Flash timing specifications -- commands Table 21. Flash command timing specifications Symbol Description1 trd1blk64k Read 1s Block execution time * 64 KB data flash trd1blk512k * 512 KB program flash Min. Typ. Max. Unit -- -- 0.5 ms -- -- 1.8 ms trd1sec2k Read 1s Section execution time (2 KB flash) -- -- 75 s trd1sec4k Read 1s Section execution time (4 KB flash) -- -- 100 s tpgmchk Program Check execution time -- -- 95 s tpgm8 Program Phrase execution time -- 90 150 s -- 55 475 ms -- 435 3700 ms Erase Flash Sector execution time -- 15 115 ms Program Section execution time (1KB flash) -- 5 -- ms -- -- 2.2 ms -- -- 4.4 ms -- -- 6.6 ms Read Once execution time -- -- 30 s Program Once execution time -- 90 -- s tersall Erase All Blocks execution time -- 500 4200 ms tvfykey Verify Backdoor Access Key execution time -- -- 35 s tersallu Erase All Blocks Unsecure execution time -- 500 4200 ms Program Partition for EEPROM execution time * 32 KB EEPROM backup -- 70 -- ms -- 71 -- ms tersblk64k tersblk512k tersscr tpgmsec1k trd1allx trdonce tpgmonce tpgmpart32k tpgmpart64k Erase Flash Block execution time * 64 KB data flash Notes 2 * 512 KB program flash Read 1s All Blocks execution time * 64 KB EEPROM backup (Non-Interleaved DFlash) 250 2 2 2 3, 4 ms * 64 KB EEPROM backup (Interleaved DFlash) tsetramff Set FlexRAM Function execution time: * Control Code 0xFF tsetram32k * 32 KB EEPROM backup tsetram48k * 48 KB EEPROM backup tsetram64k * 64 KB EEPROM backup teewr8b32k teewr8b48k teewr8b64k teewr16b32k teewr16b48k Byte-write to FlexRAM execution time: * 32 KB EEPROM backup * 48 KB EEPROM backup -- 70 -- s -- 0.8 1.2 ms -- 1.0 1.5 ms -- 1.3 1.9 ms -- 385 1700 s -- 430 1850 s -- 475 2000 s -- 385 1700 s -- 430 1850 s 3, 4 3, 4 * 64 KB EEPROM backup 16-bit write to FlexRAM execution time: * 32 KB EEPROM backup 3, 4 Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 28 Preliminary NXP Semiconductors Memory and memory interfaces Table 21. Flash command timing specifications (continued) Symbol teewr16b64k Description1 * 48 KB EEPROM backup Min. Typ. Max. Unit -- 475 2000 s -- 360 2000 s -- 630 2000 s -- 720 2125 s -- 810 2250 s Notes * 64 KB EEPROM backup teewr32bers 32-bit write to erased FlexRAM location execution time teewr32b32k teewr32b48k teewr32b64k tquickwr 32-bit write to FlexRAM execution time: * 32 KB EEPROM backup * 48 KB EEPROM backup 3, 4 * 64 KB EEPROM backup 32-bit Quick Write execution time : Time from CCIF clearing (start the write) until CCIF setting (32-bit write complete, ready for next 32-bit write) * 1st 32-bit write -- 200 550 s * 2nd through Next to Last (Nth-1) 32-bit write -- 150 550 s -- 200 550 s -- -- (Number of Quick Writes) * 2.0 ms 5, 6 * Last (Nth) 32-bit write (time for write only, not cleanup) tquickwrClnup Quick Write Cleanup execution time 7 1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external clocks). 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For all EEPROM Emulation terms, the specified timing shown assumes previous record clean up has occurred. This may be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM issues detected. 4. 'First time' EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2x the times shown. 5. For 'Typ.', only after the Nth write completes will any data will be valid. Emulated EEPROM record scheme cleanup overhead may occur after this point even after a brownout or reset. If power or reset occurs before the Nth write completes, the last valid record set will still be valid and the new records will be discarded. 6. Quick Write may take up to 550 s as additional cleanup may occur when crossing sector boundaries. 7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes, assuming still powered. Or via SETRAM cleanup execution command is requested at a later point. NOTE Under certain circumstances FlexMEM maximum times may be exceeded. In this case the user or application may wait, or assert reset to the FTFC macro to stop the operation. 6.3.1.2 Symbol Reliability specifications Table 22. NVM reliability specifications Description Min. Typ. Max. Unit Notes When using as Program and Data Flash Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 29 Memory and memory interfaces Table 22. NVM reliability specifications (continued) Symbol Description Min. Typ. Max. Unit tnvmretp1k Data retention after up to 1 K cycles 20 -- -- years nnvmcycp Cycling endurance 1K -- -- cycles Notes 2, 1 When using FlexMemory feature: FlexRAM as Emulated EEPROM tnvmretee nnvmwree16 nnvmwree256 Data retention Write endurance * EEPROM backup to FlexRAM ratio = 16 * EEPROM backup to FlexRAM ratio = 256 5 -- -- years 100 K -- -- writes 1.6 M -- -- writes 3, 4, 5 1. Program and Erase for PFlash and DFlash are supported across product temperature specification in Normal Mode (not supported in HSRUN mode). 2. Cycling endurance is per DFlash or PFlash Sector. 3. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across standard temperature specification in Normal Mode (not supported in HSRUN mode). Greater write endurance may be achieved with larger ratios of EEPROM backup to FlexRAM. 4. For usage of any other EEE driver other than the FlexMemory feature, the endurance specification will fall back to the specified endurance value of the D-Flash specification (1 K). 5. EEE calculator tool is available at NXP web site to help estimate the maximum write endurance achievable at specific EEPROM/FlexRAM ratio. The "In Spec" portions of the online calculator refer to the NVM reliability specifications section of data sheet. This calculator is only applies to the FlexMemory feature. 6.3.2 QuadSPI AC specifications The following table describes the QuadSPI electrical characteristics. * Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). * I/O operating voltage ranges from 2.97 V to 3.6 V * While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. * Add 50 ohm series termination on board in QuadSPI SCK for Flash A to avoid loop back reflection when using in Internal DQS (PAD Loopback) mode. * For non-Quad mode of operation if external device doesn't have pull-up feature, external pull-up needs to be added at board level for non-used pads. * With external pull-up, performance of the interface may degrade based on load associated with external pull-up. S32K1xx Data Sheet, Rev. 4, 06/2017 30 Preliminary NXP Semiconductors NXP Semiconductors Table 23. QuadSPI electrical specifications FLASH PORT Sym Unit FLASH A QuadSPI Mode RUN1 HSRUN1 SDR SDR Internal Sampling N1 Min Max FLASH B Internal DQS Internal Sampling PAD Loopback Internal Loopback Min Min Max Max Internal DQS N1 Min Max RUN/HSRUN2 PAD Loopback Internal Loopback Min Min Max Max SDR DDR3 Internal Sampling External DQS N1 Extrenal DQS Min Max Min Max Register Settings MCR[DDR_EN] - 0 0 0 0 0 0 0 1 S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary MCR[DQS_EN] - 0 1 1 0 1 1 0 1 MCR[SCLKCFG[0]] - - 1 0 - 1 0 - - MCR[SCLKCFG[1]] - - 1 0 - 1 0 - - MCR[SCLKCFG[2]] - - - - - - - - 0 MCR[SCLKCFG[3]] - - - - - - - - 0 MCR[SCLKCFG[5]] - - - - - - - - 1 SMPR[FSPHS] - 0 1 0 0 1 0 0 0 SMPR[FSDLY] - 0 0 0 0 0 0 0 0 - 0 23 - 0 30 - - SOCCR [SOCCFG[7:0]] SOCCR[SOCCFG[15:8]] - - - - - - - - 30 FLSHCR[TDH] - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 Timing Parameters - - 48 - - 40 - Table continues on the next page... - 80 - 1/fSCK - 64 1/fSCK ns - 1/fSCK tSCK 38 1/fSCK SCK Clock Period - 1/fSCK MHz 1/fSCK fSCK 50 - 20 - 204 - 50.0 - 50.04 - 31 Memory and memory interfaces SCK Clock Frequency FLASH PORT Sym Unit FLASH A RUN1 HSRUN1 SDR SDR QuadSPI Mode Internal Sampling N1 Min Max FLASH B Internal DQS Internal Sampling PAD Loopback Internal Loopback Min Min Max Max Internal DQS N1 Min Max RUN/HSRUN2 PAD Loopback Internal Loopback Min Min Max Max SDR DDR3 Internal Sampling External DQS N1 Extrenal DQS Min Max Min Max 2.5 - 10 - 14 - 1.5 - 9 - 25 - -2 - Data Input Hold Time tIH ns 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - Data Output Valid Time tOV ns - 4.5 - 4.5 - 4.5 - 4 - 4 - 4 - 10 - 10 - 5 - 5 - 5 - tSCK/2 - 2.5 tSCK/2 - 2.5 tSCK/2 - 1.5 tSCK/2 - 0.750 tSCK/2 - 0.750 tSCK/2 - 1.5 tSCK/2 - 1.5 tSCK/2 - 1.5 Data Output In-Valid Time tIV ns 5 - 5 - 5 - 5 - 35 CS to SCK Time 6 tCSSCK ns 5 - 5 - 5 - 5 - 5 - 5 - 10 - 10 - SCK to CS Time 7 tSCKCS ns 5 - 5 - 5 - 5 - 5 - 5 - 5 - 5 - Output Load NXP Semiconductors 1. 2. 3. 4. 5. 6. 7. tSCK/2 + 2.5 - tSCK/2 + 2.5 15 tSCK/2 + 1.5 ns tSCK/2 + 1.5 tIS tSCK/2 + 1.5 Data Input Setup Time tSCK/2 + 1.5 ns tSCK/2 + 1.5 tSDC tSCK/2 - 1.5 S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary SCK Duty Cycle pf 25 25 See Reference Manual for details on mode settings See Reference Manual for details on mode settings Valid for HyperRAM only RWDS(External DQS CLK) frequency For operating frequency 64 Mhz,Output invalid time is 5 ns. Program register value QuadSPI_FLSHCR[TCSS] = 4h2 Program register value QuadSPI_FLSHCR[TCSH] = 4h1 25 25 25 25 25 25 Memory and memory interfaces 32 Table 23. QuadSPI electrical specifications (continued) Memory and memory interfaces 1 2 Clock 3 tSCK tSDC tSDC SCK CS tIH tIS Data in Figure 9. QuadSPI input timing (SDR mode) diagram 1 2 3 Clock tSCK tSDC tSDC SCK tSCKCS tCSSCK CS tIV tOV Data out Figure 10. QuadSPI output timing (SDR mode) diagram tSCK RWDS tSDC tSDC tIS tIH DI[7:0] Figure 11. QuadSPI input timing (HyperRAM mode) diagram S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 33 Analog modules CK tIV tOV Output Invalid Data Figure 12. QuadSPI output timing (HyperRAM mode) diagram 6.4 Analog modules 6.4.1 ADC electrical specifications 6.4.1.1 12-bit ADC operating conditions Table 24. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Delta to VDD (VDD - VDDA) -0.1 0 +0.1 V 2 VREFH ADC reference voltage high See Voltage and current operating requirements for values VDDA See Voltage and current operating requirements for values V 3 VREFL ADC reference voltage low See Voltage and current operating requirements for values 0 See Voltage and current operating requirements for values mV 3 VADIN Input voltage VREFL -- VREFH V -- -- 5 k RS Source impedendance fADCK < 4 MHz RSW1 Channel Selection Switch Impedance -- -0.75 1.2 k RAD Sampling Switch Impedance -- 2 5 k CP1 Pin Capacitance -- 10 -- pF Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 34 Preliminary NXP Semiconductors ADC electrical specifications Table 24. 12-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes CP2 Analog Bus Capacitance -- -- 4 pF CS Sampling capacitance -- 4 5 pF fADCK ADC conversion clock frequency Normal usage 2 40 50 MHz 4, 5 fCONV ADC conversion frequency No ADC hardware averaging.6 Continuous conversions enabled, subsequent conversion time 46.4 928 1160 Ksps 7, 8 ADC hardware averaging set to 32. 6 Continuous conversions enabled, subsequent conversion time 1.45 29 36.25 Ksps 7, 8 1. Typical values assume VDDA = 5 V, Temp = 25 C, fADCK = 40 MHz, RAS=20 , and CAS=10 nF unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for details. 4. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual . 5. ADC conversion will become less reliable above maximum frequency. 6. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS. 7. Numbers based on the minimum sampling time of 275 ns. 8. For guidelines and examples of conversion rate calculation, see the Reference Manual or download the ADC calculator tool. Figure 13. ADC input impedance equivalency diagram S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 35 ADC electrical specifications 6.4.1.2 12-bit ADC electrical characteristics NOTE ADC performance specifications are documented using a single ADC. For parallel/simultaneous operation of both ADCs, either for sampling the same channel by both ADCs or for sampling different channels by each ADC, some amount of decrease in performance can be expected. Care must be taken to stagger the two ADC conversions, in particular the sample phase, to minimize the impact of simultaneous conversions. Table 25. 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS) Symbol Description VDDA Supply voltage IDDA_ADC Conditions 1 Supply current per ADC SMPLTS Sample Time Min. Typ.2 Max. Unit 2.7 -- 3 V -- 0.6 1.5 mA 275 -- Refer to the Reference Manual ns Notes 3 TUE4 Total unadjusted error -- 4 8 LSB5 6, 7, 8, 9 DNL Differential non-linearity -- 1.0 -- LSB5 6, 7, 8, 9 INL Integral non-linearity -- 2.0 -- LSB5 6, 7, 8, 9 1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to half the ADC clock frequency. 2. Typical values assume VDDA = 3 V, Temp = 25 C, fADCK = 40 MHz, RAS=20 , and CAS=10 nF, 100 LQFP package unless otherwise stated. 3. The ADC supply current depends on the ADC conversion rate. 4. Represents total static error, which includes offset and full scale error. 5. 1 LSB = (VREFH - VREFL)/2N 6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings for AVGS. 7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC performance may be observed. 8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the internal analog parameters, assume minor degradation. 9. All the parameters in the table are given assuming system clock as the clocking source for ADC. Table 26. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS) Min. Typ.2 Max. Unit Supply voltage 3 -- 5.5 V Supply current per ADC -- 1 2.1 mA 275 -- Refer to the Reference Manual ns Symbol Description VDDA IDDA_ADC SMPLTS Sample Time Conditions 1 Notes 3 Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 36 Preliminary NXP Semiconductors ADC electrical specifications Table 26. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS) (continued) Symbol Description Conditions 1 Min. Typ.2 Max. Unit Notes TUE4 Total unadjusted error -- 4 8 LSB5 6, 7, 8, 9 DNL Differential non-linearity -- 0.7 -- LSB5 6, 7, 8, 9 INL Integral non-linearity -- 1.0 -- LSB5 6, 7, 8, 9 1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to half the ADC clock frequency. 2. Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 40 MHz, RAS=20 , and CAS=10 nF unless otherwise stated. 3. The ADC supply current depends on the ADC conversion rate. 4. Represents total static error, which includes offset and full scale error. 5. 1 LSB = (VREFH - VREFL)/2N 6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings for AVGS. 7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC performance may be observed. 8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the internal analog parameters, assume minor degradation. 9. All the parameters in the table are given assuming system clock as the clocking source for ADC. NOTE When using high speed interfaces such as the QuadSPI, SAI0, SAI1 or ENET there may be some ADC degradation on the adjacent analog input paths. See following table for details. Pin name TGATE purpose PTE8 CMP0_IN3 PTC3 ADC0_SE11/CMP0_IN4 PTC2 ADC0_SE10/CMP0_IN5 PTD7 CMP0_IN6 PTD6 CMP0_IN7 PTD28 ADC1_SE22 PTD27 ADC1_SE21 6.4.2 CMP with 8-bit DAC electrical specifications Table 28. Comparator with 8-bit DAC electrical specifications Symbol IDDHS Description Min. Max. Supply current, High-speed mode1 Supply current, Low-speed Unit A -40 - 125 IDDLS Typ. -- 230 300 mode1 A -40 - 105 -- -40 - 125 5 10 5 13 Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 37 ADC electrical specifications Table 28. Comparator with 8-bit DAC electrical specifications (continued) Symbol Description VAIN Analog input voltage VAIO Analog input offset voltage, High-speed mode -40 - 125 VAIO Typ. Max. Unit 0 0 - VDDA VDDA V mV -25 mV -40 Propagation delay, High-speed -- Propagation delay, High-speed 300 Propagation delay, Low-speed -- 0.5 2 -- 0.5 3 -- 70 400 -- 70 500 mode3 s -40 - 105 -- 1 5 -40 - 125 -- 1 5 Initialization delay, High-speed mode4 s -40 - 125 -- Initialization delay, Low-speed 1.5 3 mode4 s -40 - 125 -- 10 30 Analog comparator hysteresis, Hyst0 (VAIO) -40 - 125 VHYST1 30 ns -40 - 125 VHYST0 200 mode3 -40 - 105 tIDLS 30 s -40 - 125 tIDHS 40 Propagation delay, Low-speed mode2 -40 - 105 tDLSS 4 ns -40 - 125 tDHSS 25 mode2 -40 - 105 tDLSB 1 Analog input offset voltage, Low-speed mode -40 - 125 tDHSB Min. mV -- 0 -- Analog comparator hysteresis, Hyst1, High-speed mode -40 - 125 mV -- 16 66 -- 11 40 Analog comparator hysteresis, Hyst1, Low-speed mode -40 - 125 VHYST2 Analog comparator hysteresis, Hyst2, High-speed mode -40 - 125 mV -- 32 133 -- 22 80 Analog comparator hysteresis, Hyst2, Low-speed mode -40 - 125 VHYST3 Analog comparator hysteresis, Hyst3, High-speed mode -40 - 125 mV -- 48 200 -- 33 120 Analog comparator hysteresis, Hyst3, Low-speed mode -40 - 125 Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 38 Preliminary NXP Semiconductors ADC electrical specifications Table 28. Comparator with 8-bit DAC electrical specifications (continued) Symbol IDAC8b 1. 2. 3. 4. 5. 6. Description Min. Typ. Max. Unit 3.3V Reference Voltage -- 6 9 A 5V Reference Voltage -- 10 16 A 8-bit DAC current adder (enabled) INL5 8-bit DAC integral non-linearity -0.75 -- 0.75 LSB6 DNL 8-bit DAC differential non-linearity -0.5 -- 0.5 LSB6 tDDAC Initialization and switching settling time -- -- 30 s Difference at input > 200mV Applied (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point. Applied (30 mV + 2 x VHYST0/1/2/3+ max. of VAIO) around switch point. Applied (100 mV + VHYST0/1/2/3). Calculation method used: Linear Regression Least Square Method 1 LSB = Vreference/256 NOTE For comparator IN signals adjacent to VDD/VSS or XTAL/ EXTAL or switching pins cross coupling may happen and hence hysteresis settings can be used to obtain the desired comparator performance. Additionally, an external capacitor (1nF) should be used to filter noise on input signal. Also, source drive should not be weak (Signal with < 50 K pull up/down is recommended). Figure 14. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 0) S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 39 ADC electrical specifications Figure 15. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 1) Figure 16. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 0) S32K1xx Data Sheet, Rev. 4, 06/2017 40 Preliminary NXP Semiconductors Communication modules Figure 17. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1) 6.5 Communication modules 6.5.1 LPUART electrical specifications Refer to General AC specifications for LPUART specifications. 6.5.1.1 Supported baud rate Baud rate = Baud clock / ((OSR+1) * SBR). For details, see section: 'Baud rate generation' of the Reference Manual. 6.5.2 LPSPI electrical specifications The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. * All timing is shown with respect to 20% VDD and 80% VDD thresholds. * All measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew setting ( DSE = 1 ). S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 41 Num Symbol Description Run Mode2 Conditions 5.0 V IO HSRUN Mode2 3.3 V IO 5.0 V IO VLPR Mode 3.3 V IO 5.0 V IO Unit 3.3 V IO Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Slave - 40 - 40 - 56 - 56 - 8 - 8 Master - 40 - 40 - 56 - 56 - 8 - 8 Master Loopback 5 - 40 - 48 - 48 - 48 - 8 - 8 Master Loopback(Slow) - 48 - 48 - 48 - 48 - 8 - 8 Frequency of Slave operation Master - 10 - 10 - 14 - 14 - 4 - 4 - 10 - 10 - 14 - 14 - 4 - 4 Master - 20 - 12 - 24 - 12 - 4 - 4 - 12 - 12 - 12 - 12 - 4 - 4 Slave 100 - 100 - 72 - 72 - 250 - 250 - Master 100 - 100 - 72 - 72 - 250 - 250 - Master Loopback5 50 - 83 - 42 - 83 - 250 - 250 - Master Loopback(slow) 83 - 83 - 83 - 83 - 250 - 250 - - - - - - - - - - - - - fperiph, 3, 4 Peripheral Frequency MHz 6 Preliminary S32K1xx Data Sheet, Rev. 4, 06/2017 1 fop MHz Loopback5 Master Loopback(slow) 6 2 tSPSCK SPSCK period ns 6 3 tLead7 Enable lead Slave time (PCS to SPSCK delay) NXP Semiconductors Table continues on the next page... ns Communication modules 42 Table 29. LPSPI electrical specifications1 NXP Semiconductors Table 29. LPSPI electrical specifications1 (continued) Num Symbol Description Run Mode2 Conditions 5.0 V IO Min. Master HSRUN Mode2 3.3 V IO Max. Min. - Max. 5.0 V IO Min. - Max. VLPR Mode 3.3 V IO Min. - Max. 5.0 V IO Min. - Max. Unit 3.3 V IO Min. - Max. - Master Loopback5 Slave - Master - - - - - - - - (PCSSCK + 1)*tSPSCK - 50 (PCSSCK + 1)*tSPSCK - 50 (PCSSCK + 1)*tSPSCK - 25 (PCSSCK + 1)*tSPSCK - 25 - - - - - - - ns - Master 43 Communication modules Table continues on the next page... (SCKPCS + 1)*tSPSCK - 50 6 (SCKPCS + 1)*tSPSCK - 50 Master Loopback(slow) (SCKPCS + 1)*tSPSCK - 25 Loopback5 (SCKPCS + 1)*tSPSCK - 25 Enable lag time (After SPSCK delay) (SCKPCS + 1)*tSPSCK - 25 tLag8 (SCKPCS + 1)*tSPSCK - 25 S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary 4 (PCSSCK + 1)*tSPSCK - 25 6 (PCSSCK + 1)*tSPSCK - 25 Master Loopback(slow) Symbol Description Run Mode2 Conditions 5.0 V IO Min. Preliminary Min. Max. Min. Max. 5.0 V IO Min. Max. 3.3 V IO Min. Max. ns tSPSCK/2 + 5 tSPSCK/2 - 5 tSPSCK/2 + 5 tSPSCK/2 - 5 tSPSCK/2 + 3 tSPSCK/2 - 3 tSPSCK/2 + 3 tSPSCK/2 + 3 Master Loopback5 tSPSCK/2 - 3 S32K1xx Data Sheet, Rev. 4, 06/2017 Data setup time(inputs) Max. 3.3 V IO Unit Master 6 tSU Min. 5.0 V IO VLPR Mode Slave Master Loopback(slow) 6 3.3 V IO Max. tSPSCK/2 + 3 tWSPSCK Clock(SPSC K) high or low time (SPSCK duty cycle) tSPSCK/2 - 3 5 HSRUN Mode2 tSPSCK/2 - 3 Num Slave 3 - 5 - 3 - 5 - 18 - 18 - Master 29 - 38 - 26 - 37 - 72 - 78 - Master 7 - 8 - 5 - 7 - 20 - 20 - Master Loopback(slow) 8 - 10 - 7 - 9 - 20 - 20 - Slave 3 - 3 - 3 - 3 - 14 - 14 - Master 0 - 0 - 0 - 0 - 0 - 0 - Master 3 - 3 - 2 - 3 - 11 - 11 - 3 - 3 - 3 - 3 - 12 - 12 - ns Loopback5 6 7 tHI Data hold time(inputs) ns Loopback5 Master Loopback(slow) 6 NXP Semiconductors 8 ta Slave access Slave time - 50 - 50 - 50 - 50 - 100 - 100 ns 9 tdis Slave MISO (SOUT) disable time - 50 - 50 - 50 - 50 - 100 - 100 ns Slave Table continues on the next page... Communication modules 44 Table 29. LPSPI electrical specifications1 (continued) NXP Semiconductors Table 29. LPSPI electrical specifications1 (continued) Num Symbol Description Run Mode2 Conditions 5.0 V IO 10 tv Data valid (after SPSCK edge) HSRUN Mode2 3.3 V IO 5.0 V IO VLPR Mode 3.3 V IO 5.0 V IO Unit 3.3 V IO Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Slave - 30 - 39 - 26 - 36 - 92 - 96 Master - 12 - 16 - 11 - 15 - 47 - 48 Master Loopback5 - 12 - 16 - 11 - 15 - 47 - 48 Master Loopback(slow) - 8 - 10 - 7 - 9 - 44 - 44 4 - 4 - 4 - 4 - 4 - 4 - -15 - -22 - -15 - -23 - -22 - -29 - ns 6 Preliminary S32K1xx Data Sheet, Rev. 4, 06/2017 11 tHO Data hold Slave time(outputs) Master ns Master Loopback5 -10 - -14 - -10 - -14 - -14 - -19 - Master Loopback(slow) -15 - -22 - -15 - -22 - -21 - -27 - 1 - 1 - 1 - 1 - 1 ns 25 ns 6 12 tRI/FI Rise/Fall time input Slave - 1 - Master - - - - - - Master Loopback5 - - - - - - Master Loopback(slow) - - - - - - Slave - Master - - - - - - Master Loopback 5 - - - - - - Master Loopback(slow) - - - - - - 6 13 tRO/FO Rise/Fall time output 25 - 25 - 25 - 45 1. 2. 3. Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode. While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz. fperiph = LPSPI peripheral clock - 25 - Communication modules 6 25 6. 7. 8. tperiph = 1/fperiph Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1. Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0. Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1. Clock pad used is PTB2. Applicable only for LPSPI0. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255. Communication modules 46 4. 5. S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary NXP Semiconductors Communication modules SS1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 12 13 12 13 4 5 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 LSB IN 10 MOSI (OUTPUT) MSB OUT2 11 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 18. LPSPI master mode timing (CPHA = 0) SS1 (OUTPUT) 2 3 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 5 13 12 13 4 7 MSB IN2 BIT 6 . . . 1 LSB IN 11 10 MOSI (OUTPUT) 12 PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 19. LPSPI master mode timing (CPHA = 1) S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 47 Communication modules SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 MISO (OUTPUT) see note SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN Figure 20. LPSPI slave mode timing (CPHA = 0) SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note 8 MOSI (INPUT) SLAVE 13 12 13 11 10 MISO (OUTPUT) 12 MSB OUT 6 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN Figure 21. LPSPI slave mode timing (CPHA = 1) 6.5.3 LPI2C electrical specifications See General AC specifications for LPI2C specifications. For supported baud rate see section 'Chip-specific LPI2C information' of the Reference Manual. S32K1xx Data Sheet, Rev. 4, 06/2017 48 Preliminary NXP Semiconductors Communication modules 6.5.4 FlexCAN electical specifications For supported baud rate, see section 'Protocol timing' of the Reference Manual. 6.5.5 SAI electrical specifications The following table describes the SAI electrical characteristics. * Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). * I/O operating voltage ranges from 2.97 V to 3.6 V * While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. Table 30. Master mode timing specifications Symbol Description Min. Max. Unit 2.97 3.6 V 40 -- ns 45% 55% MCLK period 80 -- ns 45% 55% BCLK period -- Operating voltage S1 SAI_MCLK cycle time S2 SAI_MCLK pulse width high/low S3 SAI_BCLK cycle time S4 SAI_BCLK pulse width high/low S5 SAI_RXD input setup before SAI_BCLK 28 -- ns S6 SAI_RXD input hold after SAI_BCLK 0 -- ns S7 SAI_BCLK to SAI_TXD output valid -- 8 ns S8 SAI_BCLK to SAI_TXD output invalid -2 -- ns S9 SAI_FS input setup before SAI_BCLK 28 -- ns S10 SAI_FS input hold after SAI_BCLK 0 -- ns S11 SAI_BCLK to SAI_FS output valid -- 8 ns S12 SAI_BCLK to SAI_FS output invalid -2 -- ns S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 49 Communication modules S1 S2 S2 SAI_MCLK (output) S3 SAI_BCLK (output) S4 S4 S12 S11 SAI_FS (output) S10 S9 SAI_FS (input) S7 S8 S7 S8 SAI_TXD S5 S6 SAI_RXD Figure 22. SAI Timing -- Master modes Table 31. Slave mode timing specifications Symbol -- Description Operating voltage Min. Max. Unit 2.97 3.6 V 80 -- ns 45% 55% BCLK period S13 SAI_BCLK cycle time (input) S141 SAI_BCLK pulse width high/low (input) S15 SAI_RXD input setup before SAI_BCLK 8 -- ns S16 SAI_RXD input hold after SAI_BCLK 2 -- ns S17 SAI_BCLK to SAI_TXD output valid -- 28 ns S18 SAI_BCLK to SAI_TXD output invalid 0 -- ns S19 SAI_FS input setup before SAI_BCLK 8 -- ns S20 SAI_FS input hold after SAI_BCLK 2 -- ns S21 SAI_BCLK to SAI_FS output valid -- 28 ns S22 SAI_BCLK to SAI_FS output invalid 0 -- ns 1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle input must be taken care during the board design or by the master timing. S32K1xx Data Sheet, Rev. 4, 06/2017 50 Preliminary NXP Semiconductors Communication modules S13 S14 SAI_BCLK (input) S14 S21 S22 SAI_FS (output) S19 S20 SAI_FS (input) S17 S18 S17 S18 SAI_TXD S15 S16 SAI_RXD Figure 23. SAI Timing -- Slave modes 6.5.6 Ethernet AC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. The following table describes the MII electrical characteristics. * Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). * I/O operating voltage ranges from 2.97 V to 3.6 V * While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. Table 32. MII signal switching specifications Symbol -- Description RXCLK frequency Min. Max. Unit -- 25 MHz MII1 RXCLK pulse width high 35% 65% RXCLK period MII2 RXCLK pulse width low 35% 65% RXCLK period MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 -- ns MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 -- ns TXCLK frequency -- 25 MHz -- MII5 TXCLK pulse width high 35% 65% TXCLK period MII6 TXCLK pulse width low 35% 65% TXCLK period MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 -- ns MII8 TXCLK to TXD[3:0], TXEN, TXER valid -- 25 ns S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 51 Communication modules MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 24. MII receive diagram MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 25. MII transmit signal diagram The following table describes the RMII electrical characteristics. * Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). * I/O operating voltage ranges from 2.97 V to 3.6 V * While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. Table 33. RMII signal switching specifications Symbol Min. Max. Unit -- 50 MHz RMII1, RMII5 RMII_CLK pulse width high 35% 65% RMII_CLK period RMII2, RMII6 RMII_CLK pulse width low 35% 65% RMII_CLK period -- Description RMII input clock RMII_CLK Frequency RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 -- ns RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 -- ns Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 52 Preliminary NXP Semiconductors Communication modules Table 33. RMII signal switching specifications (continued) Symbol Description Min. Max. Unit RMII7 RMII_CLK to TXD[1:0], TXEN invalid 2 -- ns RMII8 RMII_CLK to TXD[1:0], TXEN valid -- 15 ns RMII2 RMII1 RMII3 RMII4 RMII_CLK(input) RXD[n:0] Valid data CRS_DV Valid data RXER Valid data Figure 26. RMII receive diagram RMII6 RMII5 RMII_CLK (input) RMII8 RMII7 TXD[n:0] Valid data TXEN Valid data Figure 27. RMII transmit diagram The following table describes the MDIO electrical characteristics. * Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). * I/O operating voltage ranges from 2.97 V to 3.6 V * While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. * MDIO pin must have external Pull-up. Table 34. MDIO timing specifications Symbol -- Description MDC Clock Frequency Min. Max. Unit -- 2.5 MHz Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 53 Debug modules Table 34. MDIO timing specifications (continued) Symbol Description Min. Max. Unit MDC1 MDC pulse width high 40% 60% MDC period MDC2 MDC pulse width low 40% 60% MDC period MDC3 MDIO (input) to MDC rising edge setup 25 -- ns MDC4 MDIO (input) to MDC rising edge hold 0 -- ns MDC5 MDC falling edge to MDIO output valid (maximum propagation delay) -- 25 ns MDC6 MDC falling edge to MDIO output invalid (minimum propagation delay) -10 -- ns MDC1 MDC2 MDC (output) MDC6 MDIO (output) MDC5 MDIO (input) MDC3 MDC4 Figure 28. MII/RMII serial management channel timing diagram 6.5.7 Clockout frequency Maximum supported clock out frequency for this device is 20 MHz 6.6 Debug modules 6.6.1 SWD electrical specofications S32K1xx Data Sheet, Rev. 4, 06/2017 54 Preliminary NXP Semiconductors Symbol Description Run Mode 5.0 V IO HSRUN Mode 3.3 V IO 5.0 V IO VLPR Mode 3.3 V IO 5.0 V IO Unit 3.3 V IO Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary 25 - 25 - 25 - 10 - 10 MHz S2 SWD_CLK cycle period 1/S1 - 1/S1 - 1/S1 - 1/S1 - 1/S1 - 1/S1 - ns S3 SWD_CLK clock pulse width S4 SWD_CLK rise and fall times - 1 - 1 - 1 - 1 - 1 - 1 ns S9 SWD_DIO input data setup time to SWD_CLK rise 4 - 4 - 4 - 4 - 16 - 16 - ns S10 SWD_DIO input data hold time after SWD_CLK rise 3 - 3 - 3 - 3 - 10 - 10 - ns S11 SWD_CLK high to SWD_DIO data valid - 28 - 38 - 28 - 38 - 70 - 77 ns S12 SWD_CLK high to SWD_DIO high-Z - 28 - 38 - 28 - 38 - 70 - 77 ns S13 SWD_CLK high to SWD_DIO data invalid 0 - 0 - 0 - 0 - 0 - 0 - ns ns S2/2 + 5 S2/2 - 5 S2/2 - 5 S2/2 - 5 S2/2 - 5 S2/2 - 5 S2/2 + 5 - S2/2 + 5 25 S2/2 + 5 - S2/2 + 5 SWD_CLK frequency of operation S2/2 + 5 S1 S2/2 - 5 NXP Semiconductors Table 35. SWD electrical specifications Debug modules 55 Debug modules S2 S3 S3 SWD_CLK (input) S4 S4 Figure 29. Serial wire clock input timing SWD_CLK S9 SWD_DIO S10 Input data valid S11 S13 SWD_DIO Output data valid S12 SWD_DIO Figure 30. Serial wire data timing 6.6.2 Trace electrical specifications The following table describes the Trace electrical characteristics. * Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). * While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. Table 36. Trace specifications Symbol -- Fsys Description System frequency RUN Mode 80 48 HSRUN Mode 40 112 80 VLPR Mode Unit 4 MHz Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 56 Preliminary NXP Semiconductors Debug modules Table 36. Trace specifications (continued) Symbol Trace on fast pads fTRACE RUN Mode Max Trace frequency 80 HSRUN Mode VLPR Mode Unit 48 40 74.667 80 4 MHz tDVO Data Output Valid 4 4 4 4 4 20 ns tDIV Data Output Invalid -2 -2 -2 -2 -2 -10 ns 24 20 22.4 22.86 4 MHz fTRACE Trace on slow pads Description Max Trace frequency 22.86 tDVO Data Output Valid 8 8 8 8 8 20 ns tDIV Data Output Invalid -4 -4 -4 -4 -4 -10 ns Figure 31. TRACE CLKOUT specifications 6.6.3 JTAG electrical specifications S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 57 Symbol Description Run Mode 5.0 V IO Min. 3.3 V IO Max. Min. 5.0 V IO Max. Min. VLPR Mode 3.3 V IO Max. Min. 5.0 V IO Max. Min. Unit 3.3 V IO Max. Min. Max. TCLK frequency of operation MHz Boundary Scan - 20 - 20 - 20 - 20 - 10 - 10 JTAG - 20 - 20 - 20 - 20 - 10 - 10 - 1/JI - 1/JI - 1/JI - 1/JI - 1/JI - Preliminary J2/2 + 5 J2/2 - 5 J2/2 + 5 J2/2 - 5 J2/2 + 5 J2/2 - 5 S32K1xx Data Sheet, Rev. 4, 06/2017 JTAG J2/2 + 5 Boundary Scan ns ns J2/2 - 5 TCLK clock pulse width J2/2 + 5 J3 1/JI J2/2 - 5 TCLK cycle period J2/2 + 5 J2 J2/2 - 5 JI HSRUN Mode NXP Semiconductors J4 TCLK rise and fall times - 1 - 1 - 1 - 1 - 1 - 1 ns J5 Boundary scan input data setup time to TCLK rise 5 - 5 - 5 - 5 - 15 - 15 - ns J6 Boundary scan input data hold time after TCLK rise 5 - 5 - 5 - 5 - 8 - 8 - ns J7 TCLK low to boundary scan output data valid - 28 - 32 - 28 - 32 - 80 - 80 ns J8 TCLK low to boundary scan output data invalid 0 - 0 - 0 - 0 - 0 - 0 - J9 TCLK low to boundary scan output high-Z - 28 - 32 - 28 - 32 - 80 - 80 ns J10 TMS, TDI input data setup time to TCLK rise 3 - 3 - 3 - 3 - 15 - 15 - ns J11 TMS, TDI input data hold time after TCLK rise 2 - 2 - 2 - 2 - 8 - 8 - ns J12 TCLK low to TDO data valid - 28 - 32 - 28 - 32 - 80 - 80 ns J13 TCLK low to TDO data invalid 0 - 0 - 0 - 0 - 0 - 0 - ns J14 TCLK low to TDO high-Z - 28 - 32 - 28 - 32 - 80 - 80 ns Debug modules 58 Table 37. JTAG electrical specifications Debug modules J2 J3 J3 TCLK (input) J4 J4 Figure 32. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 J8 Data outputs Output data valid J9 Data outputs Figure 33. Boundary scan (JTAG) timing S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 59 Thermal attributes TCLK J10 TDI/TMS J11 Input data valid J12 J13 TDO Output data valid J14 TDO Figure 34. Test Access Port timing 7 Thermal attributes 7.1 Description The tables in the following sections describe the thermal characteristics of the device. NOTE Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting side (board) temperature, ambient temperature, air flow, power dissipation or other components on the board, and board thermal resistance. 7.2 Thermal characteristics S32K1xx Data Sheet, Rev. 4, 06/2017 60 Preliminary NXP Semiconductors NXP Semiconductors Table 38. Thermal characteristics for the 64/100/144/176-pin LQFP package Rating Conditions Symbol Packages Values S32K11x S32K142 S32K144 Thermal resistance, Junction to Ambient (Natural Convection)1, 2 Thermal resistance, Junction to Ambient (Natural Convection)1 Preliminary S32K1xx Data Sheet, Rev. 4, 06/2017 Thermal resistance, Junction to Ambient (Natural Convection)1, 2 Thermal resistance, Junction to Ambient (@200 ft/min)1, 3 Thermal resistance, Junction to Ambient (@200 ft/min)1 Thermal resistance, Junction to Ambient (@200 ft/min)1, 3 Two layer board (1s1p) Four layer board (2s2p) Single layer board (1s) Two layer board (1s1p) Four layer board (2s2p) -- RJA RJA RJA RJMA RJMA RJMA RJB S32K146 S32K148 64 TBD 61 61 59 NA C/W 100 TBD 53 52 21 NA C/W 144 TBD NA NA 51 44 C/W 176 TBD NA NA NA 42 C/W 64 TBD 45 45 44 NA C/W 100 TBD 42 42 40 NA C/W 144 TBD NA NA 44 37 C/W 176 TBD NA NA NA 36 C/W 64 TBD 43 43 41 NA C/W 100 TBD 40 40 39 NA C/W 144 TBD NA NA 42 36 C/W 176 TBD NA NA NA 35 C/W 64 TBD 49 49 48 NA C/W 100 TBD 43 42 41 NA C/W 144 TBD NA NA 42 36 C/W 176 TBD NA NA NA 34 C/W 64 TBD 38 38 37 NA C/W 100 TBD 35 35 34 NA C/W 144 TBD NA NA 37 31 C/W 176 TBD NA NA NA 30 C/W 64 TBD 36 36 35 NA C/W 100 TBD 34 34 33 NA C/W 144 TBD NA NA 36 30 C/W 176 TBD NA NA NA 29 C/W 64 TBD 25 25 23 NA C/W 100 TBD 25 25 24 NA C/W 144 TBD NA NA 30 24 C/W 176 TBD NA NA NA 24 C/W 61 Table continues on the next page... Thermal attributes Thermal resistance, Junction to Board4 Single layer board (1s) Unit Rating Conditions Symbol Packages Values S32K11x S32K142 S32K144 Thermal resistance, Junction to Case 5 Thermal resistance, Junction to Package Top6 Preliminary S32K1xx Data Sheet, Rev. 4, 06/2017 1. 2. 3. 4. 5. 6. -- Natural Convection RJC JT Unit S32K146 S32K148 64 TBD 13 12 11 NA C/W 100 TBD 13 12 11 NA C/W 144 TBD NA NA 12 9 C/W 176 TBD NA NA NA 9 C/W 64 TBD 2 2 2 NA C/W 100 TBD 2 2 2 NA C/W 144 TBD NA NA 2 1 C/W 176 TBD NA NA NA 1 C/W Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Thermal attributes 62 Table 38. Thermal characteristics for the 64/100/144/176-pin LQFP package (continued) NXP Semiconductors NXP Semiconductors Table 39. Thermal characteristics for the 100 MAPBGA package Rating Conditions Symbol Values Unit S32K146 S32K144 S32K148 Thermal resistance, Junction to Ambient (Natural Convection) 1, 2 Single layer board (1s) RJA 57.2 61.0 52.5 C/W Thermal resistance, Junction to Ambient (Natural Convection) 1, 2, 3 Four layer board (2s2p) RJA 32.1 35.6 27.5 C/W RJMA 44.1 46.6 39.0 C/W RJMA 27.2 30.9 22.8 C/W Thermal resistance, Junction to Ambient (@200 ft/min) 1, 2, 3 Single layer board (1s) Thermal resistance, Junction to Ambient (@200 ft/min)1, 3 Two layer board (2s2p) S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary Thermal resistance, Junction to Board4 -- RJB 15.3 18.9 11.2 C/W 5 -- RJC 10.2 14.2 7.5 C/W Thermal resistance, Junction to Package Top outside center6 -- JT 0.2 0.4 0.2 C/W Thermal resistance, Junction to Package Bottom outside center7 -- JB 12.2 15.9 18.3 C/W Thermal resistance, Junction to Case 1. 2. 3. 4. 5. 6. 7. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. Thermal attributes 63 Thermal attributes 7.3 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from this equation: where: * TA = ambient temperature for the package (C) * RJA = junction to ambient thermal resistance (C/W) * PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: where: * RJA = junction to ambient thermal resistance (C/W) * RJC = junction to case thermal resistance (C/W) * RCA = case to ambient thermal resistance (C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. S32K1xx Data Sheet, Rev. 4, 06/2017 64 Preliminary NXP Semiconductors Dimensions To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: where: * TT = thermocouple temperature on top of the package (C) * JT = thermal characterization parameter (C/W) * PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 8 Dimensions 8.1 Obtaining package dimensions Package dimensions are provided in the package drawings. To find a package drawing, go to http://www.nxp.com and perform a keyword search for the drawing's document number: Package option Document Number 32-pin QFN SOT617-3 1 48-pin LQFP 98ASH00962A 64-pin LQFP 98ASS23234W 100-pin LQFP 98ASS23308W 100 MAP BGA 98ASA00802D 144-pin LQFP 98ASS23177W 176-pin LQFP 98ASS23479W 1. 5x5 mm package S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 65 Pinouts 9 Pinouts 9.1 Package pinouts and signal descriptions For package pinouts and signal descriptions, refer to the Reference Manual. 10 Revision History The following table provides a revision history for this document. Table 40. Revision History Rev. No. Date 1 12 Aug 2016 2 03 March 2017 Substantial Changes Initial release * * * * * * * * * * * * * Updated descpition of QSPI and Clock interfaces in Key Features section Updated figure: High-level architecture diagram for the S32K1xx family Updated figure: S32K1xx product series comparison Added note in section Determining valid orderable parts Updated figure: Ordering information In table: Absolute maximum ratings : * Added footnote to IINJPAD_DC * Updated min and max value of IINJPAD_DC * Updated description, max and min values for IINJSUM * Updated VIN_TRANSIENT In table: Voltage and current operating requirements : * Renamed VSUP_OFF * Updated max value of VDD_OFF * Removed VINA and VIN * Added VREFH and VREFL * Updated footnote "Typical conditions assumes VDD = VDDA = VREFH = 5 V ... * Removed INJSUM_AF Updated footnotes in table Table 4 Updated section Power mode transition operating behaviors In table: Power consumption * Added footnote "With PMC_REGSC[CLKBIASDIS] ... " * Updated conditions for VLPR * Removed Idd/MHz for S32K144 * Updated numbers for S32K142 and S32K148 * Removed use case footnotes In section Modes configuration : * Replaced table "Modes configuration" with spreadsheet attachment: 'S32K1xx_Power_Modes _Master_configuration_sheet' In table: DC electrical specifications at 3.3 V Range : * Added footnotes to Vih Input Buffer High Voltage and Vih Input Buffer Low Voltage * Added footnote to High drive port pins In table: DC electrical specifications at 5.0 V Range : Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 66 Preliminary NXP Semiconductors Revision History Table 40. Revision History Rev. No. Date Substantial Changes * * * * * * * * * * * * * * * Added footnotes Vih Input Buffer High Voltage and Vih Input Buffer Low Voltage Updated table: AC electrical specifications at 3.3 V range Updated table: AC electrical specifications at 5 V range In table: Standard input pin capacitance * Added footnote to Normal run mode (S32K14x series) Removed note from 1M ohms Feedback Resistor in figure Oscillator connections scheme In table: External System Oscillator electrical specifications * Updated typical of IDDOSC Supply current -- low-gain mode (low-power mode) (HGO=0) 1 for 4 and 8 MHz * Removed rows for Ilk_ext EXTAL/XTAL impedence High-frequency, lowgain mode (low-power mode) and high-frequency, high-gain mode and VEXTAL * Updated Typ. of RS low-gain mode * Updated description of RF, RS, and VPP * Removed footnote from RF Feedback resistor * Updated footnote for C1 C2 and RF In table: Table 16 * Removed mention of high-frequency * Added HGO 0, 1 information In table: Fast internal RC Oscillator electrical specifications * Updated FFIRC * Updated description of F * Updated typ and max values of TJIT cycle-to-cycle jitter and TJIT Long term jitter over 1000 cycles * Added footnotes to TJIT cycle-to-cycle jitter and TJIT Long term jitter over 1000 cycles * Updated naming convention of IDDFIRC Supply current * Added footnote to IDDFIRC Supply current * Added footnote to column Parameter In table: Slow internal RC oscillator (SIRC) electrical specifications * Removed VDD Supply current in 2 MHz Mode * Removed footnote and updated description of F * Updated footnote to FSIRC and IDDSIRC In table: SPLL electrical specifications * Added row for FSPLL_REF PLL Reference * Updated naming convention throughout the table * Updated the max value of TSPLL_LOCK Lock detector detection time In table: Table 21 * Added footnotes: * All command times assumes ... * For all EEPROM Emulation terms ... * 'First time' EERAM writes after a POR ... * Removed footnote 'Assumes 25 MHz or ...' * Updated Max of teewr32bers * Added parameters tquickwr and tquickwrClnup In table: Table 22 * Removed Typ. values for all parameters * Removed footnote 'Typical values represent ... ' * Added footnote 'Any other EEE driver usage ... ' Updated QuadSPI AC specifications Removed topic: Reliability, Safety and Security modules In table: 12-bit ADC operating conditions * Updated VDDA Table continues on the next page... S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 67 Revision History Table 40. Revision History (continued) Rev. No. Date Substantial Changes * * * * * * * * * * * 3 14 March 2017 4 02 June 2017 * Updated values for VREFH and VREFL to add refernce to the section "voltage and current operating requirments" for Min and Max valaues * Updated footnote to Typ. * Removed footnote from RAS Analog source resistance * Updated figure: ADC input impedance equivalency diagram In table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS) * Removed rows for VTEMP_S and VTEMP25 * Updated footnote to Typ. In table: 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS) * Removed rows for VTEMP_S and VTEMP25 * Removed number for TUE * Updated footnote to Typ. In table: Comparator with 8-bit DAC electrical specifications * Updated Typ. of IDDLS Supply current, Low-speed mode * Updated Typ. of tDLSB Propagation delay, Low-speed mode * Updated Typ. of tDHSS Propagation delay, High-speed mode * Updated tDLSS Propagation delay * Added row for tDDAC Initialization and switching settling time * Updated footnote Updated section LPSPI electrical specifications Added section: SAI electrical specifications Updated section: Ethernet AC specifications Added section: Clockout frequency Added section: Trace electrical specifications Updated table: Table 38 : Updated numbers for S32K142 and S32K148 Updated table: Table 39 : Updated numbers for S32K148 Updated Document number for 32-pin QFN in topic Obtaining package dimensions * In Table 2 * Updated min. value of VDD_OFF * Added parameter IINJSUM_AF * Updated Power mode transition operating behaviors * Updated Power consumption * Updated footnote to TSPLL_LOCK in SPLL electrical specifications * In 12-bit ADC electrical characteristics * Updated table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS) * Added typ. value to IDDA_ADC, TUE, DNL, and INL * Added min. value to SMPLTS * Removed footnote 'All the parameters in this table ... ' * Updated table: 12-bit ADC characteristics (3 V to 5.5 V) (VREFH = VDDA, VREFL = VSS) * Added typ. value to IDDA_ADC * Removed footnote 'All the parameters in this table ... ' * In Table 21 updated Max. value of tvfykey to 33 s * In section: Block diagram, added block diagram for S32K11x series. * Updated figure: S32K1xx product series comparison. * In section: Determining valid orderable parts , added reference to attachement S32K_Part_Numbers.xlsx. * In section: Ordering information * Updated figure: Ordering information. * In Table 1, S32K1xx Data Sheet, Rev. 4, 06/2017 68 Preliminary NXP Semiconductors Revision History Table 40. Revision History Rev. No. Date Substantial Changes * * * * * * * * * * * * * * * * * * Updated note 'All the limits defined ... ' * Updated parameter 'IINJPAD_DC_ABS', 'VIN_DC', IINJSUM_DC_ABS. In Table 2, * Updated parameter IINJPAD_DC_OP and IINJSUM_DC_OP. In Table 5, updated TBDs for VLVR_HYST, VLVD_HYST, and VLVW_HYST In Table 6, * Added VLPR VLPS * Added VLPS VLPR * Updated TBDs for VLPS Asynchronous DMA Wakeup, STOP1 Asynchronous DMA Wakeup, and STOP2 Asynchronous DMA Wakeup In Table 7, updated the specifications for S32K144. Updated the attachment S32K1xx_Power_Modes _Configuration.xlsx. In Table 13, removed CIN_A. In Table 15, * Updated specificatins for gmXOSC. * Removed IDDOSC In Table 17, * Added parameter F125. * Removed IDDFIRC In Table 18, * Added parameter F125. * Removed IDDSIRC In Table 19, removed ILPO Updated section: Flash memory module (FTFC) electrical specifications In section: 12-bit ADC operating conditions, * Updated TBDs for IDDA_ADC and TUE in Table 25 * Updated TBDs for IDDA_ADC and TUE in Table 26 In section: QuadSPI AC specifications, updated figure 'QuadSPI output timing (HyperRAM mode) diagram'. In section: 12-bit ADC operating conditions, updated Table 24. In section: CMP with 8-bit DAC electrical specifications, added note 'For comparator IN signals adjacent ... ' In table: Table 29, minor update in footnote 6. In table: Table 38, updated specifications for S32K146. S32K1xx Data Sheet, Rev. 4, 06/2017 NXP Semiconductors Preliminary 69 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. 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ARM, AMBA, ARM Powered, Artisan, Cortex, Jazelle, Keil, SecurCore, Thumb, TrustZone, and Vision are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. ARM7, ARM9, ARM11, big.LITTLE, CoreLink, CoreSight, DesignStart, Mali, mbed, NEON, POP, Sensinode, Socrates, ULINK and Versatile are trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. (c) 2015-2017 NXP B.V. Document Number S32K1XX Revision 4, 06/2017 Preliminary