ISO7221xD
1
2
3
4 5
6
7
8
GND2
INB
VCC2
VCC1
OUTB
GND1
INA
OUTA
Isolation
ISO7220xD
1
2
3
4 5
6
7
8
GND2
INB
VCC2
VCC1
OUTB
GND1
OUTA
INA
Isolation
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
DUAL DIGITAL ISOLATORS
Check for Samples: ISO7220A,ISO7220B,ISO7220C,ISO7220M,ISO7221A,ISO7221B,ISO7221C,ISO7221M
1FEATURES
2•1, 5, 25, and 150-Mbps Signaling Rate Options •4 kV ESD Protection
–Low Channel-to-Channel Output Skew; •High Electromagnetic Immunity
1 ns max • –40°C to 125°C Operating Range
–Low Pulse-Width Distortion (PWD);
1 ns max APPLICATIONS
–Low Jitter Content; 1 ns Typ at 150 Mbps •Industrial Fieldbus
•Typical 25-Year Life at Rated Voltage –Modbus
(see app. note SLLA197 and Figure 20)–Profibus™
•4000-VPK VIOTM, 560 VPK VIORM per IEC –DeviceNet™Data Buses
60747-5-2 (VDE 0884, Rev2) •Computer Peripheral Interface
•UL 1577, IEC 61010-1, IEC 60950-1 and CSA •Servo Control Interface
Approved •Data Acquisition
•50 kV/μs Typical Transient Immunity
•Operates with 2.8-V (C-Grade), 3.3-V or 5-V
Supplies
DESCRIPTION
The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented
in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input
and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to
4000 VPK. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds,
and prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or
damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be
unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
The small capacitance and resulting time constant provide fast operation with signaling rates available from 0
Mbps (dc) to 150 Mbps.(1) The A-, B- and C-option devices have TTL input thresholds and a noise filter at the
input that prevents transient pulses from being passed to the output of the device. The M-option devices have
CMOS VCC/2 input thresholds and do not have the input noise-filter and the additional propagation delay.
(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DeviceNet is a trademark of Open DeviceNet Vendors Association.
PRODUCTION DATA information is current as of publication date. Copyright ©2006–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Input
+
Filter
GalvanicIsolation
Barrier
Vref
Vref
DataMUX
OUT
IN
OSC
+
PWM
ACDetect
OutputBuffer
DCChannel
ACChannel
Filter
PulseWidth
Demodulation
CarrierDetect
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
These devices require two supply voltages of 2.8 V (C-Grade), 3.3 V, 5 V, or any combination. All inputs are 5-V
tolerant when supplied from a 2.8-V or 3.3-V supply and all outputs are 4-mA CMOS.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
SINGLE-CHANNEL FUNCTION DIAGRAM
AVAILABLE OPTIONS
MAX INPUT CHANNEL MARKED ORDERING
PRODUCT SIGNALING PACKAGE THRESHOLD DIRECTION AS NUMBER
RATE
ISO7220AD (rail)
≉1.5 V (TTL)
ISO7220A 1 Mbps SOIC-8 I7220A
(CMOS compatible) ISO7220ADR (reel)
ISO7220BD (rail)
≉1.5 V (TTL)
ISO7220B 5 Mbps SOIC-8 I7220B
(CMOS compatible ISO7220BDR (reel)
Same direction ISO7220CD (rail)
≉1.5 V (TTL)
ISO7220C 25 Mbps SOIC-8 I7220C
(CMOS compatible) ISO7220CDR (reel)
ISO7220MD (rail)
ISO7220M 150 Mbps SOIC-8 VCC/2 (CMOS) I7220M ISO7220MDR (reel)
ISO7221AD (rail)
≉1.5 V (TTL)
ISO7221A 1 Mbps SOIC-8 I7221A
(CMOS compatible) ISO7221ADR (reel)
ISO7221BD (rail)
≉1.5 V (TTL)
ISO7221B 5 Mbps SOIC-8 I7221B
(CMOS compatible) ISO7221ABR (reel)
Opposite directions ISO7221CD (rail)
≉1.5 V (TTL)
ISO7221C 25 Mbps SOIC-8 I7221C
(CMOS compatible) ISO7221CDR (reel)
ISO7221MD (rail)
ISO7221M 150 Mbps SOIC-8 VCC/2 (CMOS) I7221M ISO7221MDR (reel)
2Copyright ©2006–2012, Texas Instruments Incorporated
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
REGULATORY INFORMATION
VDE CSA UL
Approved under CSA Component Recognized under UL 1577 Component
Certified according to IEC 60747-5-2 Acceptance Notice 5A Recognition Program
Basic Insulation Evaluated to CSA 60950-1-07 and IEC 60950-1 (2nd
Maximum Transient Overvoltage, 4000 VPK Ed.) for products with working voltages ≤125 VRMS for Single Protection, 2500 VRMS(1)
Maximum Surge Voltage, 4000 VPK reinforced insulation or ≤400 VRMS for basic insulation
Maximum Working Voltage, 560 VPK
File Number: 40016131 File Number: 220991 File Number: E181974
(1) Production tested ≥3000 VRMS for 1 second in accordance with UL 1577.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
VCC Supply voltage(2), VCC1, VCC2 –0.5 to 6 V
VIVoltage at IN, OUT –0.5 to 6 V
IOOutput current ±15 mA
Electrostatic discharge JEDEC Standard 22,
Human Body Model ±4
Test Method A114-C.01 kV
Electrostatic
ESD All pins
discharge Field-Induced-Charged Device Model JEDEC Standard 22, Test Method C101 ±1
Machine Model ANSI/ESDS5.2-1996 ±200 V
TJMaximum junction temperature 170 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
ISO722xA, ISO722xB, 3 5.5
ISO722xM
VCC Supply voltage(1), VCC1, VCC2 V
ISO722xC 2.8 5.5
IOH High-level output current -4 mA
IOL Low-level output current 4 mA
ISO722xA 1 0.67 μs
ISO722xB 200 100
tui Input pulse width(2) ISO722xC 40 33 ns
ISO722xM 6.67 5
ISO722xA 0 1500 1000 kbps
ISO722xB 0 10 5
1/tui Signaling rate(2) ISO722xC 0 30 25 Mbps
ISO722xM 0 200 150
VIH High-level input voltage 2 VCC V
ISO722xA, ISO722xB,
ISO722xC
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 0.7 VCC VCC V
ISO722xM
VIL Low-level input voltage 0 0.3 VCC V
TJJunction temperature –40 150 °C
H External magnetic field-strength immunity per IEC 61000-4-8 &IEC 61000-4-9 certification 1000 A/m
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
For the 2.8-V operation, VCC1 or VCC2 is specified at 2.8 V.
(2) Typical signaling rate and Input pulse width are measured at ideal conditions at 25°C.
Copyright ©2006–2012, Texas Instruments Incorporated 3
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISO7220x 1 2
Quiescent VI= VCC or 0 V, no load
ISO7221 8.5 17
ISO7220A, ISO7220B 2 3
ICC1 1 Mbps 0.5 MHz Input Clock Signal, no load
ISO7221A, ISO7221B 10 18
ISO7220C, ISO7220M 4 9
12.5 MHz Input Clock Signal, no
25 Mbps load
ISO7221C, ISO7221M 12 22 mA
ISO7220x 16 31
Quiescent VI= VCC or 0 V, no load
ISO7221x 8.5 17
ISO7220A, ISO7220B 17 32
ICC2 1 Mbps 0.5 MHz Input Clock Signal, no load
ISO7221A, ISO7221B 10 18
ISO7220C, ISO7220M 20 34
12.5 MHz Input Clock Signal, no
25 Mbps load
ISO7221C, ISO7221M 12 22
IOH =–4 mA, See Figure 1 VCC –0.8 4.6
VOH High-level output voltage V
IOH =–20 μA, See Figure 1 VCC –0.1 5
IOL = 4 mA, See Figure 1 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA, See Figure 1 0 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V to VCC μA
IIL Low-level input current –10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 1 pF
CMTI Common-mode transient immunity VI= VCC or 0 V, See Figure 3 25 50 kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH,Propagation delay 280 405 475
tpHL ISO722xA
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 14
tpLH,Propagation delay 42 55 70
tpHL ISO722xB
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 3
See Figure 1 ns
tpLH,Propagation delay 22 32 42
tpHL ISO722xC
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 2
tpLH,Propagation delay 6 10 16
tpHL ISO722xM
PWD Pulse-width distortion |tpHL –tpLH|(1) 0.5 1
ISO722xA 180
ISO722xB 17
tsk(pp) Part-to-part skew (2) ns
ISO722xC 10
ISO722xM 3
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4Copyright ©2006–2012, Texas Instruments Incorporated
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO722xA 3 15 ns
tsk(o) Channel-to-channel output skew (3) ISO722xB 0.6 3
ISO722xC/M 0.2 1
trOutput signal rise time 1
See Figure 1 ns
tfOutput signal fall time 1
tfs Failsafe output delay time from input power loss See Figure 2 3μs
150 Mbps PRBS NRZ data, 5-bit max
same polarity input, both channels, See 1
Figure 4,Figure 17
tjit(pp) Peak-to-peak eye-pattern jitter ISO722xM ns
150 Mbps unrestricted bit run length 2
data input, both channels, See Figure 4
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISO7220x 1 2
Quiescent VI= VCC or 0 V, no load
ISO7221x 8.5 17
ISO7220A, ISO7220B 2 3
0.5 MHz Input Clock Signal, no
ICC1 1 Mbps load
ISO7221A, ISO7221B 10 18
ISO7220C, ISO7220M 4 9
12.5 MHz Input Clock Signal,
25 Mbps no load
ISO7221C, ISO7221M 12 22 mA
ISO7220x 8 18
Quiescent VI= VCC or 0 V, no load
ISO7221x 4.3 9.5
ISO7220A, ISO7220B 9 19
0.5 MHz Input Clock Signal, no
ICC2 1 Mbps load
ISO7221A, ISO7221B 5 11
ISO7220C, ISO7220M 10 20
12.5 MHz Input Clock Signal,
25 Mbps no load
ISO7221C, ISO7221M 6 12
ISO7220x IOH =–4 mA, See Figure 1 VCC –0.4
VOH High-level output voltage ISO7221x (5-V side) VCC –0.8 V
IOH =–20 μA, See Figure 1 VCC –0.1
IOL = 4 mA, See Figure 1 0.4
VOL Low-level output voltage V
IOL = 20 μA, See Figure 1 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V to VCC μA
IIL Low-level input current –10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 1 pF
CMTI Common-mode transient immunity VI= VCC or 0 V, See Figure 3 15 40 kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
Copyright ©2006–2012, Texas Instruments Incorporated 5
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH,Propagation delay 285 410 480
tpHL ISO722xA
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 14
tpLH,Propagation delay 45 58 75
tpHL ISO722xB
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 3
See Figure 1 ns
tpLH,Propagation delay 25 36 48
tpHL ISO722xC
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 2
tpLH,Propagation delay 7 12 20
tpHL ISO722xM
PWD Pulse-width distortion |tpHL –tpLH|(1) 0.5 1
ISO722xA 180
ISO722xB 17
tsk(pp) Part-to-part skew (2) ISO722xC 10
ISO722xM 5 ns
ISO722xA 3 15
tsk(o) Channel-to-channel output skew (3) ISO722xB 0.6 3
ISO722xC/M 0.2 1
trOutput signal rise time 2
See Figure 1 ns
tfOutput signal fall time 2
tfs Failsafe output delay time from input power loss See Figure 2 3μs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See Figure 4, 1
Figure 17
tjit(pp) Peak-to-peak eye-pattern jitter ISO722xM ns
150 Mbps unrestricted bit run length data 2
input, both channels, See Figure 4
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
6Copyright ©2006–2012, Texas Instruments Incorporated
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISO7220x 0.6 1
Quiescent VI= VCC or 0 V, no load
ISO7221x 4.3 9.5
ISO7220A, ISO7220B 1 2
ICC1 1 Mbps 0.5 MHz Input Clock Signal, no load
ISO7221A, ISO7221B 5 11
ISO7220C, ISO7220M 2 4
25 Mbps 12.5 MHz Input Clock Signal, no load
ISO7221C, ISO7221M 6 12 mA
ISO7220x 16 31
Quiescent VI= VCC or 0 V, no load
ISO7221x 8.5 17
ISO7220A, ISO7220B 18 32
ICC2 1 Mbps 0.5 MHz Input Clock Signal, no load
ISO7221A, ISO7221B 10 18
ISO7220C, ISO7220M 20 34
25 Mbps 12.5 MHz Input Clock Signal, no load
ISO7221C, ISO7221M 12 22
ISO7220x VCC –0.8
IOH =–4 mA, See Figure 1
ISO7221x
VOH High-level output voltage VCC –0.4
(3.3-V side) V
IOH =–20 μA, See Figure 1 VCC –0.1
IOL = 4 mA, See Figure 1 0.4
VOL Low-level output voltage IOL = 20 μA, See Figure 1 0 0.1
VI(HYS) Input threshold voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V or VCC μA
IIL Low-level input current –10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 1 pF
CMTI Common-mode transient immunity VI= VCC or 0 V, See Figure 3 15 40 kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
Copyright ©2006–2012, Texas Instruments Incorporated 7
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH,Propagation delay 285 395 480
tpHL ISO722xA
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 18
tpLH,Propagation delay 45 58 75
tpHL ISO722xB
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 4
See Figure 1
tpLH,Propagation delay 25 36 48
tpHL ISO722xC
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 3
tpLH,Propagation delay 7 12 21
tpHL ISO722xM ns
PWD Pulse-width distortion |tpHL –tpLH|(1) 0.5 1
ISO722xA 190
ISO722xB 17
tsk(pp) Part-to-part skew (2) ISO722xC 10
ISO722xM 5
ISO722xA 3 15
tsk(o) Channel-to-channel output skew (3) ISO722xB 0.6 3
ISO7220C/M 0.2 1
trOutput signal rise time 1
See Figure 1
tfOutput signal fall time 1
tfs Failsafe output delay time from input power loss See Figure 2 3μs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See Figure 4, 1
Figure 17
tjit(pp) Peak-to-peak eye-pattern jitter ISO722xM ns
150 Mbps unrestricted bit run length data input, 2
both channels, See Figure 4
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
8Copyright ©2006–2012, Texas Instruments Incorporated
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISO7220x 0.6 1
Quiescent VI= VCC or 0 V, no load
ISO7221x 4.3 9.5
ISO7220A, ISO7220B 1 2
ICC1 1 Mbps 0.5 MHz Input Clock Signal, no load
ISO7221A, ISO7221B 5 11
ISO7220C, ISO7220M 2 4
25 Mbps 12.5 MHz Input Clock Signal, no load
ISO7221C, ISO7221M 6 12 mA
ISO7220x 8 18
Quiescent VI= VCC or 0 V, no load
ISO7221x 4.3 9.5
ISO7220A, ISO7220B 9 19
ICC2 1 Mbps 0.5 MHz Input Clock Signal, no load
ISO7221A, ISO7221B 5 11
ISO7220C, ISO7220M 10 20
25 Mbps 12.5 MHz Input Clock Signal, no load
ISO7221C, ISO7221M 6 12
IOH =–4 mA, See Figure 1 VCC –0.4 3
VOH High-level output voltage IOH =–20 μA, See Figure 1 VCC –0.1 3.3 V
IOL = 4 mA, See Figure 1 0.2 0.4
VOL Low-level output voltage IOL = 20 μA, See Figure 1 0 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V or VCC μA
IIL Low-level input current –10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 1 pF
CMTI Common-mode transient immunity VI= VCC or 0 V, See Figure 3 15 40 kV/μs
(1) For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
Copyright ©2006–2012, Texas Instruments Incorporated 9
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH,Propagation delay 290 400 485
tpHL ISO722xA
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 18
tpLH,Propagation delay 46 62 78
tpHL ISO722xB
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 4
See Figure 1
tpLH,Propagation delay 26 40 52
tpHL ISO722xC
PWD Pulse-width distortion |tpHL –tpLH|(1) 1 3
tpLH,Propagation delay 8 16 25
tpHL ISO722xM ns
PWD Pulse-width distortion |tpHL –tpLH|(1) 0.5 1
ISO722xA 190
ISO722xB 17
tsk(pp) Part-to-part skew(2) ISO722xC 10
ISO722xM 5
ISO722xA 3 15
tsk(o) Channel-to-channel output skew (3) ISO722xB 0.6 3
ISO722xC/M 0.2 1
trOutput signal rise time 2
See Figure 1
tfOutput signal fall time 2
tfs Failsafe output delay time from input power loss See Figure 2 3μs
150 Mbps PRBS NRZ data, 5-bit max same
polarity input, both channels, See Figure 4, 1
Figure 17
tjit(pp) Peak-to-peak eye-pattern jitter ISO722xM ns
150 Mbps unrestricted bit run length data 2
input, both channels, See Figure 4
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
10 Copyright ©2006–2012, Texas Instruments Incorporated
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 2.8 V (ISO722xC-only)(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISO7220C 0.4 0.9
Quiescent VI= VCC or 0 V, no load
ISO7221C 3.7 7.5
ICC1 ISO7220C 1.5 3.5
25 Mbps 12.5 MHz Input Clock Signal, no load
ISO7221C 4.5 10 mA
ISO7220C 6.8 15
Quiescent VI= VCC or 0 V, no load
ISO7221C 3.7 7.5
ICC2 ISO7220C 9 17
25 Mbps 12.5 MHz Input Clock Signal, no load
ISO7221C 4.5 10
IOH =–4 mA, See Figure 1 VCC –0.6 2.55
VOH High-level output voltage IOH =–20 μA, See Figure 1 VCC –0.1 2.8 V
IOL = 4 mA, See Figure 1 0.25 0.6
VOL Low-level output voltage IOL = 20 μA, See Figure 1 0 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V or VCC μA
IIL Low-level input current –10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 1 pF
CMTI Common-mode transient immunity VI= VCC or 0 V, See Figure 3 10 30 kV/μs
(1) 2.8-V operation is only guaranteed for ISO722xC with production screening starting in January 2012. The first two digits of the Lot Trace
Code (YMSLLLLG4) written on top of each device can be used to identify year and month of production respectively.
Copyright ©2006–2012, Texas Instruments Incorporated 11
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 2.8 V operation, over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH,Propagation delay 26 45 65
tpHL ISO722xC See Figure 1
PWD Pulse-width distortion |tpHL –tpLH|(1) 1.5 5
tsk(pp) Part-to-part skew(2) ISO722xC 12 ns
tsk(o) Channel-to-channel output skew (3) ISO722xC 0.2 5
trOutput signal rise time 2
See Figure 1
tfOutput signal fall time 2
tfs Failsafe output delay time from input power loss See Figure 2 4.6 μs
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
12 Copyright ©2006–2012, Texas Instruments Incorporated
IN OUT
VOCL
Input
Generator 50 W
VI
NOTE A NOTE B
V /2
CC
tf
tr
10%
90%
50%
0 V
50%
VI
tPLH tPHL
VOH
VOL
ISOLATION BARRIER
VO
V /2
CC
VCC
tfs
FAILSAFE HIGH
OUT
ISOLATION BARRIER
VCC
VI
CL
NOTE A
VO
VI
VO50%
VCC
0 V
VOH
VOL
2.7 V
IN = 0 V
VCM
IN OUT
GND1
NOTE A
S1
V or V
OH OL
ISOLATION BARRIER
VCC1 VCC2
C = 0.1 F± 1%mC = 0.1 F± 1%m
GND2
Pass-fail criteria:
Output must
remain stable
OUT
Tektronix
HFS9009
PATTERN
GENERATOR
IN
DUT
Tektronix
784D
VCC
0 V
V / 2
C C
Jitter
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
PARAMETER MEASUREMENT INFORMATION
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr≤3
ns, tf≤3 ns, ZO= 50Ω.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Common-Mode Transient Immunity Test Circuit
NOTE: PRBS bit pattern run length is 216 –1. Transition time is 800 ps.
Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
Copyright ©2006–2012, Texas Instruments Incorporated 13
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
DEVICE INFORMATION
IEC PACKAGE CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 4.8 mm
SOIC-8
L(I02) Minimum external tracking Shortest terminal-to-terminal distance across the 4.3 mm
(Creepage) package surface
CTI Tracking resistance (Comparative DIN IEC 60112 / VDE 0303 Part 1 ≥400 V
Tracking Index)
Minimum Internal Gap (Internal Distance through the insulation 0.008 mm
Clearance) Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device, >1012 Ω
RIO Isolation resistance TA<100°C
Input to output, VIO = 500 V, 100°C≤TA≤max >1011 Ω
CIO Barrier capacitance Input to output VI= 0.4 sin (4E6πt) 1 pF
CIInput capacitance to ground VI= 0.4 sin (4E6πt) 1 pF
NOTE: Creepage and clearance requirements should be applied according to the specific equipment isolation
standards of an application. Care should be taken to maintain the creepage and clearance distance of a board
design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques
shown in the Isolation Glossary . Techniques such as inserting grooves and/or ribs on a printed circuit
board are used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group II
Rated mains voltage ≤150 VRMS I-IV
Installation classification Rated mains voltage ≤300 VRMS I-III
Rated mains voltage ≤400 VRMS I-II
IEC 60747-5-2 INSULATION CHARACTERISTICS(1)
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
VIORM Maximum working insulation 560
voltage Method b1, VPR = VIORM ×1.875, VPK
VPR Input to output test voltage 1050
100% Production test with t = 1 s, Partial discharge <5 pC
VIOTM Transient overvoltage t = 60 s 4000
RSInsulation resistance VIO = 500 V at TS>109Ω
Pollution degree 2
(1) Climatic Classification 40/125/21
14 Copyright ©2006–2012, Texas Instruments Incorporated
OUT
8W
13 W
IN
750kW
500 W
Input Output
VCC1 VCC1 VCC1
VCC2
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
DEVICE I/O SCHEMATICS
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
θJA = 212°C/W, VI= 5.5 V, TJ= 170°C, TA= 25°C 124
Safety input, output, or
ISSOIC-8 mA
supply current θJA = 212°C/W, VI= 3.6 V, TJ= 170°C, TA= 25°C 190
TSMaximum case temperature SOIC-8 150 °C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
Copyright ©2006–2012, Texas Instruments Incorporated 15
0
25
50
75
100
125
150
175
200
225
250
0 50 100 150 200
T -CaseTemperature-°C
C
SafetyLimitingCurrent-mA
V at3.6V
CC1,2
V at5.5V
CC1,2
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
SOIC-8 PACKAGE THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-K Thermal Resistance(1) 212
θJA Junction-to-air High-K Thermal Resistance 122 °C/W
θJB Junction-to-Board Thermal Resistance 37
θJC Junction-to-Case Thermal Resistance 69.1
PDDevice Power Dissipation ISO722xM VCC1 = VCC2 = 5.5 V, TJ= 150°C, CL= 15 pF, 390 mW
Input a 150 Mbps 50% duty cycle square wave
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
Figure 5. SOIC-8 θJC THERMAL DERATING CURVE per IEC 60747-5-2
DEVICE FUNCTION TABLE
Table 1. ISO7220x or ISO7221x(1)
INPUT SIDE VCC OUTPUT SIDE VCC INPUT IN OUTPUT OUT
H H
PU PU L L
Open H
PD PU X H
(1) PU = Powered Up(Vcc ≥3.0V); PD = Powered Down (Vcc ≤2.5V); X = Irrelevant; H = High Level;
L = Low Level
16 Copyright ©2006–2012, Texas Instruments Incorporated
0
2
4
6
8
10
12
14
16
18
20
0 25 50 75 100
SignalingRate-Mbps
I -SupplyCurrent-mA
CC
T =25°C,
15pFLoad
A
ISO7220x ICC2
ISO7220x ICC1
ISO7221x ICC1&2
Temperature-°C
125
350
360
370
380
390
400
410
420
430
440
450
-40 -15 10 35 60 85 110
PropagationDelay-ns
VCC =3.3V
VCC =5V
15pFLoad
tpLH &tpHL
tpLH &tpHL
45
50
55
60
65
70
-40 25 125
Temperature-°C
PropagationDelay-ns
V =3.3V
CC
t &t
PLH PHL
t &t
PLH PHL
V =5V
CC
T =25°C,
15pFLoad
A
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
TYPICAL CHARACTERISTIC CURVES
3.3-V RMS SUPPLY CURRENT 5-V RMS SUPPLY CURRENT
vs vs
SIGNALING RATE (Mbps) SIGNALING RATE (Mbps)
Figure 6. Figure 7.
PROPAGATION DELAY PROPAGATION DELAY
vs vs
FREE-AIR TEMPERATURE, ISO722xA FREE-AIR TEMPERATURE, ISO722xB
Figure 8. Figure 9.
Copyright ©2006–2012, Texas Instruments Incorporated 17
Temperature-°C
125
-40 -15 10 35 60 85 110
PropagationDelay-ns
VCC =3.3V
VCC =5V
15pFLoad
tpLH &tpHL
tpLH &tpHL
0
5
10
15
20
25
30
Temperature-°C
125
-40 -15 10 35 60 85 110
PropagationDelay-ns
VCC =3.3V
VCC =5V
15pFLoad
tpLH &tpHL
tpLH &tpHL
0
5
10
15
20
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
TYPICAL CHARACTERISTIC CURVES (continued)
PROPAGATION DELAY PROPAGATION DELAY
vs vs
FREE-AIR TEMPERATURE, ISO722xC FREE-AIR TEMPERATURE, ISO722xM
Figure 10. Figure 11.
ISO722xA, ISO722xB AND ISO722xC INPUT VOLTAGE
LOW-TO-HIGH SWITCHING THRESHOLD ISO722xM INPUT VOLTAGE HIGH-TO-LOW
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 12. Figure 13.
18 Copyright ©2006–2012, Texas Instruments Incorporated
Free-Air Temperature - °C
Power Supply Undervoltage Threshold - V
2.48
2.52
2.56
2.6
2.64
2.68
-40 -25 -10 5 20 35 50 65 80 95 110 125
V Rising
CC
V Falling
CC
V =5V
CC
15pFLoad
T =25°C
A
V -V
OUT
I -mA
OUT
V =3.3V
CC
0 2 4 6
-80
-70
-60
-50
-40
-30
-20
-10
0
V =5V
CC
15pFLoad
T =25°C
A
V -V
OUT
I -mA
OUT
V =3.3V
CC
0
10
20
30
40
50
60
70
0 1 2 3 4 5
0 50 100 150 200
0
200
400
600
800
1000
1200
1400
1600
1800
2000
V =V =5V
CC1 CC2
15pFLoad
T =25°C
A
SignalingRate-Mbps
Jitter − ps
V =V =3.3V
CC1 CC2
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
TYPICAL CHARACTERISTIC CURVES (continued)
VCC UNDERVOLTAGE THRESHOLD HIGH-LEVEL OUTPUT CURRENT
vs vs
FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE
Figure 14. Figure 15.
LOW-LEVEL OUTPUT CURRENT ISO722xM JITTER
vs vs
LOW-LEVEL OUTPUT VOLTAGE SIGNALING RATE
Figure 16. Figure 17.
Copyright ©2006–2012, Texas Instruments Incorporated 19
1
2
3
4 5
6
7
8
ISO 7220
VCC 1 VCC 2
INB OUTB
GND 1 GND 2
INPUT OUTPUT
0.1mF
0.1mF
2 mm
max .
from
Vcc 1
2mm
max .
from
Vcc 2
INA OUTA
INPUT OUTPUT
1
2
3
4 5
6
7
8
ISO 7221
VCC 1 VCC 2
INB OUTB
GND 1 GND 2
INPUT OUTPUT
0.1mF
0.1mF
2mm
max .
from
Vcc 1
2mm
max .
from
Vcc 2
INA
OUTA
INPUT
OUTPUT
10
100
0 250 500 750 1000
WORKINGVOLTAGE(V IORM)--V
WORKING LIFE -- YEARS
V at560V
IORM
28
880120
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
APPLICATION INFORMATION
Typical Applications
Figure 18. Typical ISO7220 Application Circuit
Figure 19. Typical ISO7221 Application Circuit
Figure 20. Time Dependent Dielectric Breakdown Test Results
20 Copyright ©2006–2012, Texas Instruments Incorporated
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
ISOLATION GLOSSARY
Creepage Distance —The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance —The shortest distance between two conductive input to output leads measured through air (line of
sight).
Input-to Output Barrier Capacitance —The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to Output Barrier Resistance —The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit —An internal circuit directly connected to an external supply mains or other equivalent source
which supplies the primary circuit electric power.
Secondary Circuit —A circuit with no direct connection to primary power, and derives its power from a separate
isolated source.
Comparative Tracking Index (CTI) —CTI is an index used for electrical insulating materials which is defined as
the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the
process that produces a partially conducting path of localized deterioration on or through the surface of an
insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher
CTI value of the insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
Copyright ©2006–2012, Texas Instruments Incorporated 21
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
Insulation:
Operational insulation —Insulation needed for the correct operation of the equipment.
Basic insulation —Insulation to provide basic protection against electric shock.
Supplementary insulation —Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation —Insulation comprising both basic and supplementary insulation.
Reinforced insulation —A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
Pollution Degree:
Pollution Degree 1 —No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 —Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3 —Conductive pollution occurs or dry nonconductive pollution occurs which becomes
conductive due to condensation which is to be expected.
Pollution Degree 4 –Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category —This section is directed at insulation co-ordination by identifying the transient
overvoltages which may occur, and by assigning 4 different levels as indicated in IEC 60664.
I: Signal Level —Special equipment or parts of equipment.
II: Local Level —Portable equipment etc.
III: Distribution Level —Fixed installation
IV: Primary Supply Level —Overhead lines, cable systems
Each category should be subject to smaller transients than the category above.
SPACER
REVISION HISTORY
Changes from Original (July 2006) to Revision A Page
•Deleted "and CSA Apporved"from the UL 1577 FEATURES bullet .................................................................................... 1
•Added option A to the AVAILABLE OPTIONS table ............................................................................................................ 2
Changes from Revision A (August 2006) to Revision B Page
•Added the ELECTICAL CHARACTERISTICS tables to the data sheet ............................................................................... 3
•Added the PARAMETER MEASUREMENT INFORMATION to the data sheet ................................................................. 13
•Added the DEVICE INFORMATION section to the data sheet .......................................................................................... 14
•Added the TYPICAL CHARACTERISTIC CURVES to the data sheet. .............................................................................. 17
•Added the APPLICATION INFORMATION section to the data sheet ................................................................................ 20
•Added the ISOLATION GLOSSARY section to the data sheet .......................................................................................... 21
22 Copyright ©2006–2012, Texas Instruments Incorporated
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
www.ti.com
SLLS755L –JULY 2006–REVISED JANUARY 2012
Changes from Revision B (May 2007) to Revision C Page
•Added the Signaling rate values to the RECOMMENDED OPERATING CONDITIONS table ............................................ 3
•Added Figure 17 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS
table ...................................................................................................................................................................................... 5
•Added Figure 17 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS
table ...................................................................................................................................................................................... 6
•Added Figure 17 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS
table ...................................................................................................................................................................................... 8
•Added Figure 17 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS
table .................................................................................................................................................................................... 10
•Changed the IEC 60664-1 RATINGS TABLE - Specification I-III test conditions From: Rated mains voltage ≤150
VRMS To: Rated mains voltage ≤300 VRMS. Added a row for the I-II specifications ....................................................... 14
•Added Figure 20 - Time Dependent Dielectric Breakdown Test Results ........................................................................... 20
Changes from Revision C (May 2007) to Revision D Page
•Changed Figure 18 - Pin 2 (INA) label From: OUTPUT to INPUT ..................................................................................... 20
Changes from Revision D (June 2007) to Revision E Page
•Changed Figure 6 - New Curves ........................................................................................................................................ 17
•Changed Figure 7- Re-scaled the Y-axis ........................................................................................................................... 17
Changes from Revision E (July 2007) to Revision F Page
•Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table ....................... 4
•Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table ......................... 5
•Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table ................ 6
•Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table ................. 6
•Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION table ................ 8
•Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION table ................. 8
•Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS table ............................................................................... 10
•Added tsk(o) footnote to the SWITCHING CHARACTERISTICS table ................................................................................ 10
•Changed Figure 6 - Re-scaled the Y-axis .......................................................................................................................... 17
•Changed Figure 7 - New Curves ........................................................................................................................................ 17
Changes from Revision F (August 2007) to Revision G Page
•Added Part Numbers ISO7220B and ISO7221B to the data sheet ...................................................................................... 1
•Added 5-Mbps Signaling rate to the FEATURES list ............................................................................................................ 1
•Added Part Numbers ISO720B and ISO7221B to the AVAILABLE OPTIONS table ........................................................... 2
•Added Part Numbers ISO720B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V
table ...................................................................................................................................................................................... 4
•Added Part Numbers ISO720B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V
table ...................................................................................................................................................................................... 5
•Added Part Numbers ISO720B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V
table ...................................................................................................................................................................................... 7
•Added Part Numbers ISO720B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V ......... 9
•Added PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xB, Figure 9 ..................................................... 17
Copyright ©2006–2012, Texas Instruments Incorporated 23
ISO7220A, ISO7220B, ISO7220C, ISO7220M
ISO7221A, ISO7221B, ISO7221C, ISO7221M
SLLS755L –JULY 2006–REVISED JANUARY 2012
www.ti.com
Changes from Revision G (March 2008) to Revision H Page
•Added Note: (1) to the RECOMMENDED OPERATING CONDITIONS table ..................................................................... 3
•Added Note: (1) to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V table .................................................... 4
•Added Note: (1) to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V table ............................................ 5
•Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V table ............................................ 7
•Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V .......................................................... 9
Changes from Revision H (May 2008) to Revision I Page
•Added "IEC 61010-1, IEC 60950-1 and CSA Approved"to the UL 1577 FEATURES bullet .............................................. 1
Changes from Revision I (December 2008) to Revision J Page
•Changed ISO7221C Marked As column From: TI7221C To: I7221C in the AVAILABLE OPTIONS table .......................... 2
Changes from Revision J (May 2009) to Revision K Page
•Changed column 2 of the AVAILABLE OPTIONS table From: Signaling Rate To: Max Signaling Rate ............................. 2
•Changed the the RECOMMENDED OPERATING CONDITIONS so that Note (2) is associated with all device
options in the Input pulse width and Signaling rate .............................................................................................................. 3
•Changed Note (2) From: Typical signaling rate under ideal conditions at 25°C. To: Typical signaling rate and Input
pulse width are measured at ideal conditions at 25°C. ........................................................................................................ 3
Changes from Revision K (January 2010) to Revision L Page
•Changed Feature From: 4000-Vpeak Isolation, 560 Vpeak VIORM To: 4000-VPK VIOTM, 560 VPK VIORM per IEC 60747-5-2
(VDE 0884, Rev2) ................................................................................................................................................................. 1
•Changed Feature From: Operates with 3.3-V or 5-V Supplies To: Operates with 2.8-V (C-Grade), 3.3-V or 5-V
Supplies ................................................................................................................................................................................ 1
•Changed the REGULATORY INFORMATION table ............................................................................................................ 3
•Added device options to VCC in the RECOMMENDED OPERATING CONDITIONS table .................................................. 3
•Changed Note: (1) in the RECOMMENDED OPERATING CONDITIONS table ................................................................. 3
•Changed ICC1 and ICC2 test conditions in the 5-V table ......................................................................................................... 4
•Changed Table Note: (1) ...................................................................................................................................................... 4
•Changed ICC1 and ICC2 test conditions in the VCC1 at 5 V, VCC2 at 3.3 V table ...................................................................... 5
•Changed Table Note: (1) ...................................................................................................................................................... 5
•Changed ICC1 and ICC2 test conditions in the VCC1 at 3.3 V, VCC2 at 5 V table ...................................................................... 7
•Changed Table Note (1) ....................................................................................................................................................... 7
•Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 3.3 V table .......................................................................... 9
•Changed Table Note (1) ....................................................................................................................................................... 9
•Added ELECTRICAL and Switching CHARACTERISTICS table for VCC1 and VCC2 at 2.8 V (ISO722xC-only) ................ 11
•Changed Figure 2 ............................................................................................................................................................... 13
•Changed the CTI MIN value From: ≥175 V To: ≥400 V ..................................................................................................... 14
•Changed Figure 14 ............................................................................................................................................................. 19
24 Copyright ©2006–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ISO7220AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220BD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220BDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220BDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220MD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220MDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220MDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7220MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jan-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ISO7221ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221BD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221BDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221BDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221MD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221MDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221MDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ISO7221MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jan-2012
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7220A, ISO7221A, ISO7221C :
•Automotive: ISO7220A-Q1, ISO7221A-Q1, ISO7221C-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO7220ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7220CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7220MDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7221ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7221MDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7220ADR SOIC D 8 2500 367.0 367.0 35.0
ISO7220CDR SOIC D 8 2500 367.0 367.0 35.0
ISO7220MDR SOIC D 8 2500 533.4 186.0 36.0
ISO7221ADR SOIC D 8 2500 367.0 367.0 35.0
ISO7221MDR SOIC D 8 2500 533.4 186.0 36.0
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Aug-2012
Pack Materials-Page 2
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