M29W800AB120M1T - STMicroelectronics

1/33March 2000

M29W800AT

M29W800AB

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

Low Voltage Single Supply Flash Memory

■2.7V to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ACCESS TIME: 80ns

■PROGRAMMING TIME: 10µs typical

■PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte or Word-by-Word

– Status Register bits and Ready/Busy Output

■SECURITY PROTECTION MEMORY AREA

■INSTRUCTION ADDRESS CODING: 3 digits

■MEMORY BLOCKS

– Boot Block (Top or Bottom location)

– Parameter and Main blocks

■BLOCK, MULTI-BLOCK and CHIP ERASE

■MULTI BLOCK PROTECTION/TEMPORARY

UNPROTECTION MODES

■ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■LOW POWER CONSUMPTION

– Stand-by and Automatic Stand-by

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■20 YEARS DATA RETENTION

– Defectivity below 1ppm/year

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M29W800AT: D7h

– Bottom Device Code, M29W800AB: 5Bh

Figure 1. Logic Diagram

AI02599

A0-A18

DQ0-DQ14

VCC

M29W800AT

M29W800AB

VSS

DQ15A–1

BYTE

FBGA

TSOP48 (N)

12 x 20mm SO44 (M)

LFBGA48 (ZA)

8 x 6 solder balls

M29W800AT, M29W800AB

2/33

Figure 2. TSOP Connections

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI02179

M29W800T

M29W800B

24 25

DQ8

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

Figure 3. SO Connections

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

AI02181

M29W800

M29W800B

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

A17 A8

A18

Table 1. Signal Names

A0-A18 Address Inputs

DQ0-DQ7 Data Input/Outputs, Command Inputs

DQ8-DQ14 Data Input/Outputs

DQ15A–1 Data Input/Output or Address Input

E Chip Enable

G Output Enable

W Write Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

DU Don’t Use as Internally Connected

DESCRIPTION

TheM29W800A isa non-volatilememorythat may

be erasedelectrically at the block or chip level and

programmed in-system on a Byte-by-Byte or

Word-by-Word basis using only a single 2.7V to

3.6V VCC supply. For Program and Erase opera-

tions the necessary high voltages are generated

internally. The device can also be programmed in

standard programmers.

The array matrix organisation allows each block to

be erased and reprogrammed without affecting

other blocks. Blocks canbe protected against pro-

graming and erase on programming equipment,

and temporarily unprotected to make changes in

the application. Each block can be programmed

and erased over 100,000 cycles.

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature or Block Protection

status, Programming, Block and Chip Erase,

Erase Suspend and Resume are written to the de-

vice in cycles of commands to a Command Inter-

face using standard microprocessor write timings.

The device is offered in TSOP48 (12 x 20mm),

SO44 and LFBGA48 0.8 mm ball pitch packages.

3/33

M29W800AT, M29W800AB

Figure 4. LFBGA Connections (Top view through package)

AI00656

87654321

VSS

DQ15

A–1

A15A14A12A13

DQ3DQ11DQ10A18DURB

DQ1DQ9DQ8DQ0A6A17A7

GEA0 A4A3

DQ2

DQ6DQ13DQ14A10A8A9

DQ4VCC

DQ12DQ5DUDURPW

A11 DQ7

A1 A2 VSS

A16

BYTE

Memory Blocks

The devices feature asymmetrically blocked archi-

tecture providing system memoryintegration. Both

M29W800AT and M29W800AB devices have an

array of 19 blocks, one Boot Block of 16 KBytes or

8 KWords, two Parameter Blocks of 8 KBytes or 4

KWords, one Main Block of 32 KBytes or 16

KWords and fifteen Main Blocks of 64 KBytes or

32 KWords. The M29W800AT has the Boot Block

at the top of the memory address space and the

M29W800AB locates the Boot Block starting at the

bottom. The memory maps are showed in Figure

Each block can be erased separately, any combi-

nation of blocks can be specified for multi-block

erase or the entire chip may be erased. The Erase

operations are managed automatically by the P/

E.C. The block erase operation can be suspended

in order to read from or program to any block not

being erased, and then resumed.

Block protection provides additional data security.

Each block can be separately protected or unpro-

tected against Program or Erase on programming

equipment. All previously protected blocks can be

temporarily unprotected in the application.

Organisation

The M29W800A is organised as 1M x8 or 512K

x16 bits selectable by the BYTE signal. When

BYTE is Low the Byte-wide x8 organisation is se-

lected and the address lines are DQ15A–1 and

A0-A18. The Data Input/Output signal DQ15A–1

acts as address line A–1 which selects the lower

or upper Byte of the memory word for output on

DQ0-DQ7, DQ8-DQ14 remain at High impedance.

When BYTE isHigh the memory uses the address

inputs A0-A18 and the Data Input/Outputs DQ0-

DQ15. Memorycontrol is provided by Chip Enable

E, Output Enable G and Write Enable W inputs.

A Reset/Block Temporary Unprotection RP tri-lev-

el input provides a hardware reset when pulled

Low, and when held High (at VID) temporarily un-

protects blocks previously protected allowing them

to be programed and erased. Erase and Program

operations are controlled by an internal Program/

Erase Controller (P/E.C.). Status Register data

output on DQ7 provides a Data Polling signal, and

DQ6 and DQ2 provide Toggle signals to indicate

the state of the P/E.C operations. A Ready/Busy

RB output indicates the completion of the internal

algorithms.

M29W800AT, M29W800AB

4/33

Bus Operations

The following operations can be performed using

the appropriate buscycles: Read (Array, Electron-

ic Signature, Block Protection Status), Write com-

mand, Output Disable, Stan-by, Reset, Block

Protection, Unprotection,Protection Verify, Unpro-

tection Verify and Block Temporary Unprotection.

See Tables 5 and 6.

Command Interface

Instructions, made up of commands written in cy-

cles, can be given to the Program/Erase Controller

through a Command Interface (C.I.). For added

data protection, program or erase execution starts

after 4 or 6 cycles. The first, second, fourth and

fifth cycles are used to input Coded cycles to the

C.I. This Coded sequence is the same for all Pro-

gram/Erase Controller instructions. The ’Com-

mand’ itself and its confirmation, when applicable,

are given on the third, fourth or sixth cycles. Any

incorrect command or any improper command se-

quence will reset the device to Read Array mode.

Instructions

Seven instructions are defined to perform Read

Array, Auto Select (to read the Electronic Signa-

ture or Block Protection Status), Program, Block

Erase, Chip Erase, Erase Suspend and Erase Re-

sume.

The internal P/E.C. automatically handles all tim-

ing and verification of the Program and Erase op-

erations. The Status Register Data Polling,

Toggle, Error bits and the RB output may be read

at any time, during programming or erase, to mon-

itor the progress of the operation.

Instructions are composed of up to six cycles. The

first two cycles input a Coded sequence to the

Command Interface which is common to all in-

structions (see Table 9).

The third cycle inputs the instruction set-up com-

mand. Subsequent cycles output the addressed

data, Electronic Signature or Block Protection Sta-

tus for Read operations. Inorder to give additional

data protection, the instructions for Program and

Block or Chip Erase require further command in-

puts. For a Program instruction, the fourth com-

mand cycle inputs the address and data to be

programmed. For an Erase instruction (Block or

Chip), the fourth and fifth cycles input a further

Coded sequence before the Erase confirm com-

mand on the sixth cycle. Erasure of a memory

block may be suspended, in order to read data

from another block or to program data in another

block, and then resumed. When power is first ap-

plied or if VCC falls below VLKO, the command in-

terface is reset to Read Array.

Table 2. Absolute Maximum Ratings (1)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions forextended periods may affect device reliability. Referalso to theSTMicroelectronics SURE Program and other relevantqual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

3. Depends on range.

Symbol Parameter Value Unit

TAAmbient Operating Temperature (3) –40 to 85 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage –0.6 to 5 V

VCC Supply Voltage –0.6 to 5 V

V(A9, E, G, RP) (2) A9, E, G, RP Voltage –0.6 to 13.5 V

5/33

M29W800AT, M29W800AB

Table 3. Top Boot Block Addresses,

M29W800AT

#Size

(Kbytes) Address Range

(x8) Address Range

(x16)

18 16 FC000h-FFFFFh 7E000h-7FFFFh

17 8 FA000h-FBFFFh 7D000h-7DFFFh

16 8 F8000h-F9FFFh 7C000h-7CFFFh

15 32 F0000h-F7FFFh 78000h-7BFFFh

14 64 E0000h-EFFFFh 70000h-77FFFh

13 64 D0000h-DFFFFh 68000h-6FFFFh

12 64 C0000h-CFFFFh 60000h-67FFFh

11 64 B0000h-BFFFFh 58000h-5FFFFh

10 64 A0000h-AFFFFh 50000h-57FFFh

9 64 90000h-9FFFFh 48000h-4FFFFh

8 64 80000h-8FFFFh 40000h-47FFFh

7 64 70000h-7FFFFh 38000h-3FFFFh

6 64 60000h-6FFFFh 30000h-37FFFh

5 64 50000h-5FFFFh 28000h-2FFFFh

4 64 40000h-4FFFFh 20000h-27FFFh

3 64 30000h-3FFFFh 18000h-1FFFFh

2 64 20000h-2FFFFh 10000h-17FFFh

1 64 10000h-1FFFFh 08000h-0FFFFh

0 64 00000h-0FFFFh 00000h-07FFFh

Table 4. Bottom Boot Block Addresses,

M29W800AB

#Size

(Kbytes) Address Range

(x8) Address Range

(x16)

18 64 F0000h-FFFFFh 78000h-7FFFFh

17 64 E0000h-EFFFFh 70000h-77FFFh

16 64 D0000h-DFFFFh 68000h-6FFFFh

15 64 C0000h-CFFFFh 60000h-67FFFh

14 64 B0000h-BFFFFh 58000h-5FFFFh

13 64 A0000h-AFFFFh 50000h-57FFFh

12 64 90000h-9FFFFh 48000h-4FFFFh

11 64 80000h-8FFFFh 40000h-47FFFh

10 64 70000h-7FFFFh 38000h-3FFFFh

9 64 60000h-6FFFFh 30000h-37FFFh

8 64 50000h-5FFFFh 28000h-2FFFFh

7 64 40000h-4FFFFh 20000h-27FFFh

6 64 30000h-3FFFFh 18000h-1FFFFh

5 64 20000h-2FFFFh 10000h-17FFFh

4 64 10000h-1FFFFh 08000h-0FFFFh

3 32 08000h-0FFFFh 04000h-07FFFh

2 8 06000h-07FFFh 03000h-03FFFh

1 8 04000h-05FFFh 02000h-02FFFh

0 16 00000h-03FFFh 00000h-01FFFh

M29W800AT, M29W800AB

6/33

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A18). The address inputs

for thememory array arelatched duringa write op-

eration on the falling edge at Chip Enable E or

Write Enable W. In Word-wide organisation the

address lines are A0-A18, in Byte-wide organisa-

tion DQ15A–1 acts as an additional LSB address

line. When A9 is raised to VID, either a Read Elec-

tronic Signature Manufacturer or Device Code,

Block ProtectionStatus ora Write BlockProtection

or BlockUnprotection is enableddepending onthe

combination oflevels on A0, A1, A6, A12and A15.

Data Input/Outputs (DQ0-DQ7). These Inputs/

Outputs are used in the Byte-wide and Word-wide

organisations. Theinput isdata to be programmed

in the memory array ora command to be written to

the C.I.Both are latched on the rising edge ofChip

Enable E or Write Enable W. The output is data

from the Memory Array, the Electronic Signature

Manufacturer or Device codes, the Block Protec-

tion Status or the Status register Data Polling bit

DQ7, the Toggle Bits DQ6 and DQ2, the Error bit

DQ5 orthe Erase Timer bit DQ3. Outputs are valid

when Chip Enable E and Output Enable G are ac-

tive. The output is high impedance when the chip

is deselected or the outputs are disabled and

when RP is at a Low level.

Data Input/Outputs (DQ8-DQ14 and DQ15A–

1). These Inputs/Outputs are additionally used in

the Word-wide organisation. When BYTE is High

DQ8-DQ14 and DQ15A–1 act as the MSB of the

Data Input or Output, functioning as described for

DQ0-DQ7 above, and DQ8-DQ15 are ’don’t care’

for command inputs or status outputs. When

BYTE is Low, DQ0-DQ14 are high impedance,

DQ15A–1 is the Address A–1 input.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders andsense amplifiers. E High deselects the

memory and reduces the power consumption to

the stan-by level. E can also be used to control

writing to the command register and to the memo-

ry array, while W remains at a low level. The Chip

Enable must be forced to VID during theBlock Un-

protection operation.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

eration. When G is High the outputs are High im-

pedance. G must be forced to VID level during

Block Protection and Unprotection operations.

Write Enable (W). This input controls writing to

the Command Register and Address and Data

latches.

Byte/WordOrganization Select (BYTE). The BYTE

input selects the output configuration for the de-

vice: Byte-wide (x8) mode or Word-wide (x16)

mode. When BYTE is Low, the Byte-wide mode is

selected and the data is read and programmed on

DQ0-DQ7. In this mode, DQ8-DQ14 are at high

impedance and DQ15A–1 is the LSB address.

When BYTE is High, the Word-wide mode is se-

lected and the data is read and programmed on

DQ0-DQ15.

Ready/Busy Output (RB). Ready/Busy is an

open-drain output and gives the internal state of

the P/E.C. of the device. When RB is Low, the de-

vice is Busy with a Program or Erase operation

and it will not accept any additional program or

erase instructions except the Erase Suspend in-

struction. When RB is High, the device is ready for

any Read, Program or Erase operation. The RB

will also be High when the memory is put in Erase

Suspend or Stan-by modes.

Reset/Block Temporary Unprotect Input (RP).

The RP Input provides hardware reset and pro-

tected block(s) temporary unprotection functions.

Reset of the memory is achieved by pulling RP to

VIL for at least tPLPX. When the reset pulse is giv-

en, if the memory is in Read or Stan-by modes, it

will be available for new operations in tPHEL after

the rising edge of RP. If the memory is in Erase,

Erase Suspend or Program modes the reset will

take tPLYH during which the RB signal will be held

at VIL. Theend of the memory reset will beindicat-

ed by the rising edge of RB. A hardware reset dur-

ing an Erase or Program operation will corrupt the

data being programmed or the sector(s) being

erased. See Tables 15, 16, and Figure 11.

Temporary block unprotection is made by holding

RP at VID. In this condition previously protected

blocks can be programmed or erased. The transi-

tion of RP from VIH to VID must slower than tPH-

PHH. See Tables 17, 18, and Figure 11. When RP

is returned from VID to VIH all blocks temporarily

unprotected will be again protected.

VCC Supply Voltage. The power supply for all

operations (Read, Program and Erase).

VSS Ground. VSS is the reference for all voltage

measurements.

7/33

M29W800AT, M29W800AB

DEVICE OPERATIONS

See Tables 5, 6 and 7.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register or the BlockProtection

Status. Both Chip Enable E and Output Enable G

must below in order to read theoutput ofthe mem-

ory. A new operation is initiated either on the fol-

lowing edge of Chip Enable E or on any address

transition with E at VIL.

Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch input

data to be programmed. A write operation is initi-

ated when Chip Enable E isLow and Write Enable

W is Low with Output Enable G High. Addresses

are latchedonthe falling edgeof W orE whichever

occurs last. Commands and Input Data are

latched onthe rising edgeof W or E whichever oc-

curs first.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is High with

Write Enable W High.

Stan-by. The memory is in stan-by when Chip

Enable E is High and the P/E.C. is idle. The power

consumption is reduced to the stan-by level and

the outputs are high impedance, independent of

the OutputEnable G or Write Enable W inputs.

Automatic Stan-by. After 150ns of bus inactivity

(no address transition, CE = VIL) and when CMOS

levels aredriving the addresses, the chip automat-

ically enters a pseudo-stan-by mode where con-

sumption is reduced to the CMOS stan-by value,

while outputs still drive the bus (if G = VIL).

Electronic Signature. Two codes identifying the

manufacturer and the device can be read from the

memory. The manufacturer’s code for STMicro-

electronics is 20h, the device code is D7h for the

M29W800AT (Top Boot) and 5Bh for the

M29W800AB (Bottom Boot). These codes allow

programming equipment or applications to auto-

matically match their interface to the characteris-

tics ofthe M29W800A. The Electronic Signature is

output by a Read operation when the voltage ap-

plied to A9 is at VID and address inputs A1 is Low.

The manufacturer code is output when the Ad-

dress input A0 is Low and the device code when

this input is High. Other Address inputs are ig-

nored. The codes are output on DQ0-DQ7.

The Electronic Signature canalso beread, without

raising A9 to VID, by giving the memory the In-

struction AS. If the Byte-wide configuration is se-

lected the codes are output on DQ0-DQ7 with

DQ8-DQ14 at High impedance; if the Word-wide

configuration is selected the codes are output on

DQ0-DQ7 with DQ8-DQ15 at 00h.

Block Protection. Each block can be separately

protected against Program or Erase on program-

ming equipment. Block protection provides addi-

tional data security, as it disables all program or

erase operations. This mode is activated when

both A9 and G are raised to VID and anaddress in

the block is applied on A12-A18. Block protection

is initiated on the edge of W falling to VIL. Then af-

ter a delay of 100µs, the edge of W rising to VIH

ends the protection operations. Block protection

verify is achieved by bringing G, E, A0 and A6 to

VIL and A1 to VIH, while W is at VIH and A9 at VID.

Under these conditions, reading the data output

will yield 01h if the block defined by the inputs on

A12-A18 is protected. Any attempt to program or

erase a protected block will be ignored by the de-

vice.

Block Temporary Unprotection. Any previously

protected block can be temporarily unprotected in

order to change stored data. The temporary un-

protection mode is activatedby bringing RP toVID.

During the temporary unprotection mode the pre-

viously protected blocks are unprotected. A block

can be selected and data can bemodified by exe-

cuting the Erase or Program instruction with the

RP signal held at VID. When RP is returned toVIH,

all the previously protected blocks are again pro-

tected.

Block Unprotection. All protected blocks can be

unprotected on programming equipment to allow

updating of bit contents. All blocks must first be

protected before the unprotection operation. Block

unprotection is activated when A9, G and E are at

VID and A12, A15 at VIH. Unprotection is initiated

by the edge of W falling to VIL. After a delay of

10ms, the unprotection operation will end. Unpro-

tection verify is achieved by bringing G and E to

VIL whileA0 is at VIL, A6 and A1 are at VIH andA9

remains at VID. In these conditions, reading the

output data will yield 00h if the block defined by the

inputs A12-A18 has been successfully unprotect-

ed. Each block must be separately verified by giv-

ing its address in order to ensure that it has been

unprotected.

M29W800AT, M29W800AB

8/33

Table 5. User Bus Operations (1)

Note: 1. X = VIL or VIH.

2. Block Address must be given an A12-A18 bits.

3. See Table 7.

4. Operation performed on programming equipment.

Table 6. Read Electronic Signature (following AS instruction or with A9 = VID)

Table 7. Read Block Protection with AS Instruction

Operation E G W RP BYTE A0 A1 A6 A9 A12 A15 DQ0-

DQ7 DQ8-

DQ14 DQ15

A–1

Read Word VIL VIL VIH VIH VIH A0 A1 A6 A9 A12 A15 Data

Output Data

Output

Read Byte VIL VIL VIH VIH VIL A0 A1 A6 A9 A12 A15 Data

Output Hi-Z Address

Input

Write Word VIL VIH VIL VIH VIH A0 A1 A6 A9 A12 A15 Data

Input Data

Input

Write Byte VIL VIH VIL VIH VIL A0 A1 A6 A9 A12 A15 Data

Input Hi-Z Address

Input

Output Disable VIL VIH VIH VIH X XXXX X X Hi-Z Hi-Z Hi-Z

Stan-by VIH XX

IH X XXXX X X Hi-Z Hi-Z Hi-Z

Reset X X X VIL X XXXX X X Hi-Z Hi-Z Hi-Z

Block

Protection (2,4) VIL VID VIL Pulse VIH X XXX

ID XX X X X

Blocks

Unprotection (4) VID VID VIL Pulse VIH X XXX

ID VIH VIH XXX

Block

Protection

Verify (2,4) VIL VIL VIH VIH XVIL VIH VIL VID A12 A15 Block

Protect

Status(3) XX

Block

Unprotection

Verify (2,4) VIL VIL VIH VIH XVIL VIH VIH VID A12 A15 Block

Protect

Status(3) XX

Block

Temporary

Unprotection XX X V

ID X XXXX X X X X X

Org. Code Device E G W BYTE A0 A1 Other

Addresses DQ0-

DQ7 DQ8-

DQ14 DQ15

A–1

Word-

wide

Manufact.

Code VIL VIL VIH VIH VIL VIL Don’t Care 20h 00h 0

Device

Code M29W800AT VIL VIL VIH VIH VIH VIL Don’t Care D7h 00h 0

M29W800AB VIL VIL VIH VIH VIH VIL Don’t Care 5Bh 00h 0

Code E G W A0 A1 A12-A18 Other

Addresses DQ0-DQ7

Protected Block VIL VIL VIH VIL VIH Block Address Don’t Care 01h

Unprotected Block VIL VIL VIH VIL VIH Block Address Don’t Care 00h

9/33

M29W800AT, M29W800AB

Table 8. Commands

Hex Code Command

00h Invalid/Reserved

10h Chip Erase Confirm

20h Reserved

30h Block Erase Resume/Confirm

80h Set-up Erase

90h Read Electronic Signature/

Block Protection Status

A0h Program

B0h Erase Suspend

F0h Read Array/Reset

INSTRUCTIONS AND COMMANDS

The Command Interface latches commands writ-

ten to the memory. Instructions are made up from

one or more commands to perform Read Memory

Array, Read ElectronicSignature, ReadBlockPro-

tection, Program, Block Erase, Chip Erase, Erase

Suspend and Erase Resume. Commands are

made of address and data sequences. The in-

structions require from 1to6 cycles, the first orfirst

three ofwhich are alwayswrite operations used to

initiate the instruction. They are followed by either

further write cycles to confirm the first command or

execute thecommand immediately. Commandse-

quencing must be followed exactly. Any invalid

combination of commands will reset the device to

Read Array. The increased number of cycles has

been chosen to assure maximum datasecurity. In-

structions are initialised bytwo initial Codedcycles

which unlock the Command Interface. In addition,

for Erase, instructionconfirmation isagain preced-

ed by the two Coded cycles.

Status Register Bits

P/E.C. statusisindicated during executionby Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mand execution will automatically output these

five Status Register bits. The P/E.C.automatically

sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other

bits (DQ0, DQ1 and DQ4) are reserved for future

use and should bemasked. See Tables 10 and11.

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputs a ’0’. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a ’1’ after erasing. Data Polling is

valid and only effective during P/E.C. operation,

that is after the fourth W pulse for programming or

after the sixth W pulse for erase. It must be per-

formed at the address being programmed or at an

address within the block being erased. If all the

blocks selectedfor erasure are protected, DQ7 will

be set to’0’for about 100µs, and then returnto the

previous addressed memory data value. See Fig-

ure 13 for the Data Polling flowchart and Figure 12

for the Data Polling waveforms. DQ7 will also flag

the Erase Suspend mode by switching from ’0’ to

’1’ at the start of the Erase Suspend. In order to

monitor DQ7 in the Erase Suspend mode an ad-

dress within a block being erased must be provid-

ed. For a Read Operation in Erase Suspend

mode, DQ7 will output ’1’ if the read is attempted

on a block being erased and the data value on oth-

er blocks. During Program operation in EraseSus-

pend Mode, DQ7 will have the same behavior as

in the normal program execution outside of the

suspend mode.

Toggle Bit (DQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read DQ6 will output complementary

data. DQ6 will toggle following toggling of either G,

or E when G is low. The operation is completed

when two successive reads yield the same output

data. The next read will output the bit last pro-

grammed or a ’1’ after erasing. The toggle bit DQ6

is valid only during P/E.C. operations, that is after

the fourth W pulse for programming or after the

sixth W pulse for Erase. If the blocks selected for

erasure are protected, DQ6 will toggle for about

100µs and then return back to Read. DQ6 will be

set to ’1’ if a Read operation is attempted on an

Erase Suspend block. When erase is suspended

DQ6 will toggle during programming operations in

a block different to the blockin Erase Suspend. Ei-

ther E or G toggling will cause DQ6 to toggle. See

Figure 14 for Toggle Bit flowchart and Figure 15

for Toggle Bit waveforms.

M29W800AT, M29W800AB

10/33

Table 9. Instructions (1)

Note: 1. Commands not interpreted in this table will default toread array mode.

2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting anynew

operation (see Tables 15, 16 and Figure 11).

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-

mand cycles.

5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL willoutput Device

code.

6. Block Protection Address: A0, at VIL,A1atV

IH and A15-A18 within the Block will output the Block Protection status.

7. For Coded cycles address inputs A11-A18 are don’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be

verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit

until Erase is completed or suspended.

9. Read Data Polling, Toggle bits or RB until Erase completes.

10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

RD (2,4) Read/Reset

Memory Array

1+ Addr. (3,7) X Read Memory Array until a new write cycle is initiated.

Data F0h

3+ Addr. (3,7) Byte AAAh 555h AAAh Read Memory Arrayuntil a new write cycle is

initiated.

Word 555h 2AAh 555h

Data AAh 55h F0h

AS (4) Auto Select 3+ Addr. (3,7) Byte AAAh 555h AAAh Read Electronic Signature or Block Protection

Status until a new write cycle is initiated. See Note

5 and 6.

Word 555h 2AAh 555h

Data AAh 55h 90h

PG Program 4 Addr. (3,7) Byte AAAh 555h AAAh Program

Address Read Data Polling or Toggle Bit until

Program completes.

Word 555h 2AAh 555h

Data AAh 55h A0h Program

Data

BE Block Erase 6 Addr. (3,7) Byte AAAh 555h AAAh AAAh 555h Block

Address Additional

Block (8)

Word 555h 2AAh 555h 555h 2AAh

Data AAh 55h 80h AAh 55h 30h 30h

CE Chip Erase 6 Addr. (3,7) Byte AAAh 555h AAAh AAAh 555h AAAh

Note 9Word 555h 2AAh 555h 555h 2AAh 555h

Data AAh 55h 80h AAh 55h 10h

ES (10) Erase

Suspend 1Addr. (3,7) XRead until Togglestops, then read all the data needed from any Block(s)

not being erased then Resume Erase.

Data B0h

ER Erase

Resume 1Addr. (3,7) XRead Data Polling orToggle Bits until Erase completes or Erase is

suspended another time.

Data 30h

11/33

M29W800AT, M29W800AB

Table 10. Status Register Bits

Note: Logic level ’1’ is High, ’0’is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

DQ Name Logic Level Definition Note

7Data

Polling

’1’ Erase Complete or erase block

in Erase Suspend

Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits DQ5 for program or Erase

Success.

’0’ Erase On-going

DQ Program Complete or data of

non erase block during Erase

Suspend

DQ Program On-going

6 Toggle Bit

’-1-0-1-0-1-0-1-’ Erase or Program On-going Successive reads output complementary

data on DQ6 while Programming or Erase

operations are on-going. DQ6 remains at

constant level when P/E.C.operations are

completed or Erase Suspend is

acknowledged.

DQ Program Complete

’-1-1-1-1-1-1-1-’ Erase Complete or Erase

Suspend on currently

addressed block

5 Error Bit ’1’ Program or Erase Error This bit is set to ‘1’ in the case of

Programming or Erase failure.

’0’ Program or Erase On-going

4 Reserved

3Erase

Time Bit

’1’ Erase Timeout Period Expired P/E.C. Erase operation has started. Only

possible command entry is Erase Suspend

(ES).

’0’ Erase Timeout Period On-going An additional block to be erased in parallel

can be entered to the P/E.C.

2 Toggle Bit

’-1-0-1-0-1-0-1-’

Chip Erase, Erase or Erase

Suspend on the currently

addressed block.

Erase Error due to the currently

addressed block

(when DQ5 = ‘1’). Indicates the erase status and allows to

identify the erased block

1Program on-going, Erase on-

going on another block or

Erase Complete

DQ Erase Suspend read on non

Erase Suspend block

1 Reserved

0 Reserved

M29W800AT, M29W800AB

12/33

During the second cycle the Coded cycles consist

of writingthe data55h at address555h inthe Byte-

wide configuration and at address 2AAh in the

Word-wide configuration. In the Byte-wide config-

uration the address lines A–1 to A10 are valid, in

Word-wide A0to A11are valid, otheraddress lines

are ’don’t care’. The Coded cycles happen on first

and second cyclesof the commandwrite or on the

fourth and fifth cycles.

Instructions

See Table 9.

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

command F0h. It can be optionally preceded by

the two Coded cycles. Subsequent read opera-

tions will read the memory array addressed and

output the data read. A wait state of 10µs is nec-

essary after Read/Reset prior to any valid read if

the memory was in an Erase mode when the RD

instruction is given. The Read/Reset command is

not accepted duringErase and erase Suspend.

Auto Select (AS) Instruction. This instruction

uses the two Coded cycles followed by one write

cycle giving the command 90h to address AAAh in

the Byte-wide configuration or address 555hin the

Word-wide configuration for command set-up. A

subsequent read will output the manufacturer

code and the device code or the block protection

status depending on the levels of A0 and A1. The

manufacturer code, 20h, is output when the ad-

dresses lines A0 and A1are Low, thedevice code,

EEh for Top Boot, EFh for Bottom Boot is output

when A0 is High with A1 Low.

The AS instruction also allows access to the block

protection status. After giving the AS instruction,

A0 is set to VIL with A1 at VIH, while A12-A18 de-

fine the address of the block to be verified. A read

in these conditions will output a 01h if the block is

protected and a 00h if the block is not protected.

Program (PG) Instruction. This instruction uses

four write cycles. Both for Byte-wide configuration

and for Word-wide configuration. The Program

command A0h is written to address AAAh in the

Byte-wide configuration or to address 555h in the

Word-wide configuration on the third cycle after

two Coded cycles. A fourth write operation latches

the Address on the falling edge of W or E and the

Data to be written on the rising edge and starts the

P/E.C. Read operations output the Status Register

bits after the programming has started. Memory

programming is made only by writing ’0’ in place of

’1’. Status bits DQ6 and DQ7 determine if pro-

gramming is on-going and DQ5 allows verification

of any possible error. Programming at an address

not in blocks being erased is also possible during

erase suspend. In this case,DQ2 will toggle at the

address being programmed.

Table 11. Polling and Toggle Bits

Note: 1. Toggle if the address is within a block being erased.

’1’if the address is within a block not being erased.

Mode DQ7 DQ6 DQ2

Program DQ7 Toggle 1

Erase 0 Toggle Note 1

Erase Suspend Read

(in Erase Suspend

block) 1 1 Toggle

Erase Suspend Read

(outside Erase Suspend

block) DQ7 DQ6 DQ2

Erase Suspend Program DQ7 Toggle N/A

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. It can alsobe used to

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erased will set DQ2 to ’1’ during erase and

to DQ2 during Erase Suspend. During Chip Erase

a read operation will cause DQ2 to toggle as all

blocks are being erased. DQ2 will be set to ’1’ dur-

ing program operation and when erase is com-

plete. After erase completion and if the error bit

DQ5 is set to ’1’, DQ2 will toggle if the faulty block

is addressed.

Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.

when there is a failure of programming, block

erase, or chip erase that results in invalid data in

the memory block. In case of an error in block

erase or program, the block in which the error oc-

curred or to which the programmed data belongs,

must be discarded. The DQ5 failure condition will

also appear if a user tries to program a ’1’ to a lo-

cation that is previously programmed to ’0’. Other

Blocks may still be used. The error bit resets after

a Read/Reset (RD) instruction. In case of success

of Program or Erase, the error bit will be set to ’0’.

Erase Timer Bit (DQ3). This bit is set to ’0’by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, after 50µsto90µs, DQ3 returns

to ’1’.

Coded Cycles

The two Coded cycles unlock the Command Inter-

face. Theyare followed by an input command or a

confirmation command. The Coded cycles consist

of writing the data AAh at address AAAh in the

Byte-wide configuration and at address 555h in

the Word-wide configuration during the first cycle.

13/33

M29W800AT, M29W800AB

Figure 5. AC Testing Input Output Waveform

AI01417

1.5V

Figure 6. AC Testing Load Circuit

AI01968

0.8V

OUT

CL= 30pF or 100pF

CLincludes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 13. Capacitance (1) (TA=25°C, f = 1 MHz)

Note: Sampled only, not 100% tested.

Table 14. DC Characteristics

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 6pF

OUT Output Capacitance VOUT =0V 12 pF

Symbol Parameter Test Condition Min Typ. Max Unit

ILI Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO Output Leakage Current 0V ≤VOUT ≤VCC ±1µA

ICC1 Supply Current (Read by Word) E=V

IL,G=V

IH,f=6MHz 310mA

CC2 Supply Current (Read by Word) E=V

IL,G=V

IL, f = 6MHz 4.5 10 mA

ICC3 Supply Current (Stan-by) E = VCC ±0.2V 30 100 µA

ICC4 (1) Supply Current

(Program or Erase) Byte program, Block or

Chip Erase in progress 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 VCC VCC + 0.3 V

VOL Output Low Voltage IOL = 1.8mA 0.45 V

VOH Output High Voltage CMOS IOH = –100µAV

CC –0.4V V

VID A9 Voltage (Electronic Signature) 11.5 12.5 V

IID A9 Current (Electronic Signature) A9 = VID 30 100 µA

VLKO (1) Supply Voltage (Erase and

Program lock-out) 2.0 2.3 V

Table 12. AC Measurement Conditions

Input Rise and Fall Times ≤10ns

Input Pulse Voltages 0 to 3V

Input and Output Timing Ref. Voltages 1.5V

M29W800AT, M29W800AB

14/33

Table 15. Read AC Characteristics

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to tELQV -t

GLQV after the falling edge of E without increasing tELQV.

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

Symbol Alt Parameter Test

Condition

M29W800AT / M29W800AB

Unit

80 90

VCC = 3.0V to 3.6V

CL = 30pF VCC = 3.0V to 3.6V

CL = 30pF

Min Max Min Max

tAVAV tRC Address Validto Next

Address Valid E=V

IL,

G=V

IL 80 90 ns

tAVQV tACC Address Validto Output

Valid E=V

IL,

G=V

IL 80 90 ns

tAXQX tOH Address Transition to

Output Transition E=V

IL,

G=V

IL 00

tBHQV tFHQV BYTE Switching High to

Output Valid 50 50 ns

tBLQZ tFLQZ BYTE Switching Low to

Output High Z 50 50 ns

tEHQX tOH Chip Enable High to Output

Transition G=V

IL 00ns

EHQZ (1) tHZ Chip Enable High to Output

Hi-Z G=V

IL 30 30 ns

tELBH

tELBL tELFH

tELFL Chip Enable to BYTE

Switching Low or High 55ns

ELQV (2) tCE Chip Enable Low to Output

Valid G=V

IL 80 90 ns

tELQX (1) tLZ Chip Enable Low to Output

Transition G=V

IL 00ns

GHQX tOH Output Enable High to

Output Transition E=V

IL 00ns

GHQZ (1) tDF Output Enable High to

Output Hi-Z E=V

IL 30 30 ns

tGLQV (2) tOE Output Enable Low to

Output Valid E=V

IL 35 35 ns

tGLQX (1) tOLZ Output Enable Low to

Output Transition E=V

IL 00ns

PHEL tRH RP High to Chip Enable

Low 50 50 ns

tPLYH (1, 3) tRRB

tREADY RP Low to Read Mode 10 10 µs

tPLPX tRP RP Pulse Width 500 500 ns

15/33

M29W800AT, M29W800AB

Table 16. Read AC Characteristics

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to tELQV -t

GLQV after the falling edge of E without increasing tELQV.

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

Symbol Alt Parameter Test

Condition

M29W800AT / M29W800AB

Unit

100 120

VCC = 2.7V to 3.6V

CL = 30pF VCC = 2.7V to 3.6V

CL = 30pF

Min Max Min Max

tAVAV tRC Address Validto Next

Address Valid E=V

IL,

G=V

IL 100 120 ns

tAVQV tACC Address Validto Output

Valid E=V

IL,

G=V

IL 100 120 ns

tAXQX tOH Address Transition to

Output Transition E=V

IL,

G=V

IL 00

tBHQV tFHQV BYTE Switching High to

Output Valid 50 60 ns

tBLQZ tFLQZ BYTE Switching Low to

Output High Z 50 60 ns

tEHQX tOH Chip Enable High to Output

Transition G=V

IL 00ns

EHQZ (1) tHZ Chip Enable High to Output

Hi-Z G=V

IL 30 30 ns

tELBH

tELBL tELFH

tELFL Chip Enable to BYTE

Switching Low or High 55ns

ELQV (2) tCE Chip Enable Low to Output

Valid G=V

IL 100 120 ns

tELQX (1) tLZ Chip Enable Low to Output

Transition G=V

IL 00ns

GHQX tOH Output Enable High to

Output Transition E=V

IL 00ns

GHQZ (1) tDF Output Enable High to

Output Hi-Z E=V

IL 30 30 ns

tGLQV (2) tOE Output Enable Low to

Output Valid E=V

IL 40 50 ns

tGLQX (1) tOLZ Output Enable Low to

Output Transition E=V

IL 00ns

PHEL tRH RP High to Chip Enable

Low 50 50 ns

tPLYH (1, 3) tRRB

tREADY RP Low to Read Mode 10 10 µs

tPLPX tRP RP Pulse Width 500 500 ns

M29W800AT, M29W800AB

16/33

Figure 7. Read Mode AC Waveforms

AI02182

tAVAV

tAVQV tAXQX

tELQX tEHQX

tGLQV

tGLQX

tGHQX

VALID

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV

VALID

ADDRESS VALID

AND CHIP ENABLE OUTPUT ENABLE DATA VALID

BYTE

tBLQZtELBL/tELBH

tEHQZ

tGHQZ

tBHQV

Note: Write Enable (W) = High.

17/33

M29W800AT, M29W800AB

Table 17. Write AC Characteristics, W Controlled

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Symbol Alt Parameter

M29W800AT / M29W800AB

Unit

80 90

VCC = 3.0V to 3.6V

CL = 30pF VCC = 3.0V to 3.6V

CL = 30pF

Min Max Min Max

tAVAV tWC Address Valid to Next Address Valid 80 90 ns

tAVWL tAS Address Valid to Write Enable Low 0 0 ns

tDVWH tDS Input Valid to Write Enable High 35 45 ns

tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns

tGHWL Output Enable High to Write Enable Low 0 0 ns

tPHPHH (1, 2) tVIDR RP Rise Time to VID 500 500 ns

tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs

tPLPX tRP RP Pulse Width 500 500 ns

tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs

tWHDX tDH Write Enable High to Input Transition 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns

tWHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns

tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns

tWLAX tAH Write Enable Low to Address Transition 45 45 ns

tWLWH tWP Write Enable Low to Write Enable High 35 35 ns

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address AAAh

in the Byte-wide configuration or address 555h in

the Word-wide configuration on third cycle after

the two Coded cycles. The Block Erase Confirm

command 30h is similarly written onthe sixth cycle

after anothertwo Coded cycles.During the input of

the second command an address within the block

to beerased is given and latched into the memory.

Additional block Erase Confirm commands and

block addresses can be written subsequently to

erase other blocks in parallel, without further Cod-

ed cycles. The erase will start after the erase tim-

eout period (seeErase TimerBit DQ3 description).

Thus, additional Erase Confirmcommands for oth-

er blocks must be given within this delay. The input

of a new Erase Confirm command will restart the

timeout period. The status of the internal timer can

be monitored through the level of DQ3, if DQ3 is ’0’

the Block Erase Command has been given and

the timeoutis running, if DQ3is ’1’, the timeout has

expired and the P/E.C. is erasing the Block(s). If

the second command given is not an erase con-

firm or if the Coded cycles are wrong, the instruc-

tion aborts, and the device is reset to Read Array.

It is not necessary to program the block with 00h

as the P/E.C. will do this automatically before to

erasing to FFh. Read operations after the sixth ris-

ing edge of W orE output the status register status

bits.

M29W800AT, M29W800AB

18/33

Table 18. Write AC Characteristics, W Controlled

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Symbol Alt Parameter

M29W800AT / M29W800AB

Unit

100 120

VCC = 2.7V to 3.6V

CL = 30pF VCC = 2.7V to 3.6V

CL = 30pF

Min Max Min Max

tAVAV tWC Address Valid to Next Address Valid 100 120 ns

tAVWL tAS Address Valid to Write Enable Low 0 0 ns

tDVWH tDS Input Valid to Write Enable High 45 50 ns

tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns

tGHWL Output Enable High to Write Enable Low 0 0 ns

tPHPHH (1, 2) tVIDR RP Rise Time to VID 500 500 ns

tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs

tPLPX tRP RP Pulse Width 500 500 ns

tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs

tWHDX tDH Write Enable High to Input Transition 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns

tWHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns

tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns

tWLAX tAH Write Enable Low to Address Transition 45 50 ns

tWLWH tWP Write Enable Low to Write Enable High 35 50 ns

During the execution of the erase by the P/E.C.,

the memory accepts only the Erase Suspend ES

and Read/Reset RD instructions. Data Polling bit

DQ7 returns ’0’ while the erasure is in progress

and ’1’ when it has completed. The Toggle bit DQ2

and DQ6 toggle during the erase operation. They

stop when erase is completed. After completion

the Status Register bit DQ5 returns ’1’if there has

been an erase failure. In such a situation, the Tog-

gle bit DQ2 can be used to determine which block

is not correctly erased. In the case of erase failure,

a Read/Reset RD instruction is necessary in order

to reset the P/E.C.

Chip Erase (CE) Instruction. This instruction

uses six write cycles. The Erase Set-up command

80h is written to address AAAh in the Byte-wide

configuration or the address 555h in the Word-

wide configuration on the third cycle after the two

Coded cycles. The Chip Erase Confirm command

10h is similarly written on the sixth cycle after an-

other two Coded cycles. If the second command

given is not an erase confirm or if the Coded cy-

cles are wrong, the instruction aborts and the de-

vice is reset to Read Array. It is not necessary to

program the array with 00h first as the P/E.C. will

automatically do this before erasing it to FFh.

Read operations after the sixth rising edge of W or

E output the Status Register bits. During the exe-

cution of the erase by the P/E.C., Data Polling bit

DQ7 returns ’0’,then ’1’oncompletion. TheToggle

bits DQ2 and DQ6 toggle during erase operation

and stop when erase is completed. After comple-

tion the Status Register bit DQ5 returns ’1’if there

has been an Erase Failure.

19/33

M29W800AT, M29W800AB

Figure 8. Write AC Waveforms, W Controlled

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

AI02183

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

Erase Suspend (ES) Instruction. The Block

Erase operation may be suspended by this in-

struction which consists of writing the command

B0h without any specific address. No Coded cy-

cles are required. It permits reading of data from

another block and programming in another block

while an eraseoperation is in progress.Erase sus-

pend is accepted only during the Block Erase in-

struction execution. Writing this command during

Erase timeout will, in addition to suspending the

erase, terminate the timeout. The Toggle bit DQ6

stops toggling when the P/E.C. issuspended. The

Toggle bits will stop toggling between 0.1µs and

15µs after the Erase Suspend (ES) command has

been written. The device will then automatically be

set to Read Memory Array mode. When erase is

suspended, a Read from blocks being erased will

output DQ2 toggling and DQ6 at ’1’.A Read from

a block not being erased returns valid data. During

suspension the memory will respond only to the

Erase Resume ER and the Program PG instruc-

tions. A Program operation can be initiated during

erase suspend in one of the blocks not being

erased. It will result in both DQ2 and DQ6 toggling

when the data is being programmed. A Read/Re-

set command will definitively abort erasure and re-

sult in invalid data in the blocks being erased.

Erase Resume (ER) Instruction. If an Erase

Suspend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

M29W800AT, M29W800AB

20/33

Table 19. Write AC Characteristics, E Controlled

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Symbol Alt Parameter

M29W800AT / M29W800AB

Unit

80 90

VCC = 3.0V to 3.6V

CL = 30pF VCC = 3.0V to 3.6V

CL = 30pF

Min Max Min Max

tAVAV tWC Address Valid to Next Address Valid 80 90 ns

tAVEL tAS Address Valid to Chip Enable Low 0 0 ns

tDVEH tDS Input Valid to Chip Enable High 35 45 ns

tEHDX tDH Chip Enable High to Input Transition 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low 30 30 ns

tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns

tEHRL (1) tBUSY Program Erase Valid to RB Delay 80 90 ns

tEHWH tWH Chip Enable High to Write Enable High 0 0 ns

tELAX tAH Chip Enable Low to Address Transition 45 45 ns

tELEH tCP Chip Enable Low to Chip Enable High 35 35 ns

tGHEL Output Enable High Chip Enable Low 0 0 ns

tPHPHH (1, 2) tVIDR RP Rise TImeto VID 500 500 ns

tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs

tPLPX tRP RP Pulse Width 500 500 ns

tVCHWL tVCS VCC High to Write Enable Low 50 50 µs

tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns

POWER SUPPLY

Power Up

The memory Command Interface is reset on pow-

er up to Read Array. The device does not accept

commands on the first rising edge of W, if both W

and E are at VIL with G at VIH during power-up.

Any write cycle initiation is blocked when VCC is

below VLKO.

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

have the VCC rail decoupledwith a 0.1µF capacitor

close to the VCC and VSS pins. The PCB trace

widths should be sufficient to carry the VCC pro-

gram and erase currents required.

21/33

M29W800AT, M29W800AB

Table 20. Write AC Characteristics, E Controlled

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Symbol Alt Parameter

M29W800AT / M29W800AB

Unit

100 120

VCC = 2.7V to 3.6V

CL = 30pF VCC = 2.7V to 3.6V

CL = 30pF

Min Max Min Max

tAVAV tWC Address Valid to Next Address Valid 100 120 ns

tAVEL tAS Address Valid to Chip Enable Low 0 0 ns

tDVEH tDS Input Valid to Chip Enable High 45 50 ns

tEHDX tDH Chip Enable High to Input Transition 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low 30 30 ns

tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns

tEHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns

tEHWH tWH Chip Enable High to Write Enable High 0 0 ns

tELAX tAH Chip Enable Low to Address Transition 45 50 ns

tELEH tCP Chip Enable Low to Chip Enable High 35 50 ns

tGHEL Output Enable High Chip Enable Low 0 0 ns

tPHPHH (1,2) tVIDR RP Rise TImeto VID 500 500 ns

tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs

tPLPX tRP RP Pulse Width 500 500 ns

tVCHWL tVCS VCC High to Write Enable Low 50 50 µs

tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns

M29W800AT, M29W800AB

22/33

Figure 9. Write AC Waveforms, E Controlled

Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

Figure 10. Read and Write AC Characteristics, RP Related

AI02184

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

AI02091

RP tPLPX

tPHWL

tPLYH

tPHPHH

tPHEL

23/33

M29W800AT, M29W800AB

Table 21. Data Polling and Toggle Bit AC Characteristics (1)

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. All other timings are defined in Read AC Characteristics table.

Table 22. Data Polling and Toggle Bit AC Characteristics (1)

(TA= 0 to 70°C, –20 to 85°C or –40 to 85°C)

Note: 1. All other timings are defined in Read AC Characteristics table.

Symbol Parameter

M29W800AT / M29W800AB

Unit

80 90

VCC = 3.0V to 3.6V

CL = 30pF VCC = 3.0V to 3.6V

CL = 30pF

Min Max Min Max

tEHQ7V

Chip Enable High to DQ7 Valid

(Program, E Controlled) 10 2400 10 2400 µs

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled) 1.0 60 1.0 60 sec

tEHQV Chip Enable High to Output Valid(Program) 10 2400 10 2400 µs

Chip Enable High to Output Valid(Chip Erase) 1.0 60 1.0 60 sec

tQ7VQV Q7 Validto Output Valid (Data Polling) 35 35 ns

tWHQ7V

Write Enable High to DQ7 Valid

(Program, W Controlled) 10 2400 10 2400 ms

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled) 1.0 60 1.0 60 sec

tWHQV Write Enable High to Output Valid (Program) 10 2400 10 2400 µs

Write Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec

Symbol Parameter

M29W800AT / M29W800AB

Unit

100 120

VCC = 2.7V to 3.6V

CL = 30pF VCC = 2.7V to 3.6V

CL = 30pF

Min Max Min Max

tEHQ7V

Chip Enable High to DQ7 Valid

(Program, E Controlled) 10 2400 10 2400 µs

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled) 1.0 60 1.0 60 sec

tEHQV Chip Enable High to Output Valid(Program) 10 2400 10 2400 µs

Chip Enable High to Output Valid(Chip Erase) 1.0 60 1.0 60 sec

tQ7VQV Q7 Validto Output Valid (Data Polling) 40 50 ns

tWHQ7V

Write Enable High to DQ7 Valid

(Program, W Controlled) 10 2400 10 2400 ms

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled) 1.0 60 1.0 60 sec

tWHQV Write Enable High to Output Valid (Program) 10 2400 10 2400 µs

Write Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec

M29W800AT, M29W800AB

24/33

Figure 11. Data Polling DQ7 AC Waveforms

AI02185

A0-A18/

A–1

DQ7

IGNORE

VALID

DQ0-DQ6/

DQ8-DQ15

ADDRESS (WITHIN BLOCKS)

DATA OUTPUT VALID

tAVQV

tEHQ7V

tGLQV

tWHQ7V

VALID

tQ7VQV

DQ7

DATA POLLING (LAST) CYCLE

MEMORY

ARRAY

READ CYCLE

DATA

POLLING

READ CYCLES

LAST WRITE

CYCLE OF

PROGRAM

OR ERASE

INSTRUCTION

tELQV

25/33

M29W800AT, M29W800AB

Table 23. Program, Erase Times and Program, Erase Endurance Cycles

(TA= 0 to 70°C; VCC = 2.7V to 3.6V)

Note: 1. Excluded the time required to execute bus cycles sequence for program operation.

Parameter

M29W800AT / M29W800AB

Unit

Min Typ Typical after (1)

100k W/E Cycles Max

Chip Erase (Preprogrammed, VCC = 2.7V) 10 10 sec

Chip Erase (VCC = 2.7V) 15 15 sec

Main Block Erase (VCC = 2.7V) 1.5 15 sec

Chip Program (Byte) (1) 10 10 sec

Chip Program (Word) (1) 5 5 sec

Byte/Word Program 10 10 µs

Program/Erase Cycles (per Block) 100,000 cycles

Figure 12. Data Polling Flowchart

READ DQ5&

DQ7

at VALID ADDRESS

START

READ DQ7

FAIL PASS

AI01369

DQ7

DATA YES

YES

DQ5

DQ7

DATA YES

Figure 13. Data Toggle Flowchart

READ

DQ2, DQ5 & DQ6

START

READ DQ2, DQ6

FAIL PASS

AI01873

DQ2,

DQ6

TOGGLE NO

YES

DQ5

YES

DQ2,

DQ6

TOGGLE

M29W800AT, M29W800AB

26/33

Figure 14. Data Toggle DQ6, DQ2 AC Waveforms

AI02186

A0-A18/

A–1

DQ6,DQ2

tAVQV

STOP TOGGLE

LAST WRITE

CYCLE OF

PROGRAM

OF ERASE

INSTRUCTION

VALID

VALIDIGNORE

DATA

TOGGLE

READ CYCLE MEMORY ARRAY

READ CYCLE

tWHQV

tEHQV

tELQV

tGLQV

DATA

TOGGLE

READ CYCLE

DQ0-DQ1,DQ3-DQ5,DQ7/

DQ8-DQ15

Note: All other timings are as a normal Read cycle.

27/33

M29W800AT, M29W800AB

Table 24. Security Block Instruction

Note: 1. Address bits A10-A19 are don’t care for coded address inputs.

2. Data bits DQ8-DQ15 are don’t care for coded address inputs.

Mne. Instr. Cyc. Unlock Cycle 2nd Cyc.

1st Cyc.

RDS Read

Security

Data 1Addr. (1) AAh Read OTP Data until a new write cycle is initiated.

Data (2) B8h

Figure 15. Security Block Address Table

Security

Memory Block

AI02746

TOP BOOT BLOCK

000FFh

Security

Memory Block

00000h

0E0FFh

0E000h

BOTTOM BOOT BLOCK

Security

Memory Block

TOP BOOT BLOCK

0007Fh

Security

Memory Block

00000h

0E01Fh

0E000h

BOTTOM BOOT BLOCK

BYTE Organisation (x8)

WORD Organisation (x16)

SECURITY PROTECTION MEMORY AREA

The M29W800A features a security protection

memory area.It consistsof amemory blockof 256

bytes or128 words which is programmedin the ST

factory tostore a unique code thatuniquely identi-

fies the part.

This memory block can beread by using the Read

Security Data instruction (RDS) as shown in Table

24.

Read Security Data (RDS) Instruction. This RDS

uses asingle write cycle instruction: the command

B8h is written to the address AAh. This sets the

memory to the Read Security mode. Any succes-

sive read attempt will output the addressed Secu-

rity byte until a new write cycle is initiated.

M29W800AT, M29W800AB

28/33

Table 25. Ordering Information Scheme

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

Example: M29W800AT 80 N 1 T

Device Type

M29

Operating Voltage

W = 2.7 to 3.6V

Device Function

800A = 8 Mbit (1Mb x8 or 512Kb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

80 = 80 ns

90 = 90 ns

100 = 100 ns

120 = 120 ns

Package

N = TSOP48: 12 x 20 mm

M = SO44

ZA = LFBGA48: 0.8 mm pitch

Temperature Range

1=0to70°C

5=–20to85°C

6=–40to85°C

Option

T = Tape & Reel Packing

29/33

M29W800AT, M29W800AB

Table 26. Revision History

Date Description

November 1998 First issue

February 1999 Removed TSOP48 Package Reverse Pinout

March 1999 Program, Erase Times and Erase Endurance Cycles change

02/09/00

New document template

Document type: from Preliminary Data to Data Sheet

Program, Erase Times and Endurance Cycles change (Table23)

LFBGA Package Mechanical Data change (Table 29)

LFBGA Package Outline drawing change (Figure 18)

03/06/00 Program Erase Times change (Table 23)

M29W800AT, M29W800AB

30/33

Table 27. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 1.20 0.0472

A1 0.05 0.15 0.0020 0.0059

A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276

α0°5°0°5°

N48 48

CP 0.10 0.0039

Figure 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Drawing is not to scale.

TSOP-a

N/2

DIE

LA1 α

31/33

M29W800AT, M29W800AB

Table 28. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 2.42 2.62 0.0953 0.1031

A1 0.22 0.23 0.0087 0.0091

A2 2.25 2.35 0.0886 0.0925

B 0.50 0.0197

C 0.10 0.25 0.0039 0.0098

D 28.10 28.30 1.1063 1.1142

E 13.20 13.40 0.5197 0.5276

e 1.27 – – 0.0500 – –

H 15.90 16.10 0.6260 0.6339

L 0.80 – – 0.0315 – –

α3°––3°––

N44 44

CP 0.10 0.0039

Figure 17. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

Drawing is not to scale.

SO-b

LA1 α

M29W800AT, M29W800AB

32/33

Figure 18. LFBGA48 - 8 x 6 balls, 0.8 mm pitch, Bottom View Package Outline

Drawing is not to scale.

E1E

BGA-Z00

ddd

FE SD

BALL ”A1”

Table 29. LFBGA48 - 8 x 6 balls, 0.8 mm pitch, Package Mechanical Data

Symbol mm inch

Typ Min Max Typ Min Max

A 1.350 0.0531

A1 0.300 0.200 0.350 0.0118 0.0079 0.0138

A2 0.750 1.000 0.0295 0.0394

b 0.300 0.550 0.0118 0.0217

D 9.000 8.800 9.200 0.3543 0.3465 0.3622

D1 5.600 – – 0.2205 – –

ddd 0.150 0.0059

e 0.800 – – 0.0315 – –

E 6.000 5.800 6.200 0.2362 0.2283 0.2441

E1 4.000 – – 0.1575 – –

FD 1.700 – – 0.0669 – –

FE 1.000 – – 0.0394 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

33/33

M29W800AT, M29W800AB

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