STM32F410x8 STM32F410xB ARM(R)-Cortex(R)-M4 32b MCU+FPU, 125 DMIPS, 128KB Flash, 32KB RAM, 9 TIMs, 1 ADC, 1 DAC, 1 LPTIM, 9 comm. interfaces Datasheet - production data Features &"'! * Dynamic Efficiency Line with eBAM (enhanced Batch Acquisition Mode) - 1.7 V to 3.6 V power supply - -40 C to 85/105/125 C temperature range * Core: ARM(R) 32-bit Cortex(R)-M4 CPU with FPU, Adaptive real-time accelerator (ART AcceleratorTM) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions * Memories - Up to 128 Kbytes of Flash memory - 512 bytes of OTP memory - 32 Kbytes of SRAM * Clock, reset and supply management - 1.7 V to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - 4-to-26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration * Power consumption - Run: 89 A/MHz (peripheral off) - Stop (Flash in Stop mode, fast wakeup time): 40 A Typ @ 25 C; 49 A max @25 C - Stop (Flash in Deep power down mode, slow wakeup time): down to 6 A @ 25 C; 14 A max @25 C - Standby: 2.4 A @25 C / 1.7 V without RTC; 12 A @85 C @1.7 V - VBAT supply for RTC: 1 A @25 C * 1x12-bit, 2.4 MSPS ADC: up to 16 channels WLCSP36 LQFP48 (7x7mm) (2.553x2.579mm) LQFP64 (10x10mm) * Debug mode - Serial wire debug (SWD) & JTAG interfaces - Cortex(R) -M4 Embedded Trace MacrocellTM * Up to 50 I/O ports with interrupt capability - Up to 45 fast I/Os up to 100 MHz - Up to 49 5 V-tolerant I/Os * Up to 9 communication interfaces - Up to 3x I2C interfaces (SMBus/PMBus) including 1x I2C Fast-mode at 1 MHz - Up to 3 USARTs (2 x 12.5 Mbit/s, 1 x 6.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control) - Up to 3 SPI/I2Ss (up to 50 Mbit/s SPI or I2S audio protocol) * True random number generator * CRC calculation unit * 96-bit unique ID * RTC: subsecond accuracy, hardware calendar * All packages are ECOPACK(R)2 Table 1. Device summary * General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support * Up to 9 timers - One low-power timer (available in Stop mode) This is information on a product in full production. UFBGA64 (5x5mm) - One 16-bit advanced motor-control timer - Three 16-bit general purpose timers - One 32-bit timer up to 100 MHz with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - Two watchdog timers (independent window) - SysTick timer. * 1x12-bit D/A converter April 2017 UFQFPN48 (7x7mm) Reference Part number STM32F410x8 STM32F410T8, STM32F410C8, STM32F410R8 STM32F410xB STM32F410TB, STM32F410CB, STM32F410RB DocID028094 Rev 5 1/142 www.st.com Contents STM32F410x8/B Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 3 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 ARM(R) Cortex(R)-M4 with FPU core with embedded Flash and SRAM . . . 16 3.2 Adaptive real-time memory accelerator (ART AcceleratorTM) . . . . . . . . . 16 3.3 Batch Acquisition mode (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 17 3.7 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.16 3.15.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.15.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16.1 2/142 Internal power supply supervisor availability . . . . . . . . . . . . . . . . . . . . . 22 3.17 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.20.1 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.20.2 General-purpose timers (TIM5, TIM9 and TIM11) . . . . . . . . . . . . . . . . . 26 3.20.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DocID028094 Rev 5 STM32F410x8/B Contents 3.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.21 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.22 Universal synchronous/asynchronous receiver transmitters (USART) . . 28 3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.24 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.25 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.26 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.27 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.29 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.30 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.31 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.2 VCAP_1 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.3 Operating conditions at power-up/power-down (regulator ON) . . . . . . . 56 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 56 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 57 DocID028094 Rev 5 3/142 5 Contents 7 STM32F410x8/B 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 86 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 91 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.25 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.4 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.5 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.6.1 8 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Appendix A Recommendations when using the internal reset OFF . . . . . . . . 137 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 B.1 4/142 Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 DocID028094 Rev 5 STM32F410x8/B Contents B.2 Batch Acquisition Mode (BAM) example . . . . . . . . . . . . . . . . . . . . . . . . . 139 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DocID028094 Rev 5 5/142 5 List of tables STM32F410x8/B List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. 6/142 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F410x8/B features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 22 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM32F410x8/B pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F410x8/B register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 55 VCAP_1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 56 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 56 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V . . . 61 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V . . 62 Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.6 V. . . . . . . . . . . . . . . 63 Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.7 V. . . . . . . . . . . . . . . 64 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V . . . . . 65 Typical and maximum current consumption in Sleep mode - VDD = 3.6 V . . . . . . . . . . . . . 66 Typical and maximum current consumption in Sleep mode - VDD = 1.7 V . . . . . . . . . . . . . 68 Typical and maximum current consumptions in Stop mode - VDD = 1.7 V . . . . . . . . . . . . . 70 Typical and maximum current consumption in Stop mode - VDD=3.6 V. . . . . . . . . . . . . . . 70 Typical and maximum current consumption in Standby mode - VDD= 1.7 V . . . . . . . . . . . 70 Typical and maximum current consumption in Standby mode - VDD= 3.6 V . . . . . . . . . . . 71 Typical and maximum current consumptions in VBAT mode (LSE and RTC ON, LSE low- drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DocID028094 Rev 5 STM32F410x8/B Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. List of tables LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 EMI characteristics for LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 100 SCL frequency (fPCLK1= 42 MHz.,VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 101 FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 111 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 111 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 WLCSP36 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 121 UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data. . . . . . . . . 130 UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 133 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 137 DocID028094 Rev 5 7/142 8 List of tables Table 89. 8/142 STM32F410x8/B Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DocID028094 Rev 5 STM32F410x8/B List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM32F410x8/B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 21 LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 UFBGA64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WLCSP36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Typical VBAT current consumption (LSE and RTC ON/LSE oscillator in "low power" mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Typical VBAT current consumption (LSE and RTC ON/LSE oscillator in "high-drive" mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 FT/TC I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 WLCSP36 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat DocID028094 Rev 5 9/142 10 List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. 10/142 STM32F410x8/B package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 125 LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 129 LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 UFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Sensor hub application example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Sensor hub application example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Batch Acquisition Mode (BAM) example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DocID028094 Rev 5 STM32F410x8/B 1 Introduction Introduction This datasheet provides the description of the STM32F410x8/B microcontrollers. For information on the Cortex(R)-M4 core, please refer to the Cortex(R)-M4 programming manual (PM0214) available from www.st.com. DocID028094 Rev 5 11/142 31 Description 2 STM32F410x8/B Description The STM32F410X8/B devices are based on the high-performance ARM(R) Cortex(R) -M4 32bit RISC core operating at a frequency of up to 100 MHz. Their Cortex(R)-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F410X8/B belong to the STM32 Dynamic EfficiencyTM product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power consumption during data batching. The STM32F410X8/B incorporate high-speed embedded memories (up to 128 Kbytes of Flash memory, 32 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, one AHB bus and a 32-bit multi-AHB bus matrix. All devices offer one 12-bit ADC, one 12-bit DAC, a low-power RTC, three general-purpose 16-bit timers, one PWM timer for motor control, one general-purpose 32-bit timers and one 16-bit low-power timer. They also feature standard and advanced communication interfaces. * Up to three I2Cs * Three SPIs * Three I2Ss To achieve audio class accuracy, the I2S peripherals can be clocked via the internal PLL or via an external clock to allow synchronization. * Three USARTs. The STM32F410x8/B are offered in 5 packages ranging from 36 to 64 pins. The set of available peripherals depends on the selected package. Refer to Table 2: STM32F410x8/B features and peripheral counts for the peripherals available for each part number. The STM32F410x8/B operate in the - 40 to +125 C temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. These features make the STM32F410x8/B microcontrollers suitable for a wide range of applications: * Motor drive and application control * Medical equipment * Industrial applications: PLC, inverters, circuit breakers * Printers, and scanners * Alarm systems, video intercom, and HVAC * Home audio appliances * Mobile phone sensor hub Figure 2 shows the general block diagram of the devices. 12/142 DocID028094 Rev 5 STM32F410x8/B Description Table 2. STM32F410x8/B features and peripheral counts STM32 STM32 STM32 STM32 STM32 STM32 STM32 STM32 STM32 STM32 F410 F410 F410 F410 F410 F410 F410 F410 F410 F410 T8Y TBY C8U CBU C8T CBT R8T RBT R8I RBI Peripherals Flash memory in Kbytes 64 128 64 128 64 SRAM in Kbytes System Timers Generalpurpose 4 Low-power timer 1 Advancedcontrol 1 SPI/ I2 S 1 3 2 3 USART 2 3 12-bit ADC Number of channels 23 36 128 1 4 10 16 1 1 Maximum CPU frequency Operating temperatures 64 50 12-bit DAC Number of channels Operating voltage 128 1 I2 C GPIOs Package 64 32 Random number generator Communication interfaces 128 100 MHz 1.7 to 3.6 V 1.8 to 3.6 V 1.7 to 3.6 V 1.8 to 3.6 V 1.7 to 3.6 V Ambient temperatures: - 40 to +85 C / - 40 to + 105 C / - 40 to + 125 C Junction temperature: -40 to + 130 C WLCSP36 UFQFPN48 LQFP48 DocID028094 Rev 5 LQFP64 UFBGA64 13/142 31 Description 2.1 STM32F410x8/B Compatibility with STM32F4 series The STM32F410x8/B are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F410x8/B can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1. Compatible board design for LQFP64 package 966 9'' 966 3%QRWDYDLODEOHDQ\PRUH 5HSODFHGE\9&$3B 3& 3& 3& 3$ 3$ 3% 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3% 3& 3& 3& 3$ 3$ 3% 3% 9'' 9&$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3%QRWDYDLODEOHDQ\PRUH 5HSODFHGE\9&$3B 9'' 966 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% 3% 9&$3B 966 9'' 3% 9&$3B 9'' 3% 3% 670)[% 3% 3% 9&$3B 966 9'' 3' 670)[ 3& 3& 3& 3$ 3$ 3% 3% 3' 670)670)OLQH 9&$3LQFUHDVHGWRI 9&$3LQFUHDVHGWRI (65RUEHORZ (65RUEHORZ 9'' 966 9'' 966 9'' 06Y9 1. For STM32F410xB devices, pin 54 is bonded to PB11 instead of PD2. 14/142 DocID028094 Rev 5 STM32F410x8/B Description Figure 2. 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The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 100 MHz. DocID028094 Rev 5 15/142 31 Functional overview STM32F410x8/B 3 Functional overview 3.1 ARM(R) Cortex(R)-M4 with FPU core with embedded Flash and SRAM The ARM(R) Cortex(R)-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM(R) Cortex(R)-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F410x8/B devices are compatible with all ARM tools and software. Figure 2 shows the general block diagram of the STM32F410x8/B. Note: Cortex(R)-M4 with FPU is binary compatible with Cortex(R)-M3. 3.2 Adaptive real-time memory accelerator (ART AcceleratorTM) The ART AcceleratorTM is a memory accelerator which is optimized for STM32 industrystandard ARM(R) Cortex(R)-M4 with FPU processors. It balances the inherent performance advantage of the ARM(R) Cortex(R)-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 125 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 100 MHz. 3.3 Batch Acquisition mode (BAM) The Batch acquisition mode allows enhanced power efficiency during data batching. It enables data acquisition through any communication peripherals directly to memory using the DMA in reduced power consumption as well as data processing while the rest of the system is in low-power mode (including the flash and ART). For example in an audio system, a smart combination of PDM audio sample acquisition and processing from the I2S directly to RAM (flash and ARTTM stopped) with the DMA using BAM followed by some very short processing from flash allows to drastically reduce the power consumption of the application. A dedicated application note (AN4515) describes how to implement the STM32F410x8/B BAM to allow the best power efficiency. 16/142 DocID028094 Rev 5 STM32F410x8/B 3.4 Functional overview Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.5 Embedded Flash memory The devices embed up to 128 Kbytes of Flash memory available for storing programs and data, plus 512 bytes of OTP memory organized in 16 blocks which can be independently locked. To optimize the power consumption the Flash memory can also be switched off in Run or in Sleep mode (see Section 3.18: Low-power modes). Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between power saving and startup time. Before disabling the Flash, the code must be executed from the internal RAM. 3.6 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.7 Embedded SRAM All devices embed 32 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed with 0 wait states DocID028094 Rev 5 17/142 31 Functional overview 3.8 STM32F410x8/B Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 3. Multi-AHB matrix 6 6 6 '0$B3 *3 '0$ '0$B0(0 '0$B0(0 '0$B3, 6EXV 6 *3 '0$ 6 0 ,&2'( 0 '&2'( $&&(/ 6 'EXV ,EXV $50 &RUWH[0 )ODVK .% 0 65$0 .E\WHV 0 $+% SHULSK $3% $3% %XVPDWUL[6 06Y9 3.9 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: 18/142 * SPI and I2S * I2C * USART * General-purpose, basic and advanced-control timers TIMx * ADC * DAC. DocID028094 Rev 5 STM32F410x8/B 3.10 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)-M4 with FPU. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 50 GPIOs can be connected to the 16 external interrupt lines. 3.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the AHB bus, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB bus and highspeed APB domains is 100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz. DocID028094 Rev 5 19/142 31 Functional overview 3.13 STM32F410x8/B Boot modes At startup, boot pins are used to select one out of three boot options: * Boot from user Flash * Boot from system memory * Boot from embedded SRAM The bootloader is located in system memory. It is used to reprogram the Flash memory by using the interfaces described in Table 3. Refer to Table 9: STM32F410x8/B pin definitions) for the GPIOs available on the selected package. For more detailed information on the bootloader, refer to Application Note: AN2606, STM32TM microcontroller system memory boot mode. Table 3. Embedded bootloader interfaces Package USART1 WLCSP36 X UFQFPN48 LQFP64 3.14 20/142 USART2 PA2/PA3 PA9/PA10 I2C1 I2C2 I2C4 FM+ SPI1 SPI3 X PB10/PB3 PA15/PA5 /PB4/PB5 X PB14/PB15 X PA4/PA5/ PA6/PA7 PB12/PB13 /PC2/PC3 PB6/PB7 X PB10/PB11 Power supply schemes * VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor (POR/PDR) disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and PDR_ON pins. * VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with decoupling technique. * VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. DocID028094 Rev 5 STM32F410x8/B Functional overview 3.15 Power supply supervisor 3.15.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. The internal power supply supervisor is enabled by holding PDR_ON high. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.15.2 Internal reset OFF This feature is available on WLCSP36 package only. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to low. An external power supply supervisor should monitor VDD and should set the device in reset mode when VDD is below 1.7 V. NRST should be connected to this external power supply supervisor. Refer to Figure 4: Power supply supervisor interconnection with internal reset OFF. Figure 4. Power supply supervisor interconnection with internal reset OFF(1) 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 1567 3'5B21 9'' 06Y9 1. The PRD_ON pin is available on WLCSP36 package only. DocID028094 Rev 5 21/142 31 Functional overview STM32F410x8/B A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no longer supported: 3.16 * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. * The brownout reset (BOR) circuitry must be disabled. * The embedded programmable voltage detector (PVD) is disabled. * VBAT functionality is no more available and VBAT pin should be connected to VDD. Voltage regulator The regulator has three operating modes: - Main regulator mode (MR) - Low power regulator (LPR) - Power-down The three power modes configured by software: * MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. * LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode. * Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. An external ceramic capacitor should be connected to the VCAP_1 pin. 3.16.1 Internal power supply supervisor availability Table 4. Regulator ON/OFF and internal power supply supervisor availability Package Power supply supervisor ON Power supply supervisor OFF UFQFPN48 Yes No WLCSP36 Yes PDR_ON set to VDD Yes PDR_ON set to VSS(1) LQFP64 Yes No 1. An external power supervisor must be used (refer to Section 3.15.2: Internal reset OFF). 22/142 DocID028094 Rev 5 STM32F410x8/B 3.17 Functional overview Real-time clock (RTC) and backup registers The backup domain includes: * The real-time clock (RTC) * 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC features a reference clock detection, a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.18: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. The RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.18 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. To further reduce the power consumption, the Flash memory can be switched off before entering in Sleep mode. Note that this requires a code execution from the RAM. * Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC DocID028094 Rev 5 23/142 31 Functional overview STM32F410x8/B and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The RTC and the low-power timer (LPTIM1) can remain active in Stop mode. They can consequently be used to wake up the device from this mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, LPTIM1, the RTC alarm/ wakeup/ tamper/ time stamp events). * Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm/ wakeup/ tamper/time stamp event occurs. Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 3.19 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external super-capacitor, or from VDD when no external battery and an external super-capacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC and the backup registers. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 3.20 Timers and watchdogs The devices embed one advanced-control timer, four general purpose timers, one low power timer, two watchdog timers and one SysTick timer. All timer counters can be frozen in debug mode. Table 5 compares the features of the advanced-control and general-purpose timers. 24/142 DocID028094 Rev 5 STM32F410x8/B Functional overview Table 5. Timer feature comparison Timer type Advanced -control Complementary output Max. interface clock (MHz) Max. timer clock (MHz) Timer TIM1 16-bit Up, Down, Up/down Any integer between 1 and 65536 Yes 4 Yes 100 100 32-bit Up, Down, Up/down Any integer between 1 and 65536 Yes 4 No 50 100 Up Any integer between 1 and 65536 No 2 No 100 100 Up Any integer between 1 and 65536 No 1 No 100 100 Yes 0 No 50 100 No 2 No 50 100 TIM5 General purpose DMA Capture/ request compare generation channels Counter Counter Prescaler resolution type factor TIM9 TIM11 16-bit 16-bit Basic TIM6 16-bit Up Any integer between 1 and 65536 Lowpower LPTIM1 16-bit Up Between 1 and 128 DocID028094 Rev 5 25/142 31 Functional overview 3.20.1 STM32F410x8/B Advanced-control timers (TIM1) The advanced-control timer (TIM1) can be seen as three-phase PWM generator multiplexed on 4 independent channels. It has complementary PWM outputs with programmable inserted dead times. It can also be considered as a complete general-purpose timer. Its 4 independent channels can be used for: * Input capture * Output compare * PWM generation (edge- or center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, it has the same features as the general-purpose TIMx timers. If configured as a 16-bit PWM generator, it has full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 supports independent DMA request generation. 3.20.2 General-purpose timers (TIM5, TIM9 and TIM11) There are three synchronizable general-purpose timers embedded in the STM32F410x8/B (see Table 5 for differences). * TIM5 The STM32F410x8/B devices includes a full-featured general-purpose timer, TIM5. TIM5 timer is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. It features four independent channels for input capture/output compare, PWM or onepulse mode output. TIM5 can operate in conjunction with the other general-purpose timers and TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. TIM5 general-purpose timer can be used to generate PWM output. All TIM5 channels have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM9 and TIM11 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM11 features one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with TIM5 full-featured general-purpose timer or used as simple time bases. 3.20.3 Basic timer (TIM6) This timer is mainly used for DAC triggering and waveform generation. It can also operate as generic 16-bit timers. TIM6 supports independent DMA request generation. 26/142 DocID028094 Rev 5 STM32F410x8/B 3.20.4 Functional overview Low-power timer (LPTIM1) The devices embed one low-power timer. This timer features an independent clock and runs in Stop mode if it is clocked by LSE, LSI or by an external clock. It is able to wake up the system from Stop mode. The low-power timer main features are the following: 3.20.5 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous/ one shot mode * Selectable software/hardware input trigger * Selectable clock source - Internal clock sources: LSE, LSI, HSI or APB1 clock - External clock source over LPTIM input (working even when no internal clock source is running and used by pulse-counter applications). * Programmable digital glitch filter * Encoder mode * Active in Stop mode. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.20.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.20.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source. DocID028094 Rev 5 27/142 31 Functional overview 3.21 STM32F410x8/B Inter-integrated circuit interface (I2C) The devices feature up to three I2C bus interfaces which can operate in multimaster and slave modes: * One I2C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to 400 kHz) modes and Fast-mode plus (up to 1 MHz). * Two I2C interfaces support the Standard mode (up to 100 KHz) and the Fast mode (up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on the complete solution, refer to the nearest STMicroelectronics sales office. All I2C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave) and embed a hardware CRC generation/verification. They can be served by DMA and they support SMBus 2.0/PMBus. The devices also include programmable analog and digital noise filters (see Table 6). Table 6. Comparison of I2C analog and digital filters Pulse width of suppressed spikes 3.22 Analog filter Digital filter 50 ns Programmable length from 1 to 15 I2C peripheral clocks Universal synchronous/asynchronous receiver transmitters (USART) The devices embed three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART6). These three interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 12.5 Mbit/s. The USART2 interface communicates at up to 6.25 bit/s. USART1 and USART2 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. 28/142 DocID028094 Rev 5 STM32F410x8/B Functional overview Table 7. USART feature comparison Max. baud Max. baud USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB LIN irDA name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping by 16) by 8) USART1 X X(1) X X X X 6.25 12.5 APB2 (max. 100 MHz) USART2 X X(1) X X(1) X X(1) 3.12 6.25 APB1 (max. 50 MHz) X N.A X X(1)(2) X X(1)(2) 6.25 12.5 APB2 (max. 50 MHz) USART6 (1) 1. Not available on WLCSP36 package. 2. Not available on UFQFPN48 package. 3.23 Serial peripheral interface (SPI) The devices feature three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 and SPI5 can communicate at up to 50 Mbit/s, SPI2 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 3.24 Inter-integrated sound (I2S) Three standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be operated in master or slave mode, in simplex communication modes and can be configured to operate with a 16-/32-bit resolution as an input or output channel. All the I2Sx audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 3.25 Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. DocID028094 Rev 5 29/142 31 Functional overview 3.26 STM32F410x8/B General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 100 MHz. 3.27 Analog-to-digital converter (ADC) One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1 or TIM5 timer. 3.28 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor output voltage into a digital value. Refer to the reference manual for additional information. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.29 Digital-to-analog converter (DAC) One 12-bit buffered DAC channel can be used to convert a digital signal into an analog voltage signal output. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This digital interface supports the following features: 30/142 * 8-bit or 12-bit monotonic output * Buffer offset calibration (factory and user trimming) * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation DocID028094 Rev 5 STM32F410x8/B Functional overview * Triangular-wave generation * DMA capability for each channel * External triggers for conversion * Sample and hold low-power mode, with internal or external capacitor The DAC channel is triggered through TIM6 update output that is also connected to different DMA channels. 3.30 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.31 Embedded Trace MacrocellTM The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F410x8/B through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using any high-speed channel available. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DocID028094 Rev 5 31/142 31 Pinouts and pin description 4 STM32F410x8/B Pinouts and pin description 9'' 3'5B21 966 3% %227 3% 3% 3% 3% 3% 3$ 3$ Figure 5. LQFP48 pinout 9%$7 9'' 3&$17,B7$03 966 3&26&B,1 3$ 3&26&B287 3$ 3+26&B,1 3$ 3+26&B287 3$ 1567 3$ 966$95() 3$ 9''$95() 3% 3$:.83 3% 3$ 3% 3$ 3% 3$ 3$ 3$ 3$ 3$ 3% 3% 3% 3% 9&$3B 966 9'' /4)3 06Y9 1. The above figure shows the package top view. 9'' 966 3% 3% %227 3% 3% 3% 3% 3% 3% 3& 3& 3& 3$ 3$ Figure 6. LQFP64 pinout 9%$7 9'' 3& 966 3&26&B,1 3$ 3&26&B287 3$ 3+26&B,1 3$ 3+26&B287 3$ 1567 3$ 3& 3$ 3& 3& 3& 3& 3& 3& 966$95() 3& 9''$95() 3% 3$ 3% 3$ 3% 3$ 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 9&$3B 966 9'' /4)3 0VY9 1. The above figure shows the package top view. 32/142 DocID028094 Rev 5 STM32F410x8/B Pinouts and pin description 3$ 9'' 3& 966 3&26&B,1 3$ 3&26&B287 3$ 3+26&B,1 3$ 3+26&B287 3$ 1567 3$ 966$95() 3$ 9''$95() 3% 3% 3$ 3% 3$ 3% 966 9'' 3$ 3% 3% 3% 3% 3% %227 3% 3% 3% 3% 3% 3$ 3% 3$ 3$ 966 3$ 9%$7 3$ 9'' Figure 7. UFQFPN48 pinout 9&$3B 3$ 8)4)31 069 1. The above figure shows the package top view. Figure 8. UFBGA64 pinout $ 3& 26&B,1 9%$7 3% %227 3% 3& 3$ 3$ % 3& 26&B287 3& $17,B7$03 3% 3% 3% 3& 3$ 3$ & 3+ 26&B,1 966 3'5B21 3% 3% 3& 3$ 3$ ' 3+ 26&B287 9'' 3& 3% 3& 966 3$ 3& ( 1567 3& 3& 9'' 9'' 3$ 3& 3& ) 966$ 3& 3$ 3$ 3% 3& 3% 3% * 95() 3$:.83 3$ 3$ 3& 3% 3% 3% + 9''$ 3$ 3$ 3$ 3& 3% 9&$3B 3% 06Y9 1. The above figure shows the package top view. DocID028094 Rev 5 33/142 43 Pinouts and pin description STM32F410x8/B Figure 9. WLCSP36 pinout $ 9'' 966 3% 3% 3$ 9'' % 3& 26&B,1 9%$7 3'5B 21 3% 3$ 966 & 3& 26&B 287 3+ 26&B,1 3& 3% 3% 3$ ' 3+ 26&B287 1567 %227 3% 3$ 3$ ( 966$ 95() 3$ 3$ 3% 9&$3 B 3% ) 9''$ 95() 3$ 3$ 3% 966 9'' 06Y9 1. The above figure shows the package bump side. Table 8. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input/ output pin FT 5 V tolerant I/O TC Standard 3.3 V I/O B Dedicated BOOT0 pin NRST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers 34/142 DocID028094 Rev 5 STM32F410x8/B Pinouts and pin description Table 9. STM32F410x8/B pin definitions WLCSP36 LQFP48 UFQFPN48 LQFP64 UFBGA64 Pin type I/O structure Notes Pin Number Alternate functions B5 1 1 1 A2 VBAT S - - - VBAT - - - - C2 VSS S - - - - C4 2 2 2 B2 PC13 I/O FT (2)(3) EVENTOUT RTC_TAMP1, RTC_OUT, RTC_TS B6 3 3 3 A1 PC14OSC32_IN I/O FT (4) EVENTOUT OSC32_IN C6 4 4 4 B1 PC15OSC32_OUT I/O FT (2)(4) EVENTOUT OSC32_OUT - - - - D2 VDD S - - - - C5 5 5 5 C1 PH0 - OSC_IN I/O FT (4) EVENTOUT OSC_IN D6 6 6 6 D1 PH1 OSC_OUT I/O FT (4) EVENTOUT OSC_OUT D5 7 7 7 E1 NRST NR ST - - - - - - - 8 D3 PC0 I/O FT - LPTIM1_IN1, EVENTOUT ADC1_10, WKUP2 - - - 9 E2 PC1 I/O FT - LPTIM1_OUT, EVENTOUT ADC1_11, WKUP3 - - - 10 E3 PC2 I/O FT - LPTIM1_IN2, SPI2_MISO, EVENTOUT ADC1_12 - - - 11 F2 PC3 I/O FT - LPTIM1_ETR, SPI2_MOSI/I2S2_SD, EVENTOUT ADC1_13 E6 8 8 12 F1 VSSA/VREF- S - - - - F6 9 9 13 - VDDA/VREF+ S - - - - - - - - G1 VREF+ S - - - - - - - - H1 VDDA S - - - - E5 10 10 14 G2 PA0 I/O FT - TIM5_CH1, USART2_CTS, EVENTOUT ADC1_0, WKUP1 - 11 11 15 H2 PA1 I/O FT - TIM5_CH2, USART2_RTS, EVENTOUT ADC1_1 Pin name (function after reset)(1) DocID028094 Rev 5 (2)(3) Additional functions 35/142 43 Pinouts and pin description STM32F410x8/B 12 16 F3 PA2 Pin type UFBGA64 LQFP64 UFQFPN48 12 Pin name (function after reset)(1) I/O FT Notes E4 LQFP48 WLCSP36 Pin Number I/O structure Table 9. STM32F410x8/B pin definitions (continued) Alternate functions Additional functions - TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, EVENTOUT ADC1_2 ADC1_3 F5 13 13 17 G3 PA3 I/O FT - TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, EVENTOUT - - - 18 D5 VSS S - - - - - - - 19 E4 VDD S - - - - - 14 14 20 H3 PA4 I/O FT - SPI1_NSS/I2S1_WS, USART2_CK, EVENTOUT ADC1_4 F4 15 15 21 F4 PA5 I/O TC - SPI1_SCK/I2S1_CK, EVENTOUT ADC1_5, DAC_OUT1 ADC1_6 - 16 16 22 G4 PA6 I/O FT - TIM1_BKIN, SPI1_MISO, I2S2_MCK, EVENTOUT - 17 17 23 H4 PA7 I/O FT - TIM1_CH1N, SPI1_MOSI/I2S1_SD, EVENTOUT ADC1_7 - - - 24 G5 PC4 I/O FT - TIM9_CH1, EVENTOUT ADC1_14 - - - 25 H5 PC5 I/O FT - TIM9_CH2, I2C4_SMBA, EVENTOUT ADC1_15 - 18 18 26 F5 PB0 I/O FT - TIM1_CH2N, SPI5_SCK/I2S5_CK, EVENTOUT ADC1_8 - 19 19 27 G6 PB1 I/O TC - TIM1_CH3N, SPI5_NSS/I2S5_WS, EVENTOUT ADC1_9 F3 20 20 28 H6 PB2 I/O FT - LPTIM1_OUT, EVENTOUT BOOT1 36/142 DocID028094 Rev 5 STM32F410x8/B Pinouts and pin description 21 29 G7 PB10 I/O FT - E2 22 22 30 H7 VCAP_1 S - - - - F2 23 23 31 D6 VSS S - - - - F1 24 24 32 E5 VDD S - - - - - TIM1_BKIN, TIM5_CH1, I2C2_SMBA, SPI2_NSS/I2S2_WS, EVENTOUT - - TIM1_CH1N, I2C4_SMBA, SPI2_SCK/I2S2_CK, EVENTOUT - - TIM1_CH2N, I2C4_SDA, SPI2_MISO, EVENTOUT - - RTC_50Hz, TIM1_CH3N, I2C4_SCL, SPI2_MOSI/I2S2_SD, EVENTOUT - - TRACECLK, I2C4_SCL, I2S2_MCK, USART6_TX, EVENTOUT - - E1 - - - - 25 26 27 28 - 25 26 27 28 - 33 34 35 36 37 UFBGA64 21 LQFP64 E3 I2C2_SCL, SPI2_SCK/I2S2_CK, I2S1_MCK, I2C4_SCL, EVENTOUT LQFP48 Alternate functions WLCSP36 Notes Pin name (function after reset)(1) Pin type UFQFPN48 Pin Number I/O structure Table 9. STM32F410x8/B pin definitions (continued) H8 G8 F8 F7 F6 PB12 PB13 PB14 PB15 PC6 I/O I/O I/O I/O I/O FT FT FT FT FT Additional functions - - - - 38 E7 PC7 I/O FT - I2C4_SDA, SPI2_SCK/I2S2_CK, I2S1_MCK, USART6_RX, EVENTOUT - - - 39 E8 PC8 I/O FT - USART6_CK, EVENTOUT - - - - 40 D8 PC9 I/O FT - MCO_2, I2C4_SDA, I2S2_CKIN, EVENTOUT - DocID028094 Rev 5 37/142 43 Pinouts and pin description STM32F410x8/B 29 41 C8 PA8 I/O FT - - 30 30 42 B8 PA9 I/O FT - TIM1_CH2, USART1_TX, EVENTOUT - - TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX, EVENTOUT - - TIM1_CH4, USART1_CTS, USART6_TX, EVENTOUT - - - - 31 32 31 32 43 44 UFBGA64 29 LQFP64 D1 MCO_1, TIM1_CH1, I2C4_SCL, USART1_CK, EVENTOUT LQFP48 Alternate functions WLCSP36 Notes Pin name (function after reset)(1) Pin type UFQFPN48 Pin Number I/O structure Table 9. STM32F410x8/B pin definitions (continued) E6 D7 PA10 PA11 I/O I/O FT FT Additional functions - D2 33 33 45 A8 PA12 I/O FT - TIM1_ETR, SPI5_MISO, USART1_RTS, USART6_RX, EVENTOUT C1 34 34 46 C7 PA13 I/O FT - JTMS-SWDIO, EVENTOUT - B1 35 35 47 D5 VSS S - - - - - 36 36 48 - VDD S - - - - A1 - - - - VDD S - - - - B2 37 37 49 B7 PA14 I/O FT - JTCK-SWCLK, EVENTOUT - - A2 38 38 50 A7 PA15 I/O FT - JTDI, SPI1_NSS/I2S1_WS, USART1_TX, EVENTOUT - - - 51 C6 PC10 I/O FT - TRACED0, TIM5_CH2, EVENTOUT - - - - 52 B6 PC11 I/O FT - TRACED1, TIM5_CH3, EVENTOUT - - - - 53 A6 PC12 I/O FT - TRACED2, TIM11_CH1, EVENTOUT - 38/142 DocID028094 Rev 5 STM32F410x8/B Pinouts and pin description - 54 B5 PB11 Pin type UFBGA64 LQFP64 UFQFPN48 - Pin name (function after reset)(1) I/O FT Notes - LQFP48 WLCSP36 Pin Number I/O structure Table 9. STM32F410x8/B pin definitions (continued) Alternate functions Additional functions - TRACED3, TIM5_CH4, I2C2_SDA, I2S2_CKIN, EVENTOUT - - C2 39 39 55 A5 PB3 I/O FT - JTDO-SWO, I2C4_SDA, SPI1_SCK/I2S1_CK, USART1_RX, I2C2_SDA, EVENTOUT D3 40 40 56 C5 PB4 I/O FT - JTRST, SPI1_MISO, EVENTOUT - - LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI/I2S1_SD, EVENTOUT - - LPTIM1_ETR, I2C1_SCL, USART1_TX, EVENTOUT - - A3 B3 41 42 41 42 57 58 D4 C4 PB5 PB6 I/O I/O FT FT C3 43 43 59 B4 PB7 I/O FT - LPTIM1_IN2, I2C1_SDA, USART1_RX, EVENTOUT D4 44 44 60 A4 BOOT0 I B - - BOOT0 - LPTIM1_OUT, I2C1_SCL, SPI5_MOSI/I2S5_SD, EVENTOUT - - A4 45 45 61 B3 PB8 I/O FT - - 46 62 A3 PB9 I/O FT - TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C2_SDA, EVENTOUT A5 46 47 63 - VSS S - - - - B4 47 - - C3 PDR_ON I FT - - - A6 48 48 64 - VDD S - - - - 1. Function availability depends on the chosen device. DocID028094 Rev 5 39/142 43 Pinouts and pin description STM32F410x8/B 2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F410x8/Breference manual. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 40/142 DocID028094 Rev 5 AF0 AF1 AF2 AF3 SYS_AF TIM1/LPTIM1 TIM5 TIM9/ TIM11 PA0 - - TIM5_ CH1 - - PA1 - - TIM5_ CH2 - PA2 - - TIM5_ CH3 PA3 - - PA4 - PA5 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/I2S1/ SPI2/I2S2/ SPI5/I2S5 USART1/ USART2 USART6 I2C2/ I2C4 - - - - - SYS_AF - - USART2_ CTS - - - - - - - EVENTOUT - - - USART2_ RTS - - - - - - - EVENTOUT TIM9_ CH1 - I2S2_ CKIN - USART2_ TX - - - - - - - EVENTOUT TIM5_ CH4 TIM9_ CH2 - I2S2_MCK - USART2_ RX - - - - - - - EVENTOUT - - - - SPI1_NSS/ I2S1_WS - USART2_ CK - - - - - - - EVENTOUT - - - - - SPI1_SCK/ I2S1_CK - - - - - - - - - EVENTOUT PA6 - TIM1_BKIN - - - SPI1_MISO I2S2_MCK - - - - - - - - EVENTOUT PA7 - TIM1_CH1N - - - SPI1_MOSI /I2S1_SD - - - - - - - - - EVENTOUT PA8 MCO_1 TIM1_CH1 - - I2C4_ SCL - - USART1_ CK - - - - - - - EVENTOUT PA9 - TIM1_CH2 - - - - - USART1_ TX - - - - - - - EVENTOUT PA10 - TIM1_CH3 - - - - SPI5_MOSI USART1_ /I2S5_SD RX - - - - - - - EVENTOUT PA11 - TIM1_CH4 - - - - - USART1_ CTS USART6 _TX - - - - - - EVENTOUT PA12 - TIM1_ETR - - - - SPI5_MISO USART1_ RTS USART6 _RX - - - - - - EVENTOUT PA13 JTMSSWDIO - - - - - - - - - - - - - - EVENTOUT PA14 JTCKSWCLK - - - - - - - - - - - - - - EVENTOUT PA15 JTDI - - - - SPI1_NSS/ I2S1_WS - USART1_ TX - - - - - - - EVENTOUT DocID028094 Rev 5 Port A AF5 I2C1/I2C2 SPI1/I2S1/S /I2C4 PI2/I2S2 41/142 Pinouts and pin description AF6 Port AF4 STM32F410x8/B Table 10. Alternate function mapping AF0 AF1 AF2 AF3 SYS_AF TIM1/LPTIM1 TIM5 TIM9/ TIM11 PB0 - TIM1_CH2N - - - PB1 - TIM1_CH3N - - PB2 - LPTIM1_OUT - PB3 JTDOSWO - PB4 JTRST PB5 DocID028094 Rev 5 Port B AF5 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/I2S1/ SPI2/I2S2/ SPI5/I2S5 USART1/ USART2 USART6 I2C2/ I2C4 - - - - - SYS_AF - SPI5_SCK/ I2S5_CK - - - - - - - - EVENTOUT - - SPI5_NSS/ I2S5_WS - - - - - - - - EVENTOUT - - - - - - - - - - - - EVENTOUT - - I2C4_ SDA SPI1_SCK/I 2S1_CK - USART1_ RX - I2C2_ SDA - - - - - EVENTOUT - - - - SPI1_MISO - - - - - - - - - EVENTOUT - LPTIM1_IN1 - - I2C1_ SMBA SPI1_MOSI /I2S1_SD - - - - - - - - - EVENTOUT PB6 - LPTIM1_ETR - - I2C1_ SCL - - USART1_ TX - - - - - - - EVENTOUT PB7 - LPTIM1_IN2 - - I2C1_ SDA - - USART1_ RX - - - - - - - EVENTOUT PB8 - LPTIM1_OUT - - I2C1_ SCL - SPI5_MOSI /I2S5_SD - - - - - - - - EVENTOUT PB9 - - - TIM11_ CH1 I2C1_ SDA SPI2_NSS/ I2S2_WS - - - I2C2_ SDA - - - - - EVENTOUT PB10 - - - - I2C2_ SCL SPI2_SCK/ I2S2_CK I2S1_MCK - - I2C4_ SCL - - - - - EVENTOUT PB11 TRACED3 - TIM5_ CH4 - I2C2_ SDA I2S2_CKIN - - - - - - - - - EVENTOUT PB12 - TIM1_BKIN TIM5_ CH1 - I2C2_ SMBA SPI2_NSS/ I2S2_WS - - - - - - - - - EVENTOUT PB13 - TIM1_CH1N - - I2C4_ SMBA SPI2_SCK /I2S2_CK - - - - - - - - - EVENTOUT PB14 - TIM1_CH2N - - I2C4_ SDA SPI2_MISO - - - - - - - - - EVENTOUT PB15 RTC_ 50Hz TIM1_CH3N - - I2C4_ SCL SPI2_MOSI /I2S2_SD - - - - - - - - - EVENTOUT I2C1/I2C2 SPI1/I2S1/S /I2C4 PI2/I2S2 STM32F410x8/B AF6 Port AF4 Pinouts and pin description 42/142 Table 10. Alternate function mapping (continued) AF0 AF1 AF2 AF3 SYS_AF TIM1/LPTIM1 TIM5 TIM9/ TIM11 PC0 - LPTIM1_IN1 - - - PC1 - LPTIM1_OUT - - PC2 - LPTIM1_IN2 - PC3 - LPTIM1_ETR PC4 - PC5 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/I2S1/ SPI2/I2S2/ SPI5/I2S5 USART1/ USART2 USART6 I2C2/ I2C4 - - - - - SYS_AF - - - - - - - - - - EVENTOUT - - - - - - - - - - - EVENTOUT - - SPI2_MISO - - - - - - - - - EVENTOUT - - - SPI2_MOSI /I2S2_SD - - - - - - - - - EVENTOUT - - TIM9_ CH1 - - - - - - - - - - - EVENTOUT - - - TIM9_ CH2 I2C4_ SMBA - - - - - - - - - - EVENTOUT PC6 TRACE CLK - - - I2C4_ SCL I2S2_MCK - - USART6 _TX - - - - - - EVENTOUT PC7 - - - - I2C4_ SDA SPI2_SCK/ I2S2_CK I2S1_MCK - USART6 _RX - - - - - - EVENTOUT PC8 - - - - - - - - USART6 _CK - - - - - - EVENTOUT PC9 MCO_2 - - - I2C4_ SDA I2S2_CKIN - - - - - - - - - EVENTOUT PC10 TRACED0 - TIM5_ CH2 - - - - - - - - - - - - EVENTOUT PC11 TRACED1 - TIM5_ CH3 - - - - - - - - - - - - EVENTOUT PC12 TRACED2 - - TIM11_ CH1 - - - - - - - - - - - EVENTOUT PC13 - - - - - - - - - - - - - - - EVENTOUT PC14 - - - - - - - - - - - - - - - EVENTOUT PC15 - - - - - - - - - - - - - - - EVENTOUT PH0 - - - - - - - - - - - - - - - EVENTOUT PH1 - - - - - - - - - - - - - - - EVENTOUT DocID028094 Rev 5 Port C AF5 I2C1/I2C2 SPI1/I2S1/S /I2C4 PI2/I2S2 Port H 43/142 Pinouts and pin description AF6 Port AF4 STM32F410x8/B Table 10. Alternate function mapping (continued) Memory mapping 5 STM32F410x8/B Memory mapping The memory map is shown in Figure 10. Figure 10. Memory map 5HVHUYHG [([)))))))) &RUWH[0LQWHUQDO[([())))) SHULSKHUDOV ['))))))) 5HVHUYHG [ [)) [)))))))) [( ['))))))) 0E\WH EORFN &RUWH[0 V LQWHUQDO SHULSKHUDOV $+% 0E\WH EORFN 1RWXVHG [& [%))))))) 5HVHUYHG [ [[)))) [)) 5HVHUYHG [ [))))))) $3% 0E\WH EORFN 3HULSKHUDOV [ [))))))) [ [))))))) 0E\WH EORFN 65$0 0E\WH EORFN &RGH [ 5HVHUYHG 65$0 .%DOLDVHG [[))))))) E\ELWEDQGLQJ [[))) 5HVHUYHG 2SWLRQE\WHV 5HVHUYHG 273DUHDORFN 6\VWHPPHPRU\ 5HVHUYHG )ODVKPHPRU\ 5HVHUYHG 5HVHUYHG [)))&[))))))) [)))&[)))& [)))$[)))%))) [)))[)))$) [)))[))))) [[))()))) [[)))) [[)))))) [ [[)))) [)) $3% $OLDVHGWR)ODVK V\VWHPPHPRU\RU [[)))) 65$0GHSHQGLQJRQ WKH%227SLQV [ 06Y9 44/142 DocID028094 Rev 5 STM32F410x8/B Memory mapping Table 11. STM32F410x8/B register boundary addresses(1) Bus Boundary address - 0xE010 0000 - 0xFFFF FFFF Reserved (R) Cortex -M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals - 0x5000 0000 - 0xDFFF FFFF Reserved 0x4008 0400 - 0x4FFF FFFF Reserved 0x4008 0000 - 0x4008 03FF RNG 0x4002 6800 - 0x4007 FFFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2800 - 0x4002 2FFF Reserved 0x4002 2400 - 0x4002 27FF LPTIM1 0x4002 2000 - 0x4002 23FF Reserved 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 0C00 - 0x4002 1BFF Reserved 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA AHB1 DocID028094 Rev 5 Peripheral 45/142 47 Memory mapping STM32F410x8/B Table 11. STM32F410x8/B register boundary addresses(1) Bus APB2 46/142 Boundary address Peripheral 0x4001 5400- 0x4001 FFFF Reserved 0x4001 5000 - 0x4001 53FF SPI5/I2S5 0x4001 4C00- 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF Reserved 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1/I2S1 0x4001 2400 - 0x4001 2FF Reserved 0x4001 2000 - 0x4001 23FF ADC1 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0400 - 0x4001 0FFF Reserved 0x4001 0000 - 0x4001 03FF TIM1 DocID028094 Rev 5 STM32F410x8/B Memory mapping Table 11. STM32F410x8/B register boundary addresses(1) Bus APB1 Boundary address Peripheral 0x4000 7800 - 0x4000 FFFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6400 - 0x4000 6FFF Reserved 0x4000 6000 - 0x4000 63FF I2C4 FM+ 0x4000 5C00 - 0x4000 5FFF Reserved 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 4800 - 0x4000 53FF Reserved 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 1400 - 0x4000 27FF Reserved 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0000 - 0x4000 0BFF Reserved 1. The gray color is used for reserved boundary address. DocID028094 Rev 5 47/142 47 Electrical characteristics STM32F410x8/B 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 11. Figure 11. Pin loading conditions -#5 PIN # P& -36 48/142 DocID028094 Rev 5 STM32F410x8/B 6.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in Figure 12. Figure 12. Input voltage measurement -#5 PIN 6). -36 DocID028094 Rev 5 49/142 118 Electrical characteristics 6.1.6 STM32F410x8/B Power supply scheme Figure 13. Power supply scheme sd sd Zs K^<Zd tZ Khd 'W/K /E > WZ /K >Z <Z Wh ZD sW & s s & & s^^ sZ Z &Z WZKE s Z ZZ s sZ& & & & & Z Z W>> s^^ 06Y9 1. To connect PDR_ON pin, refer to Section 3.15: Power supply supervisor. Caution: 50/142 Each power supply pair (for example VDD/VSS, VDDA/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. DocID028094 Rev 5 STM32F410x8/B 6.1.7 Electrical characteristics Current consumption measurement Figure 14. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics, Table 13: Current characteristics, and Table 14: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 12. Voltage characteristics Symbol Ratings Min Max VDD-VSS External main supply voltage (including VDDA, VDD and VBAT)(1) -0.3 4.0 Input voltage on FT and TC pins(2) VSS-0.3 VDD+4.0 Input voltage on any other pin VSS-0.3 4.0 VSS 9.0 Variations between different VDD power pins - 50 Variations between all the different ground pins including VREF- - 50 VIN Input voltage for BOOT0 |VDDx| |VSSX -VSS| VESD(HBM) Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.14: Absolute maximum ratings (electrical sensitivity) V 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 13 for the values of the maximum allowed injected current. DocID028094 Rev 5 51/142 118 Electrical characteristics STM32F410x8/B Table 13. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD_x power lines (source)(1) 160 IVSS (1) -160 Total current out of sum of all VSS_x ground lines (sink) IVDD (1) Maximum current into each VDD_x power line (source) 100 IVSS Maximum current out of each VSS_x ground line (sink)(1) -100 IIO IIO IINJ(PIN) (3) IINJ(PIN) Output current sunk by any I/O and control pin 25 Output current sourced by any I/O and control pin Total output current sunk by sum of all I/O and control pins mA -25 (2) 120 Total output current sourced by sum of all I/Os and control pins(2) Injected current on FT and TC pins Unit -120 (4) -5/+0 Injected current on NRST and B pins (4) Total injected current (sum of all I/O and control pins)(5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. 3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics. 4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 14. Thermal characteristics Symbol TSTG TJ TLEAD Ratings Storage temperature range Maximum junction temperature Maximum lead temperature during soldering (WLCSP36, LQFP48, LQFP64, UFQFPN48, UFBGA64) Value Unit -65 to +150 130 C see note (1) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS directive 2011/65/EU, July 2011). 52/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 15. General operating conditions Symbol fHCLK Parameter Internal AHB clock frequency Conditions Min Typ Max Power Scale3: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x01 0 - 64 Power Scale2: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x10 0 - 84 Power Scale1: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x11 0 - 100 Unit MHz fPCLK1 Internal APB1 clock frequency - 0 - 50 MHz fPCLK2 Internal APB2 clock frequency - 0 - 100 MHz - 1.7(1) - 3.6 V 1.7(1) - 2.4 VDD VDDA(2)(3) VBAT V12 Standard operating voltage Analog operating voltage (ADC limited to 1.2 M samples) Analog operating voltage (ADC limited to 2.4 M samples) Must be the same potential as VDD(4) 2.4 - 3.6 - 1.65 - 3.6 VOS[1:0] bits in PWR_CR register = 0x01 Max frequency 64 MHz 1.08 1.14 1.20(5) VOS[1:0] bits in PWR_CR register = 0x10 Max frequency 84 MHz 1.20 1.26 1.32(5) 1.26 1.32 1.38 1.10 1.14 1.20 1.20 1.26 1.32 1.26 1.32 1.38 Backup operating voltage Regulator ON: 1.2 V internal voltage on VCAP_1 pins VOS[1:0] bits in PWR_CR register = 0x11 Max frequency 100 MHz V12 VIN V Max frequency 64 MHz Regulator OFF: 1.2 V external voltage must be supplied on Max frequency 84 MHz VCAP_1 pins Max frequency 100 MHz (5) (5) Input voltage on RST, FT and TC pins(6) 2 V VDD 3.6 V -0.3 - 5.5 VDD 2 V -0.3 - 5.2 Input voltage on BOOT0 pin - 0 - 9 DocID028094 Rev 5 V V V V 53/142 118 Electrical characteristics STM32F410x8/B Table 15. General operating conditions (continued) Symbol Parameter Conditions Min Typ Max - - 364 - - 435 - - 606 - - 328 UFBGA64 - - 253 LQFP48 - - 91 LQFP64 - - 108 UFQFPN48 - - 151 WLCSP36 - - 81 UFBGA64 - - 63 -40 - 85 -40 - 105 LQFP48 LQFP64 Maximum allowed package power dissipation at UFQFPN48 TA = 85 C (range 6) or 105 C (7) (range 7) WLCSP36 PD Power dissipation at TA = 125 C for range 3(7) TA TJ Ambient temperature for range 6 Maximum power dissipation Ambient temperature for range 7 Maximum power dissipation -40 - 105 Low power dissipation(8) -40 - 125 Ambient temperature for range 3 Maximum power dissipation -40 - 110 -40 - 130 Range 6 -40 - 105 Range 7 -40 - 125 Range 3 -40 - 130 Junction temperature range Low power Low power dissipation(8) dissipation(8) 1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 2. When the ADC is used, refer to Table 66: ADC characteristics. 3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. 4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 5. Guaranteed by test in production. 6. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 8. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. 54/142 DocID028094 Rev 5 Unit mW C STM32F410x8/B Electrical characteristics Table 16. Features depending on the operating power supply range Operating power supply range ADC operation VDD =1.7 to 2.1 V(4) Conversion time up to 1.2 Msps VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps VDD = 2.7 to 3.6 V Conversion time up to 2.4 Msps Maximum Flash memory access frequency with no wait states (fFlashmax) Maximum Flash memory access frequency with wait states (1)(2) I/O operation Possible Flash memory operations Clock output frequency on I/O pins(3) 100 MHz with 6 wait states - No I/O up to 30 MHz compensation 8-bit erase and program operations only 18 MHz 100 MHz with 5 wait states - No I/O up to 30 MHz compensation 16-bit erase and program operations 24 MHz 100 MHz with 4 wait states - I/O compensation up to 50 MHz works 16-bit erase and program operations 100 MHz with 3 wait states - up to 100 MHz when VDD = - I/O 3.0 to 3.6 V compensation - up to works 50 MHz when VDD = 2.7 to 3.0 V 32-bit erase and program operations 16 MHz (5) 30 MHz 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. Refer to Table 57: I/O AC characteristics for frequencies vs. external load. 4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 5. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power. DocID028094 Rev 5 55/142 118 Electrical characteristics 6.3.2 STM32F410x8/B VCAP_1 external capacitor Stabilization for the main regulator is achieved by connecting the external capacitor CEXT to the VCAP_1 pin. CEXT is specified in Table 17. Figure 15. External capacitor CEXT & (65 5/HDN 069 1. Legend: ESR is the equivalent series resistance. Table 17. VCAP_1 operating conditions 6.3.3 Symbol Parameter Conditions CEXT Capacitance of external capacitor 4.7 F ESR ESR of external capacitor <1 Operating conditions at power-up/power-down (regulator ON) Subject to general operating conditions for TA. Table 18. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD 6.3.4 Parameter Min Max VDD rise time rate 20 VDD fall time rate 20 Unit s/V Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 19. Operating conditions at power-up / power-down (regulator OFF)(1) Symbol tVDD tVCAP Parameter Conditions Min Max VDD rise time rate Power-up 20 VDD fall time rate Power-down 20 VCAP_1 rise time rate Power-up 20 VCAP_1 fall time rate Power-down 20 1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below 1.08 V. 56/142 DocID028094 Rev 5 Unit s/V STM32F410x8/B 6.3.5 Electrical characteristics Embedded reset and power control block characteristics The parameters given in Table 20 are derived from tests performed under ambient temperature and VDD supply voltage @ 3.3V. Table 20. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst(2) PVD hysteresis VPOR/PDR Typ Max PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 PLS[2:0]=100 (falling edge) 2.59 2.66 2.71 PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 PLS[2:0]=101 (falling edge) 2.65 2.84 3.02 PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 PLS[2:0]=110 (falling edge) 2.85 2.93 2.99 PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 PLS[2:0]=111 (falling edge) 2.95 3.03 3.09 - 100 - Power-on/power-down reset threshold VPDRhyst(2) PDR hysteresis Min Falling edge Rising edge - (1) 1.76 1.64 1.72 1.80 - 40 - Brownout level 1 threshold Falling edge 2.13 2.19 2.24 Rising edge 2.23 2.29 2.33 VBOR2 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 Rising edge 2.53 2.59 2.63 VBOR3 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 Rising edge 2.85 2.92 2.97 BOR hysteresis - - 100 POR reset timing - 0.5 1.5 VBORhyst TRSTTEMPO (2)(3) DocID028094 Rev 5 V mV VBOR1 (2) V mV 1.68 1.60 Unit - V mV 3.0 ms 57/142 118 Electrical characteristics STM32F410x8/B Table 20. Embedded reset and power control block characteristics (continued) Symbol IRUSH(2) ERUSH (2) Parameter Conditions Min Typ Max Unit In-Rush current on voltage regulator poweron (POR or wakeup from Standby) - 160 200 mA In-Rush energy on voltage regulator power- VDD = 1.7 V, TA = 125 C, on (POR or wakeup from IRUSH = 171 mA for 31 s Standby) - - 5.4 C 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design. 3. The reset timing is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first instruction is fetched by the user application code. 6.3.6 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 14: Current consumption measurement scheme. All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. Typical and maximum current consumption The MCU is placed under the following conditions: 58/142 * All I/O pins are in input mode with a static value at VDD or VSS (no load). * All peripherals are disabled except if it is explicitly mentioned. * The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges (refer to Table 16: Features depending on the operating power supply range). * The voltage scaling is adjusted to fHCLK frequency as follows: - Scale 3 for fHCLK 64 MHz - Scale 2 for 64 MHz < fHCLK 84 MHz - Scale 1 for 84 MHz < fHCLK 100 MHz * The system clock is HCLK, fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK. * External clock is 4 MHz and PLL is ON except if it is explicitly mentioned. * The maximum values are obtained for VDD = 3.6 V and a maximum ambient temperature (TA), and the typical values for TA= 25 C and VDD = 3.3 V unless otherwise specified. DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 21. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V Symbol Parameter Conditions External clock, all peripherals enabled(3)(4) IDD Supply current in Run mode HSI, PLL off, all peripherals enabled(3)(4) External clock, all peripherals disabled(3) HSI, PLL off, all peripherals disabled(3) PLL fHCLK Voltage VCO (MHz) scale (MHz) Max(2) Typ (1) TA= 25 C TA= 25 C TA= 85 C TA= 105 C TA= 125 C 100 S1 200 17.4 18.3(5) 19.1 19.4(6) 20.2(5) 84 S2 168 14.1 14.8(5) 15.4 15.8(6) 16.6(5) 64 S3 128 9.8 10.3(5) 10.7 11.0(6) 11.7(5) 50 S3 100 7.7 8.1 8.5 8.8 9.5 25 S3 100 4.1 4.4 4.7 5.0 5.7 20 S3 160 3.5 3.8 4.1 4.4 5.1 16 S3 off 2.5 2.6 2.9 3.2 4.0 1 S3 off 0.4 0.5 0.8 1.2 2.0 100 S1 200 11.8 12.5 12.9 13.3 14.1 84 S2 168 9.6 10.1 10.4 10.8 11.6 64 S3 128 6.7 7.2 7.4 7.7 8.4 50 S3 100 5.3 5.6 5.9 6.2 6.9 25 S3 100 2.9 3.1 3.3 3.7 4.4 20 S3 160 2.5 2.7 2.9 3.2 3.9 16 S3 off 1.7 1.9 2.1 2.4 3.2 1 S3 off 0.3 0.4 0.7 1.1 1.9 Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization, unless otherwise specified 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) 5. Guaranteed by tests in production. 6. Guaranteed by test in production for temperature range 7 salestypes only. DocID028094 Rev 5 59/142 118 Electrical characteristics STM32F410x8/B Table 22. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.6 V Symbol Parameter Conditions External clock, all peripherals enabled(3)(4) IDD Supply current in Run mode HSI, PLL off, all peripherals enabled(3)(4) External clock, all peripherals disabled(3) HSI, PLL off, all peripherals disabled(3) fHCLK (MHz) PLL Voltage VCO scale (MHz) Max(2) Typ (1) TA= 25 C TA= 25 C TA= TA= TA= 85 C 105 C 125 C 100 S1 200 17.7 19.1(5) 19.3 19.7(6) 20.5(5) 84 S2 168 14.4 15.3(5) 15.7 16.0(6) 16.8(5) 64 S3 128 10.1 10.6(5) 11.0 11.3(6) 12.0(5) 50 S3 100 8.0 8.4 8.8 9.1 9.8 25 S3 100 4.4 4.7 4.9 5.2 5.9 20 S3 160 3.8 4.1 4.3 4.6 5.3 16 S3 off 2.5 2.6 2.9 3.2 4.0 1 S3 off 0.4 0.5 0.8 1.2 2.0 100 S1 200 12.1 13.1(5) 13.1 13.5(6) 14.3(5) 84 S2 168 9.8 10.6(5) 10.7 11.0(6) 11.8(5) 64 S3 128 7.0 7.4(5) 7.6 7.9(6) 8.6(5) 50 S3 100 5.6 5.9 6.1 6.4 7.2 25 S3 100 3.1 3.3 3.5 3.9 4.8 20 S3 160 2.8 3.0 3.2 3.5 4.4 16 S3 off 1.7 1.8 2.1 2.4 3.3 1 S3 off 0.4 0.4 0.7 1.1 1.8 Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization. 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) 5. Guaranteed by tests in production. 6. Guaranteed by test in production for temperature range 7 salestypes only. 60/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 23. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V Symbol Parameter Conditions External clock, all peripherals enabled(3)(4) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(3)(4) External clock, all peripherals disabled(3) HSI, PLL OFF, all peripherals disabled(3) PLL fHCLK Voltage VCO (MHz) scale (MHz) Max(2) Typ (1) TA= 25 C TA = 25 C TA = TA = TA = 85 C 105 C 125 C 100 S1 200 15.7 16.5 16.5 16.9 17.8 84 S2 168 12.7 13.3 13.4 13.8 14.6 64 S3 128 8.8 9.3 9.4 9.7 10.6 50 S3 100 7.0 7.4 7.5 7.8 8.6 25 S3 100 3.9 4.1 4.3 4.7 5.6 20 S3 160 3.4 3.6 3.8 4.2 5.1 16 S3 off 2.4 2.5 2.8 3.2 4.1 1 S3 off 0.6 0.7 1.0 1.4 2.3 100 S1 200 10.1 10.7 10.8 11.2 12.0 84 S2 168 8.2 8.6 8.7 9.1 10.0 64 S3 128 5.7 6.1 6.2 6.6 7.4 50 S3 100 4.6 4.9 5.0 5.4 6.3 25 S3 100 2.6 2.8 3.0 3.4 4.3 20 S3 160 2.4 2.5 2.8 3.1 4.0 16 S3 off 1.7 1.8 2.1 2.4 3.3 1 S3 off 0.6 0.6 1.0 1.4 2.2 Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization, unless otherwise specified. 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) DocID028094 Rev 5 61/142 118 Electrical characteristics STM32F410x8/B Table 24. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V Symbol Parameter Conditions External clock, all peripherals enabled(3)(4) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(3)(4) External clock, all peripherals disabled(3) HSI, PLL OFF, all peripherals disabled(3) Max(2) fHCLK (MHz) Voltage scale PLL VCO (MHz) Typ (1) TA= 25 C TA = 25 C TA = 85 C TA = TA = 105 C 125 C 100 S1 200 16.3 17.3(5) 17.1 17.5(6) 18.4(5) 84 S2 168 13.2 14.1 14.0 14.3 15.2 64 S3 128 9.3 10.0 9.9 10.2 11.1 50 S3 100 7.4 8.0 8.0 8.3 9.2 25 S3 100 4.2 4.7 4.8 5.0 5.9 20 S3 160 3.7 4.2 4.3 4.6 5.5 16 S3 off 2.4 2.8 3.0 3.4 4.3 1 S3 off 0.6 1.0 1.2 1.5 2.4 100 S1 200 10.6 11.4(5) 11.4 84 S2 168 8.7 9.4 9.3 9.7 10.6 64 S3 128 6.2 6.8 6.8 7.1 7.9 50 S3 100 5.0 5.5 5.5 5.8 6.8 25 S3 100 2.9 3.4 3.5 3.8 4.7 20 S3 160 2.7 3.1 3.2 3.5 4.4 16 S3 off 1.7 2.1 2.3 2.6 3.5 1 S3 off 0.6 0.9 1.1 1.5 2.4 11.7(6) 12.6(5) Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization, unless otherwise specified. 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) 5. Guaranteed by tests in production. 6. Guaranteed by test in production on temperature range 7 salestypes only. 62/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 25. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.6 V Symbol Parameter Conditions External clock, all peripherals enabled(3)(4) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(3)(4) External clock, all peripherals disabled(3) HSI, PLL OFF, all peripherals disabled(3) fHCLK (MHz) PLL Voltage VCO scale (MHz) Max(2) Typ (1) TA= 25 C TA = 25 C TA = 85 C TA = TA = 105 C 125 C 100 S1 200 24.7 26.3 26.5 27.0 28.0 84 S2 168 21.6 23.0 23.2 23.7 24.7 64 S3 128 15.9 17.0 17.1 17.6 18.6 50 S3 100 13.1 14.2 14.3 14.7 15.7 25 S3 100 7.5 8.2 8.3 8.7 9.7 20 S3 160 6.5 7.1 7.2 7.5 8.5 16 S3 off 4.7 5.3 5.5 5.9 6.9 1 S3 off 0.8 1.2 1.6 1.9 2.9 100 S1 200 19.1 20.5 20.7 21.3 22.3 84 S2 168 17.1 18.3 18.6 19.1 20.1 64 S3 128 12.8 13.8 14.0 14.5 15.5 50 S3 100 10.7 11.7 11.8 12.2 13.2 25 S3 100 6.3 7.0 7.1 7.4 8.3 20 S3 160 5.4 6.0 6.2 6.5 7.4 16 S3 off 4.0 4.5 5.0 5.1 6.0 1 S3 off 0.8 1.1 1.5 1.8 2.7 Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization, unless otherwise specified. 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) DocID028094 Rev 5 63/142 118 Electrical characteristics STM32F410x8/B Table 26. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.7 V Symbol Parameter Conditions External clock, all peripherals enabled(3)(4) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(3)(4) External clock, all peripherals disabled(3) HSI, PLL OFF, all peripherals disabled(3) fHCLK (MHz) PLL Voltage VCO scale (MHz) (1) Max(2) Typ TA= TA = 25 C 25 C TA = TA = TA = 85 C 105 C 125 C 100 S1 200 24.2 26.2 25.7 26.5 27.6 84 S2 168 20.0 21.8 21.4 22.1 23.1 64 S3 128 15.8 17.2 17.0 17.7 18.7 50 S3 100 13.3 16.5 14.4 15.0 16.0 25 S3 100 7.5 9.5 8.3 8.8 9.8 20 S3 160 6.7 8.2 7.3 7.7 8.6 16 S3 off 5.1 6.4 5.7 6.2 7.1 1 S3 off 0.8 1.0 1.3 1.7 2.6 100 S1 200 18.6 23.0 23.4 23.9 24.9 84 S2 168 15.5 19.3 19.9 20.4 21.4 64 S3 128 12.7 16.1 16.7 17.0 18.0 50 S3 100 10.9 13.9 14.3 14.7 15.7 25 S3 100 6.3 8.1 8.4 8.7 9.7 20 S3 160 5.6 7.2 7.3 7.6 8.4 16 S3 off 4.3 5.5 5.8 6.2 7.1 1 S3 off 0.8 1.0 1.3 1.6 2.5 Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization, unless otherwise specified. 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) 64/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 27. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V Symbol Parameter Conditions External clock, all peripherals enabled(3)(4) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(3)(4) External clock, all peripherals disabled(3) HSI, PLL OFF, all peripherals disabled(3) fHCLK (MHz) PLL Voltage VCO scale (MHz) Max(2) Typ (1) TA= 25 C TA = 25 C TA = 85 C TA = TA = 105 C 125 C 100 S1 200 27.1 28.9 28.9 29.5 30.5 84 S2 168 23.2 24.8 24.9 25.5 26.5 64 S3 128 17.0 18.3 18.4 18.8 19.8 50 S3 100 13.6 14.7 14.7 15.2 16.2 25 S3 100 7.5 8.2 8.3 8.7 9.7 20 S3 160 6.5 7.1 7.2 7.5 8.5 16 S3 off 4.7 5.3 5.5 5.9 6.9 1 S3 off 0.8 1.2 1.4 1.8 2.8 100 S1 200 21.5 23.0 23.2 23.8 24.8 84 S2 168 18.7 20.0 20.3 20.8 21.8 64 S3 128 14.0 15.1 15.2 15.7 16.7 50 S3 100 11.2 12.2 12.3 12.7 13.7 25 S3 100 6.3 7.0 7.1 7.4 8.4 20 S3 160 5.4 6.0 6.2 6.5 7.5 16 S3 off 4.0 4.5 4.8 5.1 6.1 1 S3 off 0.8 1.1 1.4 1.7 2.7 Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization, unless otherwise specified. 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) DocID028094 Rev 5 65/142 118 Electrical characteristics STM32F410x8/B Table 28. Typical and maximum current consumption in Sleep mode - VDD = 3.6 V Symbol Parameter Conditions All peripherals enabled(3)(4), External clock, PLL ON, Flash memory in Deep power down mode IDD Supply current in Sleep mode All peripherals enabled(3)(4), HSI, PLL OFF, Flash memory in Deep power down mode All peripherals enabled(3)(4), External clock, PLL ON, Flash memory ON All peripherals enabled(3), HSI, PLL OFF, Flash memory ON 66/142 PLL fHCLK Voltage VCO (MHz) scale (MHz) Max(2) Typ (1) TA= 25 C TA = 25 C TA = TA = TA = 85 C 105 C 125 C 100 S1 200 8.0 8.2(5) 9.0 9.4(6) 10.2(5) 84 S2 168 6.5 6.7 7.4 7.7 8.5 64 S3 128 4.6 4.7 5.2 5.5 6.3 50 S3 100 3.7 3.9 4.3 4.6 5.4 25 S3 100 2.2 2.3 2.6 2.9 3.8 20 S3 160 2.1 2.2 2.5 2.8 3.6 16 S3 off 1.1 1.2 1.5 1.9 2.7 1 S3 off 0.3 0.4 0.7 1.1 1.9 Unit mA 100 S1 200 8.4 8.7 9.5 9.9 10.7 84 S2 168 6.9 7.1 7.7 8.1 8.9 64 S3 128 4.9 5.1 5.5 5.9 6.7 50 S3 100 4.0 4.2 4.6 4.9 5.7 25 S3 100 2.5 2.6 2.9 3.2 4.0 20 S3 160 2.4 2.5 2.7 3.1 3.9 16 S3 off 1.4 1.4 1.8 2.2 3.0 1 S3 off 0.6 0.6 1.0 1.3 2.0 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 28. Typical and maximum current consumption in Sleep mode - VDD = 3.6 V (continued) Symbol Parameter Conditions All peripherals disabled, External clock, PLL ON, Flash memory in Deep power down mode Supply current in IDD Sleep (continued) mode (continued) All peripherals disabled, HSI, PLL OFF, Flash memory in Deep power down mode All peripherals disabled, External clock, PLL ON, Flash memory ON All peripherals disabled, HSI, PLL OFF, Flash memory in Deep power down mode PLL fHCLK Voltage VCO (MHz) scale (MHz) Max(2) Typ (1) TA= 25 C TA = 25 C TA = TA = TA = 85 C 105 C 125 C 100 S1 200 2.2 2.3(5) 2.6 3.0(6) 3.8(5) 84 S2 168 1.8 1.9 2.2 2.6 3.4 64 S3 128 1.4 1.5 1.8 2.1 2.9 50 S3 100 1.2 1.3 1.6 1.9 2.7 25 S3 100 0.9 1.0 1.3 1.7 2.5 20 S3 160 1.0 1.2 1.4 1.7 2.5 16 S3 off 0.3 0.4 0.7 1.1 1.9 1 S3 off 0.3 0.3 0.7 1.0 1.8 100 S1 200 2.6 2.7 3.0 3.4 4.2 84 S2 168 2.2 2.3 2.6 3.0 3.8 64 S3 128 1.8 1.9 2.1 2.5 3.3 50 S3 100 1.5 1.6 1.9 2.2 3.1 25 S3 100 1.2 1.4 1.6 2.0 2.8 20 S3 160 1.3 1.4 1.7 2.0 2.8 16 S3 off 0.6 0.6 1.0 1.3 2.0 1 S3 off 0.5 0.6 0.9 1.3 2.0 Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization, unless otherwise specified. 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) 5. Guaranteed by tests in production. 6. Guaranteed by test in production on temperature range 7 salestypes only. DocID028094 Rev 5 67/142 118 Electrical characteristics STM32F410x8/B Table 29. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V Symbol Parameter Conditions All peripherals enabled(3) (4), External clock, PLL ON, Flash memory in Deep power down mode IDD Supply current in Sleep mode All peripherals enabled(3)(4), HSI, PLL OFF, Flash memory in Deep power down mode All peripherals enabled(3)(4), External clock, PLL ON, Flash memory ON All peripherals enabled(3)(4), HSI, PLL OFF, Flash memory ON 68/142 PLL fHCLK Voltage VCO (MHz) scale (MHz)(1) Max(2) Typ TA= 25 C TA = 25 C TA = TA = TA = 85 C 105 C 125 C 100 S1 200 7.7 7,9 8,8 9,2 10.0 84 S2 168 6.2 6,4 7,1 7,5 8.3 64 S3 128 4.3 4,5 5,0 5,3 6.1 50 S3 100 3.4 3,6 4,0 4,4 5.2 25 S3 100 2.0 2,1 2,4 2,7 3.5 20 S3 160 1.8 1,9 2,3 2,6 3.4 16 S3 off 1.1 1,2 1,5 1,9 2.7 1 S3 off 0.3 0,4 0,7 1,0 1.8 100 S1 200 8.1 8,4 9,3 9,7 10.5 84 S2 168 6.6 6,8 7,5 7,9 8.7 64 S3 128 4.7 4,8 5,4 5,7 6.5 50 S3 100 3.8 3,9 4,4 4,7 5.5 25 S3 100 2.3 2,4 2,7 3,1 3.9 20 S3 160 2.1 2,2 2,6 2,9 3.7 16 S3 off 1.4 1,5 1,8 2,2 3.0 1 S3 off 0.5 0,6 1,0 1,3 2.0 Unit mA DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 29. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V (continued) Symbol Parameter Conditions All peripherals disabled, External clock, PLL ON, Flash memory in Deep power down mode Supply current in IDD Sleep (continued) mode (continued) All peripherals disabled, HSI, PLL OFF, Flash memory in Deep power down mode All peripherals disabled, External clock, PLL ON, Flash memory ON All peripherals disabled, HSI, PLL OFF, Flash memory in Deep power down mode fHCLK Voltage (MHz) scale PLL VCO (MHz)(1) Max(2) Typ TA= 25 C TA = 25 C TA = TA = TA = 85 C 105 C 125 C 100 S1 200 1.9 2,0 2,4 2,7 3.5 84 S2 168 1.6 1,7 2,0 2,4 3.2 64 S3 128 1.1 1,2 1,5 1,9 2.7 50 S3 100 0.9 1,0 1,3 1,7 2.5 25 S3 100 0.7 0,8 1,1 1,4 2.2 20 S3 160 0.8 0,8 1,2 1,5 2.3 16 S3 off 0.3 0,4 0,7 1,0 1.8 1 S3 off 0.2 0,3 0,6 1,0 1.8 100 S1 200 2.3 2,4 2,9 3,3 4.0 84 S2 168 2.0 2,1 2,4 2,8 3.6 64 S3 128 1.5 1,6 1,9 2,3 3.1 50 S3 100 1.3 1,4 1,7 2,0 2.8 25 S3 100 1.0 1,1 1,4 1,7 2.5 20 S3 160 1.0 1,2 1,5 1,8 2.6 16 S3 off 0.6 0,6 1,0 1,4 2.1 1 S3 off 0.5 0,6 0,9 1,3 2.0 Unit mA 1. Refer to Table 44 and RM0401 for the possible PLL VCO setting 2. Guaranteed by characterization, unless otherwise specified. 3. When the ADC is ON (ADON bit set in ADC_CR2), an additional power consumption of 1.6 mA must be added. 4. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register) DocID028094 Rev 5 69/142 118 Electrical characteristics STM32F410x8/B Table 30. Typical and maximum current consumptions in Stop mode - VDD = 1.7 V Typ Symbol Conditions Max TA = TA = TA = TA = TA = 25 C 25 C(1) 85 C 105 C(1) 125 C(1) Flash in Stop mode, Main regulator usage 105.6 all oscillators OFF, no independent Low power regulator usage 39.5 watchdog IDD_STOP Flash in Deep power Main regulator usage down mode, all Low power regulator usage oscillators OFF, no independent Low power low voltage watchdog regulator usage 117.1 385.1 665.7 1270.0 48.7 287.5 548.4 1070.0 77.8 87.5 351.3 630.1 1222.0 11.0 20.0 254.2 512.0 1006.0 6.1 13.6 217.0 442.5 941.0 Unit A 1. Guaranteed by characterization. Table 31. Typical and maximum current consumption in Stop mode - VDD=3.6 V Symbol Conditions Flash in Stop mode, all oscillators OFF, no independent watchdog IDD_STOP Flash in Deep power down mode, all oscillators OFF, no independent watchdog Typ Max TA = 25 C TA = TA = TA = TA = 25 C(1) 85 C 105 C(1) 125 C(1) 392.8 675.4(3) 1280.0(2) 41.03 50.31(2) 290.9 554.2(3) 1077.0(2) Main regulator usage 80.32 94.0(2) 357.0 639.5(3) 1232.0(2) Low power regulator usage 12.41 21.5(2) 258.1 518.1(3) 1010.0(2) Low power low voltage regulator usage 7.53 15.2(2) 221.6 449.2(3) 947.0(2) Main regulator usage 108.6 Low power regulator usage 126(2) Unit A 1. Guaranteed by characterization. 2. Guaranteed by tests in production. 3. Guaranteed by test in production on temperature range 7 salestypes only. Table 32. Typical and maximum current consumption in Standby mode - VDD= 1.7 V Typ Symbol Parameter Conditions IDD_STBY Supply current in Standby mode TA = 25 C TA = 25 C(1) TA = 85 C TA = 105 C(1) TA = 125 C(1) Low-speed oscillator (LSE) and RTC ON 2.1 2.9 6.5 18.2 60.0 RTC and LSE OFF 1.2 1.9 5.5 17.1 59.0 1. Guaranteed by characterization, unless otherwise specified. 70/142 Max DocID028094 Rev 5 Unit A STM32F410x8/B Electrical characteristics Table 33. Typical and maximum current consumption in Standby mode - VDD= 3.6 V Typ Symbol Parameter Conditions IDD_STBY Supply current in Standby mode Low-speed oscillator (LSE) and RTC ON RTC and LSE OFF Max TA = 25 C TA = 25 C(1) 3.4 4.3 (2) 2.5 3.3 TA = TA = TA = 85 C 105 C(1) 125 C(1) 8.9 7.8 22.8 21.6 (3) 65.0 64.0 Uni t A (2) 1. Guaranteed by characterization, unless otherwise specified. 2. Guaranteed by tests in production. 3. Guaranteed by test in production on temperature range 7 salestypes only. Table 34. Typical and maximum current consumptions in VBAT mode (LSE and RTC ON, LSE low- drive mode) Max(2) Typ Symbol TA = 85 C TA = 25 C Conditions(1) Parameter VBAT = VBAT= VBAT = 1.7 V 2.4 V 3.3 V IDD_VBAT Backup domain supply current TA = 105 C TA = 125 C Unit VBAT = 3.6 V Low-speed oscillator (LSE in low-drive mode) and RTC ON 0.7 0.8 1.1 2.8 4.2 5.6 Low-speed oscillator (LSE in high-drive mode) and RTC ON 1.4 1.6 1.9 4.2 7.0 8.6 RTC and LSE OFF 0.1 0.1 0.1 2.0 4.0 5.8 A 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2. Guaranteed by characterization. DocID028094 Rev 5 71/142 118 Electrical characteristics STM32F410x8/B Figure 16. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator in "low power" mode selection ,''B9%$7 $ 7HPSHUDWXUH & 069 Figure 17. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator in "high-drive" mode selection) ,''B9%$7 $ 7HPSHUDWXUH & 069 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 55: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt 72/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (see Table 36: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD x f SW x C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DocID028094 Rev 5 73/142 118 Electrical characteristics STM32F410x8/B Table 35. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS IDDIO I/O switching current VDD = 3.3 V CEXT =10 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT + CS I/O toggling Typ frequency (fSW) 2 MHz 0.05 8 MHz 0.15 25 MHz 0.45 50 MHz 0.85 60 MHz 1.00 84 MHz 1.40 90 MHz 1.67 2 MHz 0.10 8 MHz 0.35 25 MHz 1.05 50 MHz 2.20 60 MHz 2.40 84 MHz 3.55 90 MHz 4.23 2 MHz 0.20 8 MHz 0.65 25 MHz 1.85 50 MHz 2.45 60 MHz 4.70 84 MHz 8.80 90 MHz 10.47 2 MHz 0.25 8 MHz 1.00 25 MHz 3.45 50 MHz 7.15 60 MHz 11.55 2 MHz 0.32 8 MHz 1.27 25 MHz 3.88 50 MHz 12.34 1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value). 74/142 DocID028094 Rev 5 Unit mA STM32F410x8/B Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions: * At startup, all I/O pins are in analog input configuration. * All peripherals are disabled unless otherwise mentioned. * The ART accelerator is ON. * Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V. * HCLK is the system clock at 100 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK. The given value is calculated by measuring the difference of current consumption * - with all peripherals clocked off - with only one peripheral clocked on Ambient operating temperature is 25 C and VDD=3.3 V. Table 36. Peripheral current consumption IDD (Typ) Peripheral AHB1 (up to 100 MHz) APB1 (up to 50 MHz) Voltage scale1 Voltage scale2 Voltage scale3 GPIOA 1.68 1.62 1.42 GPIOB 1.67 1.60 1.41 GPIOC 1.63 1.56 1.39 GPIOH 0.61 0.61 0.52 CRC 0.31 0.32 0.25 DMA1(1) 1.67N + 3.12 1.60N + 2.96 1.43N + 2.64 DMA2(1) 1.59N + 2.83 1.52N + 2.65 1.36N + 2.41 RNG 0.90 0.88 0.75 APB1 to AHB 0,78 0,74 0,63 TIM5 13,38 12,76 11,41 TIM6 2,14 1,98 1,75 LPTIM 8,22 7,88 7,06 WWDG 0,64 0,64 0,56 SPI2/I2S2 2,42 2,33 2,06 USART2 3,38 3,29 2,91 I2C1 3,46 3,33 2,97 I2C2 3,50 3,31 2,97 I2C4 4,82 4,64 4,09 PWR 0,66 0,64 0,62 DAC 0,84 0,81 0,78 DocID028094 Rev 5 Unit A/MHz A/MHz 75/142 118 Electrical characteristics STM32F410x8/B Table 36. Peripheral current consumption (continued) IDD (Typ) Peripheral APB2 (up to 100 MHz) Voltage scale1 Voltage scale2 Voltage scale3 APB2 to AHB 0,22 0,19 0,17 TIM1 6,62 6,36 5,66 USART1 3,19 3,10 2,77 USART6 3,10 2,99 2,66 ADC1 3,35 3,25 2,88 SPI1/I2S1 1,82 1,77 1,58 SYSCFG 0,83 0,81 0,72 EXTI 0,92 0,88 0,80 TIM9 2,90 2,81 2,48 TIM11 2,13 2,06 1,81 SPI5/I2S5 1,88 1,83 1,59 1.91 1.82 1.64 Bus matrix 1. Valid if all the DMA streams are activated (please refer to the reference manual RM0401). 76/142 DocID028094 Rev 5 Unit A/MHz STM32F410x8/B 6.3.7 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 37 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep modes: the wakeup event is WFE. * WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. Figure 18. Low-power mode wakeup :DNHXSIURP6WRSPRGH PDLQUHJXODWRU 2SWLRQE\WHVDUHQRWUHORDGHG &38UHVWDUW 5HJXODWRU +6,UHVWDUW )ODVKVWRSH[LW UDPSXS :DNHXSIURP6WRSPRGH PDLQUHJXODWRU IODVKLQ'HHSSRZHUGRZQPRGH 2SWLRQE\WHVDUHQRWUHORDGHG &38UHVWDUW 5HJXODWRU +6,UHVWDUW )ODVK'HHS3GUHFRYHU\ UDPSXS :DNHXSIURP6WRS UHJXODWRULQORZSRZHUPRGH 2SWLRQE\WHVDUHQRWUHORDGHG 5HJXODWRU UDPSXS &38UHVWDUW +6,UHVWDUW )ODVKVWRSH[LW :DNHXSIURP6WRS UHJXODWRULQORZSRZHUPRGH IODVKLQ'HHSSRZHUGRZQPRGH 2SWLRQE\WHVDUHQRWUHORDGHG 5HJXODWRU UDPSXS :DNHXSIURP6WDQGE\PRGH &38UHVWDUW )ODVK'HHS3GUHFRYHU\ 5HJXODWRU 2)) 5HJXODWRU UHVWDUW :DNHXSIURP6OHHSDQG )ODVKLQ'HHSSRZHUGRZQ +6,UHVWDUW &38UHVWDUW +6,UHVWDUW 5HJXODWRU 21 &38UHVWDUW )ODVK'HHS3GUHFRYHU\ 2SWLRQE\WHVORDGLQJ 2SWLRQE\WHVDUHQRWUHORDGHG )ODVK'HHS3GUHFRYHU\ 069 All timings are derived from tests performed under ambient temperature and VDD=3.3 V. DocID028094 Rev 5 77/142 118 Electrical characteristics STM32F410x8/B Table 37. Low-power mode wakeup timings(1) Symbol Parameter Min Typ Max Unit - - 4 6 CPU clock cycles Flash memory in Deep power down mode - - 40,0 Main regulator - 12.9 15.0 - 104.9 115.0 - 20.8 25.0 - 112.9 120.0 Main regulator, Flash memory in Stop or Deep power down mode - 4.9 7.0 Regulator in low-power mode, Flash memory in Stop or Deep power down mode(3) - 12.8 20.0 Wakeup from Standby mode - - 316.8 350.0 Wakeup of Flash memory From Flash_Stop mode - - 10.0 Wakeup of Flash memory From Flash Deep power down mode - - 40.0 tWUSLEEP(2) Conditions Wakeup from Sleep mode tWUSLEEPFDSM(2) tWUSTOP(2) Main regulator, Flash memory Wakeup from Stop mode, in Deep power down mode code execution from Flash Regulator in low-power mode(3) memory Regulator in low-power mode, Flash memory in Deep power down mode Wakeup from Stop mode, code execution from RAM tWUSTDBY(2)(4) tWUFLASH s 1. Guaranteed by characterization. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. The specification is valid for wakeup from regulator in low power mode or in low power low voltage mode, since the timing difference is negligible. 4. tWUSTDBY maximum value is given at - 40 C. 6.3.8 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 55. However, the recommended clock input waveform is shown in Figure 19. The characteristics given in Table 38 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 15. 78/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 38. High-speed external user clock characteristics Symbol Parameter Conditions fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage VHSEL OSC_IN input pin low level voltage tw(HSE) tw(HSE) OSC_IN high or low time(1) Min Typ Max Unit 1 - 50 MHz 0.7VDD - VDD VSS - 0.3VDD 5 - - - V ns tr(HSE) tf(HSE) OSC_IN rise or fall time Cin(HSE) (1) - - 10 - - 5 - pF - 45 - 55 % VSS VIN VDD - - 1 A OSC_IN input capacitance(1) DuCy(HSE) Duty cycle OSC_IN Input leakage current IL 1. Guaranteed by design. Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 55. However, the recommended clock input waveform is shown in Figure 20. The characteristics given in Table 39 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 15. Table 39. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD VSS - 0.3VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 Cin(LSE) DuCy(LSE) IL - V ns OSC32_IN input capacitance(1) - - 5 - pF Duty cycle - 30 - 70 % VSS VIN VDD - - 1 A OSC32_IN Input leakage current 1. Guaranteed by design. DocID028094 Rev 5 79/142 118 Electrical characteristics STM32F410x8/B Figure 19. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR(3% TF(3% T7(3% /3#?). ), T7(3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34-& AI Figure 20. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W: /6( W: /6( W 7/6( ([WHUQDO FORFNVRXUFH I/6(BH[W 26&B,1 ,/ 670) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 80/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 40. HSE 4-26 MHz oscillator characteristics(1) Symbol fOSC_IN RF IDD Parameter Conditions Min Typ Max Unit Oscillator frequency - 4 - 26 MHz Feedback resistor - - 200 - k VDD=3.3 V, ESR= 30 , CL=5 pF @25 MHz - 450 - VDD=3.3 V, ESR= 30 , CL=10 pF @25 MHz - 530 - Startup - - 1 mA/V VDD is stabilized - 2 - ms HSE current consumption Gm_crit_max Maximum critical crystal gm tSU(HSE)(2) Startup time A 1. Guaranteed by design. 2. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 21. Typical application with an 8 MHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ 0+] UHVRQDWRU &/ I+6( 26&B,1 5(;7 5) 26&B28 7 %LDV FRQWUROOHG JDLQ 670) DL 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 41. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). DocID028094 Rev 5 81/142 118 Electrical characteristics STM32F410x8/B The LSE high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption. Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter RF Feedback resistor IDD LSE current consumption Gm_crit_max Maximum critical crystal gm tSU(LSE)(2) startup time Conditions Min Typ Max Unit - - 18.4 - M Low-power mode (default) - - 1 High-drive mode - - 3 Startup, low-power mode - - 0.56 Startup, high-drive mode - - 1.50 VDD is stabilized - 2 - A A/V s 1. Guaranteed by design. 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is guaranteed by characterization. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. For information about the LSE high-power mode, refer to the reference manual RM0401. Figure 22. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU &/ I/6( 26&B,1 26&B28 7 670) DL 82/142 DocID028094 Rev 5 STM32F410x8/B Internal clock source characteristics The parameters given in Table 42 and Table 43 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15. High-speed internal (HSI) RC oscillator Table 42. HSI oscillator characteristics (1) L Symbol fHSI Parameter Frequency Conditions Min Typ Max Unit - - 16 - MHz - - 1 % -8 - 5.5 % -4 - 4 % -1 - 1 % User-trimmed with the RCC_CR register(2) ACCHSI Accuracy of the HSI oscillator Factorycalibrated TA = -40 to 125 C(3) TA = -10 to 85 TA = 25 C(4) C(3) tsu(HSI)(2) HSI oscillator startup time - - 2.2 4 s IDD(HSI)(2) HSI oscillator power consumption - - 60 80 A 1. VDD = 3.3 V, TA = -40 to 125 C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization. 4. Factory calibrated non-soldered parts. Figure 23. ACCHSI versus temperature !##(3) 6.3.9 Electrical characteristics 4! # -IN -AX 4YPICAL -36 1. Guaranteed by characterization. DocID028094 Rev 5 83/142 118 Electrical characteristics STM32F410x8/B Low-speed internal (LSI) RC oscillator Table 43. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 s LSI oscillator power consumption - 0.4 0.6 A Frequency (3) IDD(LSI)(3) 1. VDD = 3 V, TA = -40 to 125 C unless otherwise specified. 2. Guaranteed by characterization. 3. Guaranteed by design. Figure 24. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -36 6.3.10 PLL characteristics The parameters given in Table 44 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 15. Table 44. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10 MHz fPLL_OUT PLL multiplier output clock - 24 - 100 MHz fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 75 MHz fVCO_OUT PLL VCO output - 100 - 432 MHz 84/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 44. Main PLL characteristics (continued) Symbol tLOCK Parameter Conditions PLL lock time Min Typ Max VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 - 25 - - 150 - - 15 - - 200 - - 0.40 0.75 - 0.40 0.85 RMS Cycle-to-cycle jitter System clock 100 MHz Jitter(3) peak to peak RMS peak to peak Period Jitter IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 Unit s ps mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design. 3. The use of two PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization. DocID028094 Rev 5 85/142 118 Electrical characteristics 6.3.11 STM32F410x8/B PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 51: EMI characteristics for LQFP64). It is available only on the main PLL. Table 45. SSCG parameter constraints Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 kHz md Peak modulation depth 0.25 - 2 % - 215 MODEPER * INCSTEP (Modulation period) * (Increment Step) - -1 - 1. Guaranteed by design. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ( 4 x f Mod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ( 4 x 10 ) ] = 250 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 - 1 ) x md x PLLN ) ( 100 x 5 x MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = 2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 - 1 ) x 2 x 240 ) ( 100 x 5 x 250 ) ] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER x INCSTEP x 100 x 5 ) ( ( 2 15 - 1 ) x PLLN ) As a result: md quantized % = ( 250 x 126 x 100 x 5 ) ( ( 2 86/142 DocID028094 Rev 5 15 - 1 ) x 240 ) = 2.002%(peak) STM32F410x8/B Electrical characteristics Figure 25 and Figure 26 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 25. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 26. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DLE 6.3.12 Memory characteristics Flash memory The characteristics are given at TA = -40 to 125 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 46. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.7 V - 5 - Write / Erase 16-bit mode, VDD = 2.1 V - 8 - Write / Erase 32-bit mode, VDD = 3.3 V - 12 - DocID028094 Rev 5 Unit mA 87/142 118 Electrical characteristics STM32F410x8/B Table 47. Flash memory programming Symbol tprog Parameter Word programming time tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tME Vprog Mass erase time Programming voltage Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.4 2.8 Program/erase parallelism (PSIZE) = x 32 - 1 2 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.7 - 3.6 V s ms ms s 1. Guaranteed by characterization. 2. The maximum programming time is measured after 100K erase operations. Table 48. Flash memory programming with VPP voltage Symbol Parameter tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME TA = 0 to +40 C VDD = 3.3 V VPP = 8.5 V Mass erase time Min(1) Typ Max(1) Unit - 16 100(2) s - 230 - - 490 - - 875 - - 3.50 - s ms Vprog Programming voltage - 2.7 - 3.6 V VPP VPP voltage range - 7 - 9 V IPP Minimum current sunk on the VPP pin - 10 - - mA Cumulative time during which VPP is applied - - - 1 hour tVPP(3) 88/142 Conditions DocID028094 Rev 5 STM32F410x8/B Electrical characteristics 1. Guaranteed by design. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. Table 49. Flash memory endurance and data retention Value Symbol Parameter Conditions NEND Endurance TA = - 40 to +85 C (6 suffix versions) TA = - 40 to +105 C (7 suffix versions) TA = - 40 to +125 C (3 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 tRET Data retention 1 kcycle(2) Unit Min(1) at TA = 105 C 10 1 kcycle(2) at TA = 125 C 3 10 kcycle(2) at TA = 55 C 20 Kcycle Years 1. Guaranteed by characterization. 2. Cycling performed over the whole temperature range. 6.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 51. They are based on the EMS levels and classes defined in application note AN1709. Table 50. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP64, TA = +25 C, fHCLK = 100 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP64, TA = +25 C, fHCLK = 100 MHz, conforms to IEC 61000-4-4 4A DocID028094 Rev 5 89/142 118 Electrical characteristics STM32F410x8/B In noisy environments, it is recommended to avoid pin exposition to disturbances. The pins showing a middle range robustness are PA14 and PA15. As a consequence, it is recommended to add a serial resistor (1 k maximum) located as close as possible to the MCU pins exposed to noise (connected to tracks longer than 50 mm on PCB). Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 51. EMI characteristics for LQFP64 Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 8/100 MHz SEMI 90/142 Peak level VDD = 3.6 V, TA = 25 C, conforming to IEC61967-2 DocID028094 Rev 5 0.1 to 30 MHz 10 30 to 130 MHz 11 130 MHz to 1 GHz 5 SAE EMI Level 2.5 dBV - STM32F410x8/B 6.3.14 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 52. ESD absolute maximum ratings(1) Symbol Ratings Electrostatic discharge voltage (human body model) VESD(HBM) Electrostatic discharge voltage (charge device model) VESD(CDM) Class Maximum value(2) 2 2000 UFQFPN48 4 500 WLCSP36 3 250 LQFP48 4 500 LQPF64 4 500 TBD TBD Conditions TA = +25 C conforming to ANSI/JEDEC JS-001 TA = +25 C conforming to ANSI/ESD STM5.3.1 UFBGA64 Unit V 1. TBD stands for "to be defined". 2. Guaranteed by characterization. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 53. Electrical sensitivities Symbol LU 6.3.15 Parameter Static latch-up class Conditions TA = +125 C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. DocID028094 Rev 5 91/142 118 Electrical characteristics STM32F410x8/B Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 54. Table 54. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0 pin -0 NA Injected current on NRST pin -0 NA Injected current on PB3, PB4, PB5, PB6, PB7, PB8, PB9, PC13, PC14, PC15, PH1, PDR_ON, PC0, PC1, PC2, PC3 -0 NA Injected current on any other FT pin -5 NA Injected current on any other pins -5 +5 Unit mA 1. NA = not applicable. Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the conditions summarized in Table 15. All I/Os are CMOS and TTL compliant. Table 55. I/O static characteristics Symbol Parameter FT, TC and NRST I/O input low level voltage VIL 92/142 BOOT0 I/O input low level voltage Conditions Min Typ Max 1.7 VVDD3.6 V - - 0.3VDD(1) 1.75 VVDD 3.6 V, - 40 CTA 125 C - - 1.7 VVDD 3.6 V, 0 CTA 125 C - DocID028094 Rev 5 V 0.1VDD+0.1(2) - Unit STM32F410x8/B Electrical characteristics Table 55. I/O static characteristics (continued) Symbol VIH Parameter Conditions Min Typ Max FT, TC and NRST I/O input high level voltage(5) 1.7 VVDD3.6 V 0.7VDD(1) - - 0.17VDD+ 0.7(2) - - - 10% VDD(3) - V - 100 - mV VSS VIN VDD - - 1 VIN = 5 V - - 3 All pins except for PA10 (OTG_FS_ID) VIN = VSS 30 40 50 PA10 (OTG_FS_ID) - 7 10 14 All pins except for PA10 (OTG_FS_ID) VIN = VDD 30 40 50 PA10 (OTG_FS_ID) - 7 10 14 - - 5 - BOOT0 I/O input high level voltage FT, TC and NRST I/O input hysteresis VHYS BOOT0 I/O input hysteresis I/O input leakage current (4) Ilkg I/O FT/TC input leakage current (5) RPU RPD CIO(8) Weak pull-up equivalent resistor(6) Weak pull-down equivalent resistor(7) I/O pin capacitance 1.75 VVDD 3.6 V, -40 CTA 125 C 1.7 VVDD 3.6 V, 0 CTA 125 C 1.7 VVDD3.6 V 1.75 VVDD 3.6 V, - 40 CTA 125 C 1.7 VVDD 3.6 V, 0 CTA 125 C Unit V A k pF 1. Guaranteed by tests in production. 2. Guaranteed by design. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 54: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 54: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT and TC I/Os is shown in Figure 27. DocID028094 Rev 5 93/142 118 Electrical characteristics STM32F410x8/B Figure 27. FT/TC I/O input characteristics 9,/9,+ 9 ' 9' L P ,+ Q 9 QW H P LUH 77/UHTXLUHPHQW U 9,+PLQ 9 26 0 & ' 9' Q R WL XF LQ RG +P , SU 9 LQ QV WLR HG VW XOD P L 7H V LJQ HV $UHDQRW Q' R G VH GHWHUPLQHG '' D % 9 D[ ,/P QV9 ODWLR X LP V VLJQ Q'H HGR 77/UHTXLUHPHQW9,/PD[ %DV 9 7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9'' X HT 9'' 9 069 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 13). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 13). Output voltage levels Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15. All I/Os are CMOS and TTL compliant. 94/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 56. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL (1) Output low level voltage for an I/O pin VOH (3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin Conditions Min Max CMOS port(2) IIO = +8 mA 2.7 V VDD 3.6 V - 0.4 VDD-0.4 - - 0.4 2.4 - - 1.3(4) VDD-1.3(4) - - 0.4(4) VDD-0.4(4) - - 0.4(5) VDD-0.4(5) - TTL port(2) IIO =+8 mA 2.7 V VDD 3.6 V IIO = +20 mA 2.7 V VDD 3.6 V IIO = +6 mA 1.8 V VDD 3.6 V IIO = +4 mA 1.7 V VDD 3.6 V Unit V V V V V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 13. and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Guaranteed by characterization results. 5. Guaranteed by design. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 28 and Table 57, respectively. Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 15. Table 57. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) 00 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time Min Typ Max Unit CL = 50 pF, VDD 2.70 V - - 4 CL = 50 pF, VDD 1.7 V - - 2 CL = 10 pF, VDD 2.70 V - - 8 CL = 10 pF, VDD 1.7 V - - 4 CL = 50 pF, VDD = 1.7 V to 3.6 V - - 100 DocID028094 Rev 5 MHz ns 95/142 118 Electrical characteristics STM32F410x8/B Table 57. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) 01 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time fmax(IO)out Maximum frequency(3) 10 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time Fmax(IO)out Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max Unit CL = 50 pF, VDD 2.70 V - - 25 CL = 50 pF, VDD 1.7 V - - 12.5 CL = 10 pF, VDD 2.70 V - - 50 CL = 10 pF, VDD 1.7 V - - 20 CL = 50 pF, VDD 2.7 V - - 10 CL = 50 pF, VDD 1.7 V - - 20 CL = 10 pF, VDD 2.70 V - - 6 CL = 10 pF, VDD 1.7 V - - 10 CL = 40 pF, VDD 2.70 V - - 50(4) CL = 40 pF, VDD 1.7 V - - 25 CL = 10 pF, VDD 2.70 V - - CL = 10 pF, VDD 1.7 V - - 50(4) CL = 40 pF, VDD 2.70 V - - 6 CL = 40 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 2.70 V - - 4 CL = 10 pF, VDD 1.7 V - - 6 CL = 30 pF, VDD 2.70 V - - 4) ns 100( 4) CL = 30 pF, VDD 1.7 V - - CL = 30 pF, VDD 2.70 V - - 4 CL = 30 pF, VDD 1.7 V - - 6 CL = 10 pF, VDD 2.70 V - - 2.5 CL = 10 pF, VDD 1.7 V - - 4 10 - - - ns 100( MHz 50(4) Pulse width of external signals detected by the EXTI controller MHz MHz 1. Guaranteed by characterization. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 28. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. 96/142 DocID028094 Rev 5 ns ns STM32F410x8/B Electrical characteristics Figure 28. I/O AC characteristics definition (;7(51$/ 287387 21&/ WU ,2 RXW WI ,2 RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLI WUWI 7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH,2$&FKDUDFWHULVWLFV 6.3.17 DLG NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 55). Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 15. Refer to Table 55: I/O static characteristics for the values of VIH and VIL for NRST pin. Table 58. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 k VF(NRST)(2) NRST Input filtered pulse - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - s VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. DocID028094 Rev 5 97/142 118 Electrical characteristics STM32F410x8/B Figure 29. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW 1567 538 ,QWHUQDO5HVHW )LOWHU ) 670) DLF 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 58. Otherwise the reset is not taken into account by the device. 6.3.18 TIM timer characteristics The parameters given in Table 59 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 59. TIMx characteristics(1)(2) Symbol tres(TIM) fEXT ResTIM tCOUNTER tMAX_COUNT Parameter Timer resolution time Timer external clock frequency on CH1 to CH4 Conditions(3) AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 100 MHz AHB/APBx prescaler>4, fTIMxCLK = 100 MHz fTIMxCLK = 100 MHz Timer resolution 16-bit counter clock period when internal clock is selected Maximum possible count with 32-bit counter fTIMxCLK = 100 MHz fTIMxCLK = 100 MHz Min Max Unit 1 - tTIMxCLK 11.9 - ns 1 - tTIMxCLK 11.9 - ns 0 fTIMxCLK/2 MHz 0 50 MHz - 16/32 bit 0.0119 780 s - 65536 x 65536 tTIMxCLK - 51.1 S 1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK >= 4x PCLKx. 98/142 DocID028094 Rev 5 STM32F410x8/B 6.3.19 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 60. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). The I2C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400 kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the complete solution, please contact your local ST sales representative. Table 60. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - 0 900(4) s th(SDA) SDA data hold time 0 3450(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s tSP Pulse width of the spikes that are suppressed by the analog filter for standard fast mode 0 50(5) 0 50(5) ns Cb Capacitive load for each bus line - 400 - 400 pF ns s 1. Guaranteed by design. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. DocID028094 Rev 5 99/142 118 Electrical characteristics STM32F410x8/B 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. 5. The minimum width of the spikes filtered by the analog filter is above tSP (max) Figure 30. I2C bus AC waveforms and measurement circuit 9''B,& 9''B,& 53 53 670)[[ 56 6'$ ,&EXV 56 6&/ 67$575(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 67267$ 6723 WK 6'$ WZ 6&/+ 6&/ WU 6&/ WZ 6&// WI 6&/ WVX 672 06Y9 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 61. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 2 1. RP = External pull-up resistance, fSCL = I C speed 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. 100/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 62. SCL frequency (fPCLK1= 42 MHz.,VDD = VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. DocID028094 Rev 5 101/142 118 Electrical characteristics STM32F410x8/B FMPI2C characteristics The FMPI2C characteristics are described in Table 63. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 63. FMPI2C characteristics(1) Standard mode - fFMPI2CC Fast mode Fast+ mode Parameter Unit Min Max Min Max Min Max 2 - 8 - 17 16(2) - FMPI2CCLK frequency tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.5 - tw(SCLH) SCL clock high time 4.0 - 0.6 - 0.26 - tsu(SDA) SDA setup time 0.25 - 0.10 - 0.05 - tH(SDA) SDA data hold time 0 - 0 - 0 - - 3.45 - 0.9 - 0.45 tv(SDA,ACK) Data, ACK valid time tr(SDA) tr(SCL) SDA and SCL rise time - 0.100 - 0.30 - 0.12 tf(SDA) tf(SCL) SDA and SCL fall time - 0.30 - 0.30 - 0.12 th(STA) Start condition hold time 4 - 0.6 - 0.26 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - 0.26 - tsu(STO) Stop condition setup time 4 - 0.6 - 0.26 - 4.7 - 1.3 - 0.5 - tSP Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode - - 0.05 0.09 0.05 0.09 Cb Capacitive load for each bus Line - 400 - 400 - 550(3) tw(STO:STA) Stop to Start condition time (bus free) 1. Guaranteed based on test during characterization. 2. When tr(SDA,SCL)<=110 ns. 3. Can be limited. Maximum supported value can be retrieved by referring to the following formulas: tr(SDA/SCL) = 0.8473 x Rp x Cload Rp(min) = (VDD -VOL(max)) / IOL(max) 102/142 DocID028094 Rev 5 us pF STM32F410x8/B Electrical characteristics Figure 31. FMPI2C timing diagram and measurement circuit 9''B,& 9''B,& 53 53 670)[[ 56 6'$ ,&EXV 56 6&/ 67$575(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 6&/+ WZ 67267$ 6723 WK 6'$ 6&/ WZ 6&// WU 6&/ WI 6&/ WVX 672 06Y9 DocID028094 Rev 5 103/142 118 Electrical characteristics STM32F410x8/B SPI interface characteristics Unless otherwise specified, the parameters given in Table 64 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 64. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Duty(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master full duplex/receiver mode, 2.7 V < VDD < 3.6 V SPI1/4/5 - - 42 Master full duplex/receiver mode, 3.0 V < VDD < 3.6 V SPI1/4/5 - - 50 Master transmitter mode 1.7 V < VDD < 3.6 V SPI1/4/5 - - 50 Master mode 1.7 V < VDD < 3.6 V SPI1/2/3/4/5 - - 25 Slave transmitter/full duplex mode 2.7 V < VDD < 3.6 V SPI1/4/5 - - 38(2) Slave receiver mode, 1.8 V < VDD < 3.6 V SPI1/4/5 - - 50 Slave mode, 1.8 V < VDD < 3.6 V SPI1/2/3/4/5 - - 25 30 50 70 % Duty cycle of SPI clock Slave mode frequency Unit MHz tw(SCKH) tw(SCKL) SCK high and low time Master mode, SPI presc = 2 TPCLK - 1.5 TPCLK TPCLK +1.5 ns tsu(NSS) NSS setup time Slave mode, SPI presc = 2 3TPCLK - - ns th(NSS) NSS hold time Slave mode, SPI presc = 2 2TPCLK - - ns Master mode 4 - - ns Slave mode 2.5 - - ns Master mode 7.5 - - ns Slave mode 3.5 - - ns tsu(MI) tsu(SI) th(MI) th(SI) 104/142 Data input setup time Data input hold time DocID028094 Rev 5 STM32F410x8/B Electrical characteristics Table 64. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit ta(SO) Data output access time Slave mode 7 - 21 ns tdis(SO) Data output disable time Slave mode 5 - 12 ns Slave mode (after enable edge), 2.7 V < VDD < 3.6 V - 11 13 ns Slave mode (after enable edge), 1.7 V < VDD < 3.6 V - 11 18.5 ns tv(SO) Data output valid time th(SO) Data output hold time Slave mode (after enable edge), 1.7 V < VDD < 3.6 V 8 - - ns tv(MO) Data output valid time Master mode (after enable edge) - 4 6 ns Master mode (after enable edge) 0 - - ns th(MO) Data output hold time 1. Guaranteed by characterization. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50% Figure 32. SPI timing diagram - slave mode and CPHA = 0 166LQSXW 6&.,QSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ W9 62 WD 62 0,62 287387 WK 62 06%287 %,7287 06%,1 %,7,1 WU 6&. WI 6&. WGLV 62 /6%287 WVX 6, 026, ,1387 /6%,1 WK 6, DLF DocID028094 Rev 5 105/142 118 Electrical characteristics STM32F410x8/B Figure 33. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW 6&.LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06%287 %,7287 WGLV 62 /6%287 WK 6, WVX 6, 026, ,1387 WU 6&. WI 6&. 06%,1 %,7,1 /6%,1 DLE Figure 34. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ WU 6&. WI 6&. %,7,1 06%,1 /6%,1 WK 0, 026, 287387 06%287 WY 02 % , 7287 /6%287 WK 02 DLF 106/142 DocID028094 Rev 5 STM32F410x8/B Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 65 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 65. I2S dynamic characteristics(1) Symbol Parameter fMCK I2S Main clock output fCK I2S clock frequency DCK Conditions Min Max Unit 256x8K 256xFs(2) MHz Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 - I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode 0 7 th(WS) WS hold time Master mode 1.5 - tsu(WS) WS setup time Slave mode 1.5 - th(WS) WS hold time Slave mode 3 - Master receiver 1 - Slave receiver 2.5 - Master receiver 7 - Slave receiver 2.5 - Slave transmitter (after enable edge) - 20 Master transmitter (after enable edge) - 6 Slave transmitter (after enable edge) 8 - Master transmitter (after enable edge) 2 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization. 2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency). Note: Refer to the I2S section of RM0401 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. DocID028094 Rev 5 107/142 118 Electrical characteristics STM32F410x8/B Figure 35. I2S slave timing diagram (Philips protocol)(1) &.,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW WVX 6'B65 /6%UHFHLYH 6'UHFHLYH WK 6'B67 %LWQWUDQVPLW /6%WUDQVPLW WK 6'B65 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH DLE 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 36. I2S master timing diagram (Philips protocol)(1) TF#+ TR#+ #+ OUTPUT TC#+ #0/, TW#+( #0/, TV73 TH73 TW#+, 73 OUTPUT TV3$?-4 3$TRANSMIT ,3" TRANSMIT -3" TRANSMIT ,3" RECEIVE ,3" TRANSMIT TH3$?-2 TSU3$?-2 3$RECEIVE "ITN TRANSMIT TH3$?-4 -3" RECEIVE "ITN RECEIVE ,3" RECEIVE AIB 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 108/142 DocID028094 Rev 5 STM32F410x8/B 6.3.20 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 66 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 15. Table 66. ADC characteristics Symbol VDDA Parameter Power supply VREF+ Positive reference voltage VREF- Negative reference voltage Conditions Min Typ Max 1.7(1) - 3.6 (1) 1.7 - VDDA - 0 - 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.6 30 36 MHz fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 - - - 6 - - 4 7 pF VDDA -VREF+ < 1.2 V (1) fADC fTRIG(2) VAIN RAIN(2) ADC clock frequency External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor VDDA = 1.7 to 2.4 V Unit V tlat(2) Injection trigger conversion latency fADC = 30 MHz - - 0.100 s - - - 3(5) 1/fADC tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 s 1/fADC tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) - - - 2(5) fADC = 30 MHz 0.100 - 16 s - 3 - 480 1/fADC - - 2 3 s fADC = 30 MHz 12-bit resolution 0.50 - 16.40 s fADC = 30 MHz 10-bit resolution 0.43 - 16.34 s fADC = 30 MHz 8-bit resolution 0.37 - 16.27 s fADC = 30 MHz 6-bit resolution 0.30 - 16.20 s 9 to 492 (tS for sampling +n-bit resolution for successive approximation) DocID028094 Rev 5 1/fADC 109/142 118 Electrical characteristics STM32F410x8/B Table 66. ADC characteristics (continued) Symbol fS(2) Parameter Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 A IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 2. Guaranteed by characterization. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 66. Equation 1: RAIN max formula R AIN ( k - 0.5 ) - - R ADC = --------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 67. ADC accuracy at fADC = 18 MHz(1) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Typ Max(2) 3 4 2 3 1 3 1 2 2 3 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Guaranteed by characterization. 110/142 DocID028094 Rev 5 Unit LSB STM32F410x8/B Electrical characteristics Table 68. ADC accuracy at fADC = 30 MHz(1) Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 k, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA -VREF < 1.2 V Typ Max(2) 2 5 1.5 2.5 1.5 4 1 2 1.5 3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Guaranteed by characterization. Table 69. ADC accuracy at fADC = 36 MHz(1) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Typ Max(2) 4 7 2 3 3 6 2 3 3 6 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Guaranteed by characterization. Table 70. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - - -72 -67 dB 1. Guaranteed by characterization. Table 71. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC = 36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - - -72 -70 dB 1. Guaranteed by characterization. DocID028094 Rev 5 111/142 118 Electrical characteristics Note: STM32F410x8/B ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.16 does not affect the ADC accuracy. Figure 37. ADC accuracy characteristics ;,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 112/142 DocID028094 Rev 5 AIC STM32F410x8/B Electrical characteristics Figure 38. Typical connection diagram using the ADC 670) 9'' 5$,1 9$,1 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& $,1[ &SDUDVLWLF 97 9 ,/$ ELW FRQYHUWHU & $'& DL 1. Refer to Table 66 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. DocID028094 Rev 5 113/142 118 Electrical characteristics STM32F410x8/B General PCB design guidelines Power supply decoupling should be performed as shown in Figure 39. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 39. Power supply and reference decoupling 670) 95()9''$ )Q) 95()9''$ 06Y9 6.3.21 Temperature sensor characteristics Table 72. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - 1 2 C Average slope - 2.5 - mV/C Voltage at 25 C - 0.76 - V tSTART(2) Startup time - 6 10 s TS_temp(2) ADC sampling time when reading the temperature (1 C accuracy) 10 - - s TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization. 2. Guaranteed by design. Table 73. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F 114/142 DocID028094 Rev 5 STM32F410x8/B 6.3.22 Electrical characteristics VBAT monitoring characteristics Table 74. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - K Q Ratio on VBAT measurement - 4 - - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - s Er (1) TS_vbat(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.23 Embedded reference voltage The parameters given in Table 75 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15. Table 75. Embedded internal reference voltage Symbol VREFINT Parameter Internal reference voltage Conditions Min Typ Max Unit - 40 C < TA < + 125 C 1.18 1.21 1.24 V TS_vrefint(1) ADC sampling time when reading the internal reference voltage - 10 - - s VRERINT_s(2) Internal reference voltage spread over the temperature range VDD = 3 V 10m V - 3 5 mV TCoeff(2) Temperature coefficient - - 30 50 ppm/C tSTART(2) Startup time - - 6 10 s 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design Table 76. Internal reference voltage calibration values Symbol Parameter Memory address VREFIN_CAL Raw data acquired at temperature of 30 C VDDA = 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B DocID028094 Rev 5 115/142 118 Electrical characteristics 6.3.24 STM32F410x8/B DAC electrical characteristics Table 77. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit Comments - VDDA Analog supply voltage - 1.7(1) - 3.6 V VREF+ Reference supply voltage - 1.7(1) - 3.6 V VSSA Ground - 0 - 0 V RLOAD connected to VSSA 5 - - k - RLOAD connected to VDDA 25 - - k - RLOAD(2) Resistive load DAC output buffer ON VREF+ VDDA - Impedance output with buffer OFF - - - 15 When the buffer is OFF, the Minimum resistive load k between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Capacitive load - - - 50 pF Lower DAC_OUT DAC_OUT voltage with buffer (2) min ON - 0.2 - - V Higher DAC_OUT DAC_OUT voltage with buffer (2) max ON - - - VDDA - 0.2 V Lower DAC_OUT DAC_OUT voltage with buffer min(2) OFF - - 0.5 - mV - VREF+ - 1LSB RO(2) CLOAD(2) Higher DAC_OUT DAC_OUT voltage with buffer (2) max OFF IVREF+(4) 116/142 DAC DC VREF current consumption in quiescent mode (Standby mode) - - - - 170 - 50 V 240 DocID028094 Rev 5 75 It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.7 V It gives the maximum output excursion of the DAC. A - Maximum capacitive load at DAC_OUT pin (when the buffer is ON). With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs STM32F410x8/B Electrical characteristics Table 77. DAC characteristics (continued) Symbol (4) IDDA DNL(4) INL(4) Offset(4) Gain error(4) Parameter DAC DC VDDA current consumption in quiescent mode(3) Differential non linearity Difference between two consecutive code1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Gain error Total Harmonic tSETTLING( Distortion 4) Buffer ON Conditions Min Typ Max Unit Comments - - 280 380 A With no load, middle code (0x800) on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - - 475 625 A - - - 0.5 LSB Given for the DAC in 10-bit configuration. - - - 2 LSB Given for the DAC in 12-bit configuration. - - - 1 LSB Given for the DAC in 10-bit configuration. - - - 4 LSB Given for the DAC in 12-bit configuration. - - - 10 mV Given for the DAC in 12-bit configuration - - - 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - - 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - - 0.5 % Given for the DAC in 12-bit configuration - - 3 6 s CLOAD 50 pF, RLOAD 5 k CLOAD 50 pF, RLOAD 5 k THD(4) - - - - - dB Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - - 1 MS/ CLOAD 50 pF, s RLOAD 5 k DocID028094 Rev 5 117/142 118 Electrical characteristics STM32F410x8/B Table 77. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Comments - - 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. - - - -67 - 40 dB No RLOAD, CLOAD = 50 pF Wakeup time from off state (Setting tWAKEUP(4) the ENx bit in the DAC Control register) PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement) 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed based on test during characterization. Figure 40. 12-bit buffered/non-buffered DAC %XIIHUHGQRQEXIIHUHG'$& %XIIHU 5/2$' ELW GLJLWDOWR DQDORJ FRQYHUWHU '$&[B287 &/2$' DLG 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.25 RTC characteristics Table 78. RTC characteristics 118/142 Symbol Parameter - fPCLK1/RTCCLK frequency ratio Conditions Any read/write operation from/to an RTC register DocID028094 Rev 5 Min Max 4 - STM32F410x8/B 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 WLCSP36 package information Figure 41. WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package outline H EEE = ) $ %DOO$EDOOORFDWLRQ $ * 'HWDLO$ H H ) $ $ H $ %XPSVLGH 6LGHYLHZ $ $ E )URQWYLHZ %XPS $ ' HHH = = E FFF GGG ( %DOO$ RULHQWDWLRQ UHIHUHQFH = ;< = 6HDWLQJSODQH 'HWDLO$ URWDWHG DDD ; :DIHUEDFNVLGH $)B0(B9 1. Drawing is not to scale. DocID028094 Rev 5 119/142 139 Package information STM32F410x8/B Table 79. WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.170 - - 0.0069 - A2 - 0.380 - - 0.0150 - (2) A3 - 0.025 - - 0.0010 - (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.518 2.553 2.588 0.1012 0.1026 0.1039 E 2.544 2.579 2.614 0.1050 0.1064 0.1078 e - 0.400 - - 0.0157 - e1 - 2.000 - - 0.0787 - e2 - 2.000 - - 0.0787 - F - 0.2765 - - 0.0119 - G - 0.2895 - - 0.0138 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 b 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 42. WLCSP36 - 36-pin, 2.553 x 2.579 mm, 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP $)B)3B9 120/142 DocID028094 Rev 5 STM32F410x8/B Package information Table 80. WLCSP36 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm WLCSP36 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 43. WLCSP36 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ )% 5HYLVLRQFRGH 'DWHFRGH %DOO LGHQWLILHU :: < 5 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID028094 Rev 5 121/142 139 Package information 7.2 STM32F410x8/B UFQFPN48 package information Figure 44. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQLGHQWLILHU ODVHUPDUNLQJDUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO< ' ([SRVHGSDG DUHD < ' / &[ SLQFRUQHU ( 5W\S 'HWDLO= = $%B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. 122/142 DocID028094 Rev 5 STM32F410x8/B Package information Table 81. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 45. UFQFPN48 recommended footprint !"?&0?6 1. Dimensions are in millimeters. DocID028094 Rev 5 123/142 139 Package information STM32F410x8/B UFQFPN48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 46. UFQFPN48 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ 670) &%8 'DWHFRGH < :: 3LQLGHQWLILHU 5HYLVLRQFRGH 5 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 124/142 DocID028094 Rev 5 STM32F410x8/B LQFP48 package information Figure 47. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 3%!4).' 0,!.% # C ! ! ! MM '!5'% 0,!.% CCC # $ + ! $ , , $ 0). )$%.4)&)#!4)/. % % B % 7.3 Package information E "?-%?6 1. Drawing is not to scale. DocID028094 Rev 5 125/142 139 Package information STM32F410x8/B Table 82. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 126/142 DocID028094 Rev 5 STM32F410x8/B Package information Figure 48. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint AID 1. Dimensions are expressed in millimeters. DocID028094 Rev 5 127/142 139 Package information STM32F410x8/B LQFP48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 49. LQFP48 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ 670) &8 'DWHFRGH < :: 5HYLVLRQFRGH 3LQ LQGHQWLILHU $ 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 128/142 DocID028094 Rev 5 STM32F410x8/B LQFP64 package information Figure 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*(3/$1( F $ $ 6($7,1*3/$1( & $ $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( E ( 7.4 Package information H :B0(B9 1. Drawing is not to scale. DocID028094 Rev 5 129/142 139 Package information STM32F410x8/B Table 83. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 51. LQFP64 recommended footprint 1. Dimensions are in millimeters. 130/142 DocID028094 Rev 5 STM32F410x8/B Package information LQFP64 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 52. LQFP64 marking example (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670) 5%7 'DWHFRGH < :: 3LQLGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID028094 Rev 5 131/142 139 Package information 7.5 STM32F410x8/B UFBGA64 package information Figure 53. UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ( $ ) ' ' H < + %277209,(: E EDOOV HHH 0 = < ; III 0 = 7239,(: $B0(B9 1. Drawing is not to scale. Table 84. UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol 132/142 Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.080 0.130 0.180 0.0031 0.0051 0.0071 A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.170 0.280 0.330 0.0067 0.0110 0.0130 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.450 3.500 3.550 0.1358 0.1378 0.1398 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.450 3.500 3.550 0.1358 0.1378 0.1398 e - 0.500 - - 0.0197 - DocID028094 Rev 5 STM32F410x8/B Package information Table 84. UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 F 0.700 0.750 0.800 0.0276 0.0295 0.0315 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 54. UFBGA64 - 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package recommended footprint 'SDG 'VP $B)3B9 Table 85. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DocID028094 Rev 5 133/142 139 Package information STM32F410x8/B UFBGA64 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 55. UFBGA64 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ )% 'DWHFRGH <HDUZHHN < :: 5HYLVLRQ FRGH $ %DOO$ 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 134/142 DocID028094 Rev 5 STM32F410x8/B 7.6 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 53. The maximum chip-junction temperature, TJ max., in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 86. Package thermal characteristics Symbol JA 7.6.1 Parameter Value Thermal resistance junction-ambient LQFP48 55 Thermal resistance junction-ambient LQFP64 46 Thermal resistance junction-ambient UFQFPN48 33 Thermal resistance junction-ambient WLCSP36 61 Thermal resistance junction-ambient UFBGA64 79 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DocID028094 Rev 5 135/142 139 Part numbering 8 STM32F410x8/B Part numbering Table 87. Ordering information scheme Example: STM32 Device family STM32 = ARM(R)-based 32-bit microcontroller Product type F = General-purpose Device subfamily 410 = 410 line Pin count T = 36 pins C = 48 pins R = 64 pins Flash memory size 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package I = UFBGA T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = Industrial temperature range, - 40 to 85 C 3 = Industrial temperature range, - 40 to 125 C Packing TR = tape and reel No character = tray or tube 136/142 DocID028094 Rev 5 F 410 C B Y 6 TR STM32F410x8/B Recommendations when using the internal reset OFF Appendix A Recommendations when using the internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 * The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled. * The brownout reset (BRO) circuitry must be disabled. By default BOR is OFF. * The embedded programmable voltage detector (PVD) is disabled. * VBAT functionality is no more available and VBAT pin should be connected to VDD. Operating conditions Table 88. Limitations depending on the operating power supply range Operating power supply range VDD = 1.7 to 2.1 V(3) ADC operation Conversion time up to 1.2 Msps Maximum Maximum Flash memory Flash memory access access frequency frequency with no wait with no wait state states(1) (2) (fFlashmax) 20 MHz(4) 100 MHz with 6 wait states I/O operation Possible Flash memory operations No I/O compensation 8-bit erase and program operations only 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART Accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART Accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.15.1: Internal reset ON). 4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power. DocID028094 Rev 5 137/142 139 Application block diagrams Appendix B B.1 STM32F410x8/B Application block diagrams Sensor Hub application example Figure 56. Sensor hub application example 1 $FFHOHURPHWHU *\URVFRSH 670)[% :/&63SDFNDJH [*3,2V N *3,2 3% 6&/ 3% 6'$ 3$ 7; 3$ 5; 0DJQHWRPHWHU ,& 3UHVVXUH $PELHQWOLJKW 3UR[LPLW\ %227 9'' 3'5B21 6:',2 -7$* 6:&/. 6:2 3$ 3$ 3$ 3$ 3% 3% 8$57 166 6&. 63, 0,62 +267 3% 026, 1567 N+]RVFLOODWRU 3& 3$ $'& 7HPSHUDWXUHKXPLGLW\ 3& 06Y9 Figure 57. Sensor hub application example 2 $FFHOHURPHWHU *\URVFRSH 670)[% :/&63SDFNDJH [*3,2V N *3,2 3% 3% 6&/ 0DJQHWRPHWHU ,& 3UHVVXUH 6'$ $PELHQWOLJKW 3UR[LPLW\ %227 9'' 3$ 3'5B21 6:',2 -7$* 3$ 6:&/. 3$ /RZ SRZHU WLPHU ,1 287 3% 3% 3% 6&. 3$ 7; 3$ 5; 3$ 63, 0,62 0LFURSKRQH 8$57 6&/ 3% 6'$ 0+],&)0 +267 1567 N+]RVFLOODWRU 3& 3$ $'& 7HPSHUDWXUHKXPLGLW\ 3& 06Y9 138/142 DocID028094 Rev 5 STM32F410x8/B B.2 Application block diagrams Batch Acquisition Mode (BAM) example Data is transferred through the DMA from interfaces into the internal SRAM while the rest of the MCU is set in low power mode. * Code execution from RAM before switching off the Flash. * Flash is set in power down and flash interface (ART acceleratorTM) clock is stopped. * The clocks are enabled only for the required interfaces. * MCU core is set in sleep mode (core clock stopped waiting for interrupt). * Only the needed DMA channels are enabled and running. Figure 58. Batch Acquisition Mode (BAM) example 670)[% :/&63SDFNDJH [*3,2V N &RUWH[0FRUH 0+] )38038 *3,2 %227 .%)ODVK PHPRU\ 9'' 3'5B21 6:',2 -7$* /RZ SRZHU WLPHU 6:&/. ,1 *\URVFRSH 3% 3% 3$ 3% $57$FFHOHUDWRU 3$ 3$ 3$ $FFHOHURPHWHU .%5$0 3% 3$ 3$ 287 3% 3% 6&/ 0DJQHWRPHWHU ,& 3UHVVXUH 6'$ $PELHQWOLJKW 6&. 63, 0LFURSKRQH 3UR[LPLW\ 0,62 7; 8$57 5; 6&/ 6'$ 0+],&)0 +267 1567 N+]RVFLOODWRU 3& '0$ 3$ $'& 7HPSHUDWXUHKXPLGLW\ 3& /RZSRZHUEORFNV 06Y9 DocID028094 Rev 5 139/142 139 Revision history STM32F410x8/B Revision history Table 89. Document revision history Date Revision 28-Sep-2015 1 Initial release. 07-Dec-2015 2 Junction temperature range changed to -40 to + 110 C for WLCSP49 package. Updated Figure 7: UFQFPN48 pinout. 3 Updated: - Table 2: STM32F410x8/B features and peripheral counts - Table 9: STM32F410x8/B pin definitions - Table 14: Thermal characteristics - Table 15: General operating conditions - Table 20: Embedded reset and power control block characteristics - Tables from Table 21: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V to Table 34: Typical and maximum current consumptions in VBAT mode (LSE and RTC ON, LSE low- drive mode) - Table 42: HSI oscillator characteristics - Table 43: LSI oscillator characteristics - Table 49: Flash memory endurance and data retention - Table 52: ESD absolute maximum ratings - Table 55: I/O static characteristics - Table 66: ADC characteristics - Table 75: Embedded internal reference voltage - Table 77: DAC characteristics - Table 87: Ordering information scheme - Figure 16: Typical VBAT current consumption (LSE and RTC ON/LSE oscillator in "low power" mode selection - Section 7: Package information Added: - Figure 5: LQFP48 pinout - Figure 8: UFBGA64 pinout - Figure 49: LQFP48 marking example (package top view) - Figure 55: UFBGA64 marking example (package top view) 10-Aug-2016 140/142 Changes DocID028094 Rev 5 STM32F410x8/B Revision history Table 89. Document revision history (continued) Date 06-Mar-2017 04-Apr-2017 Revision Changes 4 Updated: - Features - Section 3.20: Timers and watchdogs - Table 9: STM32F410x8/B pin definitions - Table 21: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V - Table 22: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.6 V - Table 24: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V - Table 28: Typical and maximum current consumption in Sleep mode - VDD = 3.6 V - Table 31: Typical and maximum current consumption in Stop mode - VDD=3.6 V - Table 34: Typical and maximum current consumptions in VBAT mode (LSE and RTC ON, LSE low- drive mode) 5 The maximum current consumption at 30 C has been redefined to be in line with the actual silicon performance. For a typical customer application the impact on the average current consumption will be insignificant. Updated: - Table 21: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V - Table 22: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.6 V - Table 23: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V - Table 24: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V - Table 25: Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.6 V - Table 26: Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.7 V - Table 27: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V - Table 37: Low-power mode wakeup timings - Figure 30: I2C bus AC waveforms and measurement circuit - Figure 31: FMPI2C timing diagram and measurement circuit DocID028094 Rev 5 141/142 141 STM32F410x8/B IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved 142/142 DocID028094 Rev 5