A Cirrus Logic Company CS4330 CS4331 CS4333 8-Pin Stereo D/A Converter for Digital Audio Features Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering @ 18-Bit Resolution @ 94 dB Dynamic Range @ 0.003% THD @ Low Clock Jitter Sensitivity @ Single +3V or +5V Power Supply @ Filtered Line Level Outputs Linear Phase Filtering On-Chip Digital De-emphasis General Description The CS4330, CS4331 and CS4333 are complete, ste- reo digital-to-analog output systems including interpolation, 1-bit D/A conversion and output analog filtering in an 8-pin package. These devices differ in the serial interface format used to input audio data. The CS4330, CS4331 and CS4333 are based on delta-sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for infi- nite adjustment of sample rate between 2 kHz and 50 kHz while maintaining linear phase response simply by changing the master clock frequency. The CS4330, CS4331 and CS4333 contain on-chip digital de-emphasis, operate from a single +3V or +5V power supply, and consume only 60 mW of power with a 3V power supply. These features make them ideal for portable CD players and other portable playback systems. ORDERING INFORMATION: See page 21. DEM/SCLK AGND VA+ ; 2 | 6 | 7 LRCK o - D 3 Serial Input e- hast Voltage Reference emphasis SDATA Siama Analog Interpolator Belersidaa DAC Low-Pass |- AOUTL : Filter 8 Analog Interpolator Delta-Sigma DAC Low-Pass |-*0 AOUTR Modulator . Filter 5 [a MCLK Crystal Semiconductor Corporation MAY 97 P.O. Box 17847, Austin, TX 78760 Copyright Crystal Semiconductor Corporation 1997 DS136F1 (512) 445-7222 Fax: (512) 445-7581 Atio:/www.crysial.com (All Rights Reserved) i Me 2546324 0010219 554 Mmre. Vs sy i ii manana CS4330, C$4331, CS4333 ANALOG CHARACTERISTICS (ta = 25C; Logic "1" = VA+; Logic "0" = AGND; MCLK = 12.288 MHz: Full-Scale Output Sine Wave, 991 Hz; Input Sample Rate = 48 kHz; Input Data = 18 Bits; SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted; unless otherwise specified. Resistive load = 20 kQ, capaci- tive load = 100 pF) CS4330/31/33-KS | CS4330/31/33-KS | CS4330/31/33-BS VA +5V VA +3V VA +5V only Parameter Symbol; Min) Typ Max| Min Typ Max| Min Typ Max| Units Specified Temperature Range Ta -10 to 70 -10 to 70 | -40 to +85; Resolution - - 18 - - 18 - - 18 Bits Dynamic Performance Dynamic Range (A-weighted) 90 94 - - 89 - 88 94 - dB Total Harmonic Distortion - 0,003 0.007 - 0.003 - - 003 .008); % Total Harmonic Distortion + Noise THD+N 0 dB Output, - 86 = -81 - *85 -80/ -88 -86 -79/ dB -20 dB Output, - -72 = -68 - -67 - : -72 -66! dB -60 dB Output - -32 = -28 - -27 - - -32 -26| dB Deviation From Linear Phase (Note 1) - +0.5 - - +05 - - +05 - deg Passband: to 0.05 dB comer (Note 2,3) 0 to 21.77; oO to 21.77; 0 to 21.77) kHz Frequency Response 10 Hz to 20 kHz(Note 1) - +0.1 - - +0.1 - - +01 - oB Passband Ripple (Note 3) - - +0.05) - - +0.05; - - 10.05; dB StopBand (Notes 2,3) 26.23 26.23 26.23 - - kHz StopBand Attenuation (Note 4) 60 - - 60 - - 60 - - dB Group Delay (Fs = input Sample Rate) igd - 16/Fs - - 16/Fs - - 16/Fs - $s Interchannel Isolation (1 kHz) - 90 - - 90 - - 90 - dB de Accuracy Interchannel Gain Mismatch - 0.1 - - 0.1 - - 0.1 - dB Gain Error - - +10 - - +10) - - +10| % Gain Drift - 250 - - 250=C - 250 - |ppmec Analog Output Full Scale Output Voltage 3.33. 3.70 4.07] 1.66 1.85 2.03] 3.33 3.70 4.07) Vpp Output Common Mode Voltage - 2.3 - - 1.3 - - 2.3 - VDC Minimum Resistive Load - 10 - - 10 - - 20 - kQ Maximum Capacitive Load - 100 - - 100 - - 100 - pF Power Supplies Power Supply Current: normal operation| IA+ - 28 32 - 20 25 - 28 32 mA power-down| lA+ : 60 - - 20 - - 60 . pA Power Dissipation normal operation - 140 160 - 60 75 - 140 160) mW power-down - 0.3 - 0.06 - - 0.3 - mW Power Supply Rejection Ratio (1 kHz) | PSRR - 50 - - 50 - - 50 - dB Notes: 1. Combined digital and analog filter characteristics. 2. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz, the 0.05 dB passband edge is 0.4535xFs and the stopband edge is 0.5465xFs. 3. Digital filter characteristics. 4. Measurement Bandwidth is 10 Hz to Fs (kHz) 2 DS136F1 Mm 2546324 0010220 27hfeusTai iia aw Aa CS4330, CS4331, CS4333 2 eeceeecpeeemnmerrncemerin eee ieicereppemaiiees iasiaaeermamamernenme ar ememnearamas us erauunmamuuuenumramenaaaes SWITCHING CHARACTERISTICS (ta = 25 c; VA+ = 2.7V - 5.5V; Inputs: Logic 0 = OV, Logic 1 = VA+, CL = 20 pF) Switching characteristics are guaranteed by characterization. Parameter Symbol Min Typ Max Units Input Sample Rate Fs 2 - 50 kHz LRCK Duty Cycle (External SCLK only) (Note 5) 30 50 70 % MCLK Pulse Width High MCLK / LRCK = 512 10 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 512 15 . 1000 ns MCLK Pulse Width High MCLK / LRCK = 384 21 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 384 21 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 256 35 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 256 39 - 1000 ns External SCLK Mode SCLK Pulse Width Low tgciki 20 - - ns SCLK Pulse Width High tsclkh 20 - - ns . 1 SCLK Period tselkw (128)Fs - : ns SCLK rising to LRCK edge delay tsird 20 - - ns SCLK rising to LRCK edge setup time tsirs 20 - - ns SDATA valid to SCLK rising setup time . tsdirs 20 - - ns SCLK rising to SDATA hold time tsdn 20 - - ns Internal SCLK Mode SCLK Period (Note 6) | tsciiew sak - . ns SCLK rising to LRCK edge tsctkr - testo - us SDATA valid to SCLK rising setup time tedirs G DFS +15 - - ns SCLK rising to SDATA hold time =MCLK/LRCK = 256 or 512] tegn G DF +15 - : ns SCLK rising to SDATA hold time MCLK / LRCK = 384| tggh aanFs +15 - - ns Notes: 5. In Internal SCLK Mode, the Duty Cycle must be 50% +1/2 MCLK Period. 6. The SCLK/LRCK ratio may be either 32, 48, or 64. DS136F1 3 MH 2546324 0010221 102Dima HS CS4330, CS4331, CS4333 LRCK totrs tectkh sid t sci {< | ! SCLK \ | \ t sdirs+# sch SDATA X | \ External Serial Mede Input Timing *LRCK teokr SDATA teow | <-->} toairs | tsah **INTERNAL SCLK \ / / \ Internal Serial Mode Input Timing * LRCK for CS4331 ** The SCLK pulses shown are internal to the CS4330/31/33. a7 aT LRCOK . MCL V AVS 1 N N 2 *INTERNAL SCLK \ \ SS SS SDATA \ X CC C as Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4330/31/33. N equals MCLK divided by SCLK 4 ; DS136F1 Mm 25463524 OO10ee2 O444 Ee A A a ae BES i FS CS4330, CS4331, CS4333 IRIE ener EET Et IIT IRIE ITIL EIT ins aoa sermmmnuuammanonmmmmmae: DIGITAL CHARACTERISTICS (1a = 25 C; VA+ = 2.7V - 5.5V) Parameter Symbol Min Typ Max Units High-Level Input Voltage (VA+ = 5.5V) Vin 2.4 - - Vv (VA+=5.0V)} Vin 2.0 - - Vv Low-Level Input Voltage VIL - - 0.8 Vv Input Leakage Current (Note 7) lin - - +10 pA Notes: 7. lin for CS4331 LRCK is + 20 LA max. ABSOLUTE MAXIMUM RATINGS (AGND = ov; all voltages with respect to ground.) Parameter Symbol Min Max Units DC Power Supply: VA+ -0.3 6.0 Vv Input Current, Any Pin Except Supplies lin - 10 mA Digital Input Voltage VIND -0.3 (VA+)+0.4 v Ambient Operating Temperature (power applied) TA -55 125 C Storage Temperature Tstg -65 150 C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (aanb = ov: all voltages with respect to ground) Parameter Symbol Min Typ Max Units DG Power Supply: (3V mode) VA+ 2.7 3.0 4.0 Vv (5V mode) VA+ 4.75 5.0 5.5 Vv DS136F1 5 MH 25463924 00102e3 Ta5aD mn oa a ae aa aa minawmwnnnm C$4330, CS4331, CS4333 TT te +3V/+5V 7 0.1 LF GF GF 10 pF VA+ DAT. Audio 2 SDATA Data DEM/SCLK 3 10 pF 2 4kO Processor 3 j Left Audio 7 LRCK AOUTL | [| Output * *S56kQ ** Cc CS$4330 Jb CS4331 CS4333 10 uF 5 2.4kQ Right Audio 4 AOUTR Output External Clock MCLK +. += 56kK0 t Cc P AGND L * Required for AC coupling only *k _ 1 C= (2%)(24000)(Fs)(2) Figure 1. Recommended Connection Diagram 6 DS136F1 MH 2546324 O0102e4 411CS4330, CS4331, CS4333 GENERAL DESCRIPTION The CS4330, CS4331, and CS4333 are complete stereo digital-to-analog systems including digital interpolation, 128x third-order delta-sigma digi- tal-to-analog conversion, digital de-emphasis and analog filtering, Figure 2. This architecture pro- vides a high tolerance to clock jitter. The primary purpose of using delta-sigma modu- lation techniques is to avoid the limitations of laser trimmed resistive digital-to-analog con- verter architectures by using an inherently linear 1-bit digital-to-analog converter. The advantages of a 1-bit digital-to-analog converter include: ideal differential linearity, no distortion mecha- nisms due to resistor matching errors and no linearity drift over time and temperature due to variations in resistor values. Digital Interpolation Filter The digital interpolation filter increases the sam- ple rate by a factor of 32 and is followed by a 4x digital sample-and-hold to effectively achieve a 128x interpolation filter. This filter eliminates images of the baseband audio signal which exist at multiples of the input sample rate, Fs. This allows for the selection of a less complex analog filter based on out-of-band noise attenuation re- quirements rather than anti-image filtering. Following the interpolation filter, the resulting frequency spectrum has images of the input sig- nal at multiples of 128x the input sample rate. These images are removed by the external ana- log filter. Delta-Sigma Modulator The interpolation filter is followed by a third- order delta-sigma modulator which converts the 22-bit interpolation filter output into 1-bit data at 128x. Switched-Capacitor Filter The delta-sigma modulator is followed by a digital-to-analog converter which translates the 1-bit data into a series of charge packets. The magnitude of the charge in each packet is deter- mined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit signal. This technique greatly reduces the sensitivity to clock jitter and is a major improvement over earlier generations of 1-bit digital-to-analog converters. 1 . Analog Digital Delta-Sigma Analog Input interpolator Modulator DAC Low-Pass Output Filter Figure 2. System Block Diagram DS136F1 7 MH 2546324 0010225 655CS4330, CS4331, CS4333 SYSTEM DESIGN The CS4330/31/33 accept data at standard audio frequencies including 48 kHz, 44.1 kHz and 32 kHz. Audio data is input via the serial data input pin (SDATA). The Left/Right Clock (LRCK) defines the channel and delineation of data and the Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4330, CS4331 and CS4333 differ in the serial data for- mat as shown in Figures 4-7. The Master Clock (MCLK) is used to operate the digital interpola- tion filter and the delta-sigma modulator. Master Clock The MCLK must be either 256x, 384x, or 512 the desired input sample rate, Fs. Fs is the fre- quency at which words for each channel are input to the digital-to-analog converter, and is equal to the LRCK frequency. The MCLK to LRCK frequency ratio is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal dividers are set to gener- ate the proper clocks for the digital filter, delta-sigma modulator and switched-capacitor filter. Table 1 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. LRCK MCLK (MHz) (kHz) 256x 384x 512x 32 8.1920 | 12.2880 | 16.3840 44.1 11.2896 | 16.9344 | 22.5792 48 12.2880 | 18.4320 | 24.5760 Table 1. Common Clock Frequencies Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4330/31/33 sup- port both external and internal serial clock generation modes. Refer to Figures 4-7 for data formats. External Serial Clock Mode The CS4330/31/33 will enter the External Serial Clock Mode when 4 low to high transitions are detected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock Mode and de- emphasis filter cannot be accessed. The CS4330/31/33 must return to Power-Down to exit this mode. Refer to Figure 8. Internal Serial Clock Mode In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital de-emphasis function. Refer to Figure 8. While the Internal Serial Clock Mode is pro- vided to allow access to the de-emphasis filter, the Internal Serial Clock Mode also eliminates possible clock interference from an external SCLK. Use of Internal Serial Clock Mode is al- ways preferred, even when de-emphasis filtering is not required. De-Emphasis The CS4330/31/33 include on-chip digital de- emphasis. Figure 3 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency re- sponse of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 8 consecutive falling edges of LRCK. This function is available only in the internal serial clock mode. DS136F1 Me 25463924 O01L0eeb 7942p ih EA a oe 7 Fant, # Hf SE A a fae CS4330, CS4331, CS4333 Gain dB T1=50us OdB T2 = 15us -10dB F1 F2 Frequency 3.183 kHz 10.61 kHz Figure 3. De-Emphasis Curve (Fs = 44,1kHz) Initialization and Power-Down The Initialization and Power-Down sequence flow chart is shown in Figure 8. The CS4330/31/33 enter the Power-Down mode upon initial power- up. The interpolation filters and delta-sigma modulators are reset, and the internal voltage ref- erence, one-bit digital-to-analog converters and switched-capacitor low-pass filters are powered down. The device will remain in the Power- Down mode until MCLK and LRCK are presented. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal volt- age reference and the +5 or +3 Volt power supply mode is determined. Finally, power is applied to the D/A converters and switched-ca- pacitor filters, and the analog outputs will move to approximately 2.3V (1.3V in 3V mode). This process requires approximately Ims plus 1024 cycles of LRCK. The CS4330/31/33 enter the Power-Down mode within 1 period of LRCK if either MCLK or LRCK is removed. The initialization sequence begins when MCLK and LRCK are restored. If the MCLK/LRCK frequency ratio or the VA+ voltage changes during Power-Down, the CS4330/31/33 adapt to these new operating con- ditions. It is recomended that the CS4330/31/33 not be powered up with the clocks (MCLK, LRCK, SCLK) going. Power Supply Determination The nominal power supply voltage for the CS4330/31/33 may be either +5 or +3 Volts. "SMART Analog" circuitry senses the power supply voltage during the initialization sequence or when exiting the Power-Down mode. +5V op- eration will be set with a 3.7 Vpp full scale output if VA+ is between 4.75 and 5.5 Volts. The CS4330/31/33 will be set for +3V operation with a 1.85 Vpp full scale output if VA+ is between 2.7 and 4.0 Volts. Supply voltages between 4.0 and 4.75 Volts should be avoided to prevent op- eration in the 5V mode. In this condition there is insufficient headroom to produce a 3.7 Vpp out- put. Grounding and Power Supply Decoupling As with any high resolution converter, the CS4330/31/33 require careful attention to power supply and grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangements with VA+ connected to a clean +3/+5V supply. Decoupling capacitors should be located as near to the CS4330/31/33 as possible. Analog Output and Filtering The CS4330/31/33 analog filter is a switched-ca- pacitor filter. The switched-capacitor filter frequency response is clock dependent and will scale with sample rate. The digital filter of the CS4330/31/33 is de- signed to compensate for the magnitude and phase response of a single-pole low-pass filter at twice the sample rate. Output filters consisting of a 2.4 kohm resistor and capacitor are recom- DS136F1 Mi 2546324 0010227 b20LESS f FS CS4330, CS4331, C$4333 >. te . LACK Left Channet L, ; Right Channel soata [1] 0] / / _Arz|relts|rafiaiialsa[to] 9[.8{7[6/5]4]3[ 2110) Azhehshahalelisfio[#[ [716] s[s[3]2[+]of 7; t Internal SCLK Mode External SCLK Mode Right Justified, 18-Bit Data Right Justified, 18-Bit Data Data Valid on Rising Edge of SCLK Data Valid on Rising Edge of SCLK INT SCLK = 64 Fs if MCLK/LRCK = 256 or 512 SCLK must have at least 36 cycles per LRCK INT SCLK = 48 Fs if MCLK/LRCK = 384 Figure 4. CS4330 Data Format J { ? LACK Left Channei Right Channel , sax IUULUU UU UU UU, JAA UL, soata / / / /|15|1alsa[s2[14]10] 9[ 8] 7] e| 5] 4] 3[ a[ 1] ol / / / L [ [i +3[+4[13[12[ 14] 10] 9] 8] 7] 6] 5] 4] 3] 2] Tol; l / [; Internal SCLK Mode 7S, 16-Bit Data Data Valid on Rising Edge of SCLK INT SCLK = 32 Fs if MCLK/LRCK = 512 or 256 INT SCLK = 48 Fs if MCLK/LRCK = 384 Figure 5. CS4331 Internal SCLK Data Format (IS) 10 DS136F1 Me 2546324 0010228 Sb?GQ mh Ea a ae minawamwnnn/ CS4330, CS4331, CS4333 4 LRCK | Left Channel J Right Channel souk JULAUU UU UU UU, ULL Tru ) C spata / / /|17|16|ts|t4|ishi2h1 ho] 9] s{7[els[4[sl2]1 [of [, / [hrliehshahehehs hol [= ]7[e[s]4]2[2[ [oy TIT. External SCLK Mode 2S, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK must have at least 36 cycles per LRCK Figure 6. CS4331 External SCLK Data Format (s) ; LRCK Left Channel , Right Channel { seu $1 UU, ee soata TT) [TTT beshahialilss[sole]e[7le[s]<[s[2] sol 7) f 7 7 hsbababelnio[o[e]7[s]sl+[8]2 [10/7 ) C Internal SCLK Mode External SCLK Mode Right Justified, 16-Bit Data Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK Data Valid on Rising Edge of SCLK INT SCLK = 32 Fs if MCLK/LRCK = 512 or 256 SCLK must have at least 32 cycles per LRCK INT SCLK = 48 Fs if MCLK/LRCK = 384 Figure 7. CS4333 SCLK Data Format DS136F1 11 MH 2546324 0010229 4T34D mn Ef Ea a ee wha thn C$4330, C$4331, CS4333 TLRS LUTE RT NTT TI TIT I GE T TTL USER: Apply Power ee Power-Down Mode + ____________ v USER: Apply MCLK and LRCK v 256/384/512 MCLK/LRCK Determination Vv Power Supply Determination +3 or +5 Volt mode v USER: set SCLK mode Y USER: Remove Clocks USER: Remove Clocks A A we a Normal Operation Normal Operation De-emphasis De-emphasis available not available v v USER: Apply SDATA USER: Apply SDATA | Analog Output Analog Output || is Generated is Generated Figure 8. CS4330/31/33 Initialization and Power-Down Sequence 12 DS136F1 Me 2546324 0010230 1154D mE ED a ee 7 EPw@ee, 3 Hf 47 Haw a fe AAD CS4330, CS4331, CS4333 mended on the analog outputs. The required ca- pacitor value is defined by: 1 C= (2x) (Fs) (2400 Q) (2) Example: Fs = 48 kHz C = 690 pF A value of 680 pF may be used with only 1.45% error which is negligible. y Magnitude (dB) -50 -60 vo Maw wy os | \/\ 00 60040 02 603 004 05 06 O07 O08 O98 10 Frequency (x Fs) Figure 9. CS4330/31/33 Combined Digital and Analog Filter Stopband Rejection Magnitude (dB) 8 & 8 , \ n \ \ 0,450 0.475 0.500 0.525 0.550 Frequency (x Fs) Figure 10. CS4330/31/33 Combined Digital and Analog Filter Transition Band Combined Digital and Analog Filter Response The frequency response of the combined analog switched-capacitor filter, digital filter, and off- chip single pole RC-filter at 2 Fs, is shown in Figures 9, 10, 11, and 12. The overall response is clock dependent and will scale with Fs. Note that the response plots have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. Magnitude (dB) 0.45 046 0.47 0.48 0.49 0.50 0.51 0.52 Frequency (x Fs) Figure 11, CS4330/31/33 Combined Digital and Analog Filter Transition Band 1.0 05 g 3 oo 3 05 -1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 040 0.45 0.50 Frequency (x Fs) Figure 12. CS4330/31/33 Combined Digital and Analog Filter Passband Ripple DS136F1 13 MM 2546324 0010231 05],1? mh ff ED? aD ee 7 Pane & 8 SP AA a oo ae CS4330, CS4331, CS4333 Performance Plots The following CS4330/31/33 measurement plots were taken on the CDB4330/31/33 evaluation board with an Audio Precision Dual Domain System One. All plots are done in +5V mode at a 48 kHz sampling rate, and are shown in Fig- ures 13-20. Figure 13 shows the CS4330/31/33 frequency re- sponse. The response is flat to 20 kHz + 0.1dB as specified. Figure 14 shows THD+N versus signal ampli- tude for a 1 kHz 20-bit dithered input signal. Figure 15 shows a 16k FFT of a 1 kHz full-scale input signal. The signal has been filtered by a notch filter within the System One to remove the fundamental component of the signal. This mini- mizes the distortion created in the analyzer analog-to-digital converter. This technique is dis- cussed by Audio Precision in the 10th anniversary edition of AUDIO.TST. Figure 16 shows a 16k FFT of a 1 kHz -3 dBFs input signal. The signal has been filtered by a notch filter within the System One to remove the fundamental component of the signal. Figure 17 shows a 16k FFT of a 1 kHz -20 dBFs input signal. The signal has been filtered by a notch filter within the System One to remove the fundamental component of the signal. Figure 18 shows a 16k FFT of a 1 kHz -60 dBFs input signal. Figure 19 shows a 16k FFT of a 1 kHz -90 dBFs input signal. Figure 20 shows the fade-to-noise linearity. The input signal is a dithered 18-bit 500 Hz sine CS4330 FREQRESP 1.0000 -80000 60000 40000 20000 0.0 ~.4000 -1.000 20 100 ik 10k 20k Figure 13. Frequency Response S4330 THO+Nvs Amplitude at 1kHz -60.00 65.00 -70.00 -75.00 80.00 60.0 -50.0 40.0 730.0 20.0 -10.0 0.0 Figure 14. THD+N vs. Amplitude CS4330 1kHz at OdBFs 0.0 -20.00 100.0 120.0 140.0 -160.0 20,00 2.02k 4.02k 601k 8.01k 10.0k 12.0k 14.0 16,0k 18.0k 20,0k Figure 15. 0 dBFs FFT 14 DS136F1 M 2546324 0010232 198a in Ea a ae a 7 Pant aH 7 84 a 6 ASE CS4330, CS4331, CS4333 wave which fades from -60 to -120 dBFs. Dur- ing the fade, the output from the CS4330/31/33 is measured and compared to the ideal level. No- tice the very close tracking of the output level to the ideal, even at low level inputs. This indicates very good low-level linearity, one of the key benefits of delta-sigma digital-to-analog conver- sion. CS4330 1kHz at -60dBFs 0.0 20.00 +100.0 -120.0 140.0 160.0 20,00 2.02k 4.02k 6.01k 8.01k 10.0k 12.0k 14.0k 16.0k 18.0k 20.0k 22.0k Figure 18. -60 dBFs FFT S4330) 1kHz at -3dBFs 0.0 -100,0 -120.0 -140.0 -160.0 20.00 202k 402k 601k 8.01k 10.0k 12.0k 140k 160k 18.0k 20.0k Figure 16. -3 dBFs FFT S4330 1kHz at -90dBFs 0.0 20.00 100.0 -120.0 -140.0 160.0 20.00 2.02k 4.02k 6.01k 8.01k 10.0 12.0k_14.0k 16.0k_48.0k 20.0k 22.0k Figure 19. -90 dBFs FFT $4330 ikHz at -20dBFs 0.0 20.00 -80.00 =100.0 *120.0 140.0 ~160.0 20.00 202k 4.02k 601k 801k 10.0k 12.0k_14.0K_16.0k_18.0k__ 20.0k $4330 Fade-to-Noise Linearity 10.000 8.0000 6.0000 4.0000 2.0000 0.0 -2.000 4.000 6.000 8.000 ~10.00 +120 +110 -100 90.0 -80.0 -70.0 -60.0 Figure 17. -20 dBFs FFT Figure 20. Fade-to-Noise Linearity DS136F1 15 MB 25463924 0010233 4244D ih 8 aD? a a x SPane # Of SP EE ae ap fA CS4330, CS4331, CS4333 Configuration Register The CS4330, CS4331, CS4333 support multiple 2s-complement data/clock formats. The required format is governed by the contents of the Con- figuration Register. The 5-bit register determines which serial data format is acceptable, the fre- quency of the Internal Serial Clock, on which edge of SCLK audio data must be valid, and the number of bits to be loaded into the input buffer. On initial power-up, the register is loaded with the default settings, and it is not necessary to write to the register if this format is appropriate. The default settings are shown in Figures 4-7. The 8-bit code includes a 3-bit preamble to pre- vent accidental access to the Configuration Register. Each bit of the code is read on the fall- ing edge of LRCK as shown in the Figures 21 and 22. The code 01000000 is considered to be an error condition and is ignored. The configura- tion routine requires that the SDATA pin is held high, as shown in Figures 21 and 22, to prevent accidental writing to the register. The Configura- tion Register is only accessible prior to entering the External Serial Clock Mode. For IS mode, the user must set B6 to 0, and B7 to 1. SoS eer Mec) (OL matea cl mst cr Ae Confimm Optimum Schematic & Layout : Before Building Your Board. For Our Free Review Service Call Applications Engineering. Cail: (512)445-7222 | B1 | B2 | Bs | B4 | BS | Be | B7 | Bs | Bl B2 B3 Configuration Access Code 0 1 0 Access Allowed All other Codes Access Denied B4 BS Internal SCLK Mode only Sets Internal SCLK/LRCK Ratio * 0 O SCLK/LRCK = 32 0 1 Reserved 1 0 SCLK/LRCK = 64 1 1 SCLK/LRCK = 128 * The Internal SCLK will be 48 Fs, if the MCLK/LRCK ratio is 384x. 16 B4 B5 External SCLK Mode only Selects Data Sampling edge of SCLK i Oo Rising edge of SCLK 1 1 Falling edge of SCLK B6 Left or Right Justified Data in relation to LRCK transition 0 Left Justified 1 Right Justified B7 IS Data Format 0 Disabled 1 Enabled B8 Sets the number of Bits 0 18 Bits 1 16 Bits DS136F1 MB 2546324 0010234 6b0rf Vil f f Ji masa hin CS4330, CS4331, CS4333 urck J |} ty Li LI LI LI LI Dewscik Bi / pz \ 83 / ps X65 pe Br Be Y 0 1 0 Configuration Register Bits Preamble Load Configuration Register SDATA / / \ Figure 21. Configuration Operation LRCK | torn it pit > c DEM/SCLK pi / po \ Bs / B4 ? x BS a 2 m it teetup ce thold pi qe SDATA i ce \ 3 a Figure 22. Configuration Timing Parameter | Symbol | Min | Typ | Max | Units DEM/SCLK TIMING DEM/SCLK valid to LRCK falling setup time tclrs 20 - - ns LRCK falling to DEM/SCLK hold time teirh 20 - - ns SDATA setup time tsetup 1 - - us SDATA hold time thold 1 - - us Table 2. Configuration Timing Characteristics DS136F1 17 MH 2546324 0010235 717DP i EE A a ee a 7 Wane | A EAD a @ AAD CS4330, CS4331, CS4333 REFERENCES 1)"An 18-Bit, 8-Pin Stereo Digital-to-Analog Converter" by J.J. Paulos, A.W. Krone, G.D Kamath, and S.T. Dupuie. Paper presented at the 97th Convention of the Audio Engineering Soci- ety, November 1994. 2)"How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 3)"Multiplier-Free Interpolation for Oversampled Digital-to-Analog Conversion" by Jeffrey W. Scott. Paper presented at the 92nd Convention of the Audio Engineering Society, March 1992. 4)"An [8-Bit Stereo D/A Converter With Inte- grated Digital and Analog Filters" by Nav S. Sooch, Jeffrey W. Scott. Paper presented at the 91st Convention of the Audio Engineering Soci- ety, November 1991. 5)CDB4330/31/33 Evaluation board Data Sheet; DS136DB2 MAR96 18 MB 2546324 0010236 633 DS136F1Dhaene tf HS CS4330, CS4331, CS4333 PIN DESCRIPTIONS SERIAL DATA INPUT SDATA ANALOG LEFT CHANNEL OUTPUT DE-EMPHASIS / SCLK DEM/SCLK ANALOG POWER LEFT / RIGHT CLOCK LRCK ANALOG GROUND MASTER CLOCK MCLK <4 ANALOG RIGHT CHANNEL OUTPUT Power Supply Connections VA+ - Positive Analog Power, PIN 7. Positive analog supply. Nominally +5V or +3V. AGND - Analog Ground, PIN 6. Analog ground reference. Analog Outputs AOUTL - Analog Left Channel Output, PIN 8. Analog output for the left channel. Typically 3.7 Vpp for a full-scale input signal at VA+ = 5V and 1.85 Vpp at VA+ = 3V. AOUTR - Analog Right Channel Output, PIN 5. Analog output for the right channel. Typically 3.7 Vpp for a full-scale input signal at VA+ = 5V and 1.85 Vpp at VA+ = 3V. Digital Inputs MCLK - Master Clock Input, PIN 4. The frequency must be 256x, 384x , or 512x the input sample rate (Fs). LRCK - Left/Right Clock, PIN 3. This input determines which channel is currently being input on the Audio Serial Data Input pin, SDATA. SDATA - Audio Serial Data Input, PIN 1. Twos complement MSB-first serial data is input on this pin. The data is clocked into the CS4330, CS4331, and CS4333 via internal or external SCLK and the channel is determined by LRCK. DEM/SCLK - De-emphasis / External serial clock input , PIN 2. A dual-purpose input used for de-emphasis filter control or external serial clock input. DS136F1 19 MH 2546324 0010237 S7TFESS f FS CS4330, CS4331, CS4333 EN Te TE Sa Ta TT a I a eer rE PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFs signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, ELAJ CP-307. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converters output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift - The change in gain value with temperature. Units in ppm/C. 20 DS136F1 ME 2546324 0010238 4Obmiaamwannnm CS4330, C$4331, CS4333 ORDERING INFORMATION: Model Temperature Package CS4330-KS -10 to +70C 8-pin Plastic SOIC CS4331-KS -10 to +70C 8-pin Plastic SOIC CS4333-KS -10 to +70C 8-pin Plastic SOIC CS4330-BS -40 to +85C 8-pin Plastic SOIC CS4331-BS -40 to +85C 8-pin Plastic SOIC CS4333-BS -40 to +85C 8-pin Plastic SOIC PACKAGE DIMENSIONS +A > MILLIMETERS INCHES AAA A DIM MIN MAX MIN MAX 8-Pin A 5.15 5.35 0.203 | 0.210 soic B 1.27 TYP 0.050 | TYP c 0 0.25 0 0.010 ul a Hl D 1.77 1.88 0.070 | 0.074 >| le! @#E E 0.33 0.51 0.013 0.020 F 0.15 0.25 0.006 | 0.010 G 0 8 o 8 + 7 H 5.18 54 0.204 | 0.213 ow FA 4 dF YS st I 0.48 0.76 0.019 | 0.030 4 Al <n | 4 J 7.67 8.1 0.302 | 0,319 ri|<+! Note: The EIAJ package is not a standard JEDEC package size DS136F1 21 Me 2546324 0010239 342meee gar a aay @. wis a a Notes PAGE(S) INTENTIONALLY BLANK Me 25463524 OOF10240 Ob4y xoA Cirrus Logic Company CDB4330 CDB4331 CDB4333 Evaluation Board for CS4330 / CS4331 / CS4333 Features Demonstrates recommended layout and grounding arrangements @ CS8412 Receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio @ Digital and Analog Patch Areas @ Requires only a digital signal source and power supplies for a complete Digital-to-Analog-Converter system General Description The CDB4330/31/33 evaluation board is an excellent means for quickly evaluating the CS4330/31/33 18-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source and a power supply. Analog outputs are provided via RCA connec- tors for both channels. The CS8412 digital audio receiver I.C. provides the system timing necessary to operate the CS4330/31/33 and will accept AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The evaluation board may also be configured to accept external timing signals for op- eration in a user application during system development. ORDERING INFORMATION: CDB4330, CDB4331, CDB4333 I/O for Clocks and Data AA Digital |g Audio Input > CS8412 - > p> Anal ici > nalo Datta >| CS4330/31/33 Filter udlo pm -> Interface Crystal Semiconductor Corporation MAR 96 P.O. Box 17847, Austin, TX 78760 Copyright Crystal Semiconductor Corporation 1996 DS136DB2 (512) 445-7222 Fax: (512) 445 7581 (Al Righis Reserved) 23 Me 2546324 0010241 TTO2 ih 0 0 4D a a 7] Fant, 4 HE ME ia ap EE AeA CDB4330, CDB4331, CDB4333 CDB4330/31/33 System Overview The CDB4330/31/33 evaluation board is an ex- cellent means of quickly evaluating the CS4330/31/33. The CS8412 digital audio inter- face receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system develop- ment. The CDB4330/31/33 schematic has been parti- tioned into 5 schematics shown in Figures 2 through 7. Each partitioned schematic is repre- sented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the interconnections between the partitioned schematics. CS4330/31/33 Digital to Analog Converter A description of the CS4330/31/33 is included in the CS4330/31/33 data sheet. CS8412 Digital Audio Receiver The system receives and decodes the standard S/PDIF data format using a CS8412 Digital Audio Receiver, Figure 4. The outputs of the CS8412 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256Fs master clock. The operation of the CS8412 and a discussion of the digital audio in- terface are included in the 1994 Crystal Semiconductor Audio Data Book. During normal operation, the CS8412 operates in the Channel Status mode where the LEDs dis- play channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8412 to decode and supply the de-empha- sis bit from the digital audio interface for control of the CS4330/31/33 de-emphasis filter via pin 3, CC/FO, of the CS8412. When the Error Information Switch is activated, the CS8412 operates in the Error and Frequency information mode. The information displayed by the LEDs can be decoded by consulting the CS8412 data sheet. If the Error Information Switch is activated, and the CS4330/31/33 is in the internal serial clock mode, then it is likely that the de-emphasis control for the CS4330/31/33 will be erroneous and produce an incorrect audio output. Encoded sample frequency information can be displayed provided a proper clock is being ap- plied to the FCK pin of the CS8412. When an LED is lit, this indicates a "1" on the corre- sponding pin located on the CS8412. When an LED is off, this indicates a "0" on the corre- sponding pin. Neither the L or R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, Fig- ure 6. It is not necessary to select the active input. However, both inputs can not be driven si- multaneously. CS8412 Data Format The CS8412 data format can be set with jumpers MO, M1, M2, and M3. These formats are shown in the CS8412 datasheet found in the 1994 Crys- tal Semiconductor Audio Data Book. The format selected must be compatible with the corre- sponding data format of the CS4330/31/33 shown in Figures 4-7 of the CS4330/31/33 datasheet. The default settings for MO-M3 on the evaluation board are given in Tables 2-4. The compatible data formats we have chosen for the CS8412 and CS4330/31/33 are: CS8412 format 6;CS4330 CS8412 format 2;CS4331 (External SCLK only) CS8412 format 5;CS4333 (External SCLK only) 24 DS136DB2 Me 2546324 OOlOe4e 13742 EA Ea a ae x Pare, # SHA 7) Sia ap EE AEP CDB4330, CDB4331, CDB4333 Analog output filter The recommended single pole filter required for the CS4330/31/33 has been combined with a unity gain output buffer (see Figure.2). The ana- log output filter uses a Motorola MC33202 single supply, dual op-amp. The low pass filter corner frequency is located at 2 Fs, or 88.2 kHz and is calculated by: i P= Om) (Aa ll Pe) (Cea) 1 P= (2x) (154Q II 6.654Q) (39095) = 88.5 kHz Power Supply Circuitry Power is supplied to the evaluation board by three binding posts (GND, +5V, +3V/+5V), See Figure 7. The +5V input supplies power to the +5 Volt digital circuitry (VD+5), while the +3V/+5V input supplies power to the Voltage Level Converter (VD+3/+5), and CS4330/31/33 (VA+3/+5) for evaluation in either +3 or +5 Volt mode. The op-amp is supplied from the analog supply (VA+) which can be derived from either the +5V post (VA+5) or the +3/+5V post (VA+3/+5) depending upon which Ferrite bead (L4 or LS) is installed. The evaluation board is configured with VA+ derived from VA+5 (L5 in- stalled). To derive VA+ from the +3V/+5V post (VA+3/+5), remove the Ferrite bead at L5, and install it at LA. Input/Output for Clocks and Data The evaluation board has been designed to allow the interface to external systems via the 10-pin header, J1. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 5. The 74HC243 transceiver functions as an I/O buffer where the CLK SOURCE jumper determines if the transceiver operates as a transmitter or receiver. The transceiver operates as a transmitter with the CLK SOURCE jumper in the 8412 position. LRCK, SDATA, and SCLK from the CS8412 will be available on J1. J22 must be in the 0 po- sition and J23 must be in the 1 position for MCLK to be an output and to avoid bus conten- tion on MCLK. The transceiver operates as a receiver with the CLK SOURCE jumper in the EXTERNAL posi- tion. LRCK, SDATA and SCLK on J1 become inputs. The CS8412 must be removed from the evaluation board for operation in this mode. There are 2 options for the source of MCLK in the External Clock Source mode. MCLK can be an input with J23 in the | position and J22 in the 0 position. However, the recommended mode of operation is to generate MCLK on the evaluation board. MCLK becomes an output with LRCK, SCLK and SDATA inputs. This technique insures that the CS4330/31/33 receives a jitter free clock to maximize performance. This can be accom- plished by installing a crystal oscillator into US, see Figure 4 (the socket for U5 is located within the footprint for the CS8412) and placing J22 in the 1 position and J23 in the 0 position. Grounding and Power Supply Decoupling The CS4330/31/33 requires careful attention to power supply and grounding arrangements to op- timize performance. Figure 2 shows the recommended power arrangements. The CS4330/31/33 is positioned over the analog ground plane near the digital/analog ground plane split. These ground planes are connected elsewhere on the board. This layout technique is used to minimizing digital noise and to insure proper power supply matching/sequencing. The decoupling capacitors are located as close to the CS4330/31/33 as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yield large re- ductions in radiated noise effects. DS136DB2 25 MB 2546324 0010243 4734 my, cw a ama manawa nnn CDB4330, CDB4331, CDB4333 CONNECTOR INPUT/OUTPUT SIGNAL PRESENT input (VD+5V) for CS8412 and digital section +5V input (VA+) for Analog output filter op-amp (configured for +5V) 43/45V input (VD+3/+5V) for Voltage Level Converter input (VA+3/+5V) for CS4330/31/33 GND input ground connection from power supply Digital Input input digital audio interface input via coax Optical Input input digital audio interface input via optical Meee LK, input/output I/O for master, serial, and left/right clocks SDATA input/output I/O for serial data AOUTL output left channel analog output AOUTR output right channel analog output Table 1. System Connections JUMPER PURPOSE POSITION FUNCTION SELECTED selects channel for L CSLR/FCK CS8412 channel status See CS8412 data sheet for details information R Clock Selects source of *8412 CS8412 clock/data source Select system clocks and data EXT External clock/data source J22 Selects MCLK as Input *0 See Input/Output for Clocks and J23 or Output 4 Data section of text Ne ane See CS8412 d h *Hi ee CS84 ata sheet Ne CS8412 mode select High for details M3 *Low INT internal SCLK Mode SCLK Selects SCLK Mode EXT External SCLK Mode DEM 8412 Selects source of de- *Low CS8412 de-emphasis emphasis control High De-emphasis input static high * Default setting from factory Table 2. CDB4330 Jumper Selectable Options 26 DS136DB2 Me 25463924 0910244 70Ta me JUMPER CSLR/FCK Clock Select J22 J23 Mo Mi M2 M3 SCLK DEM_8412 PURPOSE selects channel for CS8412 channel status information Selects source of system clocks and data Selects MCLK as Input or Output CS8412 mode select Selects SCLK Mode Selects source of de- emphasis control * Default setting from factory Note 1. The CS8412 output data format requires the CS4331 be in the External SCLK Mode Table 3. CDB4331 Jumper Selectable Options JUMPER CSLR/FCK Clock Select J22 J23 Mo M1 M2 M3 SCLK DEM_8412 PURPOSE selects channel! for CS8412 channel status information Selects source of system clocks and data Selects MCLK as Input or Output CS8412 mode select Selects SCLK Mode Selects source of de- emphasis control * Default setting from factory Note 1. The CS8412 output data format requires the CS4333 be in the External SCLK Mode POSITION L R *8412 EXT *0 *{ *Low *High *Low *Low INT *EXT *Low High POSITION L R *8412 EXT *0 * *High *Low *High *Low INT *EXT *Low High CDB4330, CDB4331, CDB4333 FUNCTION SELECTED See CS8412 data sheet for details CS8412 clock/data source External clock/data source See /nput/Output for Clocks and Data section of text See CS8412 data sheet for details Internal SCLK Mode (Note 1) External SCLK Mode (Note 1) CS8412 de-emphasis De-emphasis input static high FUNCTION SELECTED See CS8412 data sheet for details CS8412 clock/data source External clock/data source See /nput/Output for Clocks and Data section of text See CS8412 data sheet for details Internal SCLK Mode (Note 1) External SCLK Mode (Note 1) CS8412 de-emphasis De-emphasis input static high Table 4. CDB4333 Jumper Selectable Options DS136DB2 27 WM 2546324 0010245 bubGh Ef EAD? a a 7 aean MP iia a eas Aa 2 haw CDB4330, CDB4331, CDB4333 AAALAC EEE TP Digital I/O for Audio Clocks Input and Data Fig 6 Fig 5 AA Zi a a) MCLK > voltae (MCEK AOUTL oltage Sik r) bevel soi >) Os#ssors1e rite +>) Converter ISDATA "| AOUTR css412 |SDATA Sen Fig2 |-_ Fig2 Digital Audio Power Interface Down | > Fig 3 Fig 3 Fig 4 Figure 1. System Block Diagram and Signal Flow 28 DS136DB2 MW 25463924 0010044 5S4cCDB4330, CDB4331, CDB4333 a ah ae a ae aran@ 7 ae ita aw oan SUOHIIUUOD PUL EC/TE/MEEPSD Z ANS 909) 1 S900 ZO ASE YI dba gen aNoyv ONOV God-va-vou-r yOS y za sr ( O}E 1 ZOZECIN 3n anoy a YLX aNoy snr ea BOd-VU-VOU-h aa gr( OYE Z + ZOZSCOW 923 QNO wLx tT ONY ZOZSEOW [ f I IOVISeI TLNOV a 9S 6ig QNov t yen Nz xS 12 ola 903); tV/VV\-4 3901 Tez acersa alnoy S Edl wh MA +)f.493913 OSaN AOL 40d QNngy TE ylNoV 19313 adx 5 aNov 3N0t dn" ez jt 225 3 GH/E+A GL AAA 4) 7 19373 LEAN SMO By dl TLAOV 29 MM 2546324 0010247 419 DS136DB24D EE Ea a a 7 SFaet@ f AE Aa a fe AAS CDB4330, CDB4331, CDB4333 +5 VOLTS TO +3 VOLTS FROM 8412 SDATA DEM/SCLK LRCK MCLK VD+5 a + 9733 GND, C17 [ GND iI oO Zz! Qo 0K ae nn SDATAI_8/3 R15 0K _ PAA Adem /SCLK_5/3 TO 4330 Rid 0K 19 PE ROK _5/3 20 21 i R13 OK g MMA {> werk _5/3 [16 He VOrS SW2A eT 2", POWER_DOWN rr g 3 oO v0+3/35 SW-DPST/PB-EVAL 24 C15 RB X7R 1K C18 .O1uF X7R tur Figure 3. Voltage Level Conversion and Power Down Circuitry 30 DS136DB2 eS4b3e4 OO10248 355CDB4330, CDB4331, CDB4333 S27 S04? a7 8 ASE SUOTIIUO,) JAA BIOY OIPNY [EIBIC ZIPSSO *b AINSI A[Snoouey[NUlls papyeisul aq ;ouULS CEQ Puke ZF ALON W19S 1X3/LNI aan 198 #19S/N30 THNBRZ 21 n307zir8 C> a _ chee z anay 30 [63h a ston ano ve 1 T g| AZ. aNodGNOY wey $ 19H <7} $54 790 dXupg<] od ono nr wos 3, was = NKEgy<] Nx udu 3041 <4 onass D LOS Tp] vivas194/8789p- 1 10 4/189 ana 1934-037 493/818) [>> 2h z aan w/a poonee 04/8789 | [og mi ze 8H 89> cr =H, rons ' Kv 26 ONoV 23 13/09P-% TT be Or t i Zz 7 1934-037 cage wax F zueso po rac tive room| KK 0 2r0" wt 03/2. aca , fs ane zn T 6 i 1034-037 al "Ap tt roonrg | i ww 90 ew Bs t zu 23/ 80h Fe] JEN oy ; a 0 te z 193-071 soot | we sa 7 EN s3fvob-g A acn i ar ery & eu? 1934-037 a ve | sean, | Kw 60 | 4H 22 on 03/8025 fy en oy 4; asl ris|sjzie ani or A a Ly wv 10 BL-d-aiS S34 Ib ond aNd 540A 096 cw . z = = . ley bes an[ ux L ono cr 19373 5 any = 4 a9 WAI-8d, iseo-ns | fade | / St+OA 78] 4 oS tw a ston vIMS B or mL? anay Noy $ ca O343 #% YOu te Lowl am MLx e 19373 ant OW a wr 59 il [Br ef L I Ld Stan S+A StOA 31 DS136DB2 Me 2546324 0010245 25,manawa bani CDB4330, CDB4331, CDB4333 Eee eT RIE EN ee a I J22 d23 0 Jt 74HC243 A3 A2 Al AO SCLK LRCK SDATA OEA GND U6 vO0+ CLK SOURCE 8412 EXTERNAL GND Figure 5. I/O Interface for Clocks and Data DIGITAL INPUT C13 12 | f {> RXN .O1uF R5 75 GND OPTICAL INPUT OPT TORX173 6 c12 oh ye > xp LT OY ti, Olue CH 3 c14 TT -OtuF 1 2 VD+5 aT a _ H L3 5 ) 47uH IND-500 GND Figure 6. Digital Audio Input Optical Toshiba part TORX173 available through Insight Electronics 32 DS136DB2 Me 2546324 0010250 TO3BESS IME CDB4330, CDB4331, CDB4333 +5V GND +3V / +5V CON-BANANA CON-BANANA CON-BANANA JS 7 J8 Z1 z2 tft _} 1 BL P6KE6.8 PBKEB.B Cu (47 uF 47uF \IC3 ] *NELECT oF ELECT 7+ VAt5 VAt3/45 i C5 c it IL V1 lf 1 uF AGND uF X7R X7R L4 tt RI 2 FERRITE FERRITE 1 JUMPER CERRITE 3 INDUCTOR VD+5 INDUCTOR INDUCTOR VD43/+5 C254 7uF 47uF yiC4 T , +NELECT [ ELECT /I+ VAt = LS GND FERRITE INDUCTOR Figure 7. Power Supply DS136DB2 33 M@ 2546324 0010251 94T agrucra: i 1iP ? ant) 4 CDB4330, CDB4331, CDB4333 RPORATION Figure 8. CDB4330/31/33 Component Side Silkscreen 34 DS136DB2 MM 2546324 0010252 666ee A aD a ae 7 Pane. 7 S55 47 A a a Oo Ep CDB4330, CDB4331, CDB4333 Figure 9. CDB4330/31/33 Component Side (top) DS136DB2 35 MB 254635e4 00102535 7icAp ER A A 4D 4D a Bae ft iD CDB4330, CDB4331, CDB4333 Figure 10. CDB4330/31/33 Solder Side (bottom) 36 DS136DB2 Me 2546324 0010254 659