LU82551ERSL7G4 - Intel - Datasheet.World

82540EP Gigabit Ethernet Controller

Networking Silicon

Datasheet

Product Features

■PCI Bus

—PCI Revision 2.3 su pport for 32 -bit wide

interface at 33 MHz and 66 MHz

—Algorithms that optimally use advanced PCI,

MWI, MRM, and MRL commands

—CardBus Information Services (CIS) Pointer

—CLK_RUN# Signal

■MAC Specific

—Low-lat ency transmit and receive queues

—IEEE 802. 3x-complian t flow-control suppor t

with software-con trol la ble thresho ld s

—Caches up to 64 packet descriptors in a single

burst

—Programmable host memory receive buffers

(256 B to 16 KB) and cache line size (16 B to

256 B)

—Wide, optimized internal data path

architecture

—64 KB configurable Transmit and Receive

FIFO buffers

■PHY Specific

—Integrated for 10/100/1000 Mb/s operation

—IEEE 802. 3a b Auto -Ne gotia tio n supp o rt

—IEEE 802. 3a b PHY comp lia nc e and

compatibility. State-of-the-art DSP

architecture implements digital adaptive

equal ization, echo cancellation, and cross-

talk cancellation

—Aut omatic detection of cable le ngths and

MDI vs. MDI-X ca bl e at all speeds

■Host Off-Loading

—Transmit and receive IP, TCP, and UDP

checksum off-loading capabilities

—Transmit TCP segmentation

—Adva nced packed f iltering

—Jumbo frame support up to 16 KB

—IEEE 802.1q VLAN support with VLAN tag

insertion, stripping and packet filtering for

up to 4096 VLAN tag s

—Descriptor ring management hardware for

transmit and receive

—Interrupt coalescing (multiple packets per

interrupt)

■Manageability

—Manageability features: Onboard SMB port,

ASF 1.0, ACPI, Wake on LAN , and PXE

—Compliance with PCI Power Management

1.1 and ACPI 2.0 register set compliant

—SNMP and RMON statistic counters

—SDG 3.0, WfM 2.0, and PC2001 compliance

■Additional Device

—Four activity and link indication outputs that

directly drive LEDs

—JTAG (IEEE 1149.1) Test Access Port built

in silicon

—Internal PLL for clock genera tion can use a

25 MHz crystal

—Programmable LED functionality

—Industrial temperature support (-40 to

+85 °C)

317887-001

Revision 1.9

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Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to the m.

The Intel products referenced in this document may contain design defects or errors known as errata which may cause the product to deviat e from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

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*Other names and brands may be claimed as the property of others.

iii

Networking Silicon — 82540EP

Revision History

Date Revision Notes

Apr 2002 0.25 Initial Release

Nov 2002 1.0 Changed document status to Intel Confidential.

Jan 2003 1.1 Section 1.0. Replaced Block Diagram

Section 2.6. Added Table footnote

Section 4.1, 4.2, 4.3. Replaced tables

Section 5.1. Added Visual Pin Reference

Section 4.4 Removed Power Supply Characterist ics; added note to I/O Char-

acteristics

Section 5.0 Replaced Pinout Diagram

Apr 2003 1.2 Removed confidential status.

Section 1.0. Added product ordering code.

Oct 2003 1.3 Updated Table 8 to reflect correct values for internal pull-up impedance.

Nov 2004 1.4 Added product features to cover.

Updated signal names to match design guide and reference schematics.

Nov 2004 1.5 Added information about migrating from a 2-layer 0.36 mm wide-trace sub-

strate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Pack-

age and Pinout Information.

Added statement that no changes to existing soldering processes are needed

for the 2-layer 0.32 mm wide-trace substrate change in the section describing

“Package Information”.

Corrected pinout discrepancies between Tables 35 and 36.

July 2006 1.6 Added LAN-disable description to the FLSH_SO signal description in Section

Sept 2006 1.7 Added industrial temperature values to “Product Features” and Table 2.

Added a note to Figure 12 clarifying the device pin 1 location.

Feb 2007 1.8 Updated Section 5.3 “Thermal Specifications”.

Sept 2007 1.9 Updated ball G13 description to 1.5V. Updated Figure 12 (changed G13

description to 1.5V).

82540EP — Networking Silicon

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Networking Silicon — 82540EP

Contents

1.0 Introduction....................................................................................1

1.1 Document Scope.................................................................................................. 1

1.2 Reference Documents.......................................................................................... 2

1.3 Block Diagram ...................................................................................................... 3

2.0 Product Code.................................................................................5

3.0 Signal Descriptions.......................................................................7

3.1 Signal Type Definitions......................................................................................... 7

3.2 PCI Bus Interface.................................................................................................. 7

3.2.1 PCI Address, Data and Control Signals................................................... 7

3.2.2 Arbitration Signals.................................................................................... 9

3.2.3 Interrupt Signal ........................................................................................ 9

3.2.4 System Signals........................................................................................ 9

3.2.5 Error Reporting Signals ........................................................................... 9

3.2.6 Power Management Signals.................................................................. 10

3.2.7 Impedance Compensation Signals........................................................ 10

3.2.8 SMB Signals.......................................................................................... 10

3.3 EEPROM and Serial FLASH Interface Signals................................................... 10

3.4 Miscellaneous Signals........................................................................................ 11

3.4.1 LED Signa ls. .............................................. ............................................ 11

3.4.2 Other Signals......................................................................................... 11

3.5 PHY Signals........................................................................................................ 12

3.5.1 Crystal Signals....................................................................................... 12

3.5.2 Analog Signals....................................................................................... 12

3.6 Test Interfa ce Sign als............ ............................................. ................................ 13

3.7 Power Supply Connections................................................................................. 13

3.7.1 Digital Supplies...................................................................................... 13

3.7.2 Analog Supplies..................................................................................... 13

3.7.3 Ground and No Connects...................................................................... 14

3.7.4 Control Signals ...................................................................................... 14

4.0 Voltage, Temperature, and Timing Specifications ...................15

4.1 Absolute Maximum Ratings................................................................................ 15

4.2 Recommended Operating Conditions................................................................. 15

4.3 DC Specifications ............................................................................................... 16

4.4 AC Characteristics.............................................................................................. 19

4.5 Timing Specifications.......................................................................................... 20

4.5.1 PCI Bus Interface................................................................................... 20

4.5.2 Link Interface Timing ............................................................................. 24

4.5.3 EEPROM Inte rface... .......................... ....... ......................... ................... 25

82540EP — Networking Silicon

5.0 Package and Pinout Information................................................27

5.1 Device Identification ...........................................................................................27

5.2 Package Information............................................................................................28

5.3 Thermal Specifications........................................................................................29

5.4 Pinout Information ...............................................................................................30

5.5 Visual Pin Reference...........................................................................................39

Networking Silicon — 82540EP

1.0 Introduction

The Intel® 82540EP Gigabit Ethernet Controller is a single, compact componen t with an integrated

Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop,

workstation and mobile PC Network designs with critical space constraints, the Intel® 82540EP

allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with

current generation 10/100 Mbps Fast Ethernet designs

The Intel® 82540EP integrates Intel’s fourth gene r a tion gigabit MAC design with fully integ r ated,

physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,

100BASE-TX, and 10BA SE-T applicatio ns (802.3, 8 02.3u, and 802.3ab). Th e controlle r is capable

of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to

managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral

Component Interconnect (PCI) 2.2 compliant interface capable of operating at 33 or 66 MHz.

The 82540EP also incorporates the CLK_RUN# protocol and hardware supported downshift

capability to two or three-pair 100 Mb/s operation. These features optimize m o bil e applicatio ns.

The Intel® 82540EP’s on-board System Management Bus (SMB) port enables network

manageability implementations required by information technology personnel fo r remote control

and alerting via the LAN. With SMB, manag ement packets can be rou ted to or fr om a managem ent

processor. The SMB port enables industry standar ds, such as Intelligent Platform Management

Interface (IPMI) and Alert Standard Forum (ASF), to be implemented using the 82540EP. In

addition, on chip ASF 1.0 cir cuitry pro vides alerting and remote control capabilities with

standardized interfaces.

The 82540EP Gigabit Ethernet Controll er architect ure is designed to deliver high per for mance and

PCI bus efficiency. Wide internal data paths eliminate performance bottleneck s by eff icien tly

handling large address and data words. The 82540EP controller includes advanced interrupt

handling features to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for

efficient bus usage. The 82540EP caches up to 64 packet descriptors in a single burst for efficient

PCI bandwidth use. A large 64 KByte on-chip packet buffer maintains superior performance as

available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads

tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation.

The 82540EP is packaged in a 15 mm2 196-ball grid array and is pin compatible with both the

82551QM 10/100 Mbps Fast Ethernet Multifunctio n PCI/CardBus Controller and the 82540EM

Gigabit Ethernet Controller (which does not have added power saving features like CLK_RUN#).

1.1 Document Scope

This document contains datasheet specifications for the 82540EP Gigabit Ethernet Controller,

including signal descriptions, DC and AC parameters, packaging data, and pinout information.

82540EP — Networking Silicon

1.2 Ref eren ce Doc u m ents

This application assumes that the designer is acquainted with high-speed design and board layout

techniques. The following documents provide additional information:

•82544EI/82544GC Gigabit Ethernet Controller Software Developer's Manual, Revision 0.25,

Intel Corporatio n.

•PCI Local Bus Specification, Revision 2.3, PCI Special Interest Group.

•PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group.

•IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE).

•IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE).

•IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE).

•IEEE Standard 802.3z, 1998 Edition, Institute of Electrical and Electronics Engineers (IEEE).

•IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers

(IEEE).

•Intel Ethernet Control lers Timing Device Selection Guide, AP-419, Intel Corporation.

•PCI Mobile Design Guide, R ev. 1.1, PCI Special Interest Group

•82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide, AP-444. Intel

Corporation.

Networking Silicon — 82540EP

1.3 Block Diagram

Figure 1. Gigabit Ethernet Controller Block Diagram

Arb

i/f PCI I/F

RX MAC

TX MAC

descriptor

engine

Data Alignment

FIFOs

PCI

Core

DMA MAC Core

82540EP Architecture

Packet Buffer

Target

Control

Control , St atus

& Interrupt

Registers

Target Logic

Filter

Statistics

Packet Buffer Interface

ACPI

Out

Default

Configs

RX Data

Link

MDI

(Coppe

Interfac

4-wire EEPROM Interface

MDIOFlash

Flash Interface

Clo ck / Reset

EEPROM

Master

read

FIFO

Master

write

FIFO RX

descriptor

engine

FIFOs

(Many

blocks)

64K bytes

LED

ASF

PHY

SMBus Interface

TX Data

RX Data

CSR Register

Access

CSR Re gister

Access

Mgmt

FIFOs

Manageability

Flow

Ctrl

GMII

82540EP — Networking Silicon

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Networking Silicon — 82540EP

2.0 Product Code

The product ordering code for the 82540EP is: RC82540EP.

82540EP — Networking Silicon

Note: This page intentionall y lef t blank .

Networking Silicon — 82540EP

3.0 Signal Descriptions

Note: The targeted signal names are subject to change withou t notice. Verify with your local Intel sales

office that you have the latest inform ation before finalizing a design.

3.1 Signal Type Definitions

The signals of the 82540EP controller are electrically defined as follows:

3.2 PCI Bus Interface

When the Reset signal (RST#) is asserted, the 82540EP will not drive any PCI output or bi-

directional pins except the Power Management Event signal (PME#).

3.2.1 PCI Address, Data and Control Signals

Name Definition

IInput. Standard input only digital signal.

OOutput. Standard output only digital s ignal.

TS Tri-state. Bi-directional three-state digital input/output signal.

STS

Sustained Tri-state. Sustained digital three-state signal driven by one agent at a time.

An agent driving the STS pin low must actively drive it high for at least one clock before letting it

float. The next agent of the signal cannot drive the pin earlier than one clock after it has been

released by the previous agent.

Open Drain. Wired-OR with other agents.

The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a

weak pull-up resistor. The pull-up resi stor may require two or three clock periods to fully restore

the signal to the de-asserted state.

AAnalog. PHY analog data signal.

PPower. Power connection, voltage reference, or other reference connection.

Symbol Type Name and Function

AD[31:0] TS

Address and Data. Address and dat a signals are multiplexed on the same PCI pins. A

bus transaction includes an address phase followed by one or more data phases.

The address phase is the clock cycle when the Frame signal (FRAME#) is asserted

low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O,

this is a byte address, and for configuration and memory, a DWORD address . The

82540EP device uses little endian byte ordering.

During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24]

contain the most significant byte (MSB).

82540EP — Networking Silicon

C/BE#[3:0] TS

Bus Command and Byte Enables. Bus command and byte enable signals are

multiplexed on the same PCI pins. During the address phase of a transaction, C/

BE#[3:0] define the bus command. In the data phase, C/BE#[3:0] are used as byte

enables. The byte enables are valid for the ent ire dat a phase and determine which byte

lanes contain meaningful data.

C/BE#[0] applies to byte 0 (LSB) and C/BE#[3] applies to byte 3 (MSB).

PAR TS

Parity. T he Parity signal is issued to implement even parity across AD[31:0] and C/

BE#[3:0]. PAR is stable and valid one clock after the address phase. During data

phases, PAR is stable and valid one clock after either IRDY# is asserted on a write

transaction or TRDY# is asserted aft er a read transaction. Once P AR is valid, it remains

valid until one clock after the completion of the current data phase.

When the 82540EP controller is a bus master, it drives PAR for address and write data

phases, and as a slave device, drives PAR for read data phases.

FRAME# STS C ycle Frame. The Fra me sig na l i s dr iven by the 82540EP device to indicate the

beginning and length of an access and indicate the beginning of a bus transaction.

While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the

transaction is in the final data phase.

IRDY# STS

Initiator Ready. Initiator Ready indicates the ability of the 82540E P controller (as bus

master device) to complete the current data phase of the transaction. IRDY# is used in

conjunction with the Target Ready signal (TRDY#). The data phase is completed on any

clock when both IRDY# and TRDY# are asserted.

During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a

read cycle, it indicates the master is ready to accept data. W ait cycles are inserted until

both IRDY# and TRDY# are asserted together. The 82540EP controller drives IRDY#

when acting as a master and samples it when acting as a slave.

TRDY# STS

Target Ready. The Target Ready signal indicates the ability of the 82540EP controller

(as a selected device) to complete the current dat a phase of the transaction. TRDY# is

used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed

on any clock when both TRDY# and IRDY# are sampled asserted.

During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write

cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both

IRDY# and TRDY# are asserted together. The 82540EP device drives TRDY# when

acting as a slave and samples it when acting as a master.

STOP# STS

Stop. The Stop signal indicates the current target is requesting the master to stop the

current transaction. As a slave, the 82540EP controller drives STOP# to request the

bus master to stop the transaction. As a master, the 82540EP controller receives

STOP# from the slave to stop the current transaction.

IDSEL# I Initia lization Device Select. The Initialization Device Select signal is used by the

82540EP as a chip select signal during configuration read and write transactions.

DEVSEL# STS

Device Select. When the Device Select signal is actively driven by the 82540EP, it

signals notifies the bus master that it has decoded its addres s as the target of the

current access. As an input, DEVSEL# indicates whether any device on the bus has

been selected.

VIO P

VIO. The VI O signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI

signaling environment). It is used as the clamping voltage.

Note: An external resistor is required between the voltage reference and the VIO pin.

The target resistor value is 100 K Ω

Symbol Type Name and Function

Networking Silicon — 82540EP

3.2.2 Arbitration Signals

3.2.3 Interrupt Signal

3.2.4 System Signals

3.2.5 Error Reporting Signals

Symbol Type Name and Function

REQ# TS Request Bus. The Request Bus signal is used to request control of the bus from the

arbiter. This signal is point-to-point.

GNT# I Grant Bus. The Grant Bus signal notifies the 82540EP that bus access has been

granted. This is a point-to-point signal.

LOCK# I Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a

target memory device during two or more separate transfers. The 82540EP device

does not implement bus locking.

Symbol Type Name and Function

INTA# TS Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82540EP. It is an

active low, level-triggered interrupt signal.

Symbol Type Name and Function

CLK I

PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus

and is an input to the 82540EP device. All other PCI signals, except the Interrupt A

(INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other

timing parameters are defined with respect to this edge.

M66EN I 66 MHz Enable. M66EN indicates whether the system bus is enabled for 66 MHz.

RST# I

PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the

Power Management Event signal (PME#), are floated and all input signals are ignored.

The PME# context is preserved, depending on power management settings.

Most of the internal state of the 82540EP is reset on the de-assertion (rising edge) of

RST#.

CLK_RUN# I/O

Clock Run. This signal is used by the system to pause the PCI clock signal. It is used

by the 82540EP controller to request the PCI clock. When the CLK_RUN# feature is

disabled, leave this pin unconnected.

Symbol Type Name and Function

SERR# OD System Error. The System Er ror signal is used by the 82540EP controller to report

address parity errors. SERR# is open drain and is actively driven for a single PCI clock

when reporting the error.

PERR# STS

Parity Error. The Parity Error signal is used by the 82540EP controller to report data

parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained

tri-state and must be driven active by the 82540EP controller two data c locks after a

data parity error is detected. The minimum duration of PERR# is one clock for each

data phase a data parity error is present.

82540EP — Networking Silicon

3.2.6 Power Management Signals

3.2.7 Impedance Com pe nsa tion Signals

3.2.8 SMB Signals

3.3 EEPROM and Serial FLASH Inte rface Signals

Symbol Type Name and Function

LAN_

PWR_

GOOD IPower Good (Power-o n Reset). The Power Good signal i s used to indicate that stable

power is available for the 82540EP. When the signal is low, the 82540EP holds itself in

reset state and floats all PCI signals.

PME# OD

Power Management Event. The 82540EP device drives this signal low when it

receives a wake-up event and either the PME Enable bit in the Power Management

Control/S tat us Register or the Advanced Power Management Enable (APME) bit of the

Wake-up Control Register (WUC) is 1b.

AUX_PWR I Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available

and the 82540EP device should support the D3cold power state.

Symbol Type Name and Function

ZN_COMP I/O

N Device Impedance Compensation. This signal should be connected to an external

precision resistor (to VDD) that is indicative of the PCI trace load. This cell is used to

dynamically determine the drive strength required on the N-channel transistors in the

PCI I/O cells.

ZP_COMP I/O

P Device Impedance Compensation. This signal should be connected to an external

precision resistor (to VSS) tha t is indicative of the PCI trace load. This cell is us ed to

dynamically determine the drive strength required on the P-channel transistors in the

PCI I/O cells.

Symbol Type Name and Function

SMBCLK I/O SMB C l ock. The SMB Clock signal is an open drain signal for serial SMB interface.

SMBDATA I/O SMB Data. The SMB Data signal is an open drain signal for serial SMB interface.

SMB_

ALERT# OSMB Aler t. The SMB Alert signal is open drain for serial SMB interface.

Symbol Type Name and Function

EEDI O EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory

device.

EEDO I EEPROM Data Output. T he EEP ROM Data Output pin is used for input from the

memory device. The EE_DO includes an internal pull-up resistor.

EECS O EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device.

EESK O EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the

EEPROM interface, which is approximately 1 MHz.

Networking Silicon — 82540EP

Note: If the LAN-disable feature is used when a Flash device is present, then care must be taken by

system designer s not to drive the FLSH_SO pin while the Flash device is driving it.

3.4 Miscellaneous Signals

3.4.1 LED Signals

3.4.2 Other Signal s

FL_CE# O FLASH Chip Enab le Output. Used to enable FLASH device.

FL_SCK O FLASH Serial Clock Output. The clock rate of the serial FLASH interface is

approximately 1 MHz.

FL_SI O FLASH Serial Data Input. This pin is an output to the memory device.

FLSH_SO I

FLASH Serial Data Output. This pin is an input from the FLASH memory.

Note: The 82540EP LAN-disable mechanism is implemented using this pin. It is

generally used when no Flash device is present (Flash disabled). If this pin is 1b (Vcc)

then the 82540EP is enabled. If the pin is 0b (Vss) then the 82540EP is disabled. This

signal should be sampled within 1µs of the rising edge of LAN_PWR_GOOD and

PCI_RST_N. Note that this pin also has an internal pull-up that is sufficient enough to

enable the 82540EP if no Flash device is present.

Symbol Type Name and Function

LINK_UP# O LED0 / LINK Up. Programmable LED indication. Defaults to indicate link

connectivity.

ACTIVITY# O LED1 / Activity. Programmable LED indication. Defaults to flash to indicate

transmit or receive activity.

LINK100# O LED2 / LINK 100. Programm able LED indication. Defaults to indicate link at

100 Mbps.

LINK1000# O LED3 / LINK 1000. Programm able LED indication. Defaults to indicate link at

1000 Mbps.

Symbol Type Name and Function

SDP[7:6]

SDP[1:0] TS

Software Defined Pins. The Software Defined Pins are reserved and programmable

with respect to input and output capability. These default to input signals upon power-up

but may be configured differently by the EEPROM. The upper four bit s may be mapped

to the General Purpose Interrupt bits if they are configured as input signals.

Note: SDP5 is not included in the group of Software Defined Pins.

82540EP — Networking Silicon

3.5 PHY Signals

3.5.1 Crystal Signals

3.5.2 A nalog Sign als

Symbol Type Name and Function

XTAL1 I Crystal One. The Crystal One pin is a 25 MHz +/- 30 ppm input signal. It can be

connected to either an oscillator or crystal. If a crystal is used, Crystal T wo (XTAL2)

must also be connected.

XTAL2 O Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a

crystal into oscillation. If an external oscillator is used in the design, XTAL2 must be

disconnected.

Symbol Type Name and Function

REF P Reference. This Reference signal should be connected to VSS through an external

2.49 K Ω resistor.

MDI[0]+/- A

Media Dependent Interface [0].

1000BASE-T: In MDI configuration, MDI[0]+/- corresponds to BI_DA+/-, and in MDI-X

configuration, MDI[0]+/- corresponds to BI_DB+/-.

100BASE-TX: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X

configuration, MDI[0]+/- is used for the receive pair.

10BASE-T: In MDI configuration, MDI[0]+/- is used for the transmit pair, and in MDI-X

configuration, MDI[0]+/- is used for the receive pair.

MDI[1]+/- A

Media Dependent Interface [1].

1000BASE-T: In MDI configuration, MDI[1]+/- corresponds to BI_DB+/-, and in MDI-X

configuration, MDI[1]+/- corresponds to BI_DA+/-.

100BASE-TX: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI -X

configuration, MDI[1]+/- is used for the transit pair.

10BASE-T: In MDI configuration, MDI[1]+/- is used for the receive pair, and in MDI-X

configuration, MDI[1]+/- is used for the transit pair.

MDI[2]+/- A

Media Dependent Interface [2].

1000BASE-T: In MDI configuration, MDI[2]+/- corresponds to BI_DC+/-, and in MDI-X

configuration, MDI[2]+/- corresponds to BI_DD+/-.

100BASE-TX: Unused.

10BASE-T: Unused.

MDI[3]+/- A

Media Dependent Interface [3].

1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DD+/-, and in MDI-X

configuration, MDI[3]+/- corresponds to BI_DC+/-.

100BASE-TX: Unused.

10BASE-T: Unused.

Networking Silicon — 82540EP

3.6 Test Interface Signals

3.7 Power Supply Connections

3.7.1 Digital Supplies

3.7.2 Analog Supplies

Symbol Type Name and Funct ion

JTAG_TCK I JTAG Clock.

JTAG_TDI I JTAG TDI.

JTAG_TDO O JTAG TDO.

JTAG_TMS I JTAG TMS.

JTAG_

TRST# IJTAG Reset. This is an active low reset signal for JTAG. This signal should be

terminated using a pull-down resistor to ground. It must not be left unconnected.

TEST I Factory Test Pin.

CLK_VIEW O Clock View. Output for GTX_CLK and RX_CLK during IEEE PHY conformance

testing. The clock is selected by register programming.

ALTCLK_125 I Alternate CLK125 Input. Factory use only.

For normal component operation, connect to VSS.

CLK_BYP# I Clock Bypass Enable. Factory use only.

For normal component operation, no connect.

HSDACP I PHY High Speed Test Interface. Factory use only.

For normal component operation, no connect.

HSDACN I PHY High Speed Test Interface. Factory use only.

For normal component operation, no connect.

PHY_TSTPT I PHY Test Point. Factory use only.

For normal component operation, no connect.

Symbol Type Name and Function

VDDO P 3.3 V I/O Power Supply.

DVDD P 1.5 V Digit al Core Power Supply.

Symbol Type Name and Function

AVDDH P 3.3 V Analog Power Supply.

AVDDL P 2.5 V Analog Power Supply.

82540EP — Networking Silicon

3.7.3 Ground and No Connects

3.7.4 Control Signals

Symbol Type Name and Function

GND P Ground.

NC P No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors

should not be connected to these pins.

Symbol Type Name and Function

CTRL15 A

1.5V Control. LDO voltage regulator output to drive external pass transistor. If 1.5 V is

already present in the system, leave output unconnected. To achieve optimal D3 power

consumption (<50 mw), leave the output unconnected and use a high-efficiency

external switching regulator.

CTRL25 A

2.5V Control. LDO voltage regulator output to drive external pass transistor. If 2.5 V is

already present in the system, leave output unconnected. To achieve optimal D3 power

consumption (<50 mw), leave the output unconnected and use a high-efficiency

external switching regulator.

Networking Silicon — 82540EP

4.0 Voltage, Temperature, and Timing Specifications

Note: The specification values listed in this section are subject to change witho ut notice. Verify with your

local Intel sales office that you have the latest information befo re fina lizin g a de sign.

4.1 Absolute Maximum Ratings

4.2 Recommended Operating Conditions

Table 1. Absolute Maximum Ratingsa

Symbol Parameter Min Max Unit

VDD DC supply voltage -0.3 7 V

VIN Input voltage -1 VDD + 0.3 V

IIN DC input pin current -10 10 mA

TSTG Storage

temperature -40 125 °C

a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are

exceeded. These values should not be used as the limits for normal device operations.

Table 2. Recommended Operating Conditionsa (Sheet 1 of 2)

Symbol Parameter Condition Min Typ Max Unit

TOP Operating

Temperature -40 85 °C

VIO VIO Voltage

Range 35.25V

VDD Periphery

Voltage

Range 3.3 V ± 10% 33.33.6V

82540EP — Networking Silicon

4.3 DC Specific ations

VAH Analog High

VDD Range 3.3 V ± 10% 3 3.3 3.6 V

VDCore Digital

Voltage

Range 1.5 V ± 5% 1.425 1.5 1.575 V

VAL Analog Low

VDD Range 2.5 V ± 5% 2.375 2.5 2.625 V

a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating

limits, might result in permanent damage.

Table 3. DC Characteristics

Symbol Parameter Min Typ Max Units

VDD (3.3) DC supply voltage on VDDO or

AVDDH 3.00 3.3 3.60 V

VDD (2.5) DC supply voltage on AVDDL 2.38 2.5 2.62 V

VDD (1.5) DC supply voltage on DVDD 1.43 1.5 1.57 V

Table 2. Recommended Operating Conditionsa (Sheet 2 of 2)

Symbol Parameter Condition Min Typ Max Unit

Table 4. Power Specifications - D0a

D0a

unplugged/no link @10 Mbps @100Mbps @1000Mbps

Typ Icc

(mA) Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA)

3.3 V 40 40 55 65 65 80 125 125

2.5 V 20 20 30 35 55 60 145 150

1.5 V 100 120 95 100 115 125 400 425

Total

Device

Power 325 mW 400 mW 525 mW 1.38 W 1.5 W

Networking Silicon — 82540EP

Table 5. Power Specifications - D3cold

D3cold - wake-up enabled D3cold - wake

disabled - max

power savings

mode disabled

D3cold - wake

disabled - max

power savings

mode enableda

unplugged/no link @10 Mbps @100Mbps

Typ Icc

(mA) Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA) T yp Icc

(mA) Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA)

3.3 V 40 40 55 55 50 50 40 40 6 8

2.5 V 20 20 30 30 55 55 20 20 0.1 0.1

1.5 V 40 40 30 35 55 60 10 10 1 1

Total

Device

Power 240 mW 300 mW 385 mW 195 mW 20 mW

a. Special Note: To obtain the benefit of max power savings mode, do not use the internal voltage regulator control circuit and external pass transis-

tors. Use external switching regulators for highest efficiency.

Table 6. Power Specifications D(r) Uninitialized

D(r) Uninitialized

(LAN_PWR_GOOD=0)

Typ Icc

(mA) Max Icc

(mA)

3.3 V 40 45

2.5 V 40 45

1.5 V 190 200

Total Device

Power 520 mW

Table 7. Power Specifications - Complete Subsystem

Complete Subsystem (Reference Design)

Incl uding Magn etics, LED, Regulator Cir cu its

D3cold - wake

disabled - max

power savings

mode disabled

D3cold wake-

enabled @10Mbps D3cold wake-

enabled @100Mbps D0 @1000Mbps

active

D3cold - wake

disabled - max

power savings

mode enabled

Typ Icc

(mA) Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA)

Typ

Icc

(mA)

Max Icc

(mA) Typ Icc

(mA) Max Icc

(mA)

3.3 V 40 40 60 60 60 60 130 130 6 8

82540EP — Networking Silicon

2.5 V 20 20 40 40 80 80 240 245 0.1 0.1

1.5 V 10 10 30 35 55 60 400 425 1 1

Subsystem

3.3 V current 70 mA 135 mA 200 mA 800 mA 10 mA

Table 7. Power Specifications - Complete Subsystem

Table 8. I/O Characteristics

Symbol Parameter Condition Min Typ Max Unit

VIL Voltage input LOW -0.5 0.8 V

VIH Voltage input HIGH 2 VDD

+0.3 V

VOL Voltage output LOW 0.4 V

VOH Voltage output HIGH 2.4 V

VSH Schmitt Trigger Hysterysis 0.1 V

IOLa

Output current LOW

3mA drivers (TTL3)

6mA drivers (TTL6)

12mA drivers (TTL12)

VOL

IOHa

Output current HIGH

3mA drivers (TTL3)

6mA drivers (TTL6)

12mA drivers (TTL12)

VOH

-3

-6

-12

IIN

Input Current

TTL inputs

Inputs with pull-down resistors

TTL inputs with pull-up resistors

VIN = VDD or

VSS

VIN = VDD

VIN = VSS

-10

150

-150

±110 µA

480 µA

-480 µA

IOZ 3-state output leakage current VOH = VDD or

VSS -10 ±110 µA

CIN Input capacitance Any input and

bi-directional

buffer 2.5 pF

COUT Output capacit ance Any output

buffer 2pF

CPUD Pull-up/down Resistor value 15 20 30 kΩ

a. TTL 3 signals in clude: EE_DI, EE_SK, EE_CS, and JT AG_TDO.

TTL6 signals include: CLKRUN#, FL_CE#, FL_SCK, FL_SI, and CLK_VIEW.

TTL12 signals include: LED0 / LINK #, LED1 / ACT #, LED2 / LINK100 #, LED3 / LINK1000 #, SDP0, SDP1, SDP6, and SDP7.

Networking Silicon — 82540EP

4.4 AC Characteristics

Table 9. AC Characteristics: 3.3 V Interfacing

Symbol Parameter Min Typ Max Unit

CLK Clock frequency in PCI mode 66 MHz

Table 10. 25 MHz Clock Input Requirements

Symbol ParameteraMin Typ Max Unit

fi_TX_CLK TX_CLK_IN frequency 25 - 50 ppm 25 25 + 50

ppm MHz

a. This parameter applies to an oscillator connected to the Crystal One (XTAL1) input. Alternatively, a crystal may be connected

to XTAL1 and XTAL2 as the frequency source for the internal oscillator.

Table 11. Link Interface Clock Requirements

Symbol Parameter Min Typ Max Unit

fGTXaGTX_CLK frequency 125 MHz

a. GTX_CLK is used externally for test purposes only.

Table 12. EEPROM Interface Clock Requirements

Symbol Parameter Min Typ Max Unit

fSK 1MHz

Table 13. AC Test Loads for General Output Pins

Symbol Signal Name Value Units

CL TDO 10 pF

CL PME#, SDP[7:0] 16 pF

CL EEDI, EESK 18 pF

CL RX_ACTIVITY, TX_ACTIVITY, LINK_UP 20 pF

82540EP — Networking Silicon

4.5 Timing Specifications

Note: Timing specifications are subject to change. Verify with your local Intel sales office that you have

the latest information befo re finalizing a design.

4.5.1 PCI Bus Interface

4.5.1.1 PCI Bus Interface Clock

Figure 1. AC Test Loads for General Output Pins

Table 14. PCI Bus Interface Clock Parameters

Symbol Parametera

a. Ris e and fall times are s pecified in terms of the edge rate meas ured in V/ns. This sl ew rate must be met across the

minimum peak-to-peak portion of the clock waveform as shown.

PCI 66 MHz PCI 33 MHz Units

MinMaxMinMax

TCYC CLK cycle time 15 30 30 ns

TH C LK high time 6 11 ns

TL CLK low time 6 11 ns

CLK slew rate 1.5 4 1 4 V/ns

RST# slew rateb

b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system

noise cannot render a monotonic signal to appear bouncing in the switching range.

50 50 mV/ns

Networking Silicon — 82540EP

4.5.1.2 PCI Bus Interface Timing

NOTES:

1. Output timing measurements are as shown.

2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than

bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.

3. Input timing measurements are as shown.

Figure 2. PCI Clock Timing

Table 15. PCI Bus Interface Timing Parameters

Symbol Parameter PCI 66MHz PCI 33 MHz Units

Min Max Min Max

TVAL CLK to signal valid delay: bussed

signals 26211ns

TVAL(ptp) CLK to signal valid delay: point-

to-point signals 26212ns

TON F loat to active delay 2 2 ns

TOFF Active to float delay 14 28 ns

TSU Input setup time to CLK: bussed

signals 37ns

TSU(ptp) Input setup time to CLK: point-to-

point signals 5 10, 12 ns

TH Input hold time from CLK 0 0 ns

TRRSU REQ64# to RST# setup time 10*TCYC 10*TCYC ns

TRRH RST# to REQ64# hold time 0 0 ns

0.6 Vcc

0.2 Vcc

0.5 Vcc

0.4 Vcc

0.3 Vcc

Tcyc

0.4 Vcc p-to-p

(minimum)

3.3 V Clock

PCI Clock Timing.vsd

82540EP — Networking Silicon

Figure 3. PCI Bus Interface Output Timing Measurement

VTH

VTL

VTEST

PCI_CLK

VTEST

VSTEP (3.3V Signalling

)

Output

Delay

Tri-State

Output

output current ≤

leakage current

TONTOFF

Figure 4. PCI Bus Interface Input T iming Measurement Conditions

TEST

PCI_CLK

TSU

TEST

Input V

MAX

TEST

Input

Valid

Table 16. PCI Bus Interface Timing Measurement Conditions

Symbol Parameter PCI 66 MHz

3.3 v Unit

VTH Input measurement test voltage (high) 0.6*VCC V

VTL Input measurement test voltage (low) 0.2*VCC V

VTEST Output measurem ent test voltage 0.4*VCC V

Input signal slew rate 1.5 V/ns

Networking Silicon — 82540EP

Figure 5. TVAL (max) Rising Edge Test Load

10 pF

25Ω

Pin Te s t

Poin

1/2 inch max.

Figure 6. TVAL (max) Falling Edge Test Load

10 pF

25Ω

Pin Test

Poin

1/2 inch max.

Figure 7. TVAL (min) Test Load

1kΩ

Pin Test

Point

1/2 inch max.

10 pF

1kΩ

82540EP — Networking Silicon

NOTE: Note: 50 pF load used for maximum times. Minimum times are specified with 0 pF load.

4.5.2 Link Inter face Timing

Figure 8. TVAL Test Load (PCI 5 V Signaling Environment)

50 pF

Pin Test

Point

1/2 inch max.

Table 17. Rise and Fall Times

Symbol Parameter Condition Min Max Unit

TR Clock rise time 0.8 V to 2.0 V 0.7 ns

TF Clock fall time 2.0 V to 0.8 V 0.7 ns

TR Data rise time 0.8 to 2.0 V 0.7 ns

TF Dat a fall ti me 2.0 V to 0.8 V 0.7 ns

Figure 9. Link Interface Rise/Fall Timing

2.0 V

0.8 V

Networking Silicon — 82540EP

4.5.3 EEPROM Interface

a. The EEPROM clock is derived from a 125 MHz internal clock.

Table 18. Link Interface Clock Requirements

Symbol Parameter Min Typ Max Unit

TPW EESK pulse width TPERIOD*128 ns

Table 19. Link Interface Clock Requirements

Symbol ParameteraMin Typ Max Unit

TDOS EEDO setup time TCYC*2 ns

TDOH EEDO hold time 0 ns

a. The EEDO setup and hold time is a f unction of the PCI bus CLK cycle time but is referenced to EESK.

82540EP — Networking Silicon

Note: This page intentionall y lef t blank .

Networking Silicon — 82540EP

5.0 Package and Pinout Information

This section describes the 82540EP device, manufactured in a 196-lead ball grid array measuring

15mm x 15mm. External prod uct identification is shown in Figure 10. The nominal ball pitch is

1mm. The pin number-to-signal mapping is indicated beginning with Table 19.

5.1 Device Identification

NOTE: “•“indicates the location of pin 1. It is not an actual mark on the device

Figure 10. 82540EP Device Identification Markings

82540EP Product Name

YYWW D ate Code

Tnnnnnnnn Lot Trace Code

(c)’ZZ Copyright Information

Country Country of Origin Assembly

RC82540EP

YYWW © 'ZZ

Tnnnnnnnn

Country

82540EP — Networking Silicon

5.2 Package Information

The 82540EP device is a 196-lead ball grid array (TFBGA) measuring 15 mm2. The package

dimensions are detailed in Figure 11. The nominal ball pitch is 1 mm. .

Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change.

Figure 11. Dimension Diagram for the 196-pin BGA

Substrate change from

0.36 mm to 0.32 mm

0.32 +/-0.04

Note: All dimensions are in millimeters.

0.40 +/-0.10 Seating Plate

0.85

1.56 +/-0.19

Networking Silicon — 82540EP

5.3 Thermal S pecifications

The 82540EP device is specified for operation when the ambient temperature (TA) is within the

range of -40° C to 85° C.

TC (case temperature) is calculated using the equation:

TC = TA + P (θJA - q JC)

TJ (junction temperature) is calculated using the equation:

TJ = TA + P θJA

P (pow er consumption) is c alcula t ed by using the typical ICC, as indicated in Table 4 of Section

4.0, and nominal VCC. The thermal resistances are shown in Table 18.

Thermal resistances are determined empirically with test devices mounted on standard thermal test

boards. R eal system designs may hav e dif ferent character istics due to board thickness, arr angement

of ground planes, and proximity of other components. The case temperature measurements should

be used to assure that the 82540EP device is operating under recommended conditions.

Table 18. Thermal Characteristics

Symbol Parameter Value at specified airflow (m/s) Units

0123

θJA Thermal resistance, junction-to-ambient 28.1 25.0 23.7 22.8 °C/

Watt

θJC Thermal resistance, junction-to-case 6.1 6.1 6.1 6. 1 °C/

Watt

82540EP — Networking Silicon

5.4 Pi nout Infor matio n

Table 19. PCI Address, Data, and Control Signals

Signal Pin Signal Pin Signal Pin

AD[0] N7 AD[16] K1 C/BE#[0] M4

AD[1] M7 AD[17] E3 C/BE#[1] L3

AD[2] P6 AD[18] D1 C/BE#[2] F3

AD[3] P5 AD[19] D2 C/BE#[3] C4

AD[4] N5 AD[20] D3 PAR J1

AD[5] M5 AD[21] C1 FRAME# F2

AD[6] P4 AD[22] B1 IRDY# F1

AD[7] N4 AD[23] B2 TRDY# G3

AD[8] P3 AD[24] B4 STOP# H1

AD[9] N3 AD[25] A5 DEVSEL# H3

AD[10] N2 AD[26] B5 VIO G2

AD[11] M1 AD[27] B6 IDSEL A4

AD[12] M2 AD[28] C6

AD[13] M3 AD[29] C7

AD[14] L1 AD[30] A8

AD[15] L2 AD[31] B8

Table 20. PCI Arbitration Signals

Signal Pin

REQ# C3

GNT# J3

Table 21. Interrupt Signals

Signal Pin

INTA# H2

Table 22. System Signals

Signal Pin Signal Pin Signal Pin

CLK G1 M66EN C2 RST# B9

Table 23. Error Reporting Signals

Signal Pin Signal Pin

SERR# A2 PERR# J2

Networking Silicon — 82540EP

Table 24. Power Management Signals

Signal Pin Signal Pin

LAN_PWR_

GOOD A9 AUX_PWR J12

PME# A6 CLK_RUN# C8

Table 25. Impedance Compensation Signals

Signal Pin Signal Pin

ZN_COMP H4 ZP_COMP G4

Table 26. SMB Signals

Signal Pin Signal Pin Signal Pin

SMBCLK A10 SMBDATA C9 SMB_ALERT# B10

Table 27. EEPROM and Serial FLASH Interface Signals

Signal Pin Signal Pin Signal Pin

EESK M10 EEDI P10 FL_SCK N9

EEDO N10 FL_CE# M9 FLSH_SO P9

EECS P7 FL_SI M11

Table 28. LED Signals

Signal Pin Signal Pin

LINK_UP# A12 LINK100# B11

ACTIVITY# C11 LINK1000# B12

Table 29. Other Signals

Signal Pin Signal Pin Signal Pin

SDP[0] N14 SDP[6] N13 CTRL15 P11

SDP[1] P13 SDP[7] M12 CTRL25 B13

Table 30. IEEE Test Signals

Signal Pin

CLK_VIEW M8

82540EP — Networking Silicon

Table 31. PHY Signals

Signal Pin Signal Pin Signal Pin

XTAL1 K14 MDI[0]+ C13 MDI[2]+ F13

XTAL2 J14 MDI[1]- E14 MDI[3]- H14

REF B14 MDI[1]+ E13 MDI[3]+ H13

MDI[0]- C14 MDI[2]- F14

Table 32. Test Interface Signals

Signal Pin Signal Pin Signal Pin

JTAG_TCK L14 JTAG_TDO M14 JTAG_RST# L13

JTAG_TDI M13 JTAG_TMS L12 TEST A13

Table 33. Digital Power Signals

Signal Pin Signal Pin Signal Pin

DVDD (1.5V) E11 DVDD (1.5V) J8 DVDD (1.5V) L9

DVDD (1.5V) E12 DVDD (1.5V) J9 DVDD (1.5V) L10

DVDD (1.5V) G5 DVDD (1.5V) J10 VDDO (3.3V) A3

DVDD (1.5V) G6 DVDD (1.5V) J11 VDDO (3.3V) A7

DVDD (1.5V) G13 DVDD (1.5V) K5 VDDO (3.3V) A11

DVDD (1.5V) H5 DVDD (1.5V) K6 VDDO (3.3V) E1

DVDD (1.5V) H6 DVDD (1.5V) K7 VDDO (3.3V) K3

DVDD (1.5V) H7 DVDD (1.5V) K8 VDDO (3.3V) K4

DVDD (1.5V) H8 DVDD (1.5V) K9 VDDO (3.3V) K13

DVDD (1.5V) H11 DVDD (1.5V) K10 VDDO (3.3V) N6

DVDD (1.5V) J5 DVDD (1.5V) K11 VDDO (3.3V) N8

DVDD (1.5V) J6 DVDD (1.5V) L4 VDDO (3.3V) P2

DVDD (1.5V) J7 DVDD (1.5V) L5 VDDO (3.3V) P12

Table 34. Analog Power Signals

Signal Pin Signal Pin Signal Pin

AV DDL (2.5 V) D9 AVDDL (2.5 V) G12 AVDDL (2.5 V) L8

AV DDL (2.5 V) D11

Networking Silicon — 82540EP

Table 35. Grounds and No Connect Signals

Signal Pin Signal Pin Signal Pin Signal Pin

VSS B3 VSS E7 VSS G9 NC A1

VSS B7 VSS E8 VSS G10 NC A14

VSS C10 VSS E9 VSS G11 NC C5

VSS C12 VSS E10 VSS G14 NC D10

VSS D4 VSS F4 VSS H9 NC D12

VSS D5 VSS F5 VSS H10 NC D14

VSS D6 VSS F6 VSS K2 NC F12

VSS D7 VSS F7 VSS K12 NC H12

VSS D8 VSS F8 VSS L6 NC J4

VSS D13 VSS F9 VSS L11 NC J13

VSS E2 VSS F10 VSS M6 NC L7

VSS E4 VSS F11 VSS N1 NC N11

VSS E5 VSS G7 VSS N12 NC P1

VSS E6 VSS G8 VSS P8 NC P14

Table 36. Signal Names in Pin Order (Sheet 1 of 6)

Signal Name Pin

NC A1

SERR# A2

3.3V A3

IDSEL A4

AD[25] A5

PME# A6

3.3V A7

AD[30] A8

LAN_PWR_GOOD A9

SMBCLK A10

3.3V A11

LINK_UP# A12

TEST A13

NC A14

AD[22] B1

AD[23] B2

VSS B3

AD[24] B4

82540EP — Networking Silicon

AD[26] B5

AD[27] B6

VSS B7

AD[31] B8

RST# B9

SMB_ALERT# B10

LINK100# B11

LINK1000# B12

CTRL25 B13

PHY REF B14

AD[21] C1

M66EN C2

REQ# C3

C/BE#[3] C4

NC C5

AD[28] C6

AD[29] C7

CLK_RUN# C8

SMBDATA C9

VSS C10

ACTIVITY# C11

VSS C12

MDI[0]+ C13

MDI[0]- C14

AD[18] D1

AD[19] D2

AD[20] D3

ALT_CLK125 (connect to VSS) D4

VSS D5

VSS D6

VSS D7

VSS D8

2.5 V D9

NC D10

2.5 V D11

NC D12

VSS D13

NC D14

Table 36. Signal Names in Pin Order (Sheet 2 of 6) (Continued)

Signal Name Pin

Networking Silicon — 82540EP

3.3V E1

VSS E2

AD[17] E3

VSS E4

VSS E5

VSS E6

VSS E7

VSS E8

VSS E9

VSS E10

1.5V E11

1.5V E12

MDI[1]+ E13

MDI[1]- E14

IRDY# F1

FRAME# F2

C/BE#[2] F3

VSS F4

VSS F5

VSS F6

VSS F7

VSS F8

VSS F9

VSS F10

VSS F11

PHY_TS TPT (do not connect) F12

MDI[2]+ F13

MDI[2]- F14

CLK G1

VIO G2

TRDY# G3

ZP_COMP G4

1.5V G5

1.5V G6

VSS G7

VSS G8

VSS G9

VSS G10

Table 36. Signal Names in Pin Order (Sheet 3 of 6) (Continued)

Signal Name Pin

82540EP — Networking Silicon

VSS G11

2.5 V G12

1.5V G13

VSS G14

STOP# H1

INTA# H2

DEVSEL# H3

ZN_COMP H4

1.5V H5

1.5V H6

1.5V H7

1.5V H8

VSS H9

VSS H10

1.5V H11

HSDACN (do not connect) H12

MDI3]+ H13

MDI[3]- H14

PAR J1

PERR# J2

GNT# J3

NC J4

1.5V J5

1.5V J6

1.5V J7

1.5V J8

1.5V J9

1.5V J10

1.5V J11

AUX_PWR J12

HSDACP (do not connect) J13

XTAL2 J14

AD[16] K1

VSS K2

3.3V K3

3.3V K4

1.5V K5

1.5V K6

Table 36. Signal Names in Pin Order (Sheet 4 of 6) (Continued)

Signal Name Pin

Networking Silicon — 82540EP

1.5V K7

1.5V K8

1.5V K9

1.5V K10

1.5V K11

AVSS K12

3.3V K13

XTAL1 K14

AD[14] L1

AD[15] L2

C/BE#[1] L3

1.5V L4

1.5V L5

VSS L6

CLK_BYP# (do not connec t) L7

2.5 V L8

1.5V L9

1.5V L10

VSS L11

JTAG_TMS L12

JTAG_RST# L13

JTAG_TCK L14

AD[11] M1

AD[12] M2

AD[13] M3

C/BE#[0] M4

AD[5] M5

VSS M6

AD[1] M7

CLK_VIEW M8

FL_CE# M9

EESK M10

FL_SI M11

SDP[7] M12

JTAG_TDI M13

JTAG_TDO M14

VSS N1

AD[10] N2

Table 36. Signal Names in Pin Order (Sheet 5 of 6) (Continued)

Signal Name Pin

82540EP — Networking Silicon

AD[9] N3

AD[7] N4

AD[4] N5

3.3V N6

AD[0] N7

3.3V N8

FL_SCK N9

EEDO N10

NC N11

VSS N12

SDP[6] N13

SDP[0] N14

NC P1

3.3V P2

AD[8] P3

AD[6] P4

AD[3] P5

AD[2] P6

EECS P7

GND P8

FLSH_SO P9

EEDI P10

CTRL15 P11

3.3V P12

SDP[1] P13

NC P14

Table 36. Signal Names in Pin Order (Sheet 6 of 6) (Continued)

Signal Name Pin

Networking Silicon — 82540EP

5.5 Visual Pin Reference

Figure 12. Ball Grid Array / Pin Reference for 196-TFBGA (Bottom/Pin View)

Note: Figure 12 is rotated 90 degrees counter-clockwise from the pin 1 position (corner) in Figure 11.

AD[22] AD[21] AD[18] 3.3V IRDY# CLK STOP# PA R NCVSSAD[11]AD[14]AD[16]NC

AD[23] M66EN AD[19] VSS FRAME# VIO INTA# PERR# 3.3VAD[10]AD[12]AD[15]VSS

SERR#

VSS REQ# AD[20] AD[17] C/BE#[2] TRDY# DVSEL# GNT# AD[8]AD[9]AD[13]C/B3#[1]3.3V3.3V

AD[24] C/BE#[3] ALT_

CLK125

VSS VSS ZP_COMP NC AD[6]AD[7]

C/BE#[0]

1.5V3.3VIDSEL

AD[26] NC VSS VSS VSS 1.5V AD[3]AD[4]AD[5]1.5VAD[25]

AD[27] AD[28] VSS VSS VSS 1.5V AD[2]3.3VVSSVSS PME#

VSS AD[29] VSS VSS VSS VSS EECSAD[0]AD[1]CLK_BYP#3.3V

AD[31] CLK_

RUN# VSS VSS VSS VSS VSS

3.3V

CLK_VIEW

2.5VAD[30]

RST# SMBDATA 2.5V VSS VSS VSS VSS FLSH_SOFLSH_SCKFLSH_CE#1.5V

LAN_PWR_

GOOD

VSS NC VSS VSS VSS EEDI

EEDO

EESK

1.5V

SMBCLK

LINK100# ACTIVITY# 2.5V VSS VSS CTRL15

NCFLSH_SIVSS3.3V

LINK1000# VSS PHY_TSTPT HSDACN AUX_PWR 3.3V

VSS

SDP[7]

JTAG_TMS

VSS

LINK_UP#

CTRL25 MDI[0]+ VSS HSDACP SDP[1]SDP[6]

JTAG_TDI

JTAG_TRST#

3.3V

TEST

PHY REF VSS XTAL2 NC

JTAG_TDO

JTAG_TCK

XTAL1NC

ABCDEFGHJKL

MNP

SMB_

ALERT#

MDI[0]-

1.5V

VSS

MDI[1]+

MDI[2]+

1.5V

2.5V

ZN_COMP

1.5V

MDI[3]+

1.5V

SDP[0]

82540EP — Networking Silicon

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