TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Organization...524288 by 8 Bits
D
Single 5-V Power Supply
D
Industry Standard 32-Pin Dual In-Line
Package and 32-Lead Plastic Leaded Chip
Carrier
D
All Inputs/Outputs Fully TTL Compatible
D
Static Operation (No Clocks, No Refresh)
D
Max Access/Min Cycle Time
VCC ±10%
’27C/PC040-10 100 ns
’27C/PC040-12 120 ns
’27C/PC040-15 150 ns
D
8-Bit Output For Use in
Microprocessor-Based Systems
D
Power-Saving CMOS Technology
D
3-State Output Buffers
D
400-mV Assured DC Noise Immunity With
Standard TTL Loads
D
Latchup Immunity of 250 mA on All Input
and Output Pins
D
No Pullup Resistors Required
D
Low Power Dissipation (VCC = 5.5 V)
– Active...275 mW Worst Case
– Standby...0.55 mW Worst Cas E
(CMOS-Input Levels)
D
Temperature Range Options
description
The TMS27C040 devices are 524288 by 8-bit
(4194304-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
The TMS27PC040 devices are 524 288 by 8-bit
(4194304-bit), one-time programmable (OTP)
electrically programmable read-only memories
(PROMs).
These devices are fabricated using CMOS
technology for high speed and simple interface
with MOS and bipolar circuits. All inputs (including
program data inputs) can be driven by the Series
74 TTL circuits. Each output can drive one Series
74 TTL circuit without external resistors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3213231
14
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
430
15 16 17 18 19 20
TMS27C040
J PACKAGE
(TOP VIEW)
PIN NOMENCLATURE
A0–A18 Address Inputs
DQ0–DQ7 Inputs (programming)/Outputs
EChip Enable
GOutput Enable
GND Ground
VCC 5-V Supply
VPP 13-V Power Supply†
†Only in program mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A18
A17
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A14
A13
A8
A9
A11
G
A10
E
DQ7
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
A12
A15
A16
V
A18
A17
TMS27PC040
FM PACKAGE
(TOP VIEW)
DQ6
PP
GND
VCC
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
The data outputs are 3-state for connecting multiple devices to a common bus
The TMS27C040 is offered in a 600-mil ceramic dual-in-line package (J suffix). The TMS27C040 is offered with
two choices of temperature ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). (See Table 1.)
The TMS27PC040 is offered in a 32-lead plastic leaded chip carrier package (FM suffix). The TMS27PC040
is offered with two choices of temperature ranges of 0°C to 70°C (JL suffix) and –40°C to 85°C (JE suffix).
Table 1. Temperature Range Suffixes
FUNCTION SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE
RANGES
0°C to 70°C– 40°C to 85°C
TMS27C040-XXX JL JE
TMS27PC040-XXX FML FME
These EPROMs and PROMS operate from a single 5-V supply (in the read mode), and they are ideal for use
in microprocessor-based systems. One other (13 V) supply is needed for programming. All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply . All inputs are
TTL level except for VPP during programming (13 V), and VH (12 V) on A9 for the signature mode.
Table 2. Operation Modes
MODE
FUNCTION†
MODE
E G VPP VCC A9 A0 DQ0–DQ7
Read VIL VIL X VCC X X Data Out
Output Disable VIL VIH VCC VCC X X Hi-Z
Standby VIH X VCC VCC X X Hi-Z
Programming VIL VIH VPP VCC X X Data In
Program Inhibit VIH VIH VPP VCC X X Hi-Z
Verify VIH VIL VPP VCC X X Data Out
Signature Mode
VIL
VIL
VCC
VCC
V‡
VIL MFG Code 97
Signat
u
re
Mode
V
IL
V
IL
V
CC
V
CC
V
H
‡
VIH Device Code 50
†X can be VIL or VIH
‡VH = 12 V ±0.5 V
read/output disable
When the outputs of two or more TMS27C040s or TMS27PC040s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C040 and TMS27PC040 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
power down
Active ICC supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C040)
Before programming, the TMS27C040 EPROM is erased by exposing the chip through the transparent lid to
a high intensity UV-light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W⋅s/cm2 . A typical 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The
lamp must be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C040, the
window must be covered with an opaque label. After erasure (all bits in logic high state), logic lows are
programmed into the desired locations. A programmed low can be erased only by UV light.
initializing (TMS27PC040)
The OTP TMS27PC040 PROM is provided with all bits in logic high state, then logic lows are programmed into
the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C040 and TMS27PC040 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart shown in Figure 1.
The initial setup is VPP = 13 V, VCC = 6.5 V , E = VIH, and G = VIH. Once the initial location is selected, the data
is presented in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low (VIL) with a pulse duration of tw(PGM). Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified at VPP = 13 V, VCC = 6.5 V , E = VIH, and G = VIL. If the correct data
is not read, the programming is performed by pulling E low with a pulse duration of tw(PGM). This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
all bytes are verified with VCC = VPP = 5 V ± 10%.
program inhibit
Programming can be inhibited by maintaining high level inputs on the E and G pins.
program verify
Programmed bits can be verified with VPP = 13 V when G = VIL, and E = VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other
addresses must be held low. The signature code for the TMS27C040 is 9750. A0 low selects the manufacturer’s
code 97 (Hex), and A0 high selects the device code 50 (Hex), as shown in Table 3.
Table 3. Signature Mode
IDENTIFIER†
PINS
IDENTIFIER†
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
MANUFACTURER CODE VIL 1001011197
DEVICE CODE VIH 0101000050
†E = G = VIL, A1-A8 = VIL, A9 = VH, A10-A18 = VIL, VPP = VCC.
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Start
Address = First Location
VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V
Last
Address?
Address = First Location
X = 0
VCC = VPP = 5 V ± 0.5 V
Compare
All Bytes
to Original
Data
Device Passed
Increment Address
Increment
Address Verify
One Byte
Program One Pulse = tw = 100 µs
X = 10?X = X + 1
Last
Address?
Device Failed
Pass
No
Yes Yes
No
Fail
Fail
Pass
No
Program
Mode
Interactive
Mode
Final
Verification
Yes
Program One Pulse = tw = 100 µs
Figure 1. SNAP! Pulse Programming Flow Chart
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
logic symbol†
18
[PWR DWN]
&EN
A
A
A
A
A
A
A
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
E
G
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
24
EPROM 524 288 × 8
13
14
15
17
18
19
20
21
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0
524 287
0
A17
A18 31
30
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers are for the J package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC (see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VPP (see Note 1) –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (see Note 1), All inputs except A9 –0.6 V to VCC + 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A9 –0.6 V to 13 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, with respect to VSS (see Note 1) –0.6 V to VCC + 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range (’27C040-_ _JL and ’27PC040-_ _FML) 0°C to 70°C. . . . . . . . . . . . . .
Operating free-air temperature range (’27C040-_ _JE and ’27PC040 _ _ FME) – 40°C to 85°C. . . . . . . . . . .
Storage temperature range, Tstg –65°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values are with respect to GND.
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
recommended operating conditions
MIN NOM MAX UNIT
VCC
Su
pp
ly voltage
Read mode (see Note 2) 4.5 5 5.5 V
V
CC
S
u
ppl
y v
oltage
SNAP! Pulse programming algorithm 6.25 6.5 6.75 V
VPP
Su
pp
ly voltage
Read mode VCC – 0.6 VCC + 0.6 V
V
PP
S
u
ppl
y v
oltage
SNAP! Pulse programming algorithm 12.75 13 13.25 V
VIH
High level dc in
p
ut voltage
TTL 2 VCC + 0.5 V
V
IH
High
-
le
v
el
dc
inp
u
t
v
oltage
CMOS VCC – 0.2 VCC + 0.5 V
VIL
Low level dc in
p
ut voltage
TTL – 0.5 0.8 V
V
IL
Lo
w-
le
v
el
dc
inp
u
t
v
oltage
CMOS – 0.5 0.2 V
TAOperating free-air temperature ’27C040-_ _JL
’27PC040-_ _FML 0 70 °C
TAOperating free-air temperature ’27C040-_ _JE –40 85 °C
NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted
into or removed from the board when VPP or VCC is applied.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER TEST CONDITIONS MIN MAX UNIT
VOH
High level dc out
p
ut voltage
IOH = – 400 µA2.4
V
OH
High
-
le
v
el
dc
o
u
tp
u
t
v
oltage
IOH = – 20 µA VCC – 0.1
VOL
Low level dc out
p
ut voltage
IOL = 2.1 mA 0.4
V
OL
Lo
w-
le
v
el
dc
o
u
tp
u
t
v
oltage
IOL = 20 µA0.1
IIInput current (leakage) VI = 0 V to 5.5 V ±1µA
IOOutput current (leakage) VO = 0 V to VCC ±1µA
IPP1 VPP supply current VPP = VCC = 5.5 V 10 µA
IPP2 VPP supply current (during program pulse) VPP = 12.75 V 50 mA
ICC1
VCC su
pp
ly current (standby)
TTL-Input level VCC = 5.5 V, E = VIH 1mA
I
CC1
V
CC
s
u
ppl
y
c
u
rrent
(standb
y
)
CMOS-Input level VCC = 5.5 V, E = VCC 100 µA
ICC2 VCC supply current (active) E = VIL,V
CC = 5.5 V
tcycle = minimum cycle time,
outputs open†50 mA
†Minimum cycle time = maximum access time.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz‡
PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT
CiInput capacitance VI = 0 V 4 8 pF
CoOutput capacitance VO = 0 V 8 12 pF
‡All typical values are at TA = 25°C and nominal voltages.
§Capacitance measurements are made on sample basis only.
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
switching characteristics over recommended ranges of operating conditions (see Notes 3
and 4)
PARAMETER TEST CONDITIONS ’27C040-10
’27PC040-10 ’27C040-12
’27PC040-12 ’27C040-15
’27PC040-15 UNIT
MIN MAX MIN MAX MIN MAX
ta(A) Access time from address 100 120 150 ns
ta(E) Access time from chip enable
CL
=
100
p
F,
100 120 150 ns
ten(G) Output enable time from G
CL
=
100
F
,
1 Series 74 50 50 50 ns
tdis Output disable time from G or E, whichever
occurs first TTL load,
Input tr ≤ 20 ns,
In
p
ut tf≤20 ns
0 50 0 50 0 50 ns
tv(A) Output data valid time after change of
address, E, or G, whichever occurs first†
Input
tf
≤
20
ns
0 0 0 ns
†Value calculated from 0.5-V delta to measured output level.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. T iming measurements are made at 2 V for logic high and
0.8 V for logic low. (See Figure 2)
4. Common test conditions apply for tdis except during programming.
switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER MIN MAX UNIT
tdis(G) Output disable time from G 0 100 ns
ten(G) Output enable time from G 150 ns
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (See Figure 2)
timing requirements for programming
MIN NOM MAX UNIT
tw(PGM) Pulse duration, program SNAP! Pulse programming algorithm 95 100 105 µs
tsu(A) Setup time, address 2 µs
tsu(E) Setup time, E 2 µs
tsu(G) Setup time, G 2 µs
tsu(D) Setup time, data 2 µs
tsu(VPP) Setup time, VPP 2µs
tsu(VCC) Setup time, VCC 2µs
th(A) Hold time, address 0 µs
th(D) Hold time, data 2 µs
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Ω
CL = 100 pF
(see Note A)
Output
Under Test
2 V
0.8 V 2 V
0.8 V
2.4 V
0.4 V
NOTES: A. CL includes probe and fixture capacitance.
B. AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low . T iming measurements are made at 2 V for logic high and
0.8 V for logic low for both inputs and outputs.
Figure 2. AC Testing Output Load Circuit and Waveform
A0–A18
E
Addresses Valid
ta(A)
ta(E)
G
DQ0–DQ7 Hi-Z
ten(G) tv(A)
tdis
Output Valid
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Hi-Z
Figure 3. Read-Cycle Timing
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
ten(G)
A0–A18
DQ0–DQ7
VPP
VCC
Address Stable VIH
VIL
VIH/VOH
VIL/VOL
VPP†
VCC
VCC†
VCC
Program Verify
tsu(A) th(A)
tsu(D)
tsu(VPP)
tsu(VCC)
tsu(E) th(D)
tsu(G)
tw(PGM)
tdis(G)
Data-In Stable Data-Out
Stable
E
G
VIH
VIL
VIH
VIL
Hi-Z
†13-V VPP and 6.5-V VCC for SNAP! Pulse programming
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER
4040201-4/B 03/95
0.020 (0,51)
0.015 (0,38)
Seating Plane
0.140 (3,56)
0.132 (3,35)
0.123 (3,12)
0.129 (3,28)
0.043 (1,09)
0.049 (1,24)
0.008 (0,20) NOM
0.595 (15,1 1)
0.553 (14,05)
0.585 (14,86)
TYP
0.030 (0,76)
0.547 (13,89)
301
0.495 (12,57)
0.453 (11,51)
0.485 (12,32)
0.447 (11,35)
5
4
20
13
14
29
21
0.050 (1,27)
0.004 (0,10)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-016
TMS27C040 524288 BY 8-BIT UV ERASABLE
TMS27PC040 524288 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORY
SMLS040F – NOVEMBER 1990 – REVISED SEPTEMBER 1997
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
4040084/B 04/95
B
C
0.018 (0,46) MIN
0.125 (3,18) MIN
0.022 (0,56) 0.012 (0,30)
0.014 (0,36) 0.008 (0,20)
Seating Plane
A
WIDE
24
A
PINS**
DIM
MAX
MIN
NARR
0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99)
1.235(31,37) 1.235(31,37)
1.265(32,13) 1.265(32,13)
MIN
MAX
B
CMAX
MIN
0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
0.541(13,74) 0.598(15,19)
1.668(42,37) 1.668(42,37)
1.632(41,45) 1.632(41,45)
0.590(14,99) 0.590(14,99)
0.624(15,85) 0.624(15,85)
NARR 32 WIDE
0.514(13,06) 0.571(14,50)
0.541(13,74) 0.598(15,19)
1.465(37,21) 1.465(37,21)
1.435(36,45) 1.435(36,45)
0.590(14,99) 0.590(14,99)
0.624(15,85) 0.624(15,85)
NARR 28 WIDE WIDE
40
NARR
0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99)
2.032(51,61) 2.032(51,61)
2.068(52,53) 2.068(52,53)
0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50)
24 PIN SHOWN
112
24 13
0.045 (1,14)
0.065 (1,65)
0.090 (2,29)
0.060 (1,53)
Lens Protrusion
0.010 (0,25) MAX
0.175 (4,45)
0.140 (3,56)
0.100 (2,54)
0°–10°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
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Copyright 1998, Texas Instruments Incorporated