For technical support and more information, see inside back cover or visit www.ti.com
Features
•Triple Logic Voltage Outputs
(Independently Regulated !)
•Input Voltage Range:
36V to 75V
•1500VDC Isolation
•Over-Current Protection
•Over-Voltage Protection
•Over-Temperature Shutdown
•Under-Voltage Lockout
•Independently Adjustable Outputs
Ordering Information
PT4851o = +3.3/+2.5/+1.5V
PT4852o = +3.3/+1.8/+1.5V
PT4853o = +3.3/+2.5/+1.2V
PT4854o = +3.3/+1.8/+1.2V
PT4855o = +3.3/+1.5/+1.2V
PT4856o = +5.0/+3.3/+1.5V
PT Series Suffix (PT1234x)
Case/Pin Order Package
Configuration Suffix Code
Vertical N(EKD)
Horizontal A(EKA)
SMD C(EKC)
(Reference the applicable package code drawing for
the dimensions and PC layout)
Standard Application
PT4850 Series
Description
The PT4850 Excalibur™ power
modules are a series of isolated triple-
output DC/DC converters that
operate from a standard (–48V)
central office supply. These modules
are rated for a combined output of
up to 25A, and were designed for
powering mixed logic applications.
The triple-output voltage provides
a compact multiple-output power
supply in a single DC/DC module.
Output voltage options include
a low-voltage output for a DSP or
ASIC core, and two additional supply
voltages for the I/O, and other func-
tions.
The PT4850 series incorporates
many features to simplify system
integration. These include a flexible
On/Off enable control, input under-
voltage lockout and over-temperature
protection. All outputs are current
limited and short-circuit protected,
and are internally sequenced to meet
the power-up and power-down re-
quirements of popular DSP ICs.
The PT4850 series is housed in
a space-saving solderable case. The
module requires no external heat
sink. Both vertical and horizontal
pin configurations are available, in-
cluding surface mount.
Cin =Optional
Co1, Co2, Co3 =Optional. See specifications
EN1 & EN2 operation: See application notes
25-A Triple Output Isolated DC/DC
Converter For Logic Applications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
CIN
+
Co3+
Co2
+
Co1+
DSL, DSP,
or ASIC
Chipset
I/O
Logic
Core
+V
IN
–V
IN
1 =Inhibit
Q1
18,19,20
PT4850
EN 2
EN 1
+Vo1
+Vo2
+Vo3
COM
V1 Adj
V2 Adj
V3 Adj
COM
+VIN
–VIN
9,10,11
8
15,16
17
22,23
21
12,13,14
1
4
3
2
V3Sense
V2Sense
24
25
•Dual Logic On/Off Control
•Fixed Frequency Operation
•Solderable Space Saving Package:
1.97 sq. in. PCB Area (suffix N)
•IPC Lead Free 2
•Safety Approvals Pending:
UL60950
CSA 22.2 950
VDE EN60950
For technical support and more information, see inside back cover or visit www.ti.com
Pin Function
1+Vin
2–Vin
3 EN 1
4 EN 2
5 TEMP
6 Pin Not Present
7 Do Not Connect
8Vo
1 Adjust
9+Vo
1
PT4850 Series
25-A Triple Output Isolated DC/DC
Converter For Logic Applications
Pin Function
10 +Vo1
11 +Vo1
12 COM
13 COM
14 COM
15 +Vo2
16 +Vo2
17 Vo2 Adjust
18 COM
On/Off Enable Logic
Pin Configuration
Pin Descriptions
Pin 3 Pin 4 Output Status
1× Off
01 On
×0 Off
Notes:
Logic 1 =Open circuit
Logic 0 = –Vin (pin 2) potential
For positive Enable function, connect pin 3
to pin 2 and use pin 4.
For negative Enable function, leave pin 4
open and use pin 3.
+Vin: The positive input supply for the module with
respect to –Vin. When powering the module from a
–48V telecom central office supply, this input is
connected to the primary system ground.
–Vin: The negative input supply for the module, and
the 0VDC reference for the EN 1, and EN 2 inputs.
When powering the module from a +48V supply,
this input is connected to the 48V(Return).
EN 1: The negative logic input that activates the
module output. This pin must be connected to –Vin
to enable the module’s outputs. A high impedance
disables the module’s outputs.
EN 2: The positive logic input that activates the
module output. If not used, this pin should be left
open circuit. Connecting this input to –Vin disables
the module’s outputs.
TEMP: This pin produces an output signal that tracks
a temperature that is approximately the module’s
metal case. The output voltage is referenced to –Vin
and rises approximately 10mV/°C from an intital
value of 0.1VDC at –40°C. The signal is available
whenever the module is supplied with a valid input
voltage, and is independant of the enable logic status.
(Note: A load impedance of less than 1M
Ω
will adversly
affect the module’s over-temperature shutdown threshold.
Use a high-impedance input when monitoring this signal.)
Vo 1: The highest regulated output voltage, which is
referenced to the COM node.
Vo 2: The regulated output that is designed to power
logic circuitry. It is referenced to the COM node.
Vo 3: The low-voltage regulated output that provides
power for a µ-processor or DSP core, and is refer-
enced to the COM node.
COM: The secondary return reference for the module’s
three regulated output voltages. It is DC isolated from
the input supply pins.
Vo(n) Adjust: Using a single resistor, this pin allows the
associated output Vo(n) to be adjusted higher or lower
than the preset value. If not used, this pin should be
left open circuit.
Vo(n) Rem Sense: An external remote sense input is
provided for the two lowest voltage outputs, +Vo2
and +Vo3. Connecting the remote sense pins im-
proves the load regulation of the applicable output
by allowing the regulation circuit to compensate for
voltage drop between the converter and load. If
desired these inputs may be left disconnected.
Note: Shaded functions indicate those pins that are at primary-side potential.
Pin Function
19 COM
20 COM
21 Vo3 Adjust
22 +Vo3
23 +Vo3
24 Vo3 Rem Sense
25 Vo2 Rem Sense
26 Do Not Connect
SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
Environmental Specifications
Characteristics Symbols Conditions Min Typ Max Units
Operating Temperature Range TaOver Vin Range –40 — +85 (i) °C
Case Temperature Tc— — 105 °C
Storage Temperature Ts— –40 — +125 °C
Over Temperature Protection OTP Case temperature — 110 125 °C
Mechanical Shock Per Mil-STD-883D, Method 2002.3 — 500 — G’s
1 msec, ½ Sine, mounted
Mechanical Vibration Mil-STD-883D, Method 2007.2 Suffix N — 10 (ii) —
G’s
20-2000 Hz Suffix A, C — 20 (ii) —
Weight — Vertical/Horizontal — 90 — grams
Flammability — Meets UL 94V-O
Notes: (i) See SOA curves or consult factory for appropriate derating.
(ii) The case pins on through-hole pin configurations (N & A) must be soldered. For more information see the applicable package outline drawing.
For technical support and more information, see inside back cover or visit www.ti.com
PT4850 Series
25-A Triple Output Isolated DC/DC
Converter For Logic Applications
Electrical Specifications (Unless otherwise stated, the operating conditions are:- Ta =25°C, Vin =48V, and Io =0.5Iomax)
PT4850 Series (Except PT4856)
Characteristics Symbols Conditions Min Typ Max Units
Output Current IoEach output Io10—15
Io20—10A
Io30—10
Iotot Total (all three outputs) — — 25 A
Input Voltage Range Vin Continuous 36 — 75 V
Surge (1 minute) — — 80
Set-Point Voltage Tolerance Votol — — 1.5 %Vo
Temperature Variation ∆Regtemp –40°C ≤Ta ≤+85°C, Io1 =Io2 =Io3 =Iomin — ±0.5 — %Vo
Line Regulation ∆Regline All outputs, Over Vin range — ±0.2 ±0.5 %Vo
Load Regulation ∆Regload Each output, 0≤Io≤Iomax — ±5 ±10 mV
Cross Regulation ∆Regcross Any output vs. another — — ±10 mV
Total Output Voltage Variation ∆Vo tol Includes set-point, line, load, —±2±3
(1) %Vo
–40°C ≤Ta ≤+85°C
Efficiency ηIo1 =10A, Io2 =5A, Io3 =5A — 85 — %
Vo Ripple (pk-pk) Vr20MHz bandwidth, Vo =5.0V — 50 75
Io1 =Io2 =Io3 =5A Vo =3.3V — 20 50 mVpp
Vo =1.8V/2.5V — 20 30
Vo ≤1.5V — 15 25
Transient Response ttr 0.1A/µs load step, 50% to 75% Iomax — 200 — µSec
Vos Vo over/undershoot — 5 — %Vo
Output Adjust Range Voadj Vo1/Vo2/Vo3— ±10 — %Vo
Current Limit Threshold ILIM ∆Vo = –1% Vo1—20—
Vo2—15—A
Vo3—15—
Output Over-Voltage Protection OVP All outputs; module shutdown and latch off — 125 (2) —%V
o
Switching Frequency ƒsOver Vin and Io ranges 280 320 340 kHz
Under Voltage Lockout Von Vin increasing — 34 36 V
Voff Vin decreasing 30 32 —
Enable Control (pins 3 & 4) Referenced to –Vin (pin 2)
High-Level Input Voltage VIH 3.5 — Open (3) V
Low-Level Input Voltage VIL –0.2 — 0.8 (3)
Low-Level Input Current IIL — 0.5 — mA
Standby Input Current Iin standby pins 3 & 4 open circuit — 2.5 4 (1) mA
Internal Input Capacitance Cint —2 —µF
External Output Capacitance Cout Per each output 0 — 5,000 µF
Primary/Secondary Isolation V iso 1500 — — V
C iso — 2,200 — pF
R iso 10——MΩ
Temperature Sense Vtemp Output voltage at temperatures:- –40°C — 0.1 (4) —V
100°C — 1.5 (4) —
Notes:
(1) Limits are specified by design.
(2) This is a fixed parameter. Adjusting Vo1 or Vo2 higher will increase the module’s sensitivity to over-voltage detection. For more information, see the
application note on output voltage adjustment.
(3) The Enable inputs (pins 3 & 4) have internal pull-ups. Leaving pin 4 open-circuit and connecting pin 3 to –Vin (pin 2) allows the the converter to
operate when input power is applied. The maximum open-circuit voltage for the Enable inputs is 5.4V.
(4) Voltage output at “TEMP” pin is defined by the equation:- VTEMP = 0.5 + 0.01·T, where T is in °C. See pin descriptions for more information.
SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
For technical support and more information, see inside back cover or visit www.ti.com
PT4850 Series
25-A Triple Output Isolated DC/DC
Converter For Logic Applications
Efficiency vs Output Load
PT4851 Performance Characteristics (See Note A)
(Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load)
Typical Characteristics
Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR.
Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures.
Power Dissipation vs Output Load
PT4851 Safe operating Area Curves (See Note B)
(Io1 + Io2 + Io3 =25A, represents 100% load)
SOA vs Output Power @Vin =48V
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Efficiency - %
36V
48V
75V
VIN
20
30
40
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Ambient Temperature (°C)
500LFM
400LFM
300LFM
200LFM
100LFM
Nat conv
Airflow
Efficiency vs Output Load
PT4852 Performance Characteristics (See Note A)
(Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load)
Power Dissipation vs Output Load
PT4852 Safe operating Area Curves (See Note B)
(Io1 + Io2 + Io3 =25A, represents 100% load)
SOA vs Output Power @Vin =48V
20
30
40
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Ambient Temperature (°C)
500LFM
400LFM
300LFM
200LFM
100LFM
Nat conv
Airflow
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Efficiency - %
36V
48V
75V
VIN
0
4
8
12
16
0 20406080100
Out
p
ut Load
(
%
)
Pd - Watts
36V
48V
75V
VIN
0
4
8
12
16
0 20406080100
Out
p
ut Load
(
%
)
Pd - Watts
75V
48V
36V
VIN
SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
For technical support and more information, see inside back cover or visit www.ti.com
PT4850 Series
25-A Triple Output Isolated DC/DC
Converter For Logic Applications
Efficiency vs Output Load
PT4853 Performance Characteristics (See Note A)
(Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load)
Typical Characteristics
Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR.
Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures.
Power Dissipation vs Output Load
PT4853 Safe operating Area Curves (See Note B)
(Io1 + Io2 + Io3 =25A, represents 100% load)
SOA vs Output Power @Vin =48V
Efficiency vs Output Load
PT4854 Performance Characteristics (See Note A)
(Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load)
Power Dissipation vs Output Load
PT4854 Safe operating Area Curves (See Note B)
(Io1 + Io2 + Io3 =25A, represents 100% load)
SOA vs Output Power @Vin =48V
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Efficiency - %
36V
48V
75V
VIN
0
4
8
12
16
0 20406080100
Out
p
ut Power
(
%
)
Pd - Watts
36V
48V
75V
VIN
20
30
40
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Ambient Temperature (°C)
500LFM
400LFM
300LFM
200LFM
100LFM
Nat conv
Airflow
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Efficiency - %
36V
48V
75V
VIN
0
4
8
12
16
0 20406080100
Out
p
ut Load
(
%
)
Pd - Watts
75V
48V
36V
VIN
20
30
40
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Ambient Temperature (°C)
500LFM
400LFM
300LFM
200LFM
100LFM
Nat conv
Airflow
SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
For technical support and more information, see inside back cover or visit www.ti.com
PT4850 Series
25-A Triple Output Isolated DC/DC
Converter For Logic Applications
Efficiency vs Output Load
PT4855 Performance Characteristics (See Note A)
(Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load)
Typical Characteristics
Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR.
Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures.
Power Dissipation vs Output Load
PT4855 Safe operating Area Curves (See Note B)
(Io1 + Io2 + Io3 =25A, represents 100% load)
SOA vs Output Power @Vin =48V
20
30
40
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Ambient Temperature (°C)
500LFM
400LFM
300LFM
200LFM
100LFM
Nat conv
Airflow
0
4
8
12
16
0 20406080100
Out
p
ut Load
(
%
)
Pd - Watts
75V
48V
36V
VIN
SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
50
60
70
80
90
0 20406080100
Out
p
ut Load
(
%
)
Efficiency - %
36V
48V
75V
VIN
For technical support and more information, see inside back cover or visit www.ti.com
PT4856
25-A Triple Output Isolated DC/DC
Converter For Logic Applications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
PT4856 Electrical Specifications (Unless otherwise stated, the operating conditions are:- Ta =25°C, Vin =48V, and Io =0.5Iomax)
PT4856 (Only)
Characteristics Symbols Conditions Min Typ Max Units
Output Current IoEach output Io10—10
Io20—10A
Io30—10
Iotot Total (all three outputs) — — 25 A
Input Voltage Range Vin Continuous 36 — 75 V
Surge (1 minute) — — 80
Set-Point Voltage Tolerance Votol — — 1.5 %Vo
Temperature Variation ∆Regtemp –40°C ≤Ta ≤+85°C, Io1 =Io2 =Io3 =Iomin — ±0.5 — %Vo
Line Regulation ∆Regline All outputs, Over Vin range — ±0.2 ±0.5 %Vo
Load Regulation ∆Regload Each output, 0≤Io≤Iomax — ±5 ±10 mV
Cross Regulation ∆Regcross Any output vs. another — — ±10 mV
Total Output Voltage Variation ∆Vo tol Includes set-point, line, load, —±2±3
(1) %Vo
–40°C ≤Ta ≤+85°C
Efficiency ηIo1 =7A, Io2 =5A, Io3 =5A — 88 — %
Vo Ripple (pk-pk) Vr20MHz bandwidth, Vo =5.0V — 50 75
Io1 =Io2 =Io3 =5A Vo =3.3V — 20 50 mVpp
Vo =1.5V — 15 25
Transient Response ttr 0.1A/µs load step, 50% to 75% Iomax — 200 — µSec
Vos Vo over/undershoot — 5 — %Vo
Output Adjust Range Voadj Vo1/Vo2/Vo3— ±10 — %Vo
Current Limit Threshold ILIM ∆Vo = –1% Vo1—20—
Vo2—15—A
Vo3—15—
Output Over-Voltage Protection OVP All outputs; module shutdown and latch off — 125 (2) —%V
o
Switching Frequency ƒsOver Vin and Io ranges 280 320 340 kHz
Under Voltage Lockout Von Vin increasing — 34 36 V
Voff Vin decreasing 30 32 —
Enable Control (pins 3 & 4) Referenced to –Vin (pin 2)
High-Level Input Voltage VIH 3.5 — Open (3) V
Low-Level Input Voltage VIL –0.2 — 0.8 (3)
Low-Level Input Current IIL — 0.5 — mA
Standby Input Current Iin standby pins 3 & 4 open circuit — 2.5 4 (1) mA
Internal Input Capacitance Cint —2 —µF
External Output Capacitance Cout Per each output 0 — 5,000 µF
Primary/Secondary Isolation V iso 1500 — — V
C iso — 2,200 — pF
R iso 10——MΩ
Temperature Sense Vtemp Output voltage at temperatures:- –40°C — 0.1 (4) —V
100°C — 1.5 (4) —
Notes:
(1) Limits are specified by design.
(2) This is a fixed parameter. Adjusting Vo1 or Vo2 higher will increase the module’s sensitivity to over-voltage detection. For more information, see the
application note on output voltage adjustment.
(3) The Enable inputs (pins 3 & 4) have internal pull-ups. Leaving pin 4 open-circuit and connecting pin 3 to –Vin (pin 2) allows the the converter to
operate when input power is applied. The maximum open-circuit voltage for the Enable inputs is 5.4V.
(4) Voltage output at “TEMP” pin is defined by the equation:- VTEMP = 0.5 + 0.01·T, where T is in °C. See pin descriptions for more information.
For technical support and more information, see inside back cover or visit www.ti.com
PT4856
25-A Triple Output Isolated DC/DC
Converter For Logic Applications
Efficiency vs Output Load
PT4856 Performance Characteristics (See Note A)
(Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load)
Typical Characteristics
Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR.
Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures.
Power Dissipation vs Output Load
PT4856 Safe operating Area Curves (See Note B)
(Io1 + Io2 + Io3 =24A, represents 100% load)
SOA vs Output Power @Vin =48V
20
30
40
50
60
70
80
90
0 20406080100
Out
p
ut Power
(
W
)
Ambient Temperature (°C)
300LFM
200LFM
100LFM
Nat Conv
Airflow
50
60
70
80
90
100
0 20406080100
Out
p
ut Load
(
%
)
Efficiency - %
36V
48V
75V
VIN
0
5
10
15
20
25
0 20406080100
Out
p
ut Load
(
%
)
Pd - Watts
75V
48V
36V
VIN
SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
Application Notes
For technical support and more information, see inside back cover or visit www.ti.com
PT4850 Series
Operating Features of the PT4850 Triple-Output
DC/DC Converters
Over-Current Protection
The PT4850 series of DC/DC converters provide three
independently regulated logic output voltages, Vo1, Vo2,
and Vo3. Each output is current limited to protect against
load faults. The module will not be damaged by a con-
tinuous load fault applied to any output. Current will
continue to flow into the fault but is reduced as the volt-
age across the fault decreases towards zero.
Applying a load fault above the current limit threshold
to any output causes the affected output to significantly
drop. Also load faults applied to Vo1 will affect Vo2 and
Vo3, once Vo1 drops to within 0.2V of either of these
voltages. However, load faults applied to Vo2 or Vo3 will
not affect the other outputs.
Over-Temperature Protection
The PT4850 DC/DC converter series have an internal
temperature sensor, which monitors the temperature of
the module’s metal case. If the case temperature exceeds
the specified limit the converter will shut down. The
converter will automatically restart when the sensed
temperature returns to within the normal operating
range. The analog voltage generated by the sensor is
also made available at the ‘TEMP’ output (pin 5), and
can be monitored by the host system for diagnostic pur-
poses. Consult the ‘Pin Descriptions’ section of the data
sheet for more information on this feature.
Under-Voltage Lock-Out
The Under-Voltage Lock-Out (UVLO) circuit prevents
operation of the converter whenever the input voltage to
the module is insufficient to maintain output regulation.
The UVLO has approximately 2V of hysterisis. This is
to prevent oscillation with a slowly changing input voltage.
Below the UVLO threshold the module is off and the
enable control inputs, EN1 and EN2 are inoperative.
Primary-Secondary Isolation
The PT4850 series of DC/DC converters incorporate
electrical isolation between the input terminals (primary)
and the output terminals (secondary). All converters are
production tested to a withstand voltage of 1500VDC.
The isolation complies with UL60950 and EN60950,
and the requirements for operational isolation. This
allows the converter to be configured for either a positive
or negative input voltage source.
The regulation control circuitry for these modules is
located on the secondary (output) side of the isolation
barrier. Control signals are passed between the primary
and secondary sides of the converter via a proprietory
magnetic coupling scheme. This eliminates the use of
opto-couplers. The data sheet ‘Pin Descriptions’ and
‘Pin-Out Information’ provides guidance as to which
reference (primary or secondary) that must be used for
each of the external control signals.
Fuse Recommendations
If desired an input fuse may be added to protect against
the application of a reverse input voltage.
For technical support and more information, see inside back cover or visit www.ti.com
Application Notes
PT4850 Series
Figure 3; Vo1, Vo2, Vo3 Power-Up Sequence
On/Off Output Voltage Sequencing
The power-up characteristic of the PT4850 series of
DC/DC converters meets the requirements of micro-
processor and DSP chipsets. All three outputs from the
converter are internally sequenced to power up in
unison. Figure 3 shows the waveforms from a PT4851
after power is applied to the input of the converter.
During power-up, all three output voltages rise together
until each reaches their respective output voltage. The
waveforms of Figure 3 were measured with loads of ap-
proximately 50% on each output, with an input source of
48VDC. The converter typically produces a fully regu-
lated output within 150ms.
Using the On/Off Enable Controls on the PT4850
Series of Triple Output DC/DC Converters
The PT4850 (48V input) series of 25-A, triple-output
DC/DC converters incorporate two output enable controls.
EN1 (pin 3) is the Negative Enable input, and EN2 (pin 4)
is the Positive Enable input. Both inputs are electrically
referenced to -Vin (pin 2) on the primary or input side of
the converter. A pull-up resistor is not required, but may
be added if desired. Voltages of up to 70V can be safely
applied to the either of the Enable pins.
Automatic (UVLO) Power-Up
Connecting EN1 (pin 3) to -Vin (pin 2) and leaving EN2
(pin 4) open-circuit configures the converter for auto-
matic power up. (See data sheet “Typical Application”).
The converter control circuitry incorporates an “Under
Voltage Lockout” (UVLO) function, which disables the
converter until the minimum specified input voltage is
present at ±Vin. (See data sheet Specifications). The UVLO
circuitry ensures a clean transition during power-up and
power-down, allowing the converter to tolerate a slow-
rising input voltage. For most applications EN1 and
EN2, can be configured for automatic power-up.
Positive Output Enable (Negative Inhibit)
To configure the converter for a positive enable func-
tion, connect EN1 (pin 3) to -Vin (pin 2), and apply the
system On/Off control signal to EN2 (pin 4). In this
configuration, a low-level input voltage (-Vin potential)
applied to pin 4 disables the converter outputs. Figure 1
is an example of this configuration.
Negative Output Enable (Positive Inhibit)
To configure the converter for a negative enable function,
EN2 (pin 4) is left open circuit, and the system On/Off
control signal is applied to EN1 (pin 3). A low-level
input voltage (-Vin potential) must then be applied to
DC/DC
Module
EN 1*
EN 2
–Vin
–VIN
1 =Outputs Off
4
3
2
BSS138
DC/DC
Module
EN 1*
EN 2
–Vin
–VIN
1 =Outputs On
4
3
2
BSS138
Figure 2; Negative Enable Configuration
Figure 1; Positive Enable Configuration
During turn-off, all outputs drop rapidly due to the
discharging effect of actively switched rectifiers. The
voltage at Vo2 remains higher than Vo3 during this
period. The discharge time is typically 100µs, but will
vary with the amount of external load capacitance.
pin 3 in order to enable the outputs of the converter.
An example of this configuration is detailed in Figure 2.
Note: The converter will only produce and output voltage if a
valid input voltage is applied to ±Vin.
Vo1 (1V/Div)
V02 (1V/Div)
Vo3 (1V/Div)
HORIZ SCALE: 20ms/Div
Application Notes
For technical support and more information, see inside back cover or visit www.ti.com
Adjusting the Output Voltages of the PT4850
Triple-Output DC/DC Converters
The output voltages of the PT4850 series of triple-output
DC/DC converters, Vo1, Vo2 and Vo3, are independently
adjustable. The adjustment method uses a single external
resistor, 1 which may be used to adjust a selected output
by up to ±10% from the factory preset value. The value
of the resistor determines the magnitude of adjustment,
and the placement of the resistor determines the direction
of adjustment (up or down). The resistor values can be
calculated using the appropriate formula (see below),
using the constants provided in Table 3-2. Alternatively
the resistor value may be selected directly from Table 3-3
and Table 3-4, for Vo1 and Vo2/Vo3 respectively. The
placement of each resistor is as follows.
Adjust Up: To increase a specific output, add a resistor R1
between the appropriate Vx Adj (V1 Adj, V2 Adj, or V3 Adj)
and the output common (COM). See Figure 3-1(a)
and Table 3-1 for the resistor placement and pin connec-
tions.
Figure 3-1b
PT4850 Series
Calculation of Adjust Values
The adjust resistor value may also be calculated using an
equation. In each case, the equation for R1 [Adjust Up] is
different to that for (R2) [Adjust Down]. For the PT4850
series, the following points should be noted.
•Vo
1 uses different equations to Vo2 and Vo3. The
equations are defined for the desired output voltage.
• The equations for Vo2 and Vo3 are based on the
percentage of desired adjustment. Both Vo2 and Vo3
use the same constants, which are common for all
output voltages.
Vo1 Adjust:
R1 [Adjust Up] 3 = 2.5 Ro– RskΩ
Va – Vo
(R2) [Adjust Down] 3 =Ro (Va – 2.5 )
– RskΩ
Vo – Va
Where: Vo= Original output voltage
Va= Adjusted output voltage
Ro= The resistance value in Table 3-2
Rs= The series resistance from Table 3-2
Vo2 / Vo3 Adjust:
R1 [Adjust Up] 3=50 · Ro–RskΩ
n%
(R2) [Adjust Down] 3=R
o · (50 – n%) –RskΩ
n%
Where: Ro= The resistance value in Table 3-2
Rs= The series resistance from Table 3-2
n% = The desired adjustment from the
nominal (in percent)
(R2)
+Vo
x
+V
x
Adj
COM
+Vox
(Adjusted Down)
Output
Common
PT4850
#
#
#
# - See Table 3-1 for pin connections,
where Vo
x
equals Vo
1
, Vo
2
, or Vo
3
Figure 3-1a
R1
+Vo
x
+V
x
Adj
COM
+Vox
(Adjusted Up)
Output
Common
PT4850
#
#
#
# - See Table 3-1 for pin connections,
where Vo
x
equals Vo
1
, Vo
2
, or Vo
3
Adjust Down: Add a resistor (R2), between the appropriate
Vx Adj (V1 Adj, V2 Adj, or V3 Adj) and the output being
adjusted, +Vox. See Figure 3-1(b) and Table 3-1 for the
resistor placement and pin connections.
Table 3-1; Adjust Resistor Pin Connections
To Adjust Up To Adjust Down
Connect R1Connect (R2)
from to from to
Vox Adj COM Vox Adj Vox
Vo 1812 89
Vo 217 18 17 16
Vo 321 18 21 22
For technical support and more information, see inside back cover or visit www.ti.com
Application Notes
continued
3.0 (2.4)kΩ
3.05 (4.7)kΩ
3.1 (8.3)kΩ
3.15 (14.2)kΩ
3.2 (26.0)kΩ
3.25 (61.3)kΩ
3.3
3.35 216.0kΩ
3.4 106.0kΩ
3.45 68.7kΩ
3.5 50.3kΩ
3.55 39.2kΩ
3.6 31.8kΩ
•
4.5 (15.0)kΩ
4.6 (21.2)kΩ
4.7 (31.6)kΩ
4.8 (52.4)kΩ
4.9 (115.0)kΩ
5.0
5.1 120.0kΩ
5.2 57.4kΩ
5.3 36.6kΩ
5.4 26.2kΩ
5.5 20.0kΩ
R1 = Black, R2 = (Blue)
Adj. Resistors R1/(R2)
Vo(nom) 3.3V 5.0V
Va(req’d)
Table 3-2
ADJUSTMENT RANGE AND FORMULA PARAMETERS
Vo1 Bus Vo2 / Vo3 Bus
Vo(nom) 5.0V 3.3V All
Va(min) 4.5V 2.97V Vnom – 10%
Va(max) 5.5V 3.63V Vnom + 10%
Ro (kΩ)4.99 4.42 2.1
Rs (kΩΩ
ΩΩ
Ω)4.99 4.99 4.99
Table 3-4
ADJUSTMENT RESISTOR VALUES FOR Vo2 / Vo3 Buses
Vo (nom) 3.3V 2.5V 1.8V 1.5V 1.2V
% Adjust ——————— Adjusted Output Voltage ——————— R1/(R2)
–10 2.97 2.25 1.62 1.35 1.08 (3.4)kΩ
– 9 3.003 2.275 1.638 1.365 1.092 (4.6)kΩ
– 8 3.036 2.3 1.656 1.38 1.104 (6.0)kΩ
– 7 3.069 2.325 1.674 1.395 1.116 (7.9)kΩ
– 6 3.102 2.35 1.692 1.41 1.128 (10.4)kΩ
– 5 3.135 2.375 1.71 1.425 1.14 (13.9)kΩ
– 4 3.168 2.4 1.728 1.44 1.152 (19.2)kΩ
– 3 3.201 2.425 1.746 1.455 1.64 (27.9)kΩ
– 2 3.234 2.45 1.764 1.47 1.176 (45.4)kΩ
– 1 3.267 2.475 1.782 1.485 1.188 (97.9)kΩ
0 3.3 2.5 1.8 1.5 1.2
+ 1 3.333 2.525 1.818 1.515 1.212 100.0kΩ
+ 2 3.366 2.55 1.836 1.53 1.224 47.5kΩ
+ 3 3.399 2.575 1.854 1.545 1.236 30.0kΩ
+ 4 3.432 2.6 1.872 1.56 1.248 21.3kΩ
+ 5 3.465 2.625 1.89 1.575 1.26 16.0kΩ
+ 6 3.498 2.65 1.908 1.58 1.272 12.5kΩ
+ 7 3.531 2.675 1.926 1.605 1.284 10.0kΩ
+ 8 3.564 2.7 1.944 1.62 1.296 8.1kΩ
+ 9 3.597 2.725 1.962 1.635 1.308 6.7kΩ
+10 3.630 2.75 1.98 1.65 1.32 5.5kΩ
Table 3-3
ADJUSTMENT RESISTOR VALUES FOR Vo1 Bus
PT4850 Series
Notes:
1. Use only a single 1% (or better) tolerance resistor in
either the R1 or (R2) location to adjust a specific output.
Place the resistor as close to the ISR as possible.
2. Never connect capacitors to any of the ‘Vox Adj’ pins. Any
capacitance added to these control pins will affect the
stability of the respective regulated output.
3. Adjustments made to any output must also comply with
the following limitations.
Vo1≥ (Vo2 + 0.5V), and
Vo1≥ (Vo3 + 0.5V)
R1 = Black, R2 = (Blue)
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jul-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PT4851A NRND SIP MODULE EKA 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4851C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available
PT4851N NRND SIP MODULE EKD 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4852A NRND SIP MODULE EKA 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4852C NRND SIP MODULE EKC 26 TBD Call TI Level-3-215C-168HRS Samples Not Available
PT4852N NRND SIP MODULE EKD 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4853A NRND SIP MODULE EKA 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4853C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available
PT4853N NRND SIP MODULE EKD 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4854A NRND SIP MODULE EKA 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4854C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available
PT4854N NRND SIP MODULE EKD 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4855A NRND SIP MODULE EKA 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4855C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available
PT4855N NRND SIP MODULE EKD 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4856A NRND SIP MODULE EKA 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available
PT4856C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available
PT4856N NRND SIP MODULE EKD 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jul-2010
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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