SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
3-State Outputs Interface Directly With
System Bus
D
Gated Output-Control LInes for Enabling or
Disabling the Outputs
D
Fully Independent Clock Virtually
Eliminates Restrictions for Operating in
One of Two Modes:
– Parallel Load
– Do Nothing (Hold)
D
For Application as Bus Buffer Registers
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
TYPE TYPICAL
PROPAGATION
DELAY TIME
MAXIMUM
CLOCK
FREQUENCY
’173 23 ns 35 MHz
’LS173A 18 ns 50 MHz
description
The ’173 and ’LS173A 4-bit registers include
D-type flip-flops featuring totem-pole 3-state
outputs capable of driving highly capacitive
or relatively low-impedance loads. The
high-impedance third state and increased
high-logic-level drive provide these flip-flops with
the capability of being connected directly to and
driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of
the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or
54LS/74LS TTL normalized loads, respectively . Similarly, up to 49 of the SN54173 or SN54LS173A outputs can
be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,
respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that the average output disable times are shorter than the
average output enable times.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both
data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next
positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both
are low , the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at either
output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed
operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of
–55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M
N
1Q
2Q
3Q
4Q
CLK
GND
VCC
CLR
1D
2D
3D
4D
G2
G1
SN54173, SN54LS173A ...J OR W PACKAGE
SN74173 ...N PACKAGE
SN74LS173A ...D or N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
1D
2D
NC
3D
4D
1Q
2Q
NC
3Q
4Q
SN54LS173A . . . FK PACKAGE
(TOP VIEW)
N
M
NC
CLR
GND
NC CC
V
NC – No internal connection
G2
G1
CLK
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUT
CLR
CLK
DATA ENABLE DATA OUTPUT
Q
CLR
CLK
G1 G2 D
Q
H X X X X L
LLXXX Q
0
L↑HXX Q
0
L↑XHX Q
0
L↑LL
LL
L↑LLH H
When either M or N (or both) is (are) high, the output is
disabled to the high-impedance state; however , sequential
operation of the flip-flops is not affected.
logic symbol†
G2
G1
G2
G1
1Q
3
R
15
CLR
13
2D 2Q
4
12
3D 3Q
5
11
4D 4Q
6
1
M
10
7
CLK
&
†This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, N, and W packages.
&EN
C1
2
N9
1D
14
1D 1Q
3
R
15
CLR
13
2D 2Q
4
12
3D 3Q
5
11
4D 4Q
6
1
M
10
7
CLK
&
&EN
C1
2
N9
1D
14
1D
’173 ’LS173A
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
M
N
1D
CLR
CLK
2D
3D
4D
Output
Control
Data
Enable
G1
G2
1
2
14
9
10
13
7
12
11
15
3
4
5
6
1Q
2Q
3Q
4Q
Pin numbers shown are for D, J, N, and W packages.
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
Equivalent of Each Input Equivalent of Each Input
Typical of All Outputs
VCC
Input
4 kΩ NOM
VCC
Input
20 kΩ NOM
VCC
Output
90 Ω NOM
VCC
Output
100 Ω NOM
’173 ’LS173A
Typical of All Outputs
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage: ’173 –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
’LS173A –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-state output voltage –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54173 SN74173
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current –2 –5.2 mA
IOL Low-level output current 16 16 mA
TAOperating free-air temperature –55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54173 SN74173
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIK Input clamp voltage VCC = MIN, II = –12 mA –1.5 –1.5 V
VOH High-level output voltage VCC = MIN,
VIL = 0.8 V, VIH = 2 V,
IOH = MAX 2.4 2.4 V
VOL Low-level output voltage VCC = MIN,
VIL = 0.8 V, VIH = 2 V,
IOL = 16 mA 0.4 0.4 V
IO( ff)
Off-state (high-impedance state) V
CC
= MAX, VO = 2.4 V 150 40
µA
I
O(off)
(g )
output current
CC ,
VIH = 2 V VO = 0.4 V –150 –40 µ
A
IIInput current
at maximum input voltage VCC = MAX, VI = 5.5 V 1 1 mA
IIH High-level input current VCC = MAX, VI = 2.4 V 40 40 µA
IIL Low-level input current VCC = MAX, VI = 0.4 V –1.6 –1.6 mA
IOS Short-circuit output current§VCC = MAX –30 –70 –30 –70 mA
ICC Supply current VCC = MAX, See Note 4 50 72 50 72 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time.
NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V , N, G1, G2, and all data inputs grounded;
and CLK and M at 4.5 V.
timing requirements over recommended operating conditions (unless otherwise noted)
SN54173 SN74173
UNIT
MIN MAX MIN MAX
UNIT
fclock Input clock frequency 25 25 MHz
twPulse duration CLK or CLR 20 20 ns
Data enable (G1, G2) 17 17
tsu Setup time Data 10 10 ns
CLR (inactive state) 10 10
th
Hold time
Data enable (G1, G2) 2 2
ns
t
h
Hold
time
Data 10 10
ns
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TA = 25°C, RL = 400 Ω (see Figure 1)
PARAMETER
TEST CONDITIONS
SN54173 SN74173
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
fmax Maximum clock frequency 25 35 25 35 MHz
tPHL Propagation delay time,
high-to-low-level output from clear input 18 27 18 27 ns
tPLH Propagation delay time,
low-to-high-level output from clock input C
L
= 50 pF 28 43 28 43
ns
tPHL Propagation delay time,
high-to-low-level output from clock input
L
19 31 19 31
ns
tPZH Output enable time to high level 7 16 30 7 16 30
ns
tPZL Output enable time to low level 7 21 30 7 21 30
ns
tPHZ Output disable time from high level
CL=5
p
F
3 5 14 3 5 14
ns
tPLZ Output disable time from low level
C
L =
5
pF
311 20 3 11 20
ns
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54LS173A SN74LS173A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current –1 –2.6 mA
IOL Low-level output current 12 24 mA
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54LS173A SN74LS173A UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP‡MAX MIN TYP‡MAX UNIT
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V
VOH High-level output voltage VCC = MIN,
VIL = VILmax, VIH = 2 V,
IOH = MAX 2.4 3.4 2.4 3.1 V
VOL
Low level out
p
ut voltage
V
CC
= MIN, IOL = 12 mA 0.25 0.4 0.25 0.4 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
CC ,
VIL = 0.8 V, IOL = 24 mA 0.35 0.5 V
IO( ff)
Off-state (high-impedance state) V
CC
= MAX, VO = 2.7 V 20 20
V
I
O(off)
(g )
output current
CC ,
VIH = 2 V VO = 0.4 V –20 –20
V
IIInput current
at maximum input voltage VCC = MAX, VI = 7 V 0.1 0.1 mA
IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 µA
IIL Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA
IOS Short-circuit output current§VCC = MAX –30 –130 –30 –130 mA
ICC Supply current VCC = MAX, See Note 4 19 30 19 24 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time.
NOTE 4: ICC is measured with all outputs open; CLR grounded, following momentary connection to 4.5 V , N, G1, G2, and all data inputs grounded;
and CLK and M at 4.5 V.
timing requirements over recommended operating conditions (unless otherwise noted)
SN54LS173A SN74LS173A
UNIT
MIN MAX MIN MAX
UNIT
fclock Input clock frequency 30 25 MHz
twPulse duration CLK or CLR 25 25 ns
Data enable (G1, G2) 35 35
tsu Setup time Data 17 17 ns
CLR (inactive state) 10 10
th
Hold time
Data enable (G1, G2) 0 0
ns
t
h
Hold
time
Data 3 3
ns
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TA = 25°C, RL = 667 Ω (see Figure 2)
PARAMETER
TEST CONDITIONS
SN54LS173A SN74LS173A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
fmax Maximum clock frequency 30 50 30 50 MHz
tPHL Propagation delay time,
high-to-low-level output from clear input 26 35 26 35 ns
tPLH Propagation delay time,
low-to-high-level output from clock input C
L
= 45 pF 17 25 17 25
ns
tPHL Propagation delay time,
high-to-low-level output from clock input
L
22 30 22 30
ns
tPZH Output enable time to high level 15 23 15 23
ns
tPZL Output enable time to low level 18 27 18 27
ns
tPHZ Output disable time from high level
CL=5
p
F
11 20 11 20
ns
tPLZ Output disable time from low level
C
L =
5
pF
11 17 11 17
ns
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 AND 54S/74S DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point (see
Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr and tf ≤7 ns for Series
54/74 devices and tr and tf ≤2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
(see Notes C
and D)
W aveform 2
(see Notes C
and D) ≈1.5 V
VOH – 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOL
VOH
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuits and Voltage Waveforms
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
2-STATE
TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see
Note B)
VCC RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
W aveform 1
S2 Open
(see Notes C
and D)
W aveform 2
S2 Closed
(see Notes C
and D) ≈1.5 V
VOH – 0.3 V
VOL + 0.3 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOL
VOH
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
Figure 2. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
JM38510/36101B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
JM38510/36101BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
JM38510/36101BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
JM38510/36101SEA ACTIVE CDIP J 16 25 TBD A42 N / A for Pkg Type
JM38510/36101SFA ACTIVE CFP W 16 25 TBD A42 N / A for Pkg Type
M38510/36101B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
M38510/36101BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
M38510/36101BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
M38510/36101SEA ACTIVE CDIP J 16 25 TBD A42 N / A for Pkg Type
M38510/36101SFA ACTIVE CFP W 16 25 TBD A42 N / A for Pkg Type
SN54173J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN54LS173AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SN74173N OBSOLETE PDIP N 16 TBD Call TI Call TI
SN74LS173AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS173ADE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS173ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LS173AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74LS173ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ54173J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54173W OBSOLETE CFP W 16 TBD Call TI Call TI
SNJ54LS173AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LS173AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ54LS173AW ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 2
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54173, SN54LS173A, SN54LS173A-SP, SN74173, SN74LS173A :
•Catalog: SN74173, SN74LS173A, SN54LS173A
•Military: SN54173, SN54LS173A
•Space: SN54LS173A-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
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