FEATURES FUNCTIONAL BLOCK DIAGRAM 4 A peak output current Working voltage High-side or low-side relative to input: 537 V peak High frequency operation: 1 MHz maximum 3.3 V to 5 V CMOS input logic 4.5 V to 18 V output drive Secondary UVLO ADuM3224A/ADuM4224A UVLO at 4.1 V VDDA/VDDB ADuM3224B/ADuM4224B UVLO at 6.9 V VDDA/VDDB ADuM3224C/ADuM4224C UVLO at 10.5 V VDDA/VDDB Precise timing characteristics 59 ns maximum isolator and driver propagation delay 5 ns maximum channel-to-channel matching CMOS input logic levels High common-mode transient immunity: >25 kV/s Enhanced system-level ESD performance per IEC 61000-4-x High junction temperature operation: 125C Default low output Safety and regulatory approvals ADuM3224 narrow-body, 16-lead SOIC UL recognition per UL 1577 3000 V rms for 1 minute SOIC long package CSA Component Acceptance Notice 5A VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak ADuM4224 wide-body, 16-lead SOIC UL recognition per UL 1577 5000 V rms for 1 minute SOIC long package CSA Component Acceptance Notice 5A VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak Qualified for automotive applications APPLICATIONS Switching power supplies Isolated IGBT/MOSFET gate drives Industrial inverters VIA 1 VIB 2 ADuM3224/ ADuM4224 ENCODE 16 VDDA DECODE VDD1 3 15 VOA 14 GNDA GND1 4 13 NC DISABLE 5 12 NC NC 6 NC 7 11 VDDB ENCODE VDD1 8 DECODE 10 VOB 9 NC = NO CONNECT GNDB 11791-001 Data Sheet Isolated Precision Half-Bridge Driver, 4 A Output ADuM3224/ADuM4224 Figure 1. GENERAL DESCRIPTION TheADuM3224/ADuM42241 are 4 A isolated, half-bridge gate drivers that employ the Analog Devices, Inc., iCoupler(R) technology to provide independent and isolated high-side and low-side outputs. The ADuM3224 provides 3000 V rms isolation in the narrow-body, 16-lead SOIC package, and the ADuM4224 provides 5000 V rms isolation in the wide-body, 16-lead SOIC package. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to the alternatives, such as the combination of pulse transformers and gate drivers. The ADuM3224/ADuM4224 isolators each provide two independent isolated channels. They operate with an input supply ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems. In comparison to gate drivers employing high voltage level translation methodologies, the ADuM3224/ADuM4224 offer the benefit of true, galvanic isolation between the input and each output. Each output can be continuously operated up to 537 V peak relative to the input, thereby supporting low-side switching to negative voltages. The differential voltage between the high-side and low-side can be as high as 800 V peak. As a result, the ADuM3224/ADuM4224 provide reliable control over the switching characteristics of IGBT/MOSFET configurations over a wide range of positive or negative switching voltages. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,239. Other patents pending. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2013-2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM3224/ADuM4224 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions........................... 10 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 11 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 14 General Description ......................................................................... 1 Printed Circuit Board Layout ................................................... 14 Revision History ............................................................................... 2 Undervoltage Lockout ............................................................... 14 Specifications..................................................................................... 3 Propagation Delay-Related Parameters ................................... 14 Electrical Characteristics--5 V Operation................................ 3 Thermal Limitations and Switch Load Characteristics ......... 14 Electrical Characteristics--3.3 V Operation ............................. 4 Output Load Characteristics..................................................... 14 Package Characteristics ............................................................... 5 Bootstrapped Half-Bridge Operation ...................................... 15 Insulation and Safety Related Specifications ............................ 5 DC Correctness and Magnetic Field Immunity .......................... 15 Regulatory Information ............................................................... 6 Power Consumption .................................................................. 17 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 7 Insulation Lifetime ..................................................................... 17 Outline Dimensions ....................................................................... 18 Recommended Operating Conditions ...................................... 8 Ordering Guide .......................................................................... 19 Absolute Maximum Ratings............................................................ 9 Automotive Products ................................................................. 19 ESD Caution .................................................................................. 9 REVISION HISTORY 11/15--Rev. A to Rev. B Changes to Power Consumption Section .................................... 17 11/14--Rev. 0 to Rev. A Changes to Features Section and General Description Section ................................................................................................ 1 Changes to Table 5 ............................................................................ 5 Changes to Regulatory Information Section, Table 6, and Table 7 ................................................................................................ 6 Changes to Table 8 and Table 9 ....................................................... 7 12/13--Revision 0: Initial Version Rev. B | Page 2 of 19 Data Sheet ADuM3224/ADuM4224 SPECIFICATIONS ELECTRICAL CHARACTERISTICS--5 V OPERATION All voltages are relative to their respective ground. 4.5 V VDD1 5.5 V, 4.5 V VDDA 18 V, 4.5 V VDDB 18 V, unless stated otherwise. All minimum/maximum specifications apply over TJ = -40C to +125C. All typical specifications are at TJ = 25C, VDD1 = 5 V, VDDA = VDDB = 12 V. Switching specifications are tested with CMOS signal levels. Table 1. Parameter DC SPECIFICATIONS Input Supply Current, Quiescent Output Supply Current, Per Channel, Quiescent Supply Current at 1 MHz VDD1 Supply Current VDDA/VDDB Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VDDA/VDDB Supply A Grade Positive Going Threshold Negative Going Threshold Hysteresis B Grade Positive Going Threshold Negative Going Threshold Hysteresis C Grade Positive Going Threshold Negative Going Threshold Hysteresis Output Short-Circuit Pulsed Current 1 Output Pulsed Source Resistance Output Pulsed Sink Resistance SWITCHING SPECIFICATIONS Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 ADuM3224A/ADuM4224A Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) Dynamic Input Supply Current Per Channel Dynamic Output Supply Current Per Channel Refresh Rate Symbol Min Typ Max Unit IDDI(Q) IDDO(Q) 1.4 2.3 2.4 3.2 mA mA IDD1(Q) IDDA(Q)/IDDB(Q) IIA, IIB VIH VIL VOAH, VOBH 1.6 5.6 +0.01 2.5 8.0 +1 mA mA A V V V IOx = -20 mA, VIx = VIxH 0.15 V IOx = +20 mA, VIx = VIxL -1 0.7 x VDD1 0.3 x VDD1 VDDA/ VDDB - 0.1 VOAL, VOBL VDDA/ VDDB 0.0 VDDAUV+, VDDBUV+ VDDAUV-, VDDBUV- VDDAUVH, VDDBUVH 4.1 3.6 0.5 4.4 3.2 V V V VDDAUV+, VDDBUV+ VDDAUV-, VDDBUV- VDDAUVH, VDDBUVH 6.9 6.2 0.7 7.4 5.7 V V V 10.5 9.6 0.9 4.0 1.1 0.6 11.1 V V V A VDDAUV+, VDDBUV+ VDDAUV-, VDDBUV- VDDAUVH, VDDBUVH IOA(SC), IOB(SC) ROA, ROB ROA, ROB PW tDHL, tDLH tDHL, tDLH tPSK tPSKCD tPSKCD tR/tF IDDI(D) IDDO(D) fr 8.9 2.0 0.3 0.3 50 1 31 35 6 43 47 1 1 12 0.05 1.65 1.2 3.0 3.0 54 59 12 5 7 18 ns MHz ns ns ns ns ns ns mA/Mbps mA/Mbps Mbps Test Conditions/Comments Up to 1 MHz, no load Up to 1 MHz, no load 0 V VIA, VIB VDD1 VDDA/VDDB = 12 V VDDA/VDDB = 12 V VDDA/VDDB = 12 V CL = 2 nF, VDDA/VDDB = 12 V CL = 2 nF, VDDA/VDDB = 12 V CL = 2 nF, VDDA/VDDB = 12 V; see Figure 20 CL = 2 nF, VDDA/VDDB = 4.5 V; see Figure 20 CL = 2 nF, VDDA/VDDB = 12 V; see Figure 20 CL = 2 nF, VDDA/VDDB = 12 V; see Figure 20 CL = 2 nF, VDDA/VDDB = 4.5 V; see Figure 20 CL = 2 nF, VDDA/VDDB = 12 V; see Figure 20 VDDA/VDDB = 12 V VDDA/VDDB = 12 V Short-circuit duration less than 1 s. Average power must conform to the limit shown in the Absolute Maximum Ratings section. The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 4 The tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. The tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay parameters. 5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels. 1 2 Rev. B | Page 3 of 19 ADuM3224/ADuM4224 Data Sheet ELECTRICAL CHARACTERISTICS--3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V VDD1 3.6 V, 4.5 V VDDA 18 V, 4.5 V VDDB 18 V, unless stated otherwise. All minimum/maximum specifications apply over TJ = -40C to +125C. All typical specifications are at TJ = 25C, VDD1 = 3.3 V, VDDA = VDDB = 12 V. Switching specifications are tested with CMOS signal levels. Table 2. Parameter DC SPECIFICATIONS Input Supply Current, Quiescent Output Supply Current, Per Channel, Quiescent Supply Current at 1 MHz VDD1 Supply Current VDDA/VDDB Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VDDA/VDDB Supply A Grade Positive Going Threshold Negative Going Threshold Hysteresis B Grade Positive Going Threshold Negative Going Threshold Hysteresis C Grade Positive Going Threshold Negative Going Threshold Hysteresis Output Short-Circuit Pulsed Current 1 Output Pulsed Source Resistance Output Pulsed Sink Resistance SWITCHING SPECIFICATIONS Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 ADuM3224A/ADuM4224A Propagation Delay Skew 5 Channel-to-Channel Matching 6 Output Rise/Fall Time (10% to 90%) Dynamic Input Supply Current Per Channel Dynamic Output Supply Current Per Channel Refresh Rate Symbol Min Typ Max Unit IDDI(Q) IDDO(Q) 0.87 2.3 1.4 3.2 mA mA IDD1(Q) IDDA(Q)/IDDB(Q) IIA, IIB VIH VIL VOAH, VOBH 1.1 5.6 +0.01 1.5 8.0 +10 mA mA A V V V Up to 1 MHz, no load Up to 1 MHz, no load 0 V VIA, VIB VDD1 0.15 V IOx = +20 mA, VIx = VIxL -10 0.7 x VDD1 0.3 x VDD1 VDDA/ VDDB - 0.1 VOAL, VOBL VDDA/ VDDB 0.0 VDDAUV+, VDDBUV+ VDDAUV-, VDDBUV- VDDAUVH, VDDBUVH 4.1 3.6 0.5 4.4 3.2 V V V VDDAUV+, VDDBUV+ VDDAUV-, VDDBUV- VDDAUVH, VDDBUVH 6.9 6.2 0.7 7.4 5.7 V V V 10.5 9.6 0.9 4.0 1.1 0.6 11.1 V V V A VDDAUV+, VDDBUV+ VDDAUV-, VDDBUV- VDDAUVH, VDDBUVH IOA(SC), IOB(SC) ROA, ROB ROA, ROB PW tDHL, tDLH tDHL, tDLH tPSK tPSKCD tPSKCD tR/tF IDDI(D) IDDO(D) fr 8.9 2.0 0.3 0.3 50 1 35 37 6 47 51 1 1 12 0.05 1.65 1.1 3.0 3.0 59 65 12 5 7 22 ns MHz ns ns ns ns ns ns mA/Mbps mA/Mbps Mbps Test Conditions/Comments IOx = -20 mA, VIx = VIxH VDDA/VDDB = 12 V VDDA/VDDB = 12 V VDDA/VDDB = 12 V CL = 2 nF, VDDA/VDDB = 12 V CL = 2 nF, VDDA/VDDB = 12 V CL = 2 nF, VDDA/VDDB = 12 V, see Figure 20 CL = 2 nF, VDDA/VDDB = 4.5 V, see Figure 20 CL = 2 nF, VDDA/VDDB = 12 V, see Figure 20 CL = 2 nF, VDDA/VDDB = 12 V, see Figure 20 CL = 2 nF, VDDA/VDDB = 4.5 V, see Figure 20 CL = 2 nF, VDDA/VDDB = 12 V, see Figure 20 VDDA/VDDB = 12 V VDDA/VDDB = 12 V Short-circuit duration less than 1 s. Average power must conform to the limit shown in the Absolute Maximum Ratings section. The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 4 The tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. The tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay parameters. 5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels. 1 2 3 Rev. B | Page 4 of 19 Data Sheet ADuM3224/ADuM4224 PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-to-Output) Capacitance (Input-to-Output) Input Capacitance IC Junction-to-Ambient Thermal Resistance ADuM3224 ADuM4224 IC Junction-to-Case Thermal Resistance ADuM3224 ADuM4224 Symbol RI-O CI-O CI Min Typ 1012 2.0 4.0 Max Unit pF pF JA JA 76 45 C/W C/W JC JC 42 29 C/W C/W Test Conditions/Comments f = 1 MHz INSULATION AND SAFETY RELATED SPECIFICATIONS ADuM3224 Specifications Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 3000 4.0 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 4.0 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >400 II mm V Unit V rms mm Test Conditions/Comments 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM4224 Specifications Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 5000 7.6 min Minimum External Tracking (Creepage) L(I02) 7.6 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >400 II mm V Rev. B | Page 5 of 19 Test Conditions/Comments 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM3224/ADuM4224 Data Sheet REGULATORY INFORMATION The ADuM3224 is approved or pending approval by the organizations listed in Table 6. Table 6. UL Recognized under UL 1577 Component Recognition Program 1 Single/Protection 3000 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice 5A VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 2 Basic insulation per CSA 60950-1-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage File 205078 Reinforced insulation, 560 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM3224 is proof tested by applying an insulation test voltage 3600 V rms for 1 second (current leakage detection limit = 6 A). In accordance with DIN V VDE V 0884-10, each ADuM3224 is proof tested by applying an insulation test voltage 1050 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. The ADuM4224 is approved or pending approval by the organizations listed in Table 7. Table 7. UL Recognized under UL 1577 Component Recognition Program 1 Single/Protection 5000 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice 5A VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 2 Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage Basic insulation per CSA 60950-1-07 and IEC 60950-1, 760 V rms (1074 V peak) maximum working voltage File 205078 Reinforced insulation, 849 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM4224 is proof tested by applying an insulation test voltage 6000 V rms for 1 second (current leakage detection limit = 10 A). In accordance with DIN V VDE V 0884-10, each ADuM4224 is proof tested by applying an insulation test voltage 1590 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. Rev. B | Page 6 of 19 Data Sheet ADuM3224/ADuM4224 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 8. ADuM3224 VDE Characteristics (Pending) Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety-Limiting Values Maximum Junction Temperature Safety Total Dissipated Power Insulation Resistance at TS Test Conditions/Comments VIORM x 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM x 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM x 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 10 kV, 1.2 s rise time, 50 s, 50% fall time Maximum value allowed in the event of a failure (see Figure 2) VIO = 500 V Symbol Characteristic Unit I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak Vpd(m) 896 672 V peak V peak VIOTM VIOSM 4242 6000 V peak V peak TS PS RS 150 1.64 >109 C W VIORM Vpd(m) Vpd(m) Table 9. ADuM4224 VDE Characteristics (Pending) Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values Maximum Junction Temperature Safety Total Dissipated Power Insulation Resistance at TS Test Conditions/Comments VIORM x 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM x 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM x 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 10 kV, 1.2 s rise time, 50 s, 50% fall time Maximum value allowed in the event of a failure (see Figure 3) VIO = 500 V Rev. B | Page 7 of 19 Symbol Characteristic Unit I to IV I to III I to II 40/105/21 2 849 1592 V peak V peak Vpd(m) 1273 1018 V peak V peak VIOTM VIOSM 7071 6000 V peak V peak TS PS RS 150 2.77 >109 C W VIORM Vpd(m) Vpd(m) 1.6 Table 10. 1.4 Parameter Operating Junction Temperature Supply Voltages 1 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 200 AMBIENT TEMPERATURE (C) 11791-102 DD1 , PV OR PV RECOMMENDED OPERATING CONDITIONS 1.2 SAFE OPERATING PV Data Sheet 1.8 DDA DDB POWER (W) ADuM3224/ADuM4224 Figure 2. ADuM3224 Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10 VDD1 Rise Time VDDA, VDDB Rise Time Maximum Input Signal Rise and Fall Times Common-Mode Transient, Static 2 Common-Mode Transient Immunity, Dynamic 3 POWER (W) DDB OR PV DDA , PV 3.0 2.5 2.0 1.5 DD1 1.0 0.5 0 50 100 150 AMBIENT TEMPERATURE (C) 200 11791-103 SAFE OPERATING PV Rating -40C to +125C VDD1 VDDA, VDDB tVDD1 tVDDA, tVDDB tVIA, tVIB 3.0 V to 5.5 V 4.5 V to 18 V 1 V/s 10 V/s 1 ms -50 kV/s to +50 kV/s -25 kV/s to +25 kV/s All voltages are relative to their respective ground. See the Applications Information section for information on immunity to external magnetic fields. 2 Static common-mode transient immunity is defined as the largest dv/dt between GND1 and GNDA/GNDB with inputs held either high or low such that the output voltage remains either above 0.8 x VDDA/VDDB for VIA/VIB = high, or 0.8 V for VIA/VIB = low. Operation with transients above the recommended levels can cause momentary data upsets. 3 Dynamic common-mode transient immunity is defined as the largest dv/dt between GND1 and GNDA/GNDB with the switching edge coincident with the transient test pulse. Operation with transients above the recommended levels can cause momentary data upsets. 1 0 Symbol TJ Figure 3. ADuM4224 Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10 Rev. B | Page 8 of 19 Data Sheet ADuM3224/ADuM4224 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 11. Parameter Storage Temperature (TST) Operating Junction Temperature (TJ) Supply Voltages1 VDD1 VDDA, VDDB Input Voltage (VIA, VIB, DISABLE)1 Output Voltage1 VOA VOB Average Output Current, per Pin (IO)2 Common-Mode Transients (CMH, CML)3 Rating -55C to +150C -40C to +150C -0.5 V to +7.0 V -0.5 V to +20 V -0.5 V to VDD1 + 0.5 V ESD CAUTION -0.5 V to VDDA + 0.5 V -0.5 V to VDDB + 0.5 V -35 mA to +35 mA -100 kV/s to +100 kV/s All voltages are relative to their respective ground. See Figure 2 and Figure 3 for information on maximum allowable current for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum rating can cause latch-up or permanent damage. 1 2 Table 12. Maximum Continuous Working Voltage 1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform DC Voltage 1 Max 565 1131 1131 Unit V peak V peak V peak Constraint 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. Table 13. ADuM3224/ADuM4224 (Positive Logic) Truth Table 1 DISABLE L VIA Input L VIB Input L VDD1 State Powered VDDA/VDDB State Powered VOA Output L VOB Output L L L H Powered Powered L H L H L Powered Powered H L L H H Powered Powered H H H X X Powered Powered L L L L L Unpowered Powered L L X X X Powered Unpowered L L 1 X = don't care, L = low, and H = high. Rev. B | Page 9 of 19 Notes Outputs return to the input state within 1 s of DISABLE = L assertion. Outputs return to the input state within 1 s of DISABLE = L assertion. Outputs return to the input state within 1 s of DISABLE = L assertion. Outputs return to the input state within 1 s of DISABLE = L assertion. Outputs take on default low state within 3 s of DISABLE = H assertion. Outputs return to the input state within 1 s of VDD1 power restoration. Outputs return to the input state within 50 s of VDDA/VDDB power restoration. ADuM3224/ADuM4224 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIB 2 VDD1 3 GND1 4 DISABLE 5 16 VDDA ADuM3224/ ADuM4224 TOP VIEW (Not to Scale) 15 VOA 14 GNDA 13 NC 12 NC NC 6 11 VDDB NC 7 10 VOB VDD1 8 9 GNDB NOTES 1. NC = NO CONNECT. NOT INTERNALLY CONNECTED. 11791-003 VIA 1 Figure 4. Pin Configuration Table 14. ADuM3224/ADuM4224 Pin Function Descriptions Pin No.1 1 2 3, 8 4 5 Mnemonic VIA VIB VDD1 GND1 DISABLE 6, 7, 12, 13 9 10 11 14 15 16 NC GNDB VOB VDDB GNDA VOA VDDA 1 Description Logic Input A. Logic Input B. Input Supply Voltage. Ground Reference for Input Logic Signals. Input Disable. Disables the isolator inputs and refresh circuits. Outputs take on the default low state within 3 s of a DISABLE = high assertion. Outputs return to the input state within 1 s of a DISABLE = low assertion. No Connect. These pins are not internally connected. Ground Reference for Output B. Output B. Output B Supply Voltage. Ground Reference for Output A. Output A. Output A Supply Voltage. Pin 3 and Pin 8 are internally connected; connecting both pins to the VDD1 supply is recommended. Rev. B | Page 10 of 19 Data Sheet ADuM3224/ADuM4224 TYPICAL PERFORMANCE CHARACTERISTICS 1000 CH2 = VOx (5V/DIV) 800 GATE CHARGE (nC) VDDA /VDDB = 5V 2 600 VDDA /VDDB = 8V 400 CH1 = VIx (5V/DIV) VDDA /VDDB = 10V 200 1 CH1 5.00V M40.0ns 2.50GSPS 100k POINTS A CH1 2.70V 11791-105 CH1 5.00V 0 400 600 800 1000 SWITCHING FREQUENCY (kHz) Figure 8. Typical ADuM4224 Maximum Load vs. Switching Frequency (RG = 1 ) Figure 5. Output Waveform for 2 nF Load with 12 V Output Supply a 200 11791-108 VDDA /VDDB = 15V 0 3.0 b -820ps b 10.5ns 11.3ns 1.40V 11.4V 10.0V a 2.5 IDD1 SUPPLY CURRENT (mA) CH2 = VOB (5V/DIV) 2 CH1 = VOA (5V/DIV) 2.0 VDD1 = 5V 1.5 VDD1 = 3.3V 1.0 0.5 0 CH2 5.00V M20.0ns 2.50GSPS 100k POINTS A CH1 2.70V 0 11791-106 CH1 5.00V 0.50 0.75 1.00 FREQUENCY (MHz) Figure 9. Typical IDD1 Supply Current vs. Frequency Figure 6. Output Matching and Rise Time Waveforms for 2 nF Load with 12 V Output Supply 50 IDDA , IDDB SUPPLY CURRENT (mA) 500 400 GATE CHARGE (nC) 0.25 11791-109 1 VDDA /VDDB = 5V 300 VDDA /VDDB = 8V 200 VDDA /VDDB = 10V 100 VDDA /VDDB = 15V VDDA /VDDB = 10V VDDA /VDDB = 5V 40 30 20 10 200 400 600 SWITCHING FREQUENCY (kHz) 800 1000 0 11791-107 0 Figure 7. Typical ADuM3224 Maximum Load vs. Switching Frequency (RG = 1 ) 0 0.25 0.50 FREQUENCY (MHz) 0.75 1.00 11791-110 VDDA /VDDB = 15V 0 Figure 10. Typical IDDA, IDDB Supply Current vs. Frequency with 2 nF Load Rev. B | Page 11 of 19 ADuM3224/ADuM4224 Data Sheet 60 30 25 tDHL 40 RISE/FALL TIME (ns) tDLH 30 20 10 FALL TIME 10 RISE TIME 20 40 60 80 100 120 140 0 Figure 11. Typical Propagation Delay vs. Junction Temperature 5 7 9 11 13 15 11791-114 0 11791-111 -20 JUNCTION TEMPERATURE (C) 17 OUTPUT SUPPLY VOLTAGE (V) Figure 14. Typical Rise/Fall Time Variation vs. Output Supply Voltage 5 PROPAGATION DELAY CHANNEL-TO-CHANNEL MATCHING (ns) 60 tDHL 40 tDLH 30 20 0 3.0 3.5 4.0 4.5 5.0 5.5 INPUT SUPPLY VOLTAGE (V) Figure 12. Typical Propagation Delay vs. Input Supply Voltage; VDDA, VDDB = 12 V 3 2 PD MATCH tDLH 1 PD MATCH tDHL 0 11791-112 10 4 5 7 9 11 13 15 11791-115 50 PROPAGATION DELAY (ns) 15 5 0 -40 17 OUTPUT SUPPLY VOLTAGE (V) Figure 15. Typical Propagation Delay (PD) Channel-to-Channel Matching vs. Output Supply Voltage 5 PROPAGATION DELAY CHANNEL-TO-CHANNEL MATCHING (ns) 60 50 tDHL 40 tDLH 30 20 10 0 5 7 9 11 13 15 17 OUTPUT SUPPLY VOLTAGE (V) Figure 13. Typical Propagation Delay vs. Output Supply Voltage, VDD1 = 5 V 4 3 2 PD MATCH tDLH 1 0 -40 11791-113 PROPAGATION DELAY (ns) 20 PD MATCH tDHL -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 11791-116 PROPAGATION DELAY (ns) 50 Figure 16. Typical Propagation Delay (PD) Channel-to-Channel Matching vs. Temperature; VDDA, VDDB = 12 V Rev. B | Page 12 of 19 Data Sheet ADuM3224/ADuM4224 8 1.4 7 VOUT SOURCE RESISTANCE ROUT () 1.0 0.8 VOUT SINK RESISTANCE 0.6 0.4 0.2 4 6 8 10 12 14 OUTPUT SUPPLY VOLTAGE (V) 16 18 Figure 17. Typical Output Resistance (ROUT) vs. Output Supply Voltage 5 4 SOURCE IOUT 3 2 1 0 11791-117 0 SINK IOUT 6 4 6 8 10 12 14 OUTPUT SUPPLY VOLTAGE (V) 16 18 11791-118 1.2 SOURCE/SINK OUTPUT CURRENT (A) 1.6 Figure 18. Typical Source/Sink Output Current vs. Output Supply Voltage Rev. B | Page 13 of 19 ADuM3224/ADuM4224 Data Sheet APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD LAYOUT VIA VDDA VIB VOA VDD1 NC NC NC NC VDDB VOB VDD1 GNDB 11791-119 DISABLE OUTPUT 10% VIH INPUT VIL tDHL tDLH tR tF Figure 20. Propagation Delay Parameters Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM3224/ADuM4224 component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM3224/ ADuM4224 components operating under the same conditions. THERMAL LIMITATIONS AND SWITCH LOAD CHARACTERISTICS GNDA GND1 90% 11791-005 The ADuM3224/ADuM4224 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins, as shown in Figure 19. Use a small ceramic capacitor with a value between 0.01 F and 0.1 F to provide a good high frequency bypass. On the output power supply pin, VDDA or VDDB, it is recommended to also add a 10 F capacitor to provide the charge required to drive the gate capacitance at the ADuM3224/ADuM4224 outputs. On the output supply pin, avoid the use of vias on the bypass capacitor, or use multiple vias to reduce the inductance in the bypassing. The total lead length between both ends of the smaller capacitor and the input or output power supply pin must not exceed 5 mm. For specific layout guidelines, refer to the AN-1109 Application Note, Recommendations for Control of Radiated Emissions with iCoupler Devices. Figure 19. Recommended PCB Layout UNDERVOLTAGE LOCKOUT For the output of a channel of the ADuM3224/ADuM4224 to be valid, both the VDD1 and the VDDA or VDDB power supplies must be above the positive going undervoltage lockout (UVLO) threshold. If, during operation, the supply voltage drops below the negative going UVLO threshold, the output is brought low to protect the switch from being underdriven. The VDD1 threshold is typically around 2.5 V. There are three options for the secondary supply thresholds, which can be selected by the different grades (see the Ordering Guide). The UVLO of each output channel acts independently of the other, but in the case of a VDD1 UVLO, both channels are brought low. For isolated gate drivers, the necessary separation between the input and output circuits prevents the use of a single thermal pad beneath the device, and heat is, therefore, dissipated mainly through the package pins. Package thermal dissipation limits the performance of output load vs. switching frequency, as illustrated in Figure 7 and Figure 8 for the maximum load capacitance that can be driven with a 1 series gate resistance for different values of output voltage. For example, Figure 7 shows that a typical ADuM3224 can drive a large MOSFET with 140 nC gate charge at 8 V output (which is equivalent to a 17 nF load) up to a frequency of about 300 kHz. Do not allow the internal junction temperature of the ADuM3224/ADuM4224 to exceed the maximum junction temperature of 150C. Operation above this value causes damage to the device. There is no internal thermal shutdown to protect the ADuM3224/ADuM4224. If a thermal shutdown is desired, see the ADuM3223/ADuM4223 data sheet. PROPAGATION DELAY-RELATED PARAMETERS OUTPUT LOAD CHARACTERISTICS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output. The ADuM3224/ADuM4224 specify tDLH (see Figure 20) as the time between the rising input high logic threshold, VIH, to the output rising 10% threshold. Likewise, the falling propagation delay, tDHL, is defined as the time between the input falling logic low threshold, VIL, and the output falling 90% threshold. The rise and fall times are dependent on the loading conditions and are not included in the propagation delay, which is the industry standard for gate drivers. The ADuM3224/ADuM4224 output signals depend on the characteristics of the output load, which is typically an N-channel MOSFET. The driver output response to an N-channel MOSFET load can be modeled with a switch output resistance (RSW), an inductance due to the printed circuit board trace (LTRACE), a series gate resistor (RGATE), and a gate-to-source capacitance (CGS), as shown in Figure 21. Rev. B | Page 14 of 19 Data Sheet ADuM3224/ ADuM4224 VOA RSW RGATE LTRACE VO CGS 11791-006 VIA ADuM3224/ADuM4224 Figure 21. RLC Model of the Gate of an N-Channel MOSFET RSW is the switch resistance of the internal ADuM3224/ ADuM4224 driver output, which is about 1.1 . RGATE is the intrinsic gate resistance of the MOSFET and any external series resistance. A MOSFET that requires a 4 A gate driver has a typical intrinsic gate resistance of about 1 and a gate-to-source capacitance, CGS, of between 2 nF and 10 nF. LTRACE is the inductance of the printed circuit board trace, typically a value of 5 nH or less for a well designed layout with a very short and wide connection from the ADuM3224/ADuM4224 output to the gate of the MOSFET. The following equation defines the Q factor of the resistor/inductor/capacitor (RLC) circuit, which indicates how the ADuM3224/ADuM4224 output responds to a step change. For a well damped output, Q is less than 1. Adding a series gate resistance dampens the output response. Q L 1 TRACE (R SW RGATE ) C GS In Figure 5, the ADuM3224/ADuM4224 output waveforms for a 12 V output are shown for a CGS of 2 nF. Note the small amount of ringing of the output in Figure 5 with a CGS of 2 nF, RSW of 1.1 , RGATE of 0 , and a calculated Q factor of 0.75, where less than 1 is desired for good damping. Output ringing can be reduced by adding a series gate resistance to dampen the response. For applications of less than 1 nF load, it is recommended to add a series gate resistor of about 2 to 5 . BOOTSTRAPPED HALF-BRIDGE OPERATION The ADuM3224/ADuM4224 are well suited to the operation of two output gate signals that are referenced to separate grounds, as in the case of a half-bridge configuration. Because isolated auxiliary supplies are often expensive, it is beneficial to reduce the amount of supplies. One method to perform this is to use a bootstrap configuration for the high-side supply of the ADuM3224/ADuM4224. In this topology, the decoupling capacitor, CA, acts as the energy storage for the high-side supply, and is filled whenever the low-side switch is closed, bringing GNDA to GNDB. During the charging time of CA, the dv/dt of the VDDA voltage must be controlled to reduce the possibility of glitches on the output. Keeping the dv/dt below 10 V/s is recommended for the ADuM3224/ADuM4224. This can be controlled by introducing a series resistance, RBOOT, into the charging path of CA. As an example, if VAUX is 12 V, CA has a total capacitance of 10 F, and the forward voltage drop of the bootstrap diode is 1 V. VBOOT VAUX VDBOOT 12 V 1 V 0.11 dv 10 F 10 V/ s CA dtMAX DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than 1 s at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 3 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit. In addition, the outputs are in a low default state while the power is coming up before the UVLO threshold is crossed. The ADuM3224/ADuM4224 are immune to external magnetic fields. The limitation on the ADuM3224/ADuM4224 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM3224/ADuM4224 is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt) rn2, n = 1, 2, ..., N where: is the magnetic flux density (gauss). rn is the radius of the nth turn in the receiving coil (cm). N is the number of turns in the receiving coil. Rev. B | Page 15 of 19 ADuM3224/ADuM4224 Data Sheet VIA VIB VPRIM VPRIM VDD1 CDD1 1 GND1 DISABLE NC VPRIM NC VDD1 ADuM3224/ ADuM4224 1 ENCODE 2 16 DECODE 15 3 14 4 13 5 12 6 11 ENCODE 7 DECODE 10 9 8 VDDA RBOOT VOA REXT_A VDBOOT VBUS DBOOT CA GNDA NC NC VDDB VAUX REXT_B VOB CB GNDB 1GND IS CONNECTED TO THE PRIMARY SIDE GROUND, ISOLATED FROM THE SECONDARY GROUND. 1 2GND IS CONNECTED TO THE SECONDARY SIDE GROUND, ISOLATED FROM THE PRIMARY GROUND. B 11791-222 2 NC = NO CONNECT Figure 22. Circuit of Bootstrapped Half-Bridge Operation Given the geometry of the receiving coil in the ADuM3224/ ADuM4224 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 23. 10 1 1k 0.001 1k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) 11791-122 0.01 Figure 23. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.08 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and had the worst-case polarity), the received pulse is reduced from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. Rev. B | Page 16 of 19 DISTANCE = 1m 100 10 1 DISTANCE = 100mm DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) Figure 24. Maximum Allowable Current for Various Current-to-ADuM3224/ADuM4224 Spacings 100M 11791-123 0.1 MAXIMUM ALLOWABLE CURRENT (kA) MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM3224/ADuM4224 transformers. Figure 24 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 24, the ADuM3224/ ADuM4224 are immune and only can be affected by extremely large currents operated at a high frequency and very close to the component. For the 1 MHz example, a 0.2 kA current must be placed 5 mm from the ADuM3224/ADuM4224 to affect the operation of the component. Data Sheet ADuM3224/ADuM4224 POWER CONSUMPTION INSULATION LIFETIME The supply current at a given channel of the ADuM3224/ ADuM4224 isolator is a function of the supply voltage, channel data rate, and channel output load. All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM3224/ADuM4224. Alternately, use the gate charge to obtain a more precise value for PDISS. PDISS = QGATE x VDDx x fS where: QGATE is the gate charge for the MOSFET. fS is the switching frequency. This power dissipation is shared between the internal on resistances of the internal gate driver switches and the external gate resistances, RGON and RGOFF. The ratio of the internal gate resistances to the total series resistance allows the calculation of losses seen within the ADuM3224/ADuM4224 chips per channel. PDISS_IC = PDISS x 1/2 x (RDSON_P/(REXT_X + RDSON_P) + RDSON_N/(REXT_X + RDSON_N)) Taking the power dissipation found inside the chip and multiplying it by JA gives the rise above ambient temperature that the ADuM3224/ADuM4224 experiences, multiplied by two to reflect that there are two channels. TJ = JA x 2 x PDISS_IC + TAMB For the device to remain within specification, TJ must not exceed 125C. If TJ exceeds 150C (typical), the device enters TSD. The values shown in Table 12 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM3224/ADuM4224 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 25, Figure 26, and Figure 27 illustrate these different isolation voltage waveforms. A bipolar ac voltage environment is the worst case for the iCoupler products and is the 50-year operating lifetime that Analog Devices recommends for maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. Treat any cross insulation voltage waveform that does not conform to Figure 26 or Figure 27 as a bipolar ac waveform, and limit its peak voltage to the 50-year lifetime voltage value listed in Table 12. Note that the voltage presented in Figure 26 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. Quiescent power dissipation may also be added to give a more accurate number for temperature rise, but the switching power losses are often the largest source of power dissipation, and quiescent losses can often be ignored. To calculate the total supply current, the quiescent supply currents for each input and output channel corresponding to IDD1(Q), IDDA(Q), and IDDB(Q) are added. The full equation for the TJ becomes TJ = JA x (2 x PDISS_IC + VDD1 x IDD1(Q) + VDDA x IDDA(Q) + VDDB x IDDB(Q)) + TAMB RATED PEAK VOLTAGE 11791-009 PDISS = CEST x (VDDx) x fS where: CEST = CISS x 5. fS is the switching frequency. 2 Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. 0V Figure 25. Bipolar AC Waveform RATED PEAK VOLTAGE 11791-010 During the driving of a MOSFET gate, the driver must dissipate power. This power is not insignificant and can lead to thermal shutdown (TSD) if considerations are not made. The gate of a MOSFET can be simulated approximately as a capacitive load. Due to Miller capacitance and other nonlinearities, it is common practice to take the stated input capacitance, CISS, of a given MOSFET and multiply it by a factor of 5 to arrive at a conservative estimate to approximate the load being driven. With this value, the estimated total power dissipation per channel due to switching action is given by 0V Figure 26. Unipolar AC Waveform Figure 9 provides total input IDD1 supply current as a function of data rate for both input channels. Figure 10 provides total IDDA or IDDB supply current as a function of data rate for both outputs loaded with 2 nF capacitance. Rev. B | Page 17 of 19 11791-011 RATED PEAK VOLTAGE 0V Figure 27. DC Waveform ADuM3224/ADuM4224 Data Sheet OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 9 16 4.00 (0.1575) 3.80 (0.1496) 1 8 1.27 (0.0500) BSC 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 6.20 (0.2441) 5.80 (0.2283) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AC 060606-A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8 0 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 29. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. B | Page 18 of 19 1.27 (0.0500) 0.40 (0.0157) 03-27-2007-B 1 Data Sheet ADuM3224/ADuM4224 ORDERING GUIDE Model1, 2 ADuM3224WARZ ADuM3224WARZ-RL7 ADuM3224WBRZ ADuM3224WBRZ-RL7 ADuM3224WCRZ ADuM3224WCRZ-RL7 ADuM4224WARWZ ADuM4224WARWZ-RL ADuM4224WBRWZ ADuM4224WBRWZ-RL ADuM4224WCRWZ ADuM4224WCRWZ-RL 1 2 No. of Channels 2 2 2 2 2 2 2 2 2 2 2 2 Output Peak Current (A) 4 4 4 4 4 4 4 4 4 4 4 4 Minimum Output Voltage (V) 4.5 4.5 7.5 7.5 11.5 11.5 4.5 4.5 7.5 7.5 11.5 11.5 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead SOIC_N 16-Lead SOIC_N, 7" Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 7" Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 7" Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13" Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13" Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13" Tape and Reel Package Option R-16 R-16 R-16 R-16 R-16 R-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 Ordering Quantity 1,000 1,000 1,000 1,000 1,000 1,000 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADuM3224W and ADuM4224W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. (c)2013-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11791-0-11/15(B) Rev. B | Page 19 of 19 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADUM3224WARZ ADUM4224WARWZ ADUM3224WBRZ ADUM4224WCRWZ ADUM4224WCRWZ-RL ADUM4224WBRWZ-RL ADUM3224WCRZ ADUM4224WBRWZ ADUM3224WCRZ-RL7 ADUM3224WARZ-RL7 ADUM3224WBRZ-RL7 ADUM4224WARWZ-RL