HCPL-7825 - Agilent / Hewlett-Packard

1-233

5965-3591E

High CMR Analog Isolation

Amplifiers

Technical Data

Features

• Fast Propagation Delays for

Over-Current and Fault

Detection Sensing

• High Common Mode

Rejection (CMR): 30 kV/µs at

VCM = 1000 V*

• 3% Gain Tolerance:

HCPL-7820

5% Gain Tolerance:

HCPL-7825

• 0.05% Nonlinearity

• Low Offset Voltage and Off-

set Drift vs. Temperature

• 200 kHz Bandwidth

• Performance Specified for

Common Motor Control

Applications over -40°C to

100°C Temperature Range

• Worldwide Safety and

Regulatory Approval: UL

1577 (3750 V rms/1 Min),

VDE 0884 and CSA

• Compact Auto-Insertable

Standard 8-Pin DIP Package

• Advanced Sigma-Delta (Σ∆)

A/D Converter Technology

• 1 µm CMOS IC Technology

Applications

• Motor Phase and Rail

Current Sensing

• General Purpose Current

Sensing and Monitoring

• High-Voltage Monitoring

• Switched Mode Power

Supply Signal Isolation

• General Purpose Analog

Signal Isolation

• Transducer Isolation

Description

The HCPL-7820/7825 high CMR

isolation amplifier consists of a

sigma-delta analog-to-digital

converter optically coupled to an

integrated output digital-to-analog

converter. When used with a

shunt resistor in the current path,

the HCPL-7820/7825 provides a

cost-effective, auto-insertion

compatible current sense solution.

Fast propagation delays allow this

part to be used in either motor

drive or inverter applications for

either phase current monitoring

or rail current fault detection

applications. High isolation mode

*The terms common-mode rejection (CMR) and isolation-mode rejection (IMR) are used interchangeably throughout this data sheet.

A 0.1

F bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8.

rejection makes this product

suitable for noisy electrical

environments, such as those

generated by the high switching

rates of power IGBTs. Low offset

voltage together with low offset

change vs. temperature permits

accurate use of auto-calibration

techniques. Tight gain tolerance

with good nonlinearity further

provide the characteristics needed

to insure highly accurate motor

speed control. A high operating

temperature range with specified

performance parameters allow

HCPL-7820

HCPL-7825

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to

prevent damage and/or degradation which may be induced by ESD.

Functional Diagram

DD1

IN+

IN–

GND1

DD2

OUT+

OUT–

GND2

–

CMR SHIELD

1-234

this device to be used in hostile

industrial environments. This

performance is delivered in an

auto-insertable, industry standard

Ordering Information

HCPL-782x

0 = ± 3% Gain Tolerance

5 = ± 5% Gain Tolerance

Option yyy

300 = Gull Wing Surface Mount Lead Option

500 = Tape/Reel Package Option (1 k min.)

Option datasheets available. Contact your Hewlett-Packard sales representative or authorized distributor for

information.

Package Outline Drawings

Standard DIP Package

9.40 (0.370)

9.90 (0.390)

PIN ONE

1.78 (0.070) MAX.

1.19 (0.047) MAX.

HP 7820

YYWW

DATE CODE

0.76 (0.030)

1.24 (0.049) 2.28 (0.090)

2.80 (0.110)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

6.10 (0.240)

6.60 (0.260)

0.20 (0.008)

0.33 (0.013)

5° TYP.

7.36 (0.290)

7.88 (0.310)

DIMENSIONS IN MILLIMETERS AND (INCHES).

5678

4321

GND1

DD1

IN+

IN–

GND2

DD2

OUT+

OUT–

PIN DIAGRAM

PIN ONE

TYPE NUMBER

8-pin DIP package that meets

major worldwide regulatory and

safety approval ratings to help

ensure that your equipment can

be certified in many geographic

areas.

1-235

Gull Wing Surface Mount Option 300*

0.635 ± 0.25

(0.025 ± 0.010) 12° NOM.

0.20 (0.008)

0.33 (0.013)

9.65 ± 0.25

(0.380 ± 0.010)

0.51 ± 0.130

(0.020 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

9.65 ± 0.25

(0.380 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.02 (0.040)

1.19 (0.047)

1.19 (0.047)

1.78 (0.070)

9.65 ± 0.25

(0.380 ± 0.010)

4.83

(0.190)



TYP.

0.380 (0.015)

0.635 (0.025)

PIN LOCATION (FOR REFERENCE ONLY)

1.080 ± 0.320

(0.043 ± 0.013)

4.19

(0.165)MAX.

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.540

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES (UNLESS OTHERWISE SPECIFIED):



xx.xx = 0.01

xx.xxx = 0.005



HP 7820



YYWW

MOLDED

LEAD COPLANARITY 

MAXIMUM: 0.102 (0.004)

*Refer to Option 300 Data Sheet for more information.

Maximum Solder Reflow Thermal Profile

240

∆T = 115°C, 0.3°C/SEC

∆T = 100°C, 1.5°C/SEC

∆T = 145°C, 1°C/SEC

TIME – MINUTES

TEMPERATURE – °C

220

200

180

160

140

120

100

260

123456789101112

(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)

1-236

Regulatory Information

The HCPL-7820/7825 has been

approved by the following

organizations:

Recognized under UL 1577,

Component Recognition Program,

FILE E55361.

CSA

Approved under CSA Component

Acceptance Notice #5, File CA

88324.

VDE 0884 (06.92) Insulation Characteristics

Description Symbol Characteristic Unit

Installation classification per DIN VDE 0110, Table 1

for rated mains voltage ≤ 300 V rms I-IV

for rated mains voltage ≤ 600 V rms I-III

Climatic Classification 40/100/21

Pollution Degree (DIN VDE 0110, Table 1)* 2

Maximum Working Insulation Voltage VIORM 848 V peak

Input to Output Test Voltage, Method b** VPR 1591 V peak

VPR = 1.875 x VIORM, Production test with tp = 1 sec,

Partial discharge < 5 pC

Input to Output Test Voltage, Method a** VPR 1273 V peak

VPR = 1.5 x VIORM, Type and sample test with tp = 60 sec,

Partial discharge < 5 pC

Highest Allowable Overvoltage** VTR 6000 V peak

(Transient Overvoltage tTR = 10 sec)

Safety-limiting values (Maximum values allowed in the event

of a failure, also see Figure 22)

Case Temperature TS175 °C

Input Power PS,Input 80 mW

Output Power PS,Output 250 mW

Insulation Resistance at TS, VIO = 500 V RS≥1x1012 Ω

*This part may also be used in Pollution Degree 3 environments where the rated mains voltage is ≤ 300 V rms (per DIN VDE 0110).

**Refer to the front of the optocoupler section of the current catalog for a more detailed description of VDE 0884 and other product

safety requirements.

Note: Optocouplers providing safe electrical separation per VDE 0884 do so only within the safety-limiting values to which they are

qualified. Protective cut-out switches must be used to ensure that the safety limits are not exceeded.

Insulation and Safety Related Specifications

Parameter Symbol Value Units Conditions

Min. External Air Gap L(IO1) 7.4 mm Measured from input terminals to output

(External Clearance) terminals, shortest distance through air

Min. External Tracking Path L(IO2) 8.0 mm Measured from input terminals to output

(External Creepage) terminals, shortest distance path along body

Min. Internal Plastic Gap 0.5 mm Through insulation distance, conductor to

(Internal Clearance) conductor, usually the direct distance

between the photoemitter and

photodetector inside the optocoupler

cavity

Tracking Resistance CTI 175 V DIN IEC 112/VDE 0303 Part 1

(Comparative Tracking

Index)

Isolation Group III a Material Group (DIN VDE 0110, 1/89,

Table 1)

Option 300 – surface mount classification is Class A in accordance with CECC 00802.

VDE

Approved according to VDE

0884/06.92.

1-237

Absolute Maximum Ratings

Parameter Symbol Min. Max. Unit Note

Storage Temperature TS-55 125 °C

Ambient Operating Temperature TA- 40 100 °C

Supply Voltages VDD1, VDD2 0.0 5.5 V

Steady-State Input Voltage VIN+, VIN- -2.0 VDD1 +0.5 V

Two Second Transient Input Voltage -6.0

Output Voltages VOUT+, VOUT- -0.5 VDD2 +0.5 V

Lead Solder Temperature TLS 260 °C1

(1.6 mm below seating plane, 10 sec.)

Reflow Temperature Profile See Package Outline Drawings Section

Recommended Operating Conditions

Parameter Symbol Min. Max. Unit Note

Ambient Operating Temperature TA-40 100 °C

Supply Voltages VDD1, VDD2 4.5 5.5 V

Input Voltage VIN+, VIN- -200 200 mV 2

1-238

DC Electrical Specifications

All specifications are at the nominal (typical) operating conditions of VIN+ = 0 V, VIN- = 0 V, TA = 25°C,

VDD1 = 5 V and VDD2 = 5 V, unless otherwise noted.

Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note

Input Offset Voltage VOS -0.8 0.45 1.7 mV 1 3

-2.0 0.45 2.9 -40°C ≤ TA ≤ 100°C 1,2,3

4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V

Absolute Value of Input |∆VOS/∆T| 7.8 µV/ °C 1,2 3,4

Offset Change vs.

Temperature

Gain: HCPL-7820 G 7.76 8.00 8.24 V/V -200 mV ≤ VIN+ ≤ 200 mV 5

7.60 8.00 8.40 -200 mV ≤ VIN+ ≤ 200 mV 5,6,7

-40°C ≤ TA ≤ 100°C

4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V

Gain: HCPL-7825 G 7.60 8.00 8.40 V/V -200 mV ≤ VIN+ ≤ 200 mV 5

7.44 8.00 8.56 -200 mV ≤ VIN+ ≤ 200 mV 5,6,7

-40°C ≤ TA ≤ 100°C

4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V

200 mV Nonlinearity NL200 0.06 0.15 % -200 mV ≤ VIN+ ≤ 200 mV 5,8 5

0.3 -200 mV ≤ VIN+ ≤ 200 mV 5,8,

-40°C ≤ TA ≤ 100°C9,10,

4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V 12

100 mV Nonlinearity NL100 0.03 0.08 -100 mV ≤ VIN+ ≤ 100 mV 5,8

0.1 -100 mV ≤ VIN+ ≤ 100 mV 5,8,

-40°C ≤ TA ≤ 100°C9,11,

4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V 12

Maximum Input Voltage |VIN+| 320 mV 4

Before Output Clipping

Average Input Bias IIN -1 µA136

Current

Average Input Resistance RIN 280 kΩ

Input DC Common-Mode CMRRIN 52 dB

Rejection Ratio

Output Resistance RO1.2 Ω

Output Low Voltage VOL 1.30 V VIN+ = 400 mV 4 7

Output High Voltage VOH 3.90 V VIN+ = -400 mV

Output Common- VOCM 2.30 2.60 2.90 V

Mode Voltage

Input Supply Current IDD1 11.1 17.0 mA 14

Output Supply Current IDD2 10.0 14.0 mA 15

Output Short-Circuit |IOSC|12mAV

OUT = 0 V or VDD2 8

Current

-400 mV < VIN+ < 400 mV

-40°C ≤ TA ≤ 100°C

4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V

max

1-239

AC Electrical Specifications

All specifications and figures are at the nominal (typical) operating conditions of VIN+ = 0 V, VIN- = 0 V,

TA = 25°C, VDD1 = 5 V and VDD2 = 5 V, unless otherwise noted.

Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note

Isolation Mode Rejection IMR 20 30 kV/µsV

IM = 1 kV 16 9

-40°C < TA ≤ 100°C

4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V

Isolation Mode Rejection IMRR >140 dB 10

Ratio at 60 Hz

Propagation Delay to 50% tPD50 1.20 1.85 2.85 µsV

IN+ = 0 to 100 mV step 17,18

Propagation Delay to 90% tPD90 1.60 2.75 4.10

Rise/Fall Time (10-90%) tR/F 0.85 1.50 2.25

Small-Signal Bandwidth f-3dB 150 200 380 kHz -40°C ≤ TA ≤ 100°C 17,19,

(-3 dB) 4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V 20

Small-Signal Bandwidth f-45°85

(-45°)

RMS Input-Referred Noise VN1.4 mV rms In recommended 21,24 11

application circuit

Power Supply Rejection PSR 150 mV p-p 12

Package Characteristics

All specifications and figures are at the nominal (typical) operating conditions of VIN+ = 0 V, VIN- = 0 V,

TA = 25°C, VDD1 = 5 V and VDD2 = 5 V, unless otherwise noted.

Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note

Input-Output Momentary VISO 3750 V rms t = 1 min., RH ≤ 50% 13,14

Withstand Voltage*

Input-Output RI-O 1012 1013 ΩTA = 25°C V

I-O = 500 Vdc 13

1011 TA = 100°C

Input-Output CI-O 0.7 pF f = 1 MHz

Capacitance

Input IC Junction-to- θjci 96 °C/W Thermocouple located at

Case Thermal center underside of

Resistance package

Output IC Junction-to- θjco 114 °C/W

Case Thermal

Resistance

*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output

continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your

equipment level safety specification, or HP Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”

-40°C ≤ TA ≤ 100°C

4.5 V ≤ (VDD1, VDD2) ≤ 5.5 V

Resistance

1-240

Notes:

1. HP recommends the use of non-

chlorine activated fluxes.

2. If VIN- is brought above V

DD1-2 V with

respect to GND1 an internal test mode

may be activated. This test mode is not

intended for customer use.

3. Exact offset value is dependent on

layout of external bypass capacitors.

The offset value in the data sheet

corresponds to HP’s recommended

layout (see Figures 26 and 27).

4. Data sheet value is the average

magnitude of the difference in offset

voltage from TA = 25°C to TA = 100°C,

expressed in microvolts per °C.

5. Nonlinearity is defined as half of the

peak-to-peak deviation from the best-

fit gain line, expressed as a percentage

of the full-scale differential output

voltage.

6. Because of the switched-capacitor

nature of the input sigma-delta A/D

converter, time-averaged values are

shown.

7. When the differential input signal

exceeds approximately 320 mV, the

outputs will limit at the typical values

shown.

8. Short-circuit current is the amount of

output current generated when either

output is shorted to VDD2 or ground.

9. IMR (also known as CMR or Common

Mode Rejection) specifies the mini-

mum rate of rise of an isolation mode

noise signal at which small output

perturbations begin to appear. These

output perturbations can occur with

both the rising and falling edges of the

isolation mode waveform and may be

of either polarity. A CMR failure is

defined as a perturbation exceeding

200 mV at the output of the recom-

mended application circuit (Figure

24). See applications section for more

information on CMR.

10. IMRR is defined as the ratio of

differential signal gain (signal applied

differentially between pins 2 and 3) to

the isolation mode gain (input pins

tied to pin 4 and the signal applied

between the input and the output of

the isolation amplifier) at 60 Hz,

expressed in dB.

11. Output noise comes from two primary

sources: chopper noise and sigma-

delta quantization noise. Chopper

noise results from chopper stabiliza-

tion of the output op-amps. It occurs at

a specific frequency (typically

500 kHz) and is not attenuated by the

on-chip output filter. The on-chip filter

does eliminate most, but not all, of the

sigma-delta quantization noise. An

external filter circuit may be easily

added to the external post-amplifier to

reduce the total RMS output noise. See

applications section for more

information.

12. Data sheet value is the amplitude of

the transient at the differential output

of the HCPL-7820/7825 when a 1 V

p-p,

1 MHz square wave with 200 ns rise

and fall times (measured at pins 1 and

8) is applied to both VDD1 and VDD2.

13. This is a two-terminal measurement:

pins 1-4 are shorted together and pins

5-8 are shorted together.

14. In accordance with UL 1577, for

devices with minimum VISO specified at

3750 V rms, each optocoupler is

proof-tested by applying an insulation

test voltage greater than 4500 V rms

for one second (leakage current

detection limit II-O < 5 µA). This test is

performed before the method b, 100%

production test for partial discharge

shown in the VDE 0884 Insulation

Characteristics Table.

1-241

Figure 3. Input Offset Change vs. VDD1

and VDD2.Figure 4. Output Voltages vs. Input

Voltage.

∆V

– INPUT OFFSET CHANGE – mV

– SUPPLY VOLTAGE – V

0.2

0.1

-0.1

4.6

0.5

4.8 5.0 5.2

= 25°C

-0.2

0.3

vs. V

DD1

DD2

= 5 V)

0.4

4.4 5.65.4

vs. V

DD2

DD1

= 5 V)

– OUTPUT VOLTAGE – V

– INPUT VOLTAGE – V

2.5

2.0

1.5

-0.4

4.0

-0.2 0 0.2

DD1

= 5 V

DD2

= 5 V

= 25°C

1.0

3.0

3.5

-0.6 0.60.4

POSITIVE

OUTPUT

NEGATIVE

OUTPUT

Figure 5. Gain and Nonlinearity Test Circuit.

Figure 1. Input Offset Voltage Test Circuit. Figure 2. Input Offset Change vs.

Temperature.

∆V

– INPUT OFFSET CHANGE – mV

– TEMPERATURE – °C

0.3

0.2

-20

0.6

20 60

DD1

= 5 V

DD2

= 5 V

-0.1

0.4

0.5

-40 100

0.1

04080

0.1 µF

DD2

OUT

3HCPL-7820/7825

0.1 µF

10 K

DD1

+15 V

0.1 µF

-15 V

–AD624CD

GAIN = 100

0.47

µF 0.47

µF

0.1 µF

DD2

3HCPL-7820/7825

0.01 µF

10 K

+15 V

0.1 µF

-15 V

–AD624CD

GAIN = 4

0.47

µF 0.47

µF

DD1

13.2

404

OUT

+15 V

0.1 µF

-15 V

–AD624CD

GAIN = 10

10 K

0.47

µF

0.1 µF

1-242

Figure 12. Nonlinearity vs. Full-Scale

Value. Figure 13. Input Current vs. Input

Voltage.

Figure 14. Input Supply Current vs.

Input Voltage.

– INPUT CURRENT – mA

IN+

– INPUT VOLTAGE – V

-4

-6

-8

-4

-2 0 2

DD1

= 5 V

DD2

= 5 V

IN–

= 0 V

= 25°C

-10

-2

-6 64

DD1

– INPUT SUPPLY CURRENT – mA

IN+

– INPUT VOLTAGE – V

-0.2 0

DD1

= 5 V

DD2

= 5 V

IN–

= 0 V

= 100°C

-0.4 0.40.2

= -40°C

= 25°C

Figure 6. Gain Change vs.

Temperature. Figure 7. Gain Change vs. VDD1 and

VDD2.Figure 8. Nonlinearity Error Plot vs.

Input Voltage.

∆G

– GAIN CHANGE – %

– TEMPERATURE – °C

0.2

0.1

-0.2

-20

0.5

20 60

DD1

= 5 V

DD2

= 5 V

-0.3

0.3

0.4

-40 100

04080

-0.1

∆G – GAIN CHANGE – %

– SUPPLY VOLTAGE – V

-0.1

-0.4

4.6

0.3

4.8 5.0 5.2

= 25°C

-0.5

0.1

vs. V

DD1

DD2

= 5 V)

0.2

4.4 5.65.4

vs. V

DD2

DD1

= 5 V)

-0.2

-0.3

Figure 9. Nonlinearity vs.

Temperature. Figure 10. 200 mV Nonlinearity vs.

VDD1 and VDD2.Figure 11. 100 mV Nonlinearity vs.

VDD1 and VDD2.

ERROR – % OF FULL SCALE

IN+

– INPUT VOLTAGE – V

-0.02

-0.06

-0.08

-0.1

0.04

0 0.1

-0.10

200 mV ERROR

0.02

-0.2 0.2

100 mV ERROR

DD1

= 5 V

DD2

= 5 V

IN–

= 0 V

= 25°C

-0.04

NL – NONLINEARITY – %

– TEMPERATURE – °C

0.08

0.04

0.16

20 60

0.12

200 mV NL

-40 100

100 mV NL

DD1

= 5 V

DD2

= 5 V

IN–

= 0 V

-20 40 80

0.02

0.06

0.10

0.14

NL – NONLINEARITY – %

– SUPPLY VOLTAGE – V

0.034

0.026

4.6

0.040

4.8 5.0 5.2

= 25°C

0.024

vs. V

DD1

DD2

= 5 V)

0.036

4.4 5.65.4

vs. V

DD2

DD1

= 5 V)

0.030

0.028

0.032

0.038

NL – NONLINEARITY – %

VDD – SUPPLY VOLTAGE – V

0.070

0.065

0.055

4.6

0.080

4.8 5.0 5.2

TA = 25°C

0.050

vs. VDD1 (VDD2 = 5 V)

0.075

4.4 5.65.4

vs. VDD2 (VDD1 = 5 V)

0.060

NL – NONLINEARITY – %

FS – FULL-SCALE VALUE – V

0.10

±0.05

0.50

±0.10 ±0.15 ±0.20

DD1

= 5 V

DD2

= 5 V

0.01

= 100°C

0 ±0.30±0.25

= -40°C

0.05

= 25°C

1-243

Figure 19. Amplitude Response vs.

Frequency. Figure 20. 3 dB Bandwidth vs.

Temperature.

Figure 21. RMS Input-Referred Noise

vs. Recommended Application Circuit

Bandwidth.

RELATIVE AMPLITUDE – dB

f – FREQUENCY – kHz

-41 50010

-2

-1

-3

50 100

DD1

= 5 V

DD2

= 5 V

= 25 °C

f (-3 dB) – 3 dB BANDWIDTH – kHz

– TEMPERATURE – °C

260

-20 0

190

-40 10020

230

250

210

40 60 80

240

220

200

DD1

= 5 V

DD2

= 5 V

Figure 16. Isolation Mode Rejection Test Circuit.Figure 15. Output Supply Current vs.

Input Voltage.

DD2

– OUTPUT SUPPLY CURRENT – mA



IN+

– INPUT VOLTAGE – V

-0.2 0

DD1

= 5 V

DD2

= 5 V

IN–

= 0 V

= 100°C

-0.4 0.40.2

= -40°C

= 25°C

Figure 17. Propagation Delay, Rise/Fall Time and Bandwidth Test Circuit. Figure 18. Propagation Delays and

Rise/Fall Time vs. Temperature.

t – TIME – µs

– TEMPERATURE – °C

3.0

-20 0

1.0

DELAY TO 90%

-40 10020

RISE/FALL TIME

2.0

DELAY TO 50%

2.5

1.5

40 60 80

IN–

= 0 V

IN+

= 0 TO 100 mV STEP

DD1

= 5 V

DD2

= 5 V

0.1 µF

VDD2

VOUT

3HCPL-7820/7825

2 K

78L05 +15 V

0.1 µF

-15 V

–

+MC34081

75

IN OUT

0.1

µF 0.1

µF

9 V

PULSE GEN.

+–

10 K

75 pF

0.1 µF

DD2

OUT

3HCPL-7820/7825

2 K

+15 V

0.1 µF

-15 V

–

+MC34081

0.1 µF

10 K

0.01 µF

DD1

– RMS INPUT-REFERRED NOISE – mV

f – FREQUENCY – kHz

3.0

IN+

= 200 mV

5 100050

IN+

= 0 mV

1.5

IN+

= 100 mV

2.5

0.5

100 500

DD1

= 5 V

DD2

= 5 V

IN–

= 0 V

= 25 °C

2.0

1.0

1-244

signal, which is filtered to obtain

the final output signal.

Application Circuit

The recommended application

circuit is shown in Figure 24. A

floating power supply (which in

many applications could be the

same supply that is used to drive

the high-side power transistor) is

regulated to 5 V using a simple

three-terminal voltage regulator

(U1). The voltage from the cur-

rent sensing resistor, or shunt

(RSENSE), is applied to the input of

Applications Information

Functional Description

Figure 23 shows the primary

functional blocks of the HCPL-

7820/7825. In operation, the

sigma-delta modulator converts

the analog input signal into a

high-speed serial bit stream. The

time average of this bit stream is

directly proportional to the input

signal. This stream of digital data

is encoded and optically trans-

mitted to the detector circuit. The

detected signal is decoded and

converted back into an analog

Figure 22. Dependence of Safety-

Limiting Values on Temperature.

VOLTAGE

REGULATOR CLOCK

GENERATOR

Σ∆

MODULATOR ENCODER LED DRIVE

CIRCUIT DETECTOR

CIRCUIT DECODER

AND D/A FILTER ISO-AMP

OUTPUT

VOLTAGE

REGULATOR

ISO-AMP

INPUT

ISOLATION

BOUNDARY

Figure 24. Recommended Application Circuit.

Figure 23. HCPL-7820/7825 Block Diagram.

0.1 µF

+5 V

OUT

3U2

R1



2.00 KΩ

+15 V C8

0.1 µF



0.1 µF



-15 V

–

+MC34081

R3



10.0 KΩ

HCPL-7820/7825

R4

10.0 KΩ

C6

75 pF

U1

78L05

IN OUT

C1

C2



0.01

µF

R5



39 Ω

FLOATING

SUPPLY

GATE DRIVE

CIRCUIT

FLOATING

SUPPLY

• • •

HV+

• • •

HV–

• • • –+

SENSE

MOTOR

C5

75 pF

0.1

µF 0.1

µF

C3



C7



R2



2.00 KΩ

– POWER – mW

– TEMPERATURE – °C

150

100

300

100 150

MAX. OPERATING

TEMP. IS 100 °C

200 P

, OUTPUT

250

0 200

, INPUT

1-245

the HCPL-7820/7825 through an

RC anti-aliasing filter (R5, C3).

And finally, the differential output

of the isolation amplifier is con-

verted to a ground-referenced

single-ended output voltage with a

simple differential amplifier

circuit (U3 and associated

components). Although the

application circuit is relatively

simple, a few recommendations

should be followed to ensure

optimal performance.

Supplies and Bypassing

As mentioned above, an inexpen-

sive 78L05 three-terminal regula-

tor can be used to reduce the

gate-drive power supply voltage

to 5 V. To help attenuate high-

frequency power supply noise or

ripple, a resistor or inductor can

be used in series with the input of

the regulator to form a low-pass

filter with the regulator’s input

bypass capacitor.

As shown in Figure 24, 0.1 µF

bypass capacitors (C2, C4) should

be located as close as possible to

the input and output power supply

pins of the HCPL-7820/7825. The

bypass capacitors are required

because of the high-speed digital

nature of the signals inside the

isolation amplifier. A 0.01 µF

bypass capacitor (C3) is also rec-

ommended at the input pin(s) due

to the switched-capacitor nature

of the input circuit. The input

bypass capacitor should be at

least 1000 pF to maintain gain

accuracy of the isolation amplifier.

Inductive coupling between the

input power-supply bypass

capacitor and the input circuit,

which includes the input bypass

capacitor and the input leads of

the HCPL-7820/7825, can

introduce additional DC offset in

the circuit. Several steps can be

taken to minimize the mutual

coupling between the two parts of

the circuit, thereby improving the

offset performance of the design.

Separate the two bypass capaci-

tors C2 and C3 as much as

possible (even putting them on

opposite sides of the PC board),

while keeping the total lead

lengths, including traces, of each

bypass capacitor less than 20

mm. PC board traces should be

made as short as possible and

placed close together or over

ground plane to minimize loop

area and pickup of stray magnetic

fields. Avoid using sockets, as

they will typically increase both

loop area and inductance. And

finally, using capacitors with

small body size and orienting

them perpendicular to each other

on the PC board can also help.

For more information concerning

inductive coupling, see the

Application Note Designing with

Hewlett-Packard Isolation

Amplifiers.

Shunt Resistor Selection

The current-sensing shunt resistor

should have low resistance (to

minimize power dissipation), low

inductance (to minimize di/dt

induced voltage spikes which

could adversely affect operation),

and reasonable tolerance (to

maintain overall circuit accuracy).

The value of the shunt should be

chosen as a compromise between

minimizing power dissipation by

making the shunt resistance

smaller and improving circuit

accuracy by making it larger and

using more of the input range of

the HCPL-7820/7825. Hewlett-

Packard recommends 4 different

shunts which can be used to sense

average currents in motor drives

up to 35 A and 35 hp. Table 1

shows the maximum current and

horsepower range for each of the

LVR-series shunts from Dale.

Even higher currents can be

sensed with lower value shunts

available from vendors such as

Dale, IRC, and Isotek (Isabellen-

huette). When sensing currents

large enough to cause significant

heating of the shunt, the tempera-

ture coefficient of the shunt can

introduce nonlinearity due to the

amplitude dependent temperature

rise of the shunt. Using a heat

sink for the shunt or using a shunt

with a lower tempco can help

minimize this effect. The

Application Note Designing with

Hewlett-Packard Isolation

Amplifiers contains additional

information on designing with

current shunts.

The recommended method for

connecting the isolation amplifier

to the shunt resistor is shown in

Table 1. Current Shunt Summary

Shunt Resistor Shunt Maximum Maximum Maximum

Part Number Resistance Power Dissipation RMS Current Horsepower Range

LVR-3.05-1% 50 mΩ3 W 3 A 0.8-3.0 hp

LVR-3.02-1% 20 mΩ3 W 8 A 2.2-8.0 hp

LVR-3.01-1% 10 mΩ3 W 15 A 4.1-15 hp

LVR-5.005-1% 5 mΩ5 W 35 A 9.6-35 hp

1-246

Figure 24. Pin 2 (VIN+) is con-

nected to the positive terminal of

the shunt resistor, while pin 3

(VIN-) is shorted to pin 4 (GND1),

with the power-supply return path

functioning as the sense line to

the negative terminal of the

current shunt. This allows a single

pair of wires or PC board traces

to connect the isolation amplifier

circuit to the shunt resistor. In

some applications, however,

supply currents flowing through

the power-supply return path may

cause offset or noise problems. In

this case, better performance may

be obtained by connecting pin 3

to the negative terminal of the

shunt resistor separately from the

power supply return path. When

connected this way, both input

pins should be bypassed. Whether

two or three wires are used, it is

recommended that twisted-pair

wire or very close PC board traces

be used to connect the current

shunt to the isolation amplifier

circuit to minimize electro-

magnetic interference to the

sense signal.

The 39 Ω resistor in series with

the input lead forms a low-pass

anti-aliasing filter with the input

bypass capacitor with a 400 kHz

bandwidth. The resistor performs

another important function as

well; it dampens any ringing

which might be present in the

circuit formed by the shunt, the

input bypass capacitor, and the

wires or traces connecting the

two. Undamped ringing of the

input circuit near the input

sampling frequency can alias into

the baseband producing what

might appear to be noise at the

output of the device.

PC Board Layout

In addition to affecting offset, the

layout of the PC board can also

affect the common mode rejection

(CMR) performance of the

isolation amplifier, due primarily

to stray capacitive coupling

between the input and the output

circuits. To obtain optimal CMR

performance, the layout of the

printed circuit board (PCB) should

minimize any stray coupling by

maintaining the maximum pos-

sible distance between the input

and output sides of the circuit and

ensuring that any ground plane on

the PCB does not pass directly

below or extend much wider than

the HCPL-7820/7825. Using

surface-mount components can

help achieve many of the PCB

objectives discussed in the pre-

ceding paragraphs. An example

through-hole PCB layout illustrat-

ing some of the more important

layout recommendations is shown

in Figures 26 and 27. See the

Application Note Designing with

Hewlett-Packard Isolation

Amplifiers for more information

on PCB layout considerations.

Figure 25. Single-Supply Post-Amplifier Circuit.

Figure 26. Top Layer of Printed Circuit Board Layout. Figure 27. Bottom Layer of Printed Circuit Board Layout.

C2 C4

TO R

SENSE+

TO R

SENSE–

TO V

DD1

TO V

DD2

OUT+

OUT–

0.1 µF

+5 V

OUT

3U2

R1



10.0 KΩ

+5 V C8

0.1 µF

–

+MC34071

R3



10.0 KΩ

HCPL-7820/7825

R4B

20.0 KΩ

C6

75 pF



R4A

20.0 KΩ

+5 V

C5

75 pF

R2



10.0 KΩ

1-247

Post-Amplifier Circuit

The recommended application

circuit (Figure 24) includes a

post-amplifier circuit that serves

three functions: to reference the

output signal to the desired level

(usually ground), to amplify the

signal to appropriate levels, and

to help filter output noise. The

particular op-amp used in the

post-amp is not critical; however,

it should have low enough offset

and high enough bandwidth and

slew rate so that it does not

adversely affect circuit

performance. The offset of the op-

amp should be low relative to the

output offset of the HCPL-7820/

7825, or less than about 5 mV.

To maintain overall circuit band-

width, the post-amplifier circuit

should have a bandwidth at least

twice the minimum bandwidth of

the isolation amplifier, or about

400 kHz. To obtain a bandwidth

of 400 kHz with a gain of 5, the

op-amp should have a gain-

bandwidth greater than 2 MHz.

The post-amplifier circuit includes

a pair of capacitors (C5 and C6)

that form a single-pole low-pass

filter. These capacitors allow the

bandwidth of the post-amp to be

adjusted independently of the gain

and are useful for reducing the

output noise from the isolation

amplifier (doubling the capacitor

values halves the circuit band-

width). The component values

shown in Figure 24 form a

differential amplifier with a gain

of 5 and a cutoff frequency of

approximately 200 kHz and were

chosen as a compromise between

low noise and fast response times.

The overall recommended

application circuit has a band-

width of 130 kHz, a rise time of

2.6 µs and delay to 90% of

4.2 µs.

The gain-setting resistors in the

post-amp should have a tolerance

of 1% or better to ensure ade-

quate CMRR and gain tolerance

for the overall circuit. Resistor

networks with even better ratio

tolerances can be used which

offer better performance, as well

as reducing the total component

count and board space.

The post-amplifier circuit can be

easily modified to allow for single-

supply operation. Figure 25 shows

a schematic for a post-amplifier

for use in 5 V single-supply appli-

cations. One additional resistor is

needed and the gain is decreased

to allow circuit operation over the

full input voltage range. See the

Application Note Designing with

Hewlett-Packard Isolation

Amplifiers for more information

on the post-amplifier circuit.

Other Information

As mentioned above, reducing the

bandwidth of the post amplifier

circuit reduces the amount of

output noise. Figure 21 shows

how the output noise changes as a

function of the post-amplifier

bandwidth. The post-amplifier

circuit exhibits a first-order low-

pass filter characteristic. For the

same filter bandwidth, a higher-

order filter can achieve even

better attenuation of modulation

noise due to the second-order

noise shaping of the sigma-delta

modulator. For more information

on the noise characteristics of the

HCPL-7820/7825, see the

Application Note Designing with

Hewlett-Packard Isolation

Amplifiers.

The HCPL-7820/7825 can also be

used to isolate signals with

amplitudes larger than its

recommended input range with

the use of a resistive voltage

divider at its input. The only

restrictions are that the imped-

ance of the divider be relatively

small (less than 1 kΩ) so that the

input resistance (280 kΩ) and

input bias current (1 µA) do not

affect the accuracy of the

measurement. An input bypass

capacitor is still required,

although the 39 Ω series damping

resistor is not (the resistance of

the voltage divider provides the

same function). The low-pass

filter formed by the divider

resistance and the input bypass

capacitor may limit the achievable

bandwidth.