LTC1661
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For more information www.linear.com/LTC1661
Block Diagram
Features Description
Micropower Dual
10-Bit DAC in MSOP
The LT C
®
1661 integrates two accurate, serially address-
able, 10-bit digital-to-analog converters (DACs) in a single
tiny MS8 package. Each buffered DAC draws just 60µA
total supply current, yet is capable of supplying DC output
currents in excess of 5mA and reliably driving capacitive
loads up to 1000pF. Sleep mode further reduces total
supply current to a negligible 1µA.
Linear Technology’s proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor
. The double-buffered input logic provides
simultaneous update capability and can be used to write
to either DAC without interrupting sleep mode.
Ultralow supply current, power-saving sleep mode and
extremely compact size make the LTC1661 ideal for
battery-powered applications, while its straightforward
usability, high performance and wide supply range make
it an excellent choice as a general purpose converter.
For additional outputs and even greater board density,
please refer to the LTC1660 micropower octal DAC for
10-bit applications. For 8-bit applications, please consult
the LTC1665 micropower octal DAC.
Differential Nonlinearity (DNL)
applications
n Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Board Space of an SO-8
n Micropower: 60µA per DAC
Sleep Mode: 1µA for Extended Battery Life
n Rail-to-Rail Voltage Outputs Drive 1000pF
n Wide 2.7V to 5.5V Supply Range
n Double Buffered for Independent or Simultaneous
DAC Updates
n Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
n Reference Input Has Constant Impedance over All
Codes (260kΩ Typ)—Eliminates External Buffers
n 3-Wire Serial Interface with Schmitt Trigger Inputs
n Differential Nonlinearity: ≤±0.75LSB Max
n Mobile Communications
n Digitally Controlled Amplifiers and Attenuators
n Portable Battery-Powered Instruments
n Automatic Calibration for Manufacturing
n Remote Industrial Devices
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
CS/LD
1661 BD
1 4
10-BIT
DAC A
10-BIT
DAC B
ADDRESS
DECODER
CONTROL
LOGIC
SHIFT REGISTER
SCK
2
DIN REF
3
V
OUT
A
8 5
GND
7
V
CC
V
OUT
B
6
LATCH
LATCH
LATCH
LATCH
CODE
0 256 512 768
1023
LSB
1661 G02
0.75
–0.75
0.60
0.40
0.20
0
–0.20
–0.40
–0.60
LTC1661
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For more information www.linear.com/LTC1661
aBsolute maximum ratings
VCC to GND .............................................. –0.3V to 7.5V
Logic Inputs to GND ............................... –0.3V to 7.5V
VOUT A, VOUT B, REF to GND ...........–0.3V to VCC + 0.3V
Maximum Junction Temperature...........................125°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
1
2
3
4
CS
/LD
SCK
DIN
REF
8
7
6
5
V
OUT A
GND
VCC
V
OUT B
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 150°C/W
1
2
3
4
8
7
6
5
TOP VIEW
CS
/LD
SCK
DIN
REF
V
OUT A
GND
VCC
V
OUT B
N8 PACKAGE
8-LEAD PLASTIC DIP
TJMAX = 150°C, θJA = 100°C/W
pin conFiguration
electrical characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded unless otherwise noted.
orDer inFormation
Lead Free Finish
TUBE TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1661CMS8#PBF LTC1661CMS8#TRPBF LTDV 8-Lead Plastic MSOP 0°C to 70°C
LTC1661IMS8#PBF LTC1661IMS8#TRPBF LTDW 8-Lead Plastic MSOP –40°C to 85°C
LTC1661CN8#PBF LTC1661CN8#TRPBF LTC1661CN8 8-Lead Plastic DIP 0°C to 70°C
LTC1661IN8#PBF LTC1661IN8#TRPBF LTC1661IN8 8-Lead Plastic DIP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Operating Temperature Range
LTC1661C ............................................... 0°C to 70°C
LTC1661I ............................................ –40°C to 85°C
Lead Temperature (Soldering, 10 sec) ................. 300°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Accuracy
Resolution l10 Bits
Monotonicity 1V ≤ VREF ≤ VCC – 0.1V (Note 2) l10 Bits
DNL Differential Nonlinearity 1V ≤ VREF ≤ VCC – 0.1V (Note 2) l±0.1 ±0.75 LSB
INL Integral Nonlinearity 1V ≤ VREF ≤ VCC – 0.1V (Note 2) l±0.4 ±2 LSB
VOS Offset Error Measured at Code 20 l±5 ±30 mV
VOS Temperature Coefficient ±15 µV/°C
FSE Full-Scale Error VCC = 5V, VREF = 4.096V l±1 ±12 LSB
Full-Scale Error Temperature Coefficient ±30 µV/°C
(http://www.linear.com/product/LTC1661#orderinfo)
LTC1661
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electrical characteristics
timing characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded unless otherwise noted.
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSR Power Supply Rejection VREF = 2.5V 0.18 LSB/V
Reference Input
Input Voltage Range l0 VCC V
Resistance Active Mode l140 260 kΩ
Capacitance l15 pF
IREF Reference Current Sleep Mode l0.001 1 µA
Power Supply
VCC Positive Supply Voltage For Specified Performance l2.7 5.5 V
ICC Supply Current VCC = 5V (Note 3)
VCC = 3V (Note 3)
Sleep Mode (Note 3)
l
l
l
120
95
1
195
154
3
µA
µA
µA
DC Performance
Short-Circuit Current Low VOUT = 0V, VCC = VREF = 5V, Code = 1023 l10 25 100 mA
Short-Circuit Current High VOUT = VCC = VREF = 5V, Code = 0 l7 19 120 mA
AC Performance
Voltage Output Slew Rate Rising (Notes 4, 5)
Falling (Notes 4, 5)
0.60
0.25
V/µs
V/µs
Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) 30 µs
Capacitive Load Driving 1000 pF
Digital I/O
VIH Digital Input High Voltage VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
l
l
2.4
2.0
V
V
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
l
l
0.8
0.6
V
V
ILK Digital Input Leakage VIN = GND to VCC l±10 µA
CIN Digital Input Capacitance (Note 6) l10 pF
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 4.5V to 5.5V
t1DIN Valid to SCK Setup l40 ns
t2DIN Valid to SCK Hold l0 ns
t3SCK High Time (Note 6) l30 ns
t4SCK Low Time (Note 6) l30 ns
t5CS/LD Pulse Width (Note 6) l80 ns
t6LSB SCK High to CS/LD High (Note 6) l30 ns
t7CS/LD Low to SCK High (Note 6) l20 ns
t9SCK Low to CS/LD Low (Note 6) l0 ns
t11 CS/LD High to SCK Positive Edge (Note 6) l20 ns
SCK Frequency Square Wave (Note 6) l16.7 MHz
LTC1661
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For more information www.linear.com/LTC1661
timing characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V
t1DIN Valid to SCK Setup (Note 6) l60 ns
t2DIN Valid to SCK Hold (Note 6) l0 ns
t3SCK High Time (Note 6) l50 ns
t4SCK Low Time (Note 6) l50 ns
t5CS/LD Pulse Width (Note 6) l100 ns
t6LSB SCK High to CS/LD High (Note 6) l50 ns
t7CS/LD Low to SCK High (Note 6) l30 ns
t9SCK Low to CS/LD Low (Note 6) l0 ns
t11 CS/LD High to SCK Positive Edge (Note 6) l30 ns
SCK Frequency Square Wave (Note 6) l10 MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1023 (full scale). See Applications Information.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes k = 102 and k = 922.
Note 6: Guaranteed by design and not subject to test.
timing Diagram
DIN
CS
/LD
SCK
A3 A2
1661 TD
A1 X1 X0
t2
t9t11
t5t7
t6
t
1
t3t4
LTC1661
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typical perFormance characteristics
Load Regulation
vs Output Current
Load Regulation
vs Output Current Large-Signal Step Response
Minimum VOUT vs Load Current
(Output Sinking)
Integral Nonlinearity (INL)
Mid-Scale Output Voltage
vs Load Current
Differential Nonlinearity (DNL)
Mid-Scale Output Voltage
vs Load Current
Minimum Supply Headroom vs
Load Current (Output Sourcing)
CODE
0 256 512 768 1023
LSB
1661 G01
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
CODE
0 256 512 768
1023
LSB
1661 G02
0.75
–0.75
0.60
0.40
0.20
0
–0.20
–0.40
–0.60
0246810
V
CC
– V
OUT
(mV)
1661 G03
1400
1200
1000
800
600
400
200
0
–55°C
25°C
125°C
VREF = 4.096V
∆VOUT < 1LSB
CODE = 1023
|
IOUT
|
(mA) (Sourcing)
|
IOUT
|
(mA) (SINKING)
0246810
V
OUT
(mV)
1661 G04
1400
1200
1000
800
600
400
200
0
–55°C
25°C
125°C
VCC = 5V
CODE = 0
IOUT (mA)
–30 –20 –10 0 10 20 30
V
OUT
(V)
1661 G05
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
VCC = 4.5V
VCC = 5V
VCC = 5.5V
VREF = VCC
CODE = 512
SINKSOURCE
IOUT (mA)
–15 –4–8–12 0 4 8 12 15
V
OUT
(V)
1661 G06
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
VCC = 2.7V
VCC = 3V
VCC = 3.6V
VREF = VCC
CODE = 512
SINKSOURCE
IOUT (mA)
–2 –1 0 1 2
∆V
OUT
(LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
1661 G07
VCC = VREF = 5V
CODE = 512
SINKSOURCE
IOUT (µA)
–500 0
OUT
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
SINKSOURCE
VCC = VREF = 3V
CODE = 512
TIME (µs)
0 20 40 60 80
100
V
OUT
(V)
1661 G09
5
4
3
2
1
0
VCC = VREF = 5V
10% TO
90% STEP
CODE = 102
CODE = 922
LTC1661
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For more information www.linear.com/LTC1661
pin Functions
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
DIN into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the control code,
A3-A0, is (are) performed. CMOS and TTL compatible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 3): Serial Interface Data Input. Input word data on
the DIN pin is shifted into the 16-bit register on the rising
edge of SCK. CMOS and TTL compatible.
REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT A, VOUT B (Pin 8, Pin 5): DAC Analog Voltage Outputs.
The output range is
0≤VOUTA,VOUTB ≤VREF
1023
1024
⎛
⎝
⎜⎞
⎠
⎟
VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
GND (Pin 7): System Ground.
typical perFormance characteristics
Supply Current
vs Logic Input Voltage Supply Current vs Temperature
LOGIC INPUT VOLTAGE (V)
012345
SUPPLY CURRENT (mA)
1661 G10
1.0
0.8
0.6
0.4
0.2
0
ALL DIGITAL INPUTS
SHORTED TOGETHER
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105
125
SUPPLY CURRENT (µA)
1661 G11
150
140
130
120
110
100
90
80
70
60
50
VCC = 5.5V
VREF = VCC
CODE = 1023
VCC = 4.5V
VCC = 3.6V
VCC = 2.7V
LTC1661
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DeFinitions
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL =Δ
V
OUT
–LSB
LSB
where ∆VOUT is the measured voltage difference between
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual full-scale
voltage from ideal. FSE includes the effects of offset and
gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (endpoint INL). Because the output cannot go
below zero, the linearity is measured between full scale
and the lowest code which guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
INL =
VOUT – VOS – VFS – VOS
( )
Code
1023
⎛
⎝
⎜⎞
⎠
⎟
LSB
where VOUT is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB =
V
REF
1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the out-
put cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
LTC1661
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operation
Transfer Function
The transfer function for the LTC1661 is:
VOUT(DEAL) =k
1024
⎛
⎝
⎜⎞
⎠
⎟VREF
where k is the decimal equivalent of the binary DAC input
code D9-D0 and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1661 positively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) must not ever exceed the
voltage at VCC (Pin 6) by more than 0.3V. Particular care
should be taken in the power supply turn-on and turn-
off sequences to assure that this limit is observed. See
Absolute Maximum Ratings.
Serial Interface
See Table 1. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don’t-care bits.
Table 1. LTC1661 Input Word
A3 A2 A1
CONTROL CODE
A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 X1 X0D0
INPUT CODE
INPUT WORD
DON’T
CARE
After the Input word is loaded into the register (see
Figure1), it is internally converted from serial to parallel
format. The parallel 10-bit-wide input code data path is
then buffered by two latch registers.
The first of these, the input register, is used for loading
new input codes. The second buffer, the DAC register, is
used for updating the DAC outputs. Each DAC has its own
10-bit input register and 10-bit DAC register.
By selecting the appropriate 4-bit control code (see Table2)
it is possible to perform single operations, such as loading
one DAC or changing power-down status (sleep/wake).
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and wakes the part
up. The DACs can be loaded separately or together, but
the outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the DIN input
is shifted into the 16-bit shift register on the positive edge
of SCK. The 4-bit control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last. When
the full 16-bit Input word has been shifted in, CS/LD is
pulled high, causing the system to respond according to
Table2. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110b is reserved for the special sleep
instruction (see Table 2). In this mode, the digital parts
of the circuit stay active while the analog sections are
disabled; static power consumption is greatly reduced.
The reference input and analog outputs are set in a high
impedance state and all DAC settings are retained in
memory so that when Sleep mode is exited, the outputs
of DACs not updated by the wake command are restored
to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared
with new input codes during Sleep (control codes 0001b
and 0010b); then, a single command (1000b) can be used
both to wake the part and to update the output values.
LTC1661
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operation
Table 2. DAC Control Functions
CONTROL INPUT REGISTER
STATUS
DAC REGISTER
STATUS
POWER-DOWN STATUS
(SLEEP/WAKE) COMMENTSA3 A2 A1 A0
0 0 0 0 No Change No Update No Change No Operation. Power-Down Status Unchanged
(Part Stays in Wake or Sleep Mode)
0 0 0 1 Load DAC A No Update No Change Load Input Register A with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0 0 1 0 Load DAC B No Update No Change Load Input Register B with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0 0 1 1 Reserved
01 0 0 Reserved
0 1 0 1 Reserved
0 1 1 0 Reserved
0 1 1 1 Reserved
1 0 0 0 No Change Update Outputs Wake Load Both DAC Regs with Existing Contents of Input
Regs. Outputs Update. Part Wakes Up
1 0 0 1 Load DAC A Update Outputs Wake Load Input Reg A. Load DAC Regs with New Contents
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
10 1 0 Load DAC B Update Outputs Wake Load Input Reg B. Load DAC Regs with Existing
Contents of Input Reg A and New Contents of Reg B.
Outputs Update. Part Wakes Up
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 No Change No Update Wake Part Wakes Up. Input and DAC Regs Unchanged. DAC
Outputs Reflect Existing Contents of DAC Regs
1 1 1 0 No Change No Update Sleep Part Goes to Sleep. Input and DAC Regs Unchanged.
DAC Outputs Set to High Impedance State
1 1 1 1 Load DACs A, B with
Same 10-Bit Code
Update Outputs Wake Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
DIN
SCK
CS/LD
A3 A2
INPUT CODE DON’T CARE
A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
1661 F01
16151413121110987654321
(SCK ENABLED) (LTC1661
RESPONDS)
CONTROL CODE
INPUT WORD W0
Figure 1. Register Loading Sequence
LTC1661
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operation
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in the
LTC1661 can typically source or sink up to 5mA (VCC=5V).
The outputs swing to within a few millivolts of either supply
when unloaded and have an equivalent output resistance of
85Ω (typical) when driving a load to the rails. The output
amplifiers are stable driving capacitive loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1µF
load can be successfully driven by inserting a 20Ω resis-
tor in series with the VOUT pin. A 2.2µF load needs only a
10Ω resistor, and a 10µF electrolytic capacitor can be used
without any resistor (the equivalent series resistance of the
capacitor itself provides the required small resistance). In
any of these cases, larger values of resistance, capacitance
or both may be substituted for the values given.
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to volt-
ages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 2c. No full-scale limiting
can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
1661 F02
INPUT CODE
(2b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
5120 1023
INPUT CODE
OUTPUT
VOLTAGE
(2a)
VREF = VCC
VREF = VCC
(2c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (2a) Overall Transfer Function (2b) Effect of Negative
Offset for Codes Near Zero Scale (2c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
LTC1661
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typical applications
–
+
U3A
LT1368
PIN
DRIVER
(1 0F N)
VH
VLVOUT
1661 F03
LOGIC
DRIVE
4
–5V
10V
5V
VH = 7.5V
(FROM MAIN
INPUT DAC)
VL = –2.5V
(FROM MAIN
INPUT DAC)
VA1 = 2.5V
VH′ = VH + VH
VL′ = VL + ∆VL
VB1 R4
5k
0.1µF
8
3
1
CS
/LD
DIN
SCK
4 6
3
2
1
8
5
2
0.1µF
R3
50k
LTC1661
U1
DAC A
DAC B
R2
50k
R1
5k
0.1µF
+
–
U3B
LT1368
5V
VB2
VA2 = 2.5V
6
1
4 6
3
2
7
5
8
5
0.1µF
R7
50k
LTC1661
U2
DAC B
DAC A
R5
50k
R6
5k
7
R8
5k
0.1µF
0.1µF
FOR EACH U1 AND U2
CODE A CODE B ∆VH, ∆VL
512 1023 –250mV
512 512 0
512 0 250mV
–2.5V 250mV
7.5V 250mV
VA2 = 2.5VVA1 =
VH + (VA1 – VB1)VH′ = R1
R2
VL + (VA2 – VB2)VL′ =
FOR VALUES SHOWN,
∆VH, ∆VL ADJUSTMENT RANGE =
±250mV
∆VH, ∆VL STEP SIZE = 500µV
R1
R2
2
0.1µF
V
IN
≥ 4.3V
LTC1258-4.1 1
4.096V
4
REF
DIN
SCK
CS/LD
VOUTA
GND
VCC
LTC1661
VOUTB
0V TO 4.096V
(4mV/BIT)
T
0V TO 4.096V
(4mV/BIT)
1661 F04
4
3
2
1
8
5
7
6
0.1µF
Figure 3. Pin Driver VH and VL Adjustment in ATE Applications
Figure 4. Using the LTC1258 and the LTC1661 In a Single Li-Ion Battery Application
LTC1661
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package Description
MSOP (MS8) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
1 2 34
87 65
.255 ±.015*
(6.477 ±0.381)
.400*
(10.160)
MAX
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
( )
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
N8 REV I 0711
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ±.005
(3.302 ±0.127)
.020
(0.508)
MIN
.018 ±.003
(0.457 ±0.076)
.120
(3.048)
MIN
.100
(2.54)
BSC
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
Please refer to http://www.linear.com/product/LTC1661#packaging for the most recent package drawings.
LTC1661
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For more information www.linear.com/LTC1661
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision history
REV DATE DESCRIPTION PAGE NUMBER
A 11/10 Removed typical values from Timing Characteristics section 3, 4
B 4/16 Corrected typo for VCC under Power Supply 3
LTC1661
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For more information www.linear.com/LTC1661
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
LINEAR TECHNOLOGY CORPORATION 1999
LT 0416 REV B • PRINTED IN USA
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC1661
relateD parts
typical application
–
+
U3A
LT1368
PIN
DRIVER
(1 0F N)
VH
VLVOUT
1661 F03
LOGIC
DRIVE
4
–5V
10V
5V
VH = 7.5V
(FROM MAIN
INPUT DAC)
VL = –2.5V
(FROM MAIN
INPUT DAC)
VA1 = 2.5V
VH′ = VH + VH
VL′ = VL + ∆VL
VB1 R4
5k
0.1µF
8
3
1
CS
/LD
DIN
SCK
4 6
3
2
1
8
5
2
0.1µF
R3
50k
LTC1661
U1
DAC A
DAC B
R2
50k
R1
5k
0.1µF
+
–
U3B
LT1368
5V
VB2
VA2 = 2.5V
6
1
4 6
3
2
7
5
8
5
0.1µF
R7
50k
LTC1661
U2
DAC B
DAC A
R5
50k
R6
5k
7
R8
5k
0.1µF
0.1µF
FOR EACH U1 AND U2
CODE A CODE B ∆VH, ∆VL
512 1023 –250mV
512 512 0
512 0 250mV
–2.5V 250mV
7.5V 250mV
VA2 = 2.5VVA1 =
VH + (VA1 – VB1)VH′ = R1
R2
VL + (VA2 – VB2)VL′ =
FOR VALUES SHOWN,
∆VH, ∆VL ADJUSTMENT RANGE =
±250mV
∆V
H
, ∆V
L
STEP SIZE = 500µV
R1
R2
Pin Driver VH and VL Adjustment in ATE Applications
PART NUMBER DESCRIPTION COMMENTS
LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448 Dual 12-Bit VOUT DAC in SO-8 Package VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454/LTC1454L Dual 12-Bit VOUT DACs in SO-16 Package with Added
Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package
VCC: 2.7V to 5.5V
Low Power Multiplying VOUT DAC. Output Swings from GND to
REF. REF Input Can Be Tied to VCC
LTC1663 Single 10-Bit VOUT DAC in SOT-23 Package VCC = 2.7V to 5.5V, Internal Reference, 60µA
LTC1665/LTC1660 Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output