FEDR37V12841A-002-02 Issue Date: Oct. 01, 2008 MR37V12841A 128M 1-Bit Serial Production Programmed ROM (P2ROM) GENERAL DESCRIPTION The MR37V12841A is a 128Mbit Production Programmed Read-Only Memory, which is configured as 134,217,728word 1-bit. The MR37V12841A supports a simple read operation using a single 3.3V power supply and a Serial Peripheral Interface (SPI) compatible serial bus. The MR37V12841A have data programmed and have functions tested at LAPIS Semiconductor factory. (Using the DC pins for the programming function is NOT allowed ) FEATURES *Read Operation - +3.3 V power supply - 134,217,728 1-bit - Access time: 33MHz serial clock (FAST-READ) 20MHz serial clock (READ) - Read Identification Instruction - Active read current: 30mA(FAST-READ) 20mA(READ) - Standby current : 50 A - Serial Clock Input and Data Input/Output - Input Data Format : 1-byte Command code, 3-byte address, 1-byte dummy (FAST-READ) 1-byte Command code, 3-byte address (READ) PACKAGES * MR37V12841A-xxxMP - 16-pin plastic SOP (P-SOP16-375-1.27-K) PIN DESCRIPTIONS Pin name #CS Functions under Read Operation Chip Select SI Serial Data Input SO Serial Data Output SCLK Clock Input VCC Power supply voltage GND Ground DC NC Don't care ( 0v - Vcc ) <for reference> Program power supply voltage Vpp under Programming operation Non connection 1/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM READ COMMAND DEFINITION Command 03[H] 1 nd AD1 2 rd AD2 2 th AD3 2 N byte read out until #CS goes high 3 1 2 Note Read Array (byte) st 3 4 Action Note: st 1. The 1 command 03[H] is a Read command 2. AD1 to AD3 are address input data 3. Data output Details of command and address are shown as follows. 1-byte command code READ 0 3-byte address AD1: 0 0 0 0 0 1 1 A23 A22 A21 A20 A19 A18 A17 A16 AD2: A15 A14 A13 A12 A11 A10 A9 A8 AD3: A7 A6 A5 A4 A3 A2 A1 A0 2/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM FAST READ COMMAND DEFINITION Command 0B[H] 1 nd AD1 2 rd AD2 2 4 th AD3 2 5 th X 3 N byte read out until #CS goes high 4 1 2 3 Action Note: 1. 2. 3. 4. Note Read Array (byte) st st The 1 command 0B[H] is a Read command AD1 to AD3 are address input data X is a dummy cycle Data output Details of command and address are shown as follows. 1-byte command code FAST-READ 3-byte address 0 0 0 0 1 0 1 1 AD1: A23 A22 A21 A20 A19 A18 A17 A16 AD2: A15 A14 A13 A12 A11 A10 A9 A8 AD3: A7 A6 A5 A4 A3 A2 A1 A0 3/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM READ IDENTIFICATION COMMAND DEFINITION Command 1 Note Read Array (byte) st Action 9F[H] 1 3 byte read out 2 Note: st 1. The 1 command 9F[H] is a Read Identification command 2. Identification output Details of command and address are shown as follows. 1-byte command code RDID 1 0 0 1 1 1 1 1 IDENTIFICATION DEFINITION Manufacturer Identification AE[H] Device Identification Type Capacity 41[H] 16[H] 4/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM DEVICE OPERATION 1. Command "03h" or "0Bh" makes this LSI become and keep active mode until next #CS High. 2. Incorrect command makes this LSI become and keep standby mode until next #CS Low. In standby mode, SO pin is High-Z. COMMAND DESCRIPTION 1. Read Array This command consists of the 4-byte code. The 1st code is a command which decides if the device becomes standby or active mode. The 1st code "03h" activates the device. The 2nd code to the 4th code are address inputs. 2. Fast Read Array This command consists of the 5-byte code. The 1st code is a command which decides if the device becomes standby or active mode. The 1st code "0Bh"activates the device. The 2nd code to the 4th code are address. The 5th code is a dummy cycle. 3. Identification Read Array This command consists of the 1-byte code. The 1st code is a command which decides if the device becomes standby or active mode. The 1st code "9Fh"activates the device. 4. Standby When #CS is high, the device is put in standby mode at the next rising edge of SCLK. Maximum standby current is 10uA. When the above-mentioned 1st code is incorrect command, the device is put in standby mode at the next rising edge of SCLK. DATA SEQUENCE The data is serially sent out through SO pin, synchronized with the falling edge of SCLK. Meanwhile input data is also serially read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input and output data are bit7 (MSB) first, bit6, bit 5, ..., and bit0(LSB). ADDRESS SEQUENCE The address assignment is described at the COMMAND DEFINITION on page 2, 3. 5/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Tstg -- Storage temperature Value Unit -55 to 125 C -0.5 to VCC+0.5 V -0.5 to VCC+0.5 V Input voltage VI Output voltage VO Power supply voltage VCC -0.5 to 5 V Power dissipation per package PD Ta = 25C 1.0 W Output short circuit current IOS -- 10 mA relative to VSS RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit 0 -- 70 C 3.0 -- 3.6 V Operating temperature under bias VCC power supply voltage VCC Input "H" level VIH 2.4 -- VCC+0.5 V Input "L" level VIL -0.5 -- 0.6 V Ta VCC = 3.0 to 3.6 V Voltage is relative to VSS. : Vcc+1.5V(Max.) when pulse width of positive overshoot is less than 10ns. : -1.5V(Min.) when pulse width of negative overshoot is less than 10ns. PIN CAPACITANCE (VCC = 3.3 V, Ta = 25C, f = 1 MHz) Max. Unit Parameter Symbol Condition Min. Typ. Input CIN1 VI = 0 V -- -- Output COUT VO = 0 V -- -- 10 DC CDC VI = 0 V -- -- 200 8 pF 6/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM ELECTRICAL CHARACTERISTICS DC Characteristics parameter Symbol Condition Min. (VCC = 3.0V-3.6V, Ta = 0 to 70C) Typ. Max. Unit Input leakage current ILI VI = 0 to VCC -- -- 10 A Output leakage current ILO VO = 0 to VCC -- -- 10 A VCC power supply current (Standby) ISB1 #CS = VCC -- -- 50 A ISB2 #CS = VIH -- -- 1 mA -- -- 20 mA -- -- 30 mA VCC power supply current (Read) ICC1 VCC power supply current (Fast Read) ICC1F #CS = VIL ,f = 20MHz SO= open #CS = VIL ,f = 33Hz SO= open Input "H" level VIH -- 2.4 -- VCC+0.5 V Input "L" level VIL -- -0.5 -- 0.6 V Output "H" level VOH IOH = -100 A Vcc-0.2 -- -- V Output "L" level VOL IOL = 500 A -- -- 0.4 V Voltage is relative to VSS. : Vcc+1.5V(Max.) when pulse width of positive overshoot is less than 10ns. : -1.5V(Min.) when pulse width of negative overshoot is less than 10ns. 7/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM AC Characteristics Parameter Symbol Condition ( tsclk=33MHz, VCC = 3.0V-3.6V, Ta = 0 to 70C) Min. Max. Unit Clock frequency tSCLK -- -- 33 * MHz Clock High time tSKH -- 11 -- ns Clock Low time tSKL -- 11 -- ns Clock Rise time tR -- -- 4 ns Clock Fall time tF -- -- 4 ns #CS Lead Clock Time tCSA -- 5 -- ns #CS Setup Time tCS -- 5 -- ns #CS Lag Clock Time tCSB -- 5 -- ns #CS Hold Time tCH -- 5 -- ns #CS High Time tCSH -- 100 -- ns SI Setup Time tDS -- 2 -- ns SI Hold Time tDH -- 10 -- ns Access time tAA -- -- 8 ns SO Hold Time tDOH -- 0 -- ns SO Floating Time tDOZ -- -- 8 ns Symbol Condition Clock frequency tSCLK -- Clock High time tSKH -- 20 -- ns Clock Low time tSKL -- 20 -- ns Clock Rise time tR -- -- 5 ns Parameter Clock Fall time ( tsclk=20MHz VCC = 3.0V-3.6V, Ta = 0 to 70C) Min. Max. Unit -- 20 ** MHz tF -- -- 5 ns #CS Lead Clock Time tCSA -- 10 -- ns #CS Setup Time tCS -- 10 -- ns #CS Lag Clock Time tCSB -- 5 -- ns #CS Hold Time tCH -- 5 -- ns #CS High Time tCSH -- 100 -- ns SI Setup Time tDS -- 5 -- ns SI Hold Time tDH -- 10 -- ns Access time tAA -- -- 15 ns SO Hold Time tDOH -- 0 -- ns SO Floating Time tDOZ -- -- 10 ns *: FAST-READ instructions **: READ instructions Measurement conditions Input signal level Input timing reference level Output load Output timing reference level Output load Vcc/0v 2.4V/ 0.6V 30 pF 0.5 Vcc Output 30 pF (Including scope and jig) 8/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM TIMING CHART (READ CYCLE) Serial Data Input/Output Timing tCSH tCSB tCSA #CS tCS tF tR tCYC tCH SCLK tSKH BIT 7 SI tSKL BIT 6 BIT 0 tDS tDH BIT 6 BIT 7 SO tAA tDOH BIT 0 tDOZ Standby Timing #CS SCLK BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SI st 1 byte = incorrect code Hi-Z SO Standby Standby Incorrect command makes this LSI become and keep standby mode until next #CS rising edge. In standby mode, SO pin is High-Z. 9/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM Read Array Timing Waveform #CS SCLK *note1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 SI st 1 byte Command 2 nd byte AD1 SO Hi-Z #CS SCLK *note2 BIT 1 BIT 0 SI Don't Care th 4 byte AD3 SO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 Hi-Z st 1 data output 2 nd data output #CS SCLK SI SO BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 Hi-Z th (N-1) data output th N data output th (N+1) data output Note: 1. Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 4th byte. 10/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM Fast Read Array Timing Waveform #CS SCLK *note1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 SI st 1 byte Command 2 nd byte AD1 SO Hi-Z #CS SCLK *note2 BIT 1 BIT 0 SI Don't Care th 5 byte DUMMY SO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 Hi-Z st 1 data output 2 nd data output #CS SCLK SI SO BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 Hi-Z th (N-1) data output th N data output th (N+1) data output Note: 1. Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 5th byte. 11/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM Read Identification Timing Waveform #CS SCLK *note1 SI *note2 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Don't Care st 1 byte Command SO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Hi-Z Manufacturer Identification tCSB #CS SCLK Don't Care SI SO BIT 1 BIT 0 BIT15 BIT14 BIT13 BIT 2 BIT 1 BIT 0 Hi-Z Device Identification Note: 1. Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 1st byte. 12/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 13/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM REVISION HISTORY Page Document No. Date Previous Edition Current Edition FEDR37V12841A-02-01 Nov. 9, 2006 - - Final edition 1 FEDR37V12841A-02-02 Mar. 16, 2007 13 13 Replaced package diagram FEDR37V12841A-002-02 Oct. 1, 2008 - - Changed company logo and name to OKI SEMICONDUCTOR Description 14/15 FEDR37V12841A-002-02 MR37V12841A / P2ROM NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). 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