DAC5672
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SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
DUAL, 14-BIT 275 MSPS DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC5672
1FEATURES • Low Power: 330 mW
• 14-Bit Dual Transmit Digital-to-Analog • Power-Down Mode: 9 mW
Converter (DAC) • Package: 48-Pin Thin-Quad Flat Pack (TQFP)
• 275 MSPS Update Rate APPLICATIONS
• Single Supply: 3 V to 3.6 V • Cellular Base Transceiver Station Transmit
• High Spurious-Free Dynamic Range (SFDR): Channel
84 dBc at 5 MHz – CDMA: W-CDMA, CDMA2000, IS-95
• High Third-Order Two-Tone Intermodulation – TDMA: GSM, IS-136, EDGE/UWC-136
(IMD3): 79 dBc at 15.1 MHz and 16.1 MHz • Medical/Test Instrumentation
• WCDMA Adjacent Channel Leakage Ratio • Arbitrary Waveform Generators (ARB)
(ACLR): 78 dB at Baseband • Direct Digital Synthesis (DDS)
• WCDMA ACLR: 73 dB at 30.72 MHz • Cable Modem Termination System (CMTS)
• Independent or Single Resistor Gain Control
• Dual or Interleaved Data
• On-Chip 1.2-V Reference
DESCRIPTION
The DAC5672 is a monolithic, dual-channel, 14-bit, high-speed DAC with on-chip voltage reference.
Operating with update rates of up to 275 MSPS, the DAC5672 offers exceptional dynamic performance,
tight-gain, and offset matching characteristics that make it suitable in either I/Q baseband or direct IF
communication applications.
Each DAC has a high-impedance, differential-current output, suitable for single-ended or differential
analog-output configurations. External resistors allow scaling the full-scale output current for each DAC
separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is
temperature-compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may
be used.
The DAC5672 has two, 14-bit, parallel input ports with separate clocks and data latches. For flexibility, the
DAC5672 also supports multiplexed data for each DAC on one port when operating in the interleaved mode.
The DAC5672 has been specifically designed for a differential transformer-coupled output with a 50-Ω
doubly-terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output
power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm output power) are supported.
The DAC5672 is available in a 48-pin TQFP package. Pin compatibility between family members provides 12-bit
(DAC5662) and 14-bit (DAC5672) resolution. Furthermore, the DAC5672 is pin compatible to the DAC2904 and
AD9767 dual DACs. The device is characterized for operation over the industrial temperature range of -40°C to
85°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DE-
MUX
DA[13:0]
DB[13:0]
MODE
GSET
Latch A
Latch B 14−b DAC
14−b DAC IOUTA1
IOUTA2
IOUTB1
IOUTB2
1.2 V Reference
WRTB WRTA CLKB CLKA
BIASJ_A
BIASJ_B
EXTIO
DVDD DGND AVDD AGND
SLEEP
DAC5672
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
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FUNCTIONAL BLOCK DIAGRAM
AVAILABLE OPTIONS PACKAGED DEVICES
TA48-Pin TQFP
DAC5672IPFB
-40°C to 85°C DAC5672IPFBR
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13 14 15
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
DA13 (MSB)
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2 17 18 19 20
AGND
47 46 45 44 4348 42
IOUTA1
IOUTA2
BIASJ_A
EXTIO
GSET
BIASJ_B
IOUTB2
DVDD
DB13 (MSB)
DB12
DGND
DVDD
WRTA/WRTIQ
CLKA/CLKIQ
CLKB/RESETIQ
WRTB/SELECTIQ
DGND
40 39 3841
21 22 23 24
37
DA1
SLEEP
IOUTB1
MODE
AVDD
DA0 (LSB)
Top View
48−Pin TQFP
PFB Package
DAC5672
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SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
AGND 38 I Analog ground
AVDD 47 I Analog supply voltage
BIASJ_A 44 O Full-scale output current bias for DACA
BIASJ_B 41 O Full-scale output current bias for DACB
CLKA/CLKIQ 18 I Clock input for DACA, CLKIQ in interleaved mode
CLKB/RESETIQ 19 I Clock input for DACB, RESETIQ in interleaved mode
DA[13:0] 1-14 I Data port A. DA13 is MSB and DA0 is LSB. Internal pulldown.
DB[13:0] 23-36 I Data port B. DB13 is MSB and DB0 is LSB. Internal pulldown.
DGND 15, 21 I Digital ground
DVDD 16, 22 I Digital supply voltage
EXTIO 43 I/O Internal reference output (bypass with 0.1 mF to AGND) or external reference input
GSET 42 I Gain-setting mode: H – 1 resistor, L – 2 resistors. Internal pullup.
IOUTA1 46 O DACA current output. Full-scale with all bits of DA high.
IOUTA2 45 O DACA complementary current output. Full-scale with all bits of DA low.
IOUTB1 39 O DACB current output. Full-scale with all bits of DB high.
IOUTB2 40 O DACB complementary current output. Full-scale with all bits of DB low.
MODE 48 I Mode Select: H – Dual Bus, L – Interleaved. Internal pullup.
Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode.
SLEEP 37 I Internal pulldown.
WRTA/WRTIQ 17 I Input write signal for PORT A (WRTIQ in interleaving mode)
WRTB/SELECTIQ 20 I Input write signal for PORT B (SELECTIQ in interleaving mode)
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ABSOLUTE MAXIMUM RATINGS
over TA(unless otherwise noted)(1)
UNIT
AVDD(2) -0.5 V to 4 V
Supply voltage range DVDD(3) -0.5 V to 4 V
Voltage between AGND and DGND -0.5 V to 0.5 V
Voltage between AVDD and DVDD -0.5 V to 0.5 V
DA[13:0] and DB[13:0](3) -0.5 V to DVDD + 0.5 V
MODE, SLEEP, CLKA, CLKB, WRTA, WRTB(3) -0.5 V to DVDD + 0.5 V
Supply voltage range IOUTA1, IOUTA2, IOUTB1, IOUTB2(2) -1 V to AVDD + 0.5 V
EXTIO, BIASJ_A, BIASJ_B, GSET(2) -0.5 V to AVDD + 0.5 V
Peak input current (any input) +20 mA
Peak total input current (all inputs) -30 mA
Operating free-air temperature range -40 °C to 85 °C
Storage temperature range -65 °C to 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND.
(3) Measured with respect to DGND.
ELECTRICAL CHARACTERISTICS
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC Specifications
Resolution 14 Bits
DC Accuracy(1)
INL Integral nonlinearity -4 ±1.1 4 LSB
1 LSB = IOUTFS/214, TMIN to TMAX
DNL Differential nonlinearity -3 ±0.75 3 LSB
Analog Output
Offset error Midscale value ±0.03 %FSR
Offset mismatch Midscale value ±0.03 %FSR
With external reference ±0.25 %FSR
Gain error With internal reference ±0.25 %FSR
Minimum full-scale output current(2) 2 mA
Maximum full-scale output current(2) 20 mA
With external reference -2 0.2 2 %FSR
Gain mismatch With internal reference -2 0.2 2 %FSR
Output voltage compliance range(3) -1 1.25 V
ROOutput resistance 300 kΩ
COOutput capacitance 5 pF
Reference Output
Reference voltage 1.14 1.2 1.26 V
Reference output current(4) 100 nA
Reference Input
VEXTIO Input voltage 0.1 1.25 V
(1) Measured differentially through 50 Ωto AGND.
(2) Nominal full-scale current, IOUTFS, equals 32x the IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5672 device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(4) Use an external buffer amplifier with high-impedance input to drive any external load.
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ELECTRICAL CHARACTERISTICS (continued)
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RIInput resistance 1 MΩ
Small signal bandwidth 300 kHz
CIInput capacitance 100 pF
Temperature Coefficients
ppm of
Offset drift 2 FSR/°C
ppm of
With external reference ±20 FSR/°C
Gain drift ppm of
With internal reference ±40 FSR/°C
Reference voltage drift ±20 ppm/°C
ELECTRICAL CHARACTERISTICS
over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz, independent gain set mode (unless
otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
AVDD Analog supply voltage 3 3.3 3.6 V
DVDD Digital supply voltage 3 3.3 3.6 V
Including output current through load 75 90 mA
resistor
IAVDD Supply current, analog Sleep mode with clock 2.5 6 mA
Sleep mode without clock 2.5 mA
25 38 mA
IDVDD Supply current, digital Sleep mode with clock 13.4 18 mA
Sleep mode without clock 0.6 mA
330 390
Sleep mode with clock 53
Power dissipation mW
Sleep mode without clock 9.2
fDATA = 275 MSPS, fOUT = 20 MHz 350
APSRR Analog power supply rejection ratio -0.2 -0.01 0.2 %FSR/V
DPSRR Digital power supply rejection ratio -0.2 0 0.2 %FSR/V
TAOperating free-air temperature -40 85 °C
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ELECTRICAL CHARACTERISTICS
AC specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, differential 1:1 impedance
ratio transformer coupled output, 50-Ωdoubly terminated load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Output
fclk Maximum output update rate(1) 275 MSPS
tsOutput settling time to 0.1% Mid-scale transition 20 ns
(DAC)
trOutput rise time 10% to 90% 1.4 ns
(OUT)
tfOutput fall time 90% to 10% 1.5 ns
(OUT) IOUTFS = 20 mA 55 pA/√Hz
Output noise IOUTFS = 2 mA 30 pA/√Hz
AC Linearity
1st Nyquist zone, TA= 25°C,
fDATA = 50 MSPS, fOUT = 1 MHz, IOUTFS = 0 83
dB
1st Nyquist zone, TA= 25°C,
fDATA = 50 MSPS, fOUT = 1 MHz, IOUTFS = 80
-6 dB
1st Nyquist zone, TA= 25°C,
fDATA = 50 MSPS, fOUT = 1 MHz, IOUTFS = 79
-12 dB
1st Nyquist zone, TA= 25°C,
SFDR Spurious-free dynamic range dBc
84
fDATA = 100 MSPS, fOUT = 5 MHz
1st Nyquist zone, TA= 25°C, 79
fDATA = 100 MSPS, fOUT = 20 MHz
1st Nyquist zone, TMIN to TMAX,68 75
fDATA = 200 MSPS, fOUT = 20 MHz
1st Nyquist zone, TA= 25°C, 72
fDATA = 200 MSPS, fOUT = 41 MHz
1st Nyquist zone, TA= 25°C, 74
fDATA = 275 MSPS, fOUT = 20 MHz
1st Nyquist zone, TA= 25°C, 77 dB
fDATA = 100 MSPS, fOUT = 5 MHz
SNR Signal-to-noise ratio 1st Nyquist zone, TA= 25°C, 70 dB
fDATA = 160 MSPS, fOUT = 20 MHz
W-CDMA signal with 3.84-MHz Bandwidth, 75 dB
fDATA = 61.44 MSPS, IF = 15.360 MHz
W-CDMA signal with 3.84-MHz Bandwidth, 73 dB
fDATA = 122.88 MSPS, IF = 30.72 MHz
ACLR Adjacent channel leakage ratio W-CDMA signal with 3.84-MHz Bandwidth, 78 dB
fDATA = 61.44 MSPS, Baseband
W-CDMA signal with 3.84-MHz Bandwidth, 78 dB
fDATA = 122.88 MSPS, Baseband
Each tone at -6 dBFS, TA= 25°C,
fDATA = 200 MSPS, fOUT = 45.4 MHz and 65 dBc
46.4 MHz
Third-order two-tone
IMD3 intermodulation Each tone at -6 dBFS, TA= 25°C,
fDATA = 100 MSPS, fOUT = 15.1 MHz and 79 dBc
16.1 MHz
(1) Specified by design and bench characterization. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
AC specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, differential 1:1 impedance
ratio transformer coupled output, 50-Ωdoubly terminated load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Each tone at -12 dBFS, TA= 25°C
fDATA = 100 MSPS, fOUT = 15.6, 15.8, 16.2, 79 dBc
and 16.4 MHz
Each tone at -12 dBFS, TA= 25°C
IMD Four-tone intermodulation fDATA = 165 MSPS, fOUT = 68.8, 69.6, 71.2, 61 dBc
and 72.0 MHz
Each tone at -12 dBFS, TA= 25°C
fDATA = 165 MSPS 73 dBc
fOUT = 19.0, 19.1, 19.3, and 19.4 MHz
TA= 25°C, fDATA = 165 MSPS
Channel isolation fOUT (CH1) = 20 MHz, fOUT (CH2) = 21 95 dBc
MHz
ELECTRICAL CHARACTERISTICS
Digital specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital Input
VIH High-level input voltage 2 3.3 V
VIL Low-level input voltage 0 0.8 V
IIH High-level input current ±50 µA
IIL Low-level input current ±10 µA
IIH(GSET) High-level input current, GSET pin 7 µA
IIL(GSET) Low-level input current, GSET pin -80 µA
IIH(MODE) High-level input current, MODE pin -30 µA
IIL(MODE) Low-level input current, MODE pin -80 µA
CIInput capacitance 5 pF
SWITCHING CHARACTERISTICS
Digital specifications over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Timing - Dual Bus Mode
tsu Input setup time 1 ns
thInput hold time 1 ns
tLPH Input clock pulse high time 1 ns
tLAT Clock latency (WRTA/B to outputs) 4 4 clk
tPD Propagation delay time 1.5 ns
Timing - Single Bus Interleaved Mode
tsu Input setup time 0.5 ns
thInput hold time 0.5 ns
tLAT Clock latency (WRTA/B to outputs) 4 4 clk
tPD Propagation delay time 1.5 ns
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−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
0 2000 4000 6000 8000 10000 12000 14000 16000
Input Code
INL − Integral Nonlinearity Error − LSB
G001
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 2000 4000 6000 8000 10000 12000 14000 16000
Input Code
DNL − Differential Nonlinearity Error − LSB
G002
DAC5672
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
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TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
INPUT CODE
Figure 1.
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
Figure 2.
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60
65
70
75
80
85
90
95
100
0 4 8 12 16 20
fout − Output Frequency − MHz
fdata = 52 MSPS
Dual Bus Mode
SFDR − Spurious-Free Dynamic Range − dBc
0 dBfS
−12 dBfS
−6 dBfS
G003
60
65
70
75
80
85
90
95
100
0 5 10 15 20 25 30
fout − Output Frequency − MHz
fdata = 78 MSPS
Dual Bus Mode
SFDR − Spurious-Free Dynamic Range − dBc
−12 dBfS
0 dBfS
−6 dBfS
G004
60
65
70
75
80
85
90
95
100
0 5 10 15 20 25 30 35
fout − Output Frequency − MHz
fdata = 100 MSPS
Dual Bus Mode
SFDR − Spurious-Free Dynamic Range − dBc
−12 dBfS
0 dBfS
−6 dBfS
G005
60
65
70
75
80
85
90
95
100
0 5 10 15 20 25 30 35 40 45 50 55 60
fout − Output Frequency − MHz
fdata = 165 MSPS
Dual Bus Mode
SFDR − Spurious-Free Dynamic Range − dBc
−12 dBfS
0 dBfS
−6 dBfS
G006
DAC5672
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SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
SPURIOUS-FREE DYNAMIC RANGE SPURIOUS-FREE DYNAMIC RANGE
vs vs
OUTPUT FREQUENCY OUTPUT FREQUENCY
Figure 3. Figure 4.
SPURIOUS-FREE DYNAMIC RANGE SPURIOUS-FREE DYNAMIC RANGE
vs vs
OUTPUT FREQUENCY OUTPUT FREQUENCY
Figure 5. Figure 6.
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f − Frequency − MHz
−100
−80
−60
−40
−20
0
0.0 7.8 15.6 23.4 31.2 39.0
fdata = 78 MSPS
fOUT = 15 MHz
Dual Bus Mode
Power − dBm
G007
f − Frequency − MHz
−100
−80
−60
−40
−20
0
0.0 16.5 33.0 49.5 66.0 82.5
fdata = 165 MSPS
fOUT = 30.1 MHz
Dual Bus Mode
Power − dBm
G008
fout1 − Output Frequency − MHz
60
65
70
75
80
85
90
95
0 5 10 15 20 25 30 35
Two-Tone IMD3 − dBc
fdata = 78 MSPS
Dual Bus Mode
fout2 = fout1 + 1 MHz
G009
fout1 − Output Frequency − MHz
50
55
60
65
70
75
80
85
90
95
100
0 10 20 30 40 50
Two-Tone IMD3 − dBc
fdata = 165 MSPS
Dual Bus Mode
fout2 = fout1 + 1 MHz
G010
DAC5672
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TYPICAL CHARACTERISTICS (continued)
SINGLE-TONE SPECTRUM SINGLE-TONE SPECTRUM
Figure 7. Figure 8.
TWO-TONE IMD3 TWO-TONE IMD3
vs vs
OUTPUT FREQUENCY OUTPUT FREQUENCY
Figure 9. Figure 10.
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f − Frequency − MHz
−110
−90
−70
−50
−30
−10
19.0 19.5 20.0 20.5 21.0 21.5 22.0
Power − dBm
fdata = 78 MSPS
fout1 = 20.1 MHz
fout2 = 21.1 MHz
Dual Bus Mode
G011
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0 1 2 3 4 5 6 7 8 9 10
fdata = 122.88 MSPS
Baseband Signal
Dual Bus Mode
Power − dBm
G013
f − Frequency − MHz
Power − dBm
−120
−100
−80
−60
−40
−20
7.6 10.1 12.6 15.1 17.6 20.1 22.6
fdata = 61.44 MSPS
IF = 15.36 MHz
ACLR = 75.18 dB
Dual Bus Mode
G014
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TYPICAL CHARACTERISTICS (continued)
TWO-TONE SPECTRUM TWO-TONE SPECTRUM
Figure 11. Figure 12.
POWER POWER
vs vs
FREQUENCY FREQUENCY
Figure 13. Figure 14.
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f − Frequency − MHz
Power − dBm
−120
−100
−80
−60
−40
−20
7.6 10.1 12.6 15.1 17.6 20.1 22.6
fdata = 122.88 MSPS
IF = 15.36 MHz
ACLR = 77.16 dB
Dual Bus Mode
G015
f − Frequency − MHz
Power − dBm
−120
−100
−80
−60
−40
−20
23.0 25.5 28.0 30.5 33.0 35.5 38.0
fdata = 122.88 MSPS
IF = 30.72 MHz
ACLR = 72.7 dB
Dual Bus Mode
G016
DA[13:0]
DB[13:0]
SLEEP
CLKA/B
WRTA/B
Internal
DigitalIn
DVDD
400W
100kW
DGND
DAC5672
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TYPICAL CHARACTERISTICS (continued)
POWER POWER
vs vs
FREQUENCY FREQUENCY
Figure 15. Figure 16.
Digital Inputs and Timing
Digital Inputs
The data input ports of the DAC5672 accept a standard positive coding with data bits DA13 and DB13 being the
most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best
performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may
vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their
specified limits.
All digital inputs of the DAC5672 are CMOS compatible. Figure 17 and Figure 18 show schematics of the
equivalent CMOS digital inputs of the DAC5672. The pullup and pulldown circuitry is approximately equivalent to
100kΩ. The 14-bit digital data input follows the offset positive binary coding scheme. The DAC5672 is designed
to operate with a digital supply (DVDD) of 3 V to 3.6 V.
Figure 17. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
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GSET
MODE
Internal
DigitalIn
DVDD
400W
100kW
DGND
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Figure 18. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor
Input Interfaces
The DAC5672 features two operating modes selected by the MODE pin, as shown in Table 1.
• For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own
separate data input bus, clock input, and data write signal (data latch-in).
• In single-bus interleaved mode, the data must be presented interleaved at the A-channel input bus. The
B-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.
Table 1. Operating Modes
MODE Pin MODE pin connected to DGND MODE pin connected to DVDD
Bus input Single-bus interleaved mode, clock and write input equal for both DACs Dual-bus mode, DACs operate independently
Dual-Bus Data Interface and Timing
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5672 consist
of two independent, 14-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA,
WRTB) and clock (CLKA, CLKB) lines. The WRTA/B lines control the channel input latches and the CLKA/B lines
control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRTA/B line.
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock
domains having equal periods (but possibly different phases) are input to the DAC5672. This is defined by a
minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.
This essentially implies that the rising edge of CLKA/B must occur at the same time or before the rising edge of
the WRTA/B signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the
rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected
externally. Note that all specifications were measured with the WRTA/B and CLKA/B lines connected together.
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Valid Data
DA[13:0]/DB[13:0]
tsu th
tlat
tpd
tsettle
WRTA/WRTB
CLKA/CLKB
IOUT
or
IOUT
t1ph
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Figure 19. Dual-Bus Mode Operation
Single-Bus Interleaved Data Interface and Timing
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 20 shows the timing diagram. In
interleaved mode, the A- and B-channels share the write input (WRTIQ) and update clock (CLKIQ and internal
CLKDACIQ). Multiplexing logic directs the input word at the A-channel input bus to either the A-channel input
latch (SELECTIQ is high) or to the B-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data
value in the B-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is
low, the data value in the A-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the A-channel input data rate is twice the update rate of the DAC core. As in dual-bus
mode, it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch
the A- and B-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the A-
and B-DAC latches on the following falling edge of the write inputs. The DAC5672 clock input is divided by a
factor of two before it is presented to the DAC latches.
Correct pairing of the A- and B-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is
divided by two, which would translate to a non-deterministic relation between the rising edges of the CLKIQ and
CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ with respect
to the data at the input of the DAC latch is determined. CLKDACIQ is disabled (low) when RESETIQ is high.
14 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5672
Valid Data
DA[13:0]
tsu th
tlat
tpd
tsettle
SELECTIQ
WRTIQ
CLKIQ
RESETIQ
IOUT
or
IOUT
DAC5672
www.ti.com
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
Figure 20. Single-Bus Interleaved Mode Operation
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): DAC5672
IOUTFS +IOUT1 )IOUT2
IOUT1 +IOUTFS ǒCode
16384Ǔ
16383 - Code
I = I x
OUT2 OUTFS 16384
æ ö
÷
ç÷
ç÷
ç
è ø
IOUTFS +32 IREF +32 VREF
RSET
VOUT1 +IOUT1 RLOAD
VOUT2 +IOUT2 RLOAD
DAC5672
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
www.ti.com
APPLICATION INFORMATION
Theory of Operation
The architecture of the DAC5672 uses a current steering technique to enable fast switching and high update
rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to
deliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output current is formed by steering all currents to either
output summing node, IOUT1 or IOUT2. The complementary outputs deliver a differential output signal, which
improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise),
and double the peak-to-peak output signal swing by a factor of two, as compared to single-ended operation.
The segmented architecture results in a significant reduction of the glitch energy and improves the dynamic
performance (SFDR) and DNL. The current outputs maintain a very high output impedance of greater
than 300 kΩ.
When pin 42 (GSET) is high (simultaneous gain set mode), the full-scale output current for both DACs is
determined by the ratio of the internal reference voltage (1.2 V) and an external resistor (RSET) connected to
BIASJ_A. When GSET is low (independent gain set mode), the full-scale output current for each DAC is
determined by the ratio of the internal reference voltage (1.2 V) and separate external resistors (RSET) connected
to BIASJ_A and BIASJ_B. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC
output current that can range from 2 mA to 20 mA, depending on the value of RSET.
The DAC5672 is split into a digital and an analog portion, each of which is powered through its own supply pin.
The digital section includes edge-triggered input latches and the decoder logic, while the analog section
comprises both the current source array with its associated switches, and the reference circuitry.
DAC Transfer Function
Each of the DACs in the DAC5672 has a set of complementary current outputs, IOUT1 and IOUT2. The full-scale
output current, IOUTFS, is the summation of the two complementary output currents:
(1)
The individual output currents depend on the DAC code and can be expressed as:
(2)
(3)
where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the
reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).
(4)
In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage
develops at each output according to:
(5)
(6)
The value of the load resistance is limited by the output compliance specification of the DAC5672. To maintain
specified linearity performance, the voltage for IOUT1 and IOUT2 must not exceed the maximum allowable
compliance range.
16 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5672
VOUTDIFF +VOUT1 *VOUT2
VOUTDIFF +(2 Code *16383)
16384 IOUTFS RLOAD
AVDD
Current Source Array
IOUT1 IOUT2
S(1) S(1)C
RLOAD RLOAD
S(2) S(2)C S(N) S(N)C
DAC5672
www.ti.com
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
The total differential output voltage is:
(7)
(8)
Analog Outputs
The DAC5672 provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of the
analog output stage representing the differential topology is shown in Figure 21. The output impedance of IOUT1
and IOUT2 results from the parallel combination of the differential switches, along with the current sources and
associated parasitic capacitances.
Figure 21. Analog Outputs
The signal voltage swing that may develop at the two outputs, IOUT1 and IOUT2, is limited by a negative and
positive compliance. The negative limit of –1 V is given by the breakdown voltage of the CMOS process and
exceeding it compromises the reliability of the DAC5672 (or even causes permanent damage). With the full-scale
output set to 20 mA, the positive compliance equals 1.2 V. Note that the compliance range decreases to about 1
V for a selected output current of IOUTFS = 2 mA. Care must be taken that the configuration of DAC5672 does not
exceed the compliance range to avoid degradation of the distortion performance and integral linearity.
Best distortion performance is typically achieved with the maximum full-scale output signal limited to
approximately 0.5 VPP. This is the case for a 50-Ωdoubly-terminated load and a 20-mA full-scale output current.
A variety of loads can be adapted to the output of the DAC5672 by selecting a suitable transformer while
maintaining optimum voltage levels at IOUT1 and IOUT2. Furthermore, using the differential output configuration
in combination with a transformer is instrumental for achieving excellent distortion performance. Common-mode
errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly the case with
high output frequencies.
For those applications requiring the optimum distortion and noise performance, it is recommended to select a
full-scale output of 20 mA. A lower full-scale range of 2 mA may be considered for applications that require low
power consumption, but can tolerate a slight reduction in performance level.
Output Configurations
The current outputs of the DAC5672 allow for a variety of configurations. As mentioned previously, utilizing the
converter’s differential outputs yield the best dynamic performance. Such a differential output circuit may consist
of an RF transformer or a differential amplifier configuration. The transformer configuration is ideal for most
applications with ac coupling, while op amps are suitable for a dc-coupled configuration.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): DAC5672
IOUT1 1:1
IOUT2
50 Ω
50 Ω
RLOAD
50 Ω
100 ΩAGND
IOUT1 4:1
IOUT2
100 Ω
100 Ω
RLOAD
50 Ω
AGND
DAC5672
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
www.ti.com
The single-ended configuration may be considered for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs to ground converts the output current into a
ground-referenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V or
op-amp configuration may be considered.
Differential With Transformer
Using an RF transformer provides a convenient way of converting the differential output signal into a
single-ended signal while achieving excellent dynamic performance. The appropriate transformer must be
carefully selected based on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of significantly reducing common-mode signals, thus
improving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitable
impedance ratio (winding ratio) the transformer can provide optimum impedance matching while controlling the
compliance voltage for the converter outputs.
Figure 22 and Figure 23 show 50-Ωdoubly-terminated transformer configurations with 1:1 and 4:1 impedance
ratios, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable
a dc-current flow. Applying a 20-mA full-scale output current would lead to a 0.5-VPP output for a 1:1 transformer
and a 1-VPP output for a 4:1 transformer. In general, the 1:1 transformer configuration will have slightly better
output distortion, but the 4:1 transformer will have 6 dB higher output power.
Figure 22. Driving a Doubly-Terminated 50-ΩCable Using a 1:1 Impedance Ratio Transformer
Figure 23. Driving a Doubly-Terminated 50-ΩCable Using a 4:1 Impedance Ratio Transformer
18 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5672
IOUT1
IOUT2
50 Ω25 Ω
RLOAD
50 Ω
AGND
IOUTFS +32 IREF +32 VREF
RSET
DAC5672
www.ti.com
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
Single-Ended Configuration
Figure 24 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25 Ω. Node IOUT2 must be connected to AGND or terminated with a resistor of 25 Ωto
AGND. The nominal resistor load of 25 Ωgives a differential output swing of 1 VPP when applying a 20-mA
full-scale output current.
Figure 24. Driving a Doubly-Terminated 50-ΩCable Using a Single-Ended Output
Reference Operation
Internal Reference
The DAC5672 has an on-chip reference circuit which comprises a 1.2-V bandgap reference and two control
amplifiers, one for each DAC. The full-scale output current, IOUTFS, of the DAC5672 is determined by the
reference voltage, VREF, and the value of resistor RSET. IOUTFS can be calculated by:
(9)
The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which is
determined by the ratio of VREF and RSET (see Equation 9). The full-scale output current, IOUTFS, results from
multiplying IREF by a fixed factor of 32.
Using the internal reference, a 2-kΩresistor value results in a full-scale output of approximately 20 mA. Resistors
with a tolerance of 1% or better should be considered. Selecting higher values, the output current can be
adjusted from 20 mA down to 2 mA. Operating the DAC5672 at lower than 20-mA output currents may be
desirable for reasons of reducing the total power consumption, improving the distortion performance, or
observing the output compliance voltage limitations for a given load condition.
It is recommended to bypass the EXTIO pin with a ceramic chip capacitor of 0.1 µF or more. The control
amplifier is internally compensated and its small signal bandwidth is approximately 300 kHz.
External Reference
The internal reference can be disabled by simply applying an external reference voltage into the EXTIO pin,
which in this case functions as an input. The use of an external reference may be considered for applications that
require higher accuracy and drift performance or to add the ability of dynamic gain control.
While a 0.1-µF capacitor is recommended to be used with the internal reference, it is optional for the external
reference operation. The reference input, EXTIO, has a high input impedance (1 MΩ) and can easily be driven
by various sources. Note that the voltage range of the external reference must stay within the compliance range
of the reference input.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): DAC5672
DAC5672
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
www.ti.com
Gain Setting Option
The full-scale output current on the DAC5672 can be set two ways: either for each of the two DAC channels
independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42)
must be low (that is, connected to AGND). In this mode, two external resistors are required — one RSET
connected to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user
has the flexibility to set and adjust the full-scale output current for each DAC independently, allowing for the
compensation of possible gain mismatches elsewhere within the transmit signal path.
Alternatively, bringing the GSET pin high (that is, connected to AVDD), the DAC5672 switches into the
simultaneous gain set mode. Now the full-scale output current of both DAC channels is determined by only one
external RSET resistor connected to the BIASJ_A pin. The resistor at the BIASJ_B pin may be removed; however,
this is not required since this pin is not functional in this mode and the resistor has no effect on the gain equation.
Sleep Mode
The DAC5672 features a power-down function which can reduce the total supply current to approximately 3.1
mA over the specified supply range if no clock is present. Applying a logic high to the SLEEP pin initiates the
power-down mode, while a logic low enables normal operation. When left unconnected, an internal active
pulldown circuit enables the normal operation of the converter.
20 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5672
DAC5672
www.ti.com
SLAS440C –NOVEMBER 2004–REVISED DECEMBER 2010
REVISION HISTORY
Changes from Revision B (May 2009) to Revision C Page
• Changed the non-printing µ symbols in the Digital Input section of the Electrical Characteristics table (Units column)
to the correct µ symbols recognized by the PDF processor. ................................................................................................ 7
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): DAC5672
PACKAGE OPTION ADDENDUM
www.ti.com 30-Nov-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC5672IPFB ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
DAC5672IPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
DAC5672IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
DAC5672IPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5672 :
PACKAGE OPTION ADDENDUM
www.ti.com 30-Nov-2010
Addendum-Page 2
•Enhanced Product: DAC5672-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC5672IPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC5672IPFBR TQFP PFB 48 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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