PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in
LFPAK56 using NextPower-S3 Schottky-Plus technology
30 November 2017 Product data sheet
1. General description
280 Amp, logic level gate drive N-channel enhancement mode MOSFET in 150 °C LFPAK56
package using advanced TrenchMOS Superjunction technology. This product has been designed
and qualified for high performance power switching applications.
2. Features and benefits
280 A capability
Avalanche rated, 100% tested at IAS = 190 A
NextPower-S3 technology delivers 'superfast switching with soft recovery'
Low QRR, QG and QGD for high system efficiency and low EMI designs
Schottky-Plus body-diode, gives soft switching without the associated high IDSS leakage
Optimised for 4.5 V gate drive utilising NextPower-S3 Superjunction technology
High reliability LFPAK (Power SO8) package, copper-clip, solder die attach and
qualified to 150 °C
Exposed leads can be wave soldered, visual solder joint inspection and high quality solder
joints
Low parasitic inductance and resistance
3. Applications
Synchronous rectification
DC-to-DC converters
High performance & high efficiency server power supply
Motor control
Power ORing
4. Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C - - 40 V
IDdrain current VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - - 280 A
Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 198 W
Tjjunction temperature -55 - 150 °C
Static characteristics
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 10; Fig. 11
- 1.1 1.4 RDSon drain-source on-state
resistance
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10; Fig. 11
- 0.93 1.1
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 2 / 14
Symbol Parameter Conditions Min Typ Max Unit
Dynamic characteristics
QGD gate-drain charge - 17 - nC
QG(tot) total gate charge
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 12; Fig. 13 - 59 - nC
[1] 280A continuous current has been successfully demonstrated during application tests. Practically, the current will be limited by PCB,
thermal design and operation temperature.
5. Pinning information
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 S source
2 S source
3 S source
4 G gate
mb D mounting base; connected to
drain
321 4
LFPAK56; Power-
SO8 (SOT1023)
S
D
G
mbb076
6. Ordering information
Table 3. Ordering information
PackageType number
Name Description Version
PSMN1R0-40YLD LFPAK56;
Power-SO8
Plastic single-ended surface-mounted package (LFPAK56); 4
leads
SOT1023
7. Marking
Table 4. Marking codes
Type number Marking code
PSMN1R0-40YLD 1D040L
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 3 / 14
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C - 40 V
VDSM peak drain-source
voltage
tp ≤ 20 ns; f ≤ 500 kHz; EDS(AL) ≤ 200 nJ;
pulsed
- 45 V
VDGR drain-gate voltage 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 40 V
VGS gate-source voltage -20 20 V
Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 198 W
VGS = 10 V; Tmb = 25 °C; Fig. 2 [1] - 280 AIDdrain current
VGS = 10 V; Tmb = 100 °C; Fig. 2 - 198 A
IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 1284 A
Tstg storage temperature -55 150 °C
Tjjunction temperature -55 150 °C
Tsld(M) peak soldering
temperature
- 260 °C
VESD electrostatic discharge
voltage
HBM 2 - kV
Source-drain diode
ISsource current Tmb = 25 °C - 165 A
ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 1284 A
Avalanche ruggedness
ID = 85 A; Vsup ≤ 40 V; RGS = 50 Ω;
VGS = 10 V; Tj(init) = 25 °C; unclamped;
tp = 0.26 ms
[2] - 578 mJEDS(AL)S non-repetitive drain-
source avalanche
energy
ID = 25 A; Vsup ≤ 40 V; RGS = 50 Ω;
VGS = 10 V; Tj(init) = 25 °C; unclamped;
tp = 3.8 ms
[2] - 2472 mJ
IAS non-repetitive avalanche
current
Vsup ≤ 40 V; VGS = 10 V; Tj(init) = 25 °C;
RGS = 50 Ω
[2] - 190 A
[1] 280A continuous current has been successfully demonstrated during application tests. Practically, the current will be limited by PCB,
thermal design and operation temperature.
[2] Protected by 100% test
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 4 / 14
03ne36
0
40
80
120
0 50 100 150 200
Tmb (°C)
Pder
(%)
Fig. 1. Normalized total power dissipation as a
function of mounting base temperature
aaa-008711
0 50 100 150 200
0
100
200
300
400
Tmb (°C)
ID
ID
(A)(A)
(1)(1)
(1) 280A continuous current has been successfully
demonstrated during applications tests. Practically,
the current will be limited by PCB, thermal design
and operating temperature.
Fig. 2. Continuous drain current as a function of
mounting base temperature
aaa-012570
10-1 1 10 102
10-1
1
10
102
103
104
VDS (V)
ID
ID
(A)(A)
DCDC
100 ms100 ms
10 ms10 ms
1 ms1 ms
100 µs100 µs
tp = 10 µstp = 10 µs
Limit RDSon = VDS / ID
Limit RDSon = VDS / ID
Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 5 / 14
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance
from junction to
mounting base
Fig. 4 - 0.56 0.63 K/W
Fig. 5 - 50 - K/WRth(j-a) thermal resistance
from junction to
ambient Fig. 6 - 125 - K/W
aaa-009500
10-6 10-5 10-4 10-3 10-2 10-1 1
10-3
10-2
10-1
1
tp (s)
Zth(j-mb)
Zth(j-mb)
(K/W)(K/W)
P
t
tp
T
tp
δ = T
single shotsingle shot
δ = 0.5δ = 0.5
0.20.2
0.10.1
0.050.05
0.020.02
Fig. 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
aaa-005750
Fig. 5. PCB layout for thermal resistance junction to
ambient 1” square pad; FR4 Board; 2oz copper
aaa-005751
Fig. 6. PCB layout for thermal resistance junction to
ambient minimum footprint; FR4 Board; 2oz
copper
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 6 / 14
10. Characteristics
Table 7. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - VV(BR)DSS drain-source
breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V
VGS(th) gate-source threshold
voltage
ID = 1 mA; VDS=VGS; Tj = 25 °C 1.05 1.7 2.2 V
ΔVGS(th)/ΔT gate-source threshold
voltage variation with
temperature
25 °C ≤ Tj ≤ 150 °C - -5.1 - mV/K
VDS = 32 V; VGS = 0 V; Tj = 25 °C - - 1 µAIDSS drain leakage current
VDS = 32 V; VGS = 0 V; Tj = 125 °C - 9 - µA
VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nAIGSS gate leakage current
VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10; Fig. 11
- 0.93 1.1
VGS = 10 V; ID = 25 A; Tj = 150 °C;
Fig. 10; Fig. 11
- - 1.93
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 10; Fig. 11
- 1.1 1.4
RDSon drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 150 °C;
Fig. 10; Fig. 11
- - 2.45
RGgate resistance f = 1 MHz - 1.3 - Ω
Dynamic characteristics
ID = 25 A; VDS = 20 V; VGS = 10 V;
Fig. 12; Fig. 13
- 127 - nC
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 12; Fig. 13
- 59 - nC
QG(tot) total gate charge
ID = 0 A; VDS = 0 V; VGS = 10 V - 115 - nC
QGS gate-source charge - 19 - nC
QGS(th) pre-threshold gate-
source charge
- 12 - nC
QGS(th-pl) post-threshold gate-
source charge
- 8 - nC
QGD gate-drain charge
ID = 25 A; VDS = 20 V; VGS = 4.5 V;
Fig. 12; Fig. 13
- 17 - nC
VGS(pl) gate-source plateau
voltage
ID = 25 A; VDS = 20 V; Fig. 12; Fig. 13 - 2.7 - V
Ciss input capacitance - 8845 - pF
Coss output capacitance - 1878 - pF
Crss reverse transfer
capacitance
VDS = 20 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 14
- 382 - pF
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 7 / 14
Symbol Parameter Conditions Min Typ Max Unit
td(on) turn-on delay time - 52 - ns
trrise time - 62 - ns
td(off) turn-off delay time - 65 - ns
tffall time
VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V;
RG(ext) = 5 Ω
- 38 - ns
Qoss output charge VGS = 0 V; VDS = 20 V; f = 1 MHz;
Tj = 25 °C
- 51 - nC
Source-drain diode
VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.78 1.2 V
trr reverse recovery time - 48 - ns
Qrrecovered charge [1] - 67 - nC
tareverse recovery rise
time
- 28.6 - ns
tbreverse recovery fall
time
IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 20 V; Fig. 16
- 23.8 - ns
[1] includes capacitive recovery
aaa-008714
0 0.5 1 1.5 2
0
40
80
120
160
200
VDS (V)
ID
ID
(A)(A)
2.4 V2.4 V
2.6 V2.6 V
2.8 V2.8 V
VGS = 3 VVGS = 3 V
3.5 V3.5 V
4.5 V4.5 V
10 V10 V
Fig. 7. Output characteristics; drain current as a
function of drain-source voltage; typical values
aaa-008715
0 2 4 6 8 10 12 14 16
0
2
4
6
8
VGS (V)
RDSon
RDSon
(mΩ)(mΩ)
Fig. 8. Drain-source on-state resistance as a function
of gate-source voltage; typical values
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 8 / 14
aaa-008716
0 0.8 1.6 2.4 3.2 4
0
100
200
300
400
VGS (V)
ID
ID
(A)(A)
Tj = 25°CTj = 25°C150°C150°C
Fig. 9. Transfer characteristics; drain current as a
function of gate-source voltage; typical values
aaa-008717
0 40 80 120 160 200
0
1
2
3
4
5
ID (A)
RDSon
RDSon
(mΩ)(mΩ) 2.8 V2.8 V 3 V3 V
3.5 V3.5 V
4.5 V4.5 V
10 V10 V
Fig. 10. Drain-source on-state resistance as a function
of drain current; typical values
aaa-013039
-60 -30 0 30 60 90 120 150 180
0
0.4
0.8
1.2
1.6
2
Tj (°C)
aa
10 V10 V
VGS = 4.5 VVGS = 4.5 V
Fig. 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig. 12. Gate charge waveform definitions
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 9 / 14
aaa-008718
0 20 40 60 80 100 120 140
0
2
4
6
8
10
QG (nC)
VGS
VGS
(V)(V)
20 V20 V
VDS = 8 VVDS = 8 V
32 V32 V
Fig. 13. Gate-source voltage as a function of gate
charge; typical values
aaa-008719
10-1 1 10 102
10
102
103
104
105
VDS (V)
CC
(pF)(pF)
Ciss
Ciss
Coss
Coss
Crss
Crss
Fig. 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
aaa-008720
0 0.2 0.4 0.6 0.8 1 1.2
1
10
102
103
VSD (V)
IS
IS
(A)(A)
Tj = 25°CTj = 25°C150°C150°C
Fig. 15. Source current as a function of source-drain
voltage; typical values
003aal160
0
t (s)
ID
(A)
IRM
0.25 IRM
tatb
trr
Fig. 16. Reverse recovery timing definition
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 10 / 14
11. Package outline
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1023
sot1023_po
13-03-05
17-07-31
Unit
mm
max
nom
min
1.10
0.95
0.15
0.00
0.50
0.35
4.41
3.62
0.25
0.19
0.30
0.24
4.45 5.30
4.95
1.27 0.25 0.1
A
Dimensions
Note
1. Plastic or metal protrusions of 0.15 mm per side are not included.
Plastic single-ended surface-mounted package (LFPAK56E); 4 leads SOT1023
A1b b1
0.85
b2c c1D(1)
4.70
4.45
D1(1) E(1) E1(1)
3.7
3.5
e H
6.2
5.9
L
1.3
0.8
Lp
0.85
0.40
w y
8°
0°
θ
0 2.5 5 mm
scale
X
A
c
c1
mounting
base
detail X
A1
Lp
θ
C
C
y
b
b1
A
ew A
E
H
D
L
1 2 3 4
E1
D1
b2
(3x)
Fig. 17. Package outline LFPAK56; Power-SO8 (SOT1023)
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 11 / 14
12. Soldering
sot1023_fr
0.6
(3×)
0.7
(4×)
0.25
(2×)
0.25
(2×)
0.6
(4×)
4.2
4.7
0.25
(2×)
1.27
1.1
2
3.81
0.9
(3×)
SP opening =
Cu - 0.050
SR opening =
Cu + 0.075
2.15
2.55
3.45 3.5
3.3
solder lands
solder resist occupied area
solder paste
125 µm stencil
Fig. 18. Reflow soldering footprint for LFPAK56; Power-SO8 (SOT1023)
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
PSMN1R0-40YLD All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved
Product data sheet 30 November 2017 12 / 14
13. Legal information
Data sheet status
Document
status [1][2]
Product
status [3]
Definition
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nexperia.com.
Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
Nexperia does not give any representations or warranties as to the accuracy
or completeness of information included herein and shall have no liability for
the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
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modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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Applications — Applications that are described herein for any of these
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or warranty that such applications will be suitable for the specified use
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Customers are responsible for the design and operation of their applications
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or problem which is based on any weakness or default in the customer’s
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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Non-automotive qualified products — Unless this data sheet expressly
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accepts no liability for inclusion and/or use of non-automotive qualified
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In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’ warranty of the product
for such automotive applications, use and specifications, and (b) whenever
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
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Product data sheet 30 November 2017 13 / 14
customer uses the product for automotive applications beyond Nexperia’
specifications such use shall be solely at customer’s own risk, and (c)
customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
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between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Nexperia PSMN1R0-40YLD
N-channel 40 V, 1.1 mΩ, 280 A logic level MOSFET in LFPAK56 using NextPower-S3 Schottky-Plus
technology
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Product data sheet 30 November 2017 14 / 14
14. Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking.......................................................................... 2
8. Limiting values............................................................. 3
9. Thermal characteristics............................................... 5
10. Characteristics............................................................ 6
11. Package outline........................................................ 10
12. Soldering................................................................... 11
13. Legal information..................................................... 12
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Date of release: 30 November 2017