500 kbps, ESD Protected, Half-/Full-Duplex,
iCoupler, Isolated RS-485 Transceiver
Data Sheet
ADM2484E
Rev. G Document Feedback
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FEATURES
Isolated, RS-485/RS-422 transceiver, configurable as half- or
full-duplex
±15 kV ESD protection on RS-485 input/output pins
500 kbps data rate
Complies with ANSI TIA/EIA RS-485-A-1998 and
ISO 8482: 1987(E)
Suitable for 5 V or 3.3 V operation (VDD1)
High common-mode transient immunity: >25 kV/μs
True fail-safe receiver inputs
256 nodes on the bus
Thermal shutdown protection
Safety and regulatory approvals
UL recognition
5000 V rms isolation voltage for 1 minute per UL1577
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Reinforced insulation, VIORM = 849 VPEAK
CSA Component Acceptance Notice 5A
IEC 60950-1: 390 V rms (reinforced)
Operating temperature range: −40°C to +85°C
Wide body, 16-lead SOIC package
APPLICATIONS
Isolated RS-485/RS-422 interfaces
Industrial field networks
INTERBUS
Multipoint data transmission systems
FUNCTIONAL BLOCK DIAGRAM
ADM2484E
GALVANIC ISOLATION
VDD1
GND1
VDD2
GND2
Y
Z
TxD
DE
A
B
RxD
RE
06984-001
Figure 1.
GENERAL DESCRIPTION
The ADM2484E is an isolated data transceiver with ±15 kV
ESD protection suitable for high speed, half- or full-duplex
communication on multipoint transmission lines. For half-
duplex operation, the transmitter outputs and receiver inputs
share the same transmission line. Transmitter Output Pin Y
links externally to Receiver Input Pin A, and Transmitter
Output Pin Z links externally to Receiver Input Pin B.
Designed for balanced transmission lines, the ADM2484E
complies with ANSI TIA/EIA RS-485-A-1998 and ISO 8482:
1987(E). The device employs Analog Devices, Inc., iCoupler®
technology to combine a 3-channel isolator, a three-state
differential line driver, and a differential input receiver into a
single package.
The differential transmitter outputs and receiver inputs feature
electrostatic discharge circuitry that provides protection up to
±15 kV using the human body model (HBM). The logic side of
the device can be powered with either a 5 V or a 3.3 V supply,
whereas the bus side requires an isolated 3.3 V supply.
The device has current-limiting and thermal shutdown features
to protect against output short circuits and situations where bus
contention causes excessive power dissipation.
ADM2484E Data Sheet
Rev. G | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 4
Regulatory Information ............................................................... 4
Insulation and Safety-Related Specifications ............................ 5
VDE 0884 Insulation Characteristics ........................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 10
Switching Characteristics .............................................................. 11
Circuit Description......................................................................... 12
Electrical Isolation ...................................................................... 12
Tr ut h Tables ................................................................................. 12
Thermal Shutdown .................................................................... 13
True Fail-Safe Receiver Inputs .................................................. 13
Magnetic Field Immunity .......................................................... 13
Applications Information .............................................................. 14
Isolated Power Supply Circuit .................................................. 14
PC Board Layout ........................................................................ 14
Typical Applications ................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
5/2018—Rev. F to Rev. G
Change to Features Section ............................................................. 1
Changes to Table 4 ............................................................................ 4
11/2015—Rev. E to Rev. F
Added Table 8; Renumbered Sequentially .................................... 6
3/2015—Rev. D to Rev. E
Changes to CTI Value and Isolation Group, Table 5 ................... 5
3/2014—Rev. C to Rev. D
Changes to Features Section............................................................ 1
Changed VIORM from 846 VPEAK to 849 VPEAK, Table 4 .................. 4
Changes to VDE 0884 Insulation Characteristics Section .......... 5
Additional TJ Junction Temperature of 110°C, Table 7 ............... 6
11/2010—Rev. B to Rev. C
Changes to Features Section ............................................................ 1
Changes to Table 4 ............................................................................. 4
Change to Maximum Working Insulation Voltage Parameter,
Table 6 ................................................................................................. 5
Changes to Figure 30 and Figure 31............................................. 15
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
3/2010—Rev. A to Rev. B
Changes to Minimum External Tracking (Creepage) Parameter,
Table 5 ................................................................................................. 5
3/2009—Rev. 0 to Re v. A
Changes to Figure 28 ...................................................................... 14
5/2008—Revision 0: Initial Version
Data Sheet ADM2484E
Rev. G | Page 3 of 16
SPECIFICATIONS
All voltages are relative to their respective grounds, 3.0 V ≤ VDD1 ≤ 5.5 V and 3.0 V ≤ VDD2 ≤ 3.6 V, all minimum/maximum specifications
apply over the entire recommended operation range, all typical specifications are at TA = 25°C, VDD1 = 5 V, andVDD2 = 3.3 V, unless
otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
SUPPLY CURRENT
Power Supply Current, Logic Side
TxD/RxD Data Rate = 500 kbps IDD1 2.0 mA Unloaded
2.0 mA VDD2 = 3.6 V, half duplex configuration,
RTERMINATION = 120 Ω, see Figure 20
Power Supply Current, Bus Side
TxD/RxD Data Rate = 500 kbps IDD2 3.0 mA Unloaded
40 mA VDD2 = 3.6 V, half duplex configuration,
RTERMINATION = 120 Ω, see Figure 20
DRIVER
Differential Outputs
Differential Output Voltage |VOD| 2.0 3.6 V Loaded, RL = 100 Ω (RS-422), see
Figure 14
1.5
3.6
V
R
L
= 54 Ω (RS-485), see Figure 14
1.5 3.6 V −7 V ≤ VTEST ≤ 12 V, see Figure 15
∆|VOD| for Complementary Output States ∆|VOD| 0.2 V RL = 54 Ω or 100 Ω, see Figure 14
Common-Mode Output Voltage VOC 3.0 V RL = 54 Ω or 100 Ω, see Figure 14
∆|VOC| for Complementary Output States ∆|VOC| 0.2 V RL = 54 Ω or 100 Ω, see Figure 14
Output Leakage Current (Y, Z Pins) IO 30 µA DE = 0 V, VDD2 = 0 V or 3.3 V, VIN = 12 V
−30 µA DE = 0 V, VDD2 = 0 V or 3.3 V, VIN = −7 V
Short-Circuit Output Current IOS 250 mA
Logic Inputs (DE, RE, TxD)
Input Threshold Low VIL 0.25 × VDD1 V
Input Threshold High VIH 0.7 × VDD1 V
Input Current II −10 +0.01 +10 µA
RECEIVER
Differential Inputs
Differential Input Threshold Voltage VTH −200 −125 −30 mV −7 V < VCM < +12 V
Input Voltage Hysteresis VHYS 15 mV VOC = 0 V
Input Current (A, B) II 125 µA DE = 0 V, VDD = 0 V or 3.6 V, VIN = 12 V
−100 µA DE = 0 V, VDD = 0 V or 3.6 V, VIN = −7 V
Line Input Resistance RIN 96 kΩ −7 V < VCM < +12 V
Tristate Leakage Current IOZR ±1 µA VDD1 = 5 V, 0 V < VOUT < VDD1
Logic Outputs
Output Voltage Low VOLRxD 0.2 0.4 V IORxD = 1.5 mA, VA − VB = −0.2 V
Output Voltage High VOHRxD VDD1 − 0.3 VDD1 − 0.2 V IORxD = −1.5 mA, VA − VB = +0.2 V
Short-Circuit Current 100 mA
COMMON-MODE TRANSIENT IMMUNITY1 25 kV/µs VCM = 1 kV, transient magnitude = 800 V
1 CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential
difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates
apply to both rising and falling common-mode voltage edges.
ADM2484E Data Sheet
Rev. G | Page 4 of 16
TIMING SPECIFICATIONS
TA = −40°C to +85°C.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DRIVER
Propagation Delay tDPLH, tDPHL 250 700 ns RL = 54 Ω, CL1 = C L2 = 100 pF, see Figure 16 and Figure 21
Differential Driver Output Skew
(tDPLH − tDPHL)
tDSKEW 100 ns RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and Figure 21
Rise Time/Fall Time tDR, tDF 200 450 1100 ns RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and Figure 21
Enable Time
t
ZL
, t
ZH
1.5
µs
R
L
= 110 Ω, C
L
= 50 pF, see Figure 18 and Figure 22
Disable Time tLZ, tHZ 200 ns RL = 110 Ω, CL = 50 pF, see Figure 18 and Figure 22
RECEIVER
Propagation Delay
t
PLH
, t
PHL
200
ns
C
L
= 15 pF, see Figure 17 and Figure 23
Pulse Width Distortion,
PWD = |tPLH − tPHL|
tPWD 30 ns CL = 15 pF, see Figure 17 and Figure 23
Enable Time tZL, tZH 13 ns RL = 1 kΩ, CL = 15 pF, see Figure 19 and Figure 24
Disable Time tLZ, tHZ 13 ns RL = 1 kΩ, CL = 15 pF, see Figure 19 and Figure 24
PACKAGE CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
RESISTANCE
Resistance (Input-to-Output)1 RI-O 1012 Ω
CAPACITANCE
Capacitance (Input-to-Output)1 CI-O 3 pF f = 1 MHz
Input Capacitance2 CI 4 pF
THERMAL RESISTANCE
Input IC Junction-to-Case θJCI 33 °C/W Thermocouple located at center of package underside
Output IC Junction-to-Case θJCO 28 °C/W
1 Device considered a 2-terminal device: Pin 1 to Pin 8 are shorted together and Pin 9 to Pin16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
Table 4.
UL1 CSA VDE2
UL 1577 Component
Recognition Program
Approved under CSA Component Acceptance Notice 5A,
CSA 60950-1-07+A1+A2 and IEC 60950-1 second edition +A1+A2:
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-122
Basic insulation at 780 V rms (1103 V peak)
Reinforced insulation at 390 V rms (552 V peak)
CSA 61010-1-12+A1 and IEC 61010-1 third edition:
Basic 600 V rms, Overvoltage Category III
Reinforced 300 V rms, Overvoltage Category III
5000 V rms Isolation Voltage
Reinforced insulation, 849 V
PEAK
1 In accordance with UL1577, each ADM2484E is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 µA).
2 In accordance with DIN V VDE V 0884-10, each ADM2484E is proof tested by applying an insulation test voltage ≥ 1590 VPEAK for 1 second (partial discharge detection
limit = 5 pC).
Data Sheet ADM2484E
Rev. G | Page 5 of 16
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage
5000
V rms
1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.7 mm min Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.6 mm min Measured from input terminals to output
terminals, shortest distance along body
Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index)
CTI
>400
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
VDE 0884 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured
by means of protective circuits. An asterisk (*) on a package denotes VDE 0884 approval for 849 VPEAK working voltage.
Table 6.
Description Conditions Symbol Characteristic Unit
CLASSIFICATIONS
Installation Classification per DIN VDE 0110 for Rated
Mains Voltage
≤300 V rms I to IV
≤450 V rms I to II
≤600 V rms I to II
Climatic Classification 40/105/21
Pollution Degree DIN VDE 0110, see Table 1 2
VOLTAGE
Maximum Working Insulation Voltage VIORM 849 VPEAK
Input-to-Output Test Voltage VPR
Method b1 VIORM × 1.875 = VPR, 100% production tested,
tm = 1 sec, partial discharge < 5 pC
1590 VPEAK
Method a
After Environmental Tests, Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, partial
discharge < 5 pC
1357 VPEAK
After Input and/or Safety Test,
Subgroup 2/Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial
discharge < 5 pC
1018 VPEAK
Highest Allowable Overvoltage (Transient overvoltage, tTR = 10 sec) VTR 6000 VPEAK
SAFETY-LIMITING VALUES Maximum value allowed in the event of a
failure, see Figure 9
Case Temperature TS 150 °C
Input Current IS, INPUT 265 mA
Output Current IS, OUTPUT 335 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
ADM2484E Data Sheet
Rev. G | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Each voltage is relative to its
respective ground.
Table 7.
Parameter Rating
V
DD1
−0.5 V to +7 V
VDD2 −0.5 V to +6 V
Logic Input Voltages −0.5 V to VDD1 + 0.5 V
Bus Terminal Voltages −9 V to +14 V
Logic Output Voltages −0.5 V to VDD1 + 0.5 V
Average Output Current per Pin ±35 mA
ESD (Human Body Model) on A, B, Y,
and Z Pins
±15 kV
Storage Temperature Range −55°C to +150°C
Ambient Operating Temperature Range −40°C to +85°C
θJA Thermal Impedance 73°C/W
T
J
Junction Temperature
110°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination.
Table 8. Maximum Continuous Working Voltage1
Parameter Max Unit Reference Standard
AC Voltage
Bipolar Waveform
Basic Insulation 565 VPEAK 50-year minimum
lifetime
Reinforced Insulation 565 VPEAK 50-year minimum
lifetime
Unipolar Waveform
Basic Insulation
1131
V
PEAK 50-year minimum
lifetime
Reinforced Insulation 864 VPEAK Lifetime limited by
package creepage
maximum approved
working voltage per
IEC 60950-1
DC Voltage
Basic Insulation 1066 VPEAK Lifetime limited by
package creepage
maximum approved
working voltage per
IEC 60950-1
Reinforced Insulation 529 VPEAK Lifetime limited by
package creepage
maximum approved
working voltage per
IEC 60950-1
1 Refers to continuous voltage magnitude imposed across the isolation
barrier.
ESD CAUTION
Data Sheet ADM2484E
Rev. G | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1
GND12
RxD 3
RE 4
VDD2
16
GND2
15
A
14
B
13
DE 5
Z
12
TxD
6
Y
11
NC
7
NC
10
GND
18
GND
2
9
NC = NO CONNECT
ADM2484E
TOP VIEW
(No t t o Scal e)
06984-002
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Power Supply (Logic Side). Decoupling capacitor to GND1 required; capacitor value should be between 0.01 µF and 0.1 µF.
2 GND1 Ground (Logic Side).
3
RxD
Receiver Output.
4 RE Receiver Enable Input. Active low logic input. When this pin is low, the receiver is enabled; when this pin is high, the
receiver is disabled.
5 DE Driver Enable Input. Active high logic input. When this pin is high, the driver (transmitter) is enabled; when this pin
is low, the driver is disabled.
6 TxD Transmit Data.
7
NC
No Connect. This pin must be left floating.
8 GND1 Ground (Logic Side).
9 GND2 Ground (Bus Side).
10 NC No Connect. This pin must be left floating.
11 Y Driver Noninverting Output.
12 Z Driver Inverting Output.
13 B Receiver Inverting Input.
14 A Receiver Noninverting Input.
15 GND2 Ground (Bus Side).
16 VDD2 Power Supply (Bus Side). Decoupling capacitor to GND2 required; capacitor value should be between 0.01 µF and 0.1 µF.
ADM2484E Data Sheet
Rev. G | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
1.4
0
–40 –20 020 40 60 80
06984-033
TEMPERATURE (°C)
I
DD1
SUPPLY CURRE NT (mA)
1.2
1.0
0.8
0.6
0.4
0.2
NO LOAD
54Ω LOAD
100Ω LOAD
DATA RATE = 500kbp s
Figure 3. IDD1 Supply Current vs. Temperature (See Figure 20)
45
0
–40 –20 020 40 60 80
06984-034
TEMPERATURE (°C)
I
DD2
SUPPLY CURRE NT (mA)
40
35
30
25
20
15
10
5
NO LOAD
100Ω LOAD
54Ω LOAD
DATA RATE = 500kbp s
Figure 4. IDD2 Supply Current vs. Temperature (See Figure 20)
600
0
–40 –20 020 40 60 80
06984-032
TEMPERATURE (°C)
DELAY ( ns)
500
400
300
200
100
t
DPLH
t
DPHL
Figure 5. Driver Propagation Delay vs. Temperature
100
0
–40 –20 020 40 60 80
06984-035
TEMPERATURE (°C)
DELAY ( ns)
90
80
70
60
50
40
30
20
10
t
PHL
t
PLH
Figure 6. Receiver Propagation Delay vs. Temperature
06984-031
CH1 2.00V CH2 2.00V
CH3 2.00V CH4 2.00V M 200n s A CH2 1. 72V
2
4
1
T 47.80%
TxD
Z, B
T
Y, A
RxD
Figure 7. Driver/Receiver Propagation Delay, Low to High
(RL = 54 Ω, CL1 = CL2 = 100 pF)
06984-030
CH1 2.00V CH2 2.00V
CH3 2.00V CH4 2.00V M 200n s A CH2 1.72V
2
4
1
T 48.60%
TxD
Y, A
RxD
Z, B
T
Figure 8. Driver/Receiver Propagation Delay, High to Low
(RL = 54 Ω, CL1 = CL2 = 100 pF)
Data Sheet ADM2484E
Rev. G | Page 9 of 16
CASE TEMPERATURE ( °C)
SAFETY-LIMITING CURRE NT (mA)
0
0
350
300
250
200
150
100
50
50 100 150 200
SIDE 1
SIDE 2
06984-016
Figure 9. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per VDE 0884
–14
–12
–10
–8
–6
–4
–2
0
4.0 4.2 4.4 4.6 4.8 5.0
VOLTAGE (V)
CURRENT (mA)
06984-017
Figure 10. Output Current vs. Receiver Output High Voltage
0
2
4
6
8
10
12
14
16
00.2 0.4 0.6 0.8 1.0 1.2
VOLTAGE (V)
CURRENT (mA)
06984-018
Figure 11. Output Current vs. Receiver Output Low Voltage
4.66
4.67
4.68
4.70
4.72
4.74
4.69
4.71
4.73
4.75
4.76
4.77
–40 –20 020 40 60 80 100
TEMPERAT URE ( °C)
VOLTAGE (V)
06984-019
Figure 12. Receiver Output High Voltage vs. Temperature, IRxD = −4 mA
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
–40 –20 020 40 60 80 100
TEMPERAT URE ( °C)
VOLTAGE (V)
06984-022
Figure 13. Receiver Output Low Voltage vs. Temperature, IRxD = +4 mA
ADM2484E Data Sheet
Rev. G | Page 10 of 16
TEST CIRCUITS
V
OC
V
OD
R
L
2
R
L
2
06984-003
Figure 14. Driver Voltage Measurement
60Ω
VOD
375Ω
375Ω
VTEST
06984-004
Figure 15. Driver Voltage Measurement
C
L2
C
L1
R
L
Y
Z
06984-006
Figure 16. Driver Propagation Delay
CL
VOUT
A
B
06984-007
Figure 17. Receiver Propagation Delay
Y
S1 R
L
0V OR 3V
Z
DE
S2
V
CC
V
OUT
C
L
06984-008
Figure 18. Driver Enable/Disable
C
L
V
OUT
R
L
S2
V
CC
+1.5V
S1
–1.5V
RE IN
RE
06984-009
Figure 19. Receiver Enable/Disable
GALVANIC ISOLATION
VDD1
GND1
VDD2
VDD2
GND2
Y
Z
TxD
DE
A
B
RxD
RE
120Ω
06984-005
Figure 20. Supply Current Measurement Test Circuit
Data Sheet ADM2484E
Rev. G | Page 11 of 16
SWITCHING CHARACTERISTICS
t
DPHL
t
DPLH
V
DD1
0V
V
O
Z
Y
+V
O
V
DIFF
–V
O
V
DD1
/2 V
DD1
/2
t
DF
t
DR
10% POINT 10% POINT
90% POINT 90% POINT
1/2V
O
VDIFF = V(Y) – V(Z)
06984-010
Figure 21. Driver Propagation Delay, Rise/Fall Timing
DE
2.3V
0.5V
DD1
V
OH
0V
V
OL
V
OH
– 0.5V
V
DD1
0V
V
OL
+ 0.5V
0.5V
DD1
2.3V
Y, Z
Y, Z
tZL
tZH
tLZ
tHZ
06984-011
Figure 22. Driver Enable/Disable Delay
A, B
RxD
0V 0V
1.5V 1.5V
t
PLH
t
PHL
V
OH
V
OL
06984-012
Figure 23. Receiver Propagation Delay
V
OH
V
OL
V
OH
– 0.5V
V
DD1
0V
0V
V
OL
+ 0.5V
RE
RxD
RxD
0V
OUTPUT LOW
OUTPUT HIGH
1.5V
0.5V
DD1
1.5V
tZL
tZH
0.5V
DD1
tLZ
tHZ
06984-013
Figure 24. Receiver Enable/Disable Delay
ADM2484E Data Sheet
Rev. G | Page 12 of 16
CIRCUIT DESCRIPTION
ELECTRICAL ISOLATION
In the ADM2484E, electrical isolation is implemented on the
logic side of the interface. Therefore, the part has two main
sections: a digital isolation section and a transceiver section
(see Figure 25). The driver input signal, which is applied to the
TxD pin and referenced to the logic ground (GND1), is coupled
across an isolation barrier to appear at the transceiver section
referenced to the isolated ground (GND2). Similarly, the receiver
input, which is referenced to the isolated ground in the transceiver
section, is coupled across the isolation barrier to appear at the
RxD pin referenced to the logic ground.
iCoupler Technology
The digital signals transmit across the isolation barrier using
iCoupler technology. This technique uses chip scale transformer
windings to couple the digital signals magnetically from one
side of the barrier to the other. Digital inputs are encoded into
waveforms that are capable of exciting the primary transformer
winding. At the secondary winding, the induced waveforms are
decoded into the binary value that was originally transmitted.
Positive and negative logic transitions at the input cause narrow
(approximately 1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, set or reset
by the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than approximately 1 μs,
a periodic set of refresh pulses, indicative of the correct input
state, are sent to ensure dc correctness at the output. If the
decoder receives no internal pulses for more than about 5 μs,
then the input side is assumed to be unpowered or nonfunctional,
in which case the output is forced to a default state (see Table 11).
ISOLATION
BARRIER
VDD2
VDD1
A
B
GND2
GND1
DE
RxD
RE
ENCODE
DECODE
DECODE
ENCODE
R
TRANSCEIVER
DIGITAL ISOLATION
Y
Z
TxD DECODEENCODE D
06984-023
Figure 25. Digital Isolation and Transceiver Sections
TRUTH TABLES
The truth tables in this section use the abbreviations shown
in Tabl e 10.
Table 10. Truth Table Abbreviations
Letter Description
H High level
L Low level
I
Indeterminate
X Irrelevant
Z High impedance (off)
NC Disconnected
Table 11. Transmitting
Supply Status Inputs Outputs
VDD1 VDD2 DE TxD Y Z
On On H H H L
On On H L L H
On On L X Z Z
On
Off
X
X
Z
Z
Off On L X Z Z
Off Off X X Z Z
Table 12. Receiving
Supply Status Inputs Output
VDD1 VDD2 A − B (V) RE RxD
On On > −0.03 L or NC H
On On < −0.2 L or NC L
On On −0.2 < A − B < −0.03 L or NC I
On On Inputs open L or NC H
On On X H Z
On Off X L or NC H
Off Off X L or NC L
Data Sheet ADM2484E
Rev. G | Page 13 of 16
THERMAL SHUTDOWN
The ADM2484E contains thermal shutdown circuitry that
protects the part from excessive power dissipation during fault
conditions. Shorting the driver outputs to a low impedance
source can result in high driver currents. The thermal sensing
circuitry detects the increase in die temperature under this
condition and disables the driver outputs. This circuitry is
designed to disable the driver outputs when a die temperature
of 150°C is reached. As the device cools, the drivers re-enable at
a temperature of 140°C.
TRUE FAIL-SAFE RECEIVER INPUTS
The receiver inputs have a true fail-safe feature ensuring that
the receiver output is high when the inputs are open or shorted.
During line-idle conditions, when no driver on the bus is enabled,
the voltage across a terminating resistor at the receiver input decays
t o 0 V. Wi t h t r a ditional transceivers, receiver input thresholds
specified between −200 mV and +200 mV mean that external
bias resistors are required on the A and B pins to ensure that the
receiver outputs are in a known state. The true fail-safe receiver
input feature eliminates the need for bias resistors by specifying
the receiver input threshold between −30 mV and −200 mV.
The guaranteed negative threshold means that when the voltage
between A and B decays to 0 V; the receiver output is guaran-
teed to be high.
MAGNETIC FIELD IMMUNITY
The limitation on the magnetic field immunity of the iCoupler
is set by the condition in which an induced voltage in the receiving
coil of the transformer is large enough to either falsely set or reset
the decoder. The following analysis defines the conditions under
which this may occur. The 3 V operating condition of the
ADM2484E is examined because it represents the most
susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
then 1 V. The decoder has a sensing threshold of about 0.5 V,
thus establishing a 0.5 V margin in which induced voltages can
be tolerated.
The voltage induced across the receiving coil is given by
∑
π
β−
=
2
n
r
dt
d
V
;
Nn ,...,2,1=
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil and an imposed
requirement that the induced voltage is, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic
field can be determined using Figure 26.
MAG NETI C FI E LD FRE QUENCY ( Hz )
1k 10k 100k 100M1M 10M
100
10
1
0.1
0.01
0.001
MAXIMUM ALLOWABLE MAGNETIC
FLUX DENSITY (kGAUSS)
06984-024
Figure 26. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse and
is the worst-case polarity, it reduces the received pulse from
>1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of
the decoder.
Figure 27 shows the magnetic flux density values in terms of
more familiar quantities, such as maximum allowable current
flow at given distances away from the ADM2484E transformers.
MAG NETI C FI E LD FRE QUENCY ( Hz )
1k 10k 100k 100M1M 10M
DISTANCE = 1m
DISTANCE = 100mm
DISTANCE = 5mm
1000
100
0.1
1
10
0.01
MAXI MUM AL LO WABLE CURRE NT (kA)
06984-025
Figure 27. Maximum Allowable Current for
Various Current-to-ADM2484E Spacings
With combinations of strong magnetic field and high frequency,
any loops formed by PCB traces can induce error voltages large
enough to trigger the thresholds of succeeding circuitry. Take care
in the layout of such traces to avoid this possibility.
ADM2484E Data Sheet
Rev. G | Page 14 of 16
APPLICATIONS INFORMATION
ISOLATED POWER SUPPLY CIRCUIT
The ADM2484E requires isolated power capable of 3.3 V at up
to approximately 75 mA (this current is dependent on the data
rate and termination resistors used) to be supplied between the
VDD2 and the GND2 pins. A transformer driver circuit with a
center tapped transformer and LDO can be used to generate the
isolated 5 V supply, as shown in Figure 28. The center tapped
transformer provides electrical isolation of the 5 V power
supply. The primary winding of the transformer is excited with
a pair of square waveforms that are 180° out of phase with each
other. A pair of Schottky diodes and a smoothing capacitor are
used to create a rectified signal from the secondary winding.
The ADP3330 linear voltage regulator provides a regulated
power supply to the bus-side circuitry (VDD2) of the ADM2484E.
+IN OUT
SD
ERR
NR GND
ADP3330
V
CC
V
CC
V
CC
+
3.3V
10µF
22µF
ADM2484E
V
DD1
V
DD2
GND
1
GND
2
SD103C
SD103C
78253
ISOLATION
BARRIER
TRANSFORMER
DRIVER
06984-026
Figure 28. Isolated Power Supply Circuit
PC BOARD LAYOUT
The ADM2484E isolated RS-485 transceiver requires no external
interface circuitry for the logic interfaces. Power supply bypassing
is required at the input and output supply pins (see Figure 29).
Bypass capacitors are conveniently connected between Pin 1
and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2.
Best practice suggests the following:
• A capacitor value between 0.01 µF and 0.1 µF.
• A total lead length between both ends of the capacitor and
the input power supply pin that does not exceed 20 mm.
• Unless the ground pair on each package side is connected
close to the package, consider bypassing between Pin 1 and
Pin 8 and between Pin 9 and Pin 16.
V
DD1
GND
1
RxD
RE
DE
TxD
NC
GND
1
V
DD2
GND
2
A
B
Z
Y
NC
GND
2
NC = NO CONNECT
ADM2484E
06984-027
Figure 29. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this could cause voltage differentials between pins
exceeding the absolute maximum ratings of the device, thereby
leading to latch-up or permanent damage.
Data Sheet ADM2484E
Rev. G | Page 15 of 16
TYPICAL APPLICATIONS
Figure 30 and Figure 31 show typical applications of the
ADM2484E in half-duplex and full-duplex RS-485 network
configurations. Up to 256 transceivers can be connected to the
RS-485 bus. To minimize reflections, the line must be terminated
at the receiving end in its characteristic impedance, and stub
lengths off the main line must be kept as short as possible. For
half-duplex operation, this means that both ends of the line must be
terminated, because either end can be the receiving end.
NOTES
1. R
T
IS E QUAL TO THE CHARACT E RISTIC IMP E DANCE OF THE CABLE.
2. ISOLATION NOT SHOWN.
06984-028
ADM2484E
RxD DE TxD
ABZY
ADM2484E
RxD DE TxD
A B Z Y
ADM2484E
ADM2484E
A
B
Z
Y
A
B
Z
Y
R
T
RDRD
R
D
R
D
R
T
RxD
DE
TxD
RxD
DE
TxD
MAXI MUM NUMBE R OF TRANSCEIVE RS ON BUS = 256
RE
RE
RE RE
Figure 30. ADM2484E Typical Half-Duplex RS-485 Network
06984-029
R
D
RxD
RE
TxD
DE
ADM2484E
ADM2484E
A
B
Z
Y
RD
RxD TxDDE
A B Z Y
RE
R
D
RxD
TxD
DE
ADM2484E
MASTER SLAVE
SLAVE
A
B
Z
Y
RE
MAXI MUM NUMBE R OF NODES = 256
ADM2484E
RD
RxD TxDDE
A B Z Y
RE
SLAVE
NOTES
1. R
T
IS E QUAL TO THE CHARACT E RISTIC IMP E DANCE OF THE CABLE.
R
T
R
T
Figure 31. ADM2484E Typical Full Duplex RS-485 Network
ADM2484E Data Sheet
Rev. G | Page 16 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50(0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40(
0.0157)
COPLANARITY
0.100.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27(0.0500)
BSC
03-27-2007-B
Figure 32. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM2484EBRWZ −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
ADM2484EBRWZ-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
EVAL-ADM2484EEBZ Evaluation Board
1 Z = RoHS Compliant Part.
©2008–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06984-0-5/18(G)
