1
2
3
4
5
6
7
8
ISO7240
9
10
11
12
13
14
15
16
NC
IN
A
GND1
V
CC1
GND1
GND2
GND2
IN
B
IN
C
OUT
A
OUT
C
OUT
B
EN
V
CC2
IN
D
OUT
D
1
2
3
4
5
6
7
8
ISO7241
9
10
11
12
13
14
15
16
IN
A
GND1
V
CC1
GND1
GND2
GND2
IN
B
IN
C
OUT
A
OUT
C
OUT
B
V
CC2
IN
D
OUT
D
EN
2
EN
1
1
2
3
4
5
6
7
8
ISO7242
9
10
11
12
13
14
15
16
IN
A
GND1
V
CC1
GND1
GND2
GND2
IN
B
OUT
A
OUT
B
V
CC2
IN
D
OUT
D
EN
2
EN
1
OUT
C
IN
C
DISABLE
IN
A
GND1
V
CC1
GND1
IN
B
IN
C
IN
D
GND2
GND2
OUT
A
OUT
C
OUT
B
CTRL
V
CC2
OUT
D
ISO7240CF
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
HIGH SPEED QUAD DIGITAL ISOLATORS
Check for Samples: ISO7240CF,ISO7240C,ISO7240M,ISO7241C,ISO7241M,ISO7242C,ISO7242M
1FEATURES
Selectable Failsafe Output (ISO7240CF) 4 kV ESD Protection
25 and 150-Mbps Signaling Rate Options Operates With 2.8-V (ISO7241C), 3.3-V or 5-V
Supplies
Low Channel-to-Channel Output Skew;
High Electromagnetic Immunity
1 ns Max (see application report SLLA181)
Low Pulse-Width Distortion (PWD); 40°C to 125°C Operating Range
2 ns Max
Low Jitter Content; 1 ns Typ at 150 Mbps APPLICATIONS
Typical 25-Year Life at Rated Working Voltage Industrial Fieldbus
(see application note SLLA197 and Figure 17)Computer Peripheral Interface
4000-Vpeak VIOTM, 560-Vpeak VIORM per IEC Servo Control Interface
60747-5-2 (VDE 0884, Rev 2)
Data Acquisition
UL 1577 , IEC 61010-1, IEC 60950-1 and CSA
Approved
DESCRIPTION
The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations and
output enable functions. These devices have logic input and output buffers separated by TIs silicon dioxide
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,
isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging
sensitive circuitry.
The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same
direction and one channel in opposition. The ISO7242 has two channels in each direction.
The C option devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from
being passed to the output of the device. The M option devices have CMOS Vcc/2 input thresholds and do not
have the input noise-filter or the additional propagation delay.
The ISO7240CF has an input disable function on pin 7, and a selectable high or low failsafe-output function with
the CTRL pin (pin 10). The failsafe-output is a logic high when a logic-high is placed on the CTRL pin or it is left
unconnected. If a logic-low signal is applied to the CTRL pin, the failsafe-output becomes a logic-low output
state. The ISO7240CF input disable function prevents data from being passed across the isolation barrier to the
output. When the inputs are disabled, the outputs are set by the CTRL pin.
These devices may be powered from 2.8-V (ISO7241C only), 3.3-V or 5-V supplies on either side in any
combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supply level being used.
These devices are characterized for operation over the ambient temperature range of 40°C to 125°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©20072012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. Device Function Table ISO724x (1)
INPUT OUTPUT ENABLE OUTPUT
INPUT VCC OUTPUT VCC (IN) (EN) (OUT)
H H or Open H
L H or Open L
PU PU X L Z
Open H or Open H
PD PU X H or Open H
PD PU X L Z
(1) PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
Table 2. ISO7240CF Function Table
VCC1 VCC2 DATA INPUT DISABLE INPUT FAILSAFE CONTROL INPUT DATA OUTPUT
(IN) (DISABLE) (CTRL) (OUT)
PU PU H L or Open X H
PU PU L L or Open X L
X PU X H H or Open H
X PU X H L L
PD PU X X H or Open H
PD PU X X L L
AVAILABLE OPTIONS
SIGNALING INPUT CHANNEL MARKED ORDERING
PRODUCT RATE THRESHOLD CONFIGURATION AS NUMBER(1)
ISO7240CDW (rail)
~1.5 V (TTL)
ISO7240C 25 Mbps ISO7240C
(CMOS compatible) ISO7240CDWR (reel)
ISO7240CFDW (rail)
~1.5 V (TTL)
ISO7240CF 25 Mbps 4/0 ISO7240CF
(CMOS compatible) ISO7240CFDWR (reel)
ISO7240MDW (rail)
ISO7240M 150 Mbps Vcc/2 (CMOS) ISO7240M ISO7240MDWR (reel)
ISO7241CDW (rail)
~1.5 V (TTL)
ISO7241C 25 Mbps ISO7241C
(CMOS compatible) ISO7241CDWR (reel)
3/1 ISO7241MDW (rail)
ISO7241M 150 Mbps Vcc/2 (CMOS) ISO7241M ISO7241MDWR (reel)
ISO7242CDW (rail)
~1.5 V (TTL)
ISO7242C 25 Mbps ISO7242C
(CMOS compatible) ISO7242CDWR (reel)
2/2 ISO7242MDW (rail)
ISO7242M 150 Mbps Vcc/2 (CMOS) ISO7242M ISO7242MDWR (reel)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
2Copyright ©20072012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
VCC Supply voltage(2), VCC1, VCC2 0.5 to 6 V
VIVoltage at IN, OUT, EN, DISABLE, CTRL 0.5 to 6 V
IOOutput current ±15 mA
Human Body Model JEDEC Standard 22, Test Method A114-C.01 ±4kV
Electrostatic
ESD Field-Induced-Charged Device Model JEDEC Standard 22, Test Method C101 All pins ±1
discharge Machine Model ANSI/ESDS5.2-1996 ±200 V
TJMaximum junction temperature 170 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
ISO7240C/CF, ISO7242C, 3.15 5.5
ISO724xM,
VCC Supply voltage(1), VCC1, VCC2 V
ISO7241C 2.8 5.5
IOH High-level output current -4 mA
IOL Low-level output current 4 mA
ISO724xC 40
tui Input pulse width ns
ISO724xM 6.67 5
ISO724xC 0 30(2) 25
1/tui Signaling rate Mbps
ISO724xM 0 200(2) 150
VIH High-level input voltage (IN) 0.7 VCC VCC V
ISO724xM
VIL Low-level input voltage (IN) 0 0.3 VCC V
VIH High-level input voltage (IN, DISABLE, CTRL, EN) 2 VCC V
ISO724xC
VIL Low-level input voltage (IN, DISABLE, CTRL, EN) 0 0.8 V
TJJunction temperature 150 °C
H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification 1000 A/m
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
For the 2.8-V operation (ISO7241C-only), VCC1 or VCC2 is specified at 2.8 V.
(2) Typical value at room temperature and well-regulated power supply.
IEC 60747-5-2 INSULATION CHARACTERISTICS(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS SPECIFICATIONS UNIT
VIORM Maximum working insulation voltage 560 V
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM ×1.2, t = 10 s, 672 V
Partial discharge <5 pC
Method a, VPR = VIORM ×1.6,
VPR Input to output test voltage Type and sample test with t = 10 s, 896 V
Partial discharge <5 pC
Method b1, VPR = VIORM ×1.875,
100 % Production test with t = 1 s, 1050 V
Partial discharge <5 pC
VIOTM Transient overvoltage t = 60 s 4000 V
RSInsulation resistance VIO = 500 V at TS
>109
Pollution degree 2
(1) Climatic Classification 40/125/21
Copyright ©20072012, Texas Instruments Incorporated 3
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Quiescent VI= VCC or 0 V 1 3
All channels, no load,
ISO7240C/M mA
EN at 3 V
25 Mbps 12.5 MHz Input Clock Signal 7 10.5
Quiescent VI= VCC or 0 V- 6.5 11
All channels, no load,
ICC1 ISO7241C/M mA
EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 12 18
Quiescent VI= VCC or 0 V 10 16
All channels, no load,
ISO7242C/M mA
EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 15 24
Quiescent VI= VCC or 0 V- 15 22
All channels, no load,
ISO7240C/M mA
EN at 3 V
25 Mbps 12.5 MHz Input Clock Signal 17 25
Quiescent VI= VCC or 0 V 13 20
All channels, no load,
ICC2 ISO7241C/M mA
EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 18 28
Quiescent VI= VCC or 0 V 10 16
All channels, no load,
ISO7242C/M mA
EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 15 24
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current EN at 0 V, Single channel 0 μA
IOH =4 mA, See Figure 1 VCC0.8
VOH High-level output voltage V
IOH =20 μA, See Figure 1 VCC0.1
IOL = 4 mA, See Figure 1 0.4
VOL Low-level output voltage V
IOL = 20 μA, See Figure 1 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V to VCC μA
IIL Low-level input current 10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 2 pF
Common-mode transient VI= VCC or 0 V, See Figure 5
CMTI 25 50 kV/μs
immunity
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
4Copyright ©20072012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay 18 42
ISO724xC ns
PWD Pulse-width distortion(1) |tPHL tPLH| 2.5
See Figure 1
tPLH, tPHL Propagation delay 10 23
ISO724xM ns
PWD Pulse-width distortion(1) |tPHL tPLH| 1 2
ISO724xC 8
tsk(pp) Part-to-part skew (2) ns
ISO724xM 0 3
ISO724xC 2
tsk(o) Channel-to-channel output skew (3) ns
ISO724xM 0 1
trOutput signal rise time 2
See Figure 1 ns
tfOutput signal fall time 2
tPHZ Propagation delay, high-level-to-high-impedance output 15 20
tPZH Propagation delay, high-impedance-to-high-level output 15 20
See Figure 2 ns
tPLZ Propagation delay, low-level-to-high-impedance output 15 20
tPZL Propagation delay, high-impedance-to-low-level output 15 20
tfs Failsafe output delay time from input power loss See Figure 3 12 μs
twake Wake time from input disable See Figure 4 15 μs
150 Mbps NRZ data input, Same
tjit(pp) Peak-to-peak eye-pattern jitter ISO724xM polarity input on all channels, See 1 ns
Figure 6
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright ©20072012, Texas Instruments Incorporated 5
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Quiescent VI= VCC or 0 V 1 3
All channels, no load,
ISO7240C/M mA
12.5 MHz Input Clock 7 10.5
EN at 3 V
25 Mbps Signal
Quiescent VI= VCC or 0 V 6.5 11
All channels, no load,
ICC1 ISO7241C/M EN1at 3 V, mA
12.5 MHz Input Clock 12 18
25 Mbps EN2at 3 V
Signal
Quiescent VI= VCC or 0 V 10 16
All channels, no load,
ISO7242C/M EN1at 3 V, mA
12.5 MHz Input Clock 15 24
25 Mbps EN2at 3 V
Signal
Quiescent VI= VCC or 0 V 9.5 15
All channels, no load,
ISO7240C/M mA
12.5 MHz Input Clock 10.5 17
EN at 3 V
25 Mbps Signal
Quiescent VI= VCC or 0 V 8 13
All channels, no load,
ICC2 ISO7241C/M EN1at 3 V, mA
12.5 MHz Input Clock 11.5 18
25 Mbps EN2at 3 V
Signal
Quiescent VI= VCC or 0 V 6 10
All channels, no load,
ISO7242C/M EN1at 3 V, mA
12.5 MHz Input Clock 9 14
25 Mbps EN2at 3 V
Signal
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current EN at 0 V, Single channel 0 μA
ISO7240 VCC0.4
IOH =4 mA, See Figure 1
VOH High-level output voltage ISO724x (5-V side) VCC0.8 V
IOH =20 μA, See Figure 1 VCC0.1
IOL = 4 mA, See Figure 1 0.4
VOL Low-level output voltage V
IOL = 20 μA, See Figure 1 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V to VCC μA
IIL Low-level input current 10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 2 pF
Common-mode transient VI= VCC or 0 V, See Figure 5
CMTI 25 50 kV/μs
immunity
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
6Copyright ©20072012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay See Figure 1 20 50
ISO724xC ns
PWD Pulse-width distortion(1) |tPHL tPLH| 3
tPLH, tPHL Propagation delay ISO724xM 12 29 ns
PWD Pulse-width distortion(1) |tPHL tPLH| 1 2
ISO724xC 10
tsk(pp) Part-to-part skew (2) ns
ISO724xM 0 5
ISO724xC 3
tsk(o) Channel-to-channel output skew (3) ns
ISO724xM 0 1
trOutput signal rise time 2
See Figure 1 ns
tfOutput signal fall time 2
tPHZ Propagation delay, high-level-to-high-impedance output 15 20
tPZH Propagation delay, high-impedance-to-high-level output 15 20
See Figure 2 ns
tPLZ Propagation delay, low-level-to-high-impedance output 15 20
tPZL Propagation delay, high-impedance-to-low-level output 15 20
tfs Failsafe output delay time from input power loss See Figure 3 18 μs
twake Wake time from input disable See Figure 4 15 μs
150 Mbps PRBS NRZ data
tjit(pp) Peak-to-peak eye-pattern jitter ISO724xM input, Same polarity input on 1 ns
all channels, See Figure 6
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright ©20072012, Texas Instruments Incorporated 7
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Quiescent VI= VCC or 0 V 0.5 1
All channels, no
ISO7240C/M mA
load, EN at 3 V
25 Mbps 12.5 MHz Input Clock Signal 3 5
Quiescent VI= VCC or 0 V All channels, no 4 7
ISO7241C/M load, EN1at 3 V, mA
ICC1 6.5 11
25 Mbps 12.5 MHz Input Clock Signal EN2at 3 V
Quiescent VI= VCC or 0 V All channels, no 6 10
ISO724C/M load, EN1at 3 V, mA
9 14
25 Mbps 12.5 MHz Input Clock Signal EN2at 3 V
Quiescent VI= VCC or 0 V 15 22
All channels, no
ISO7240C/M mA
load, EN at 3 V
25 Mbps 12.5 MHz Input Clock Signal 17 25
Quiescent VI= VCC or 0 V All channels, no 13 20
ISO7241C/M load, EN1at 3 V, mA
ICC2 18 28
25 Mbps 12.5 MHz Input Clock Signal EN2at 3 V
Quiescent VI= VCC or 0 V All channels, no 10 16
ISO7242C/M load, EN1at 3 V, mA
15 24
25 Mbps 12.5 MHz Input Clock Signal EN2at 3 V
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current EN at 0 V, Single channel 0 μA
ISO7240 VCC 0.4
IOH =4 mA, See Figure 1
VOH High-level output voltage ISO724x (5-V side) VCC 0.8 V
IOH =20 μA, See Figure 1 VCC 0.1
IOL = 4 mA, See Figure 1 0.4
VOL Low-level output voltage V
IOL = 20 μA, See Figure 1 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V to VCC μA
IIL Low-level input current 10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 2 pF
Common-mode transient VI= VCC or 0 V, See Figure 5
CMTI 25 50 kV/μs
immunity
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
8Copyright ©20072012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay 22 51
ISO724xC ns
PWD Pulse-width distortion(1) |tPHL tPLH| 3
See Figure 1
tPLH, tPHL Propagation delay 12 30
ISO724xM ns
PWD Pulse-width distortion(1) |tPHL tPLH| 1 2
ISO724xC 10
tsk(pp) Part-to-part skew (2) ns
ISO724xM 0 5
ISO724xC 2.5
tsk(o) Channel-to-channel output skew (3) ns
ISO724xM 0 1
trOutput signal rise time 2
See Figure 1 ns
tfOutput signal fall time 2
tPHZ Propagation delay, high-level-to-high-impedance output 15 20
tPZH Propagation delay, high-impedance-to-high-level output 15 20
See Figure 2 ns
tPLZ Propagation delay, low-level-to-high-impedance output 15 20
tPZL Propagation delay, high-impedance-to-low-level output 15 20
tfs Failsafe output delay time from input power loss See Figure 3 12 μs
twake Wake time from input disable See Figure 4 15 μs
150 Mbps NRZ data input, Same
tjit(pp) Peak-to-peak eye-pattern jitter ISO724xM polarity input on all channels, See 1 ns
Figure 6
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright ©20072012, Texas Instruments Incorporated 9
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Quiescent VI= VCC or 0 V 0.5 1
All channels, no load,
ISO7240C/M mA
EN at 3 V
25 Mbps 12.5 MHz Input Clock Signal 3 5
ISO7241C/M Quiescent VI= VCC or 0 V 4 7
All channels, no load,
ICC1 EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 6.5 11 mA
ISO7242C/M Quiescent VI= VCC or 0 V 6 10
All channels, no load,
EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 9 14
Quiescent VI= VCC or 0 V 9.5 15
All channels, no load,
ISO7240C/M mA
EN at 3 V
25 Mbps 12.5 MHz Input Clock Signal 10.5 17
ISO7241C/M Quiescent VI= VCC or 0 V 8 13
All channels, no load,
ICC2 EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 11.5 18 mA
ISO7242C/M Quiescent VI= VCC or 0 V 6 10
All channels, no load,
EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 9 14
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current EN at 0 V, single channel 0 μA
IOH =4 mA, See Figure 1 VCC0.4
VOH High-level output voltage V
IOH =20 μA, See Figure 1 VCC0.1
IOL = 4 mA, See Figure 1 0.4
VOL Low-level output voltage V
IOL = 20 μA, See Figure 1 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V or VCC μA
IIL Low-level input current 10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 2 pF
CMTI Common-mode transient immunity VI= VCC or 0 V, See Figure 5 25 50 kV/μs
(1) For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
10 Copyright ©20072012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay 25 56
ISO724xC ns
PWD Pulse-width distortion |tPHL tPLH|(1) 4
See Figure 1
tPLH, tPHL Propagation delay 12 34
ISO724xM ns
PWD Pulse-width distortion |tPHL tPLH|(1) 1 2
ISO724xC 10
tsk(pp) Part-to-part skew (2) ns
ISO724xM 0 5
ISO724xC 3.5
tsk(o) Channel-to-channel output skew (3) ns
ISO724xM 0 1
trOutput signal rise time 2 ns
See Figure 1
tfOutput signal fall time 2 ns
tPHZ Propagation delay, high-level-to-high-impedance output 15 20
tPZH Propagation delay, high-impedance-to-high-level output 15 20
See Figure 2 ns
tPLZ Propagation delay, low-level-to-high-impedance output 15 20
tPZL Propagation delay, high-impedance-to-low-level output 15 20
tfs Failsafe output delay time from input power loss See Figure 3 18 μs
twake Wake time from input disable See Figure 4 15 μs
150 Mbps PRBS NRZ data input,
tjit(pp) Peak-to-peak eye-pattern jitter ISO724xM same polarity input on all channels, 1 ns
See Figure 6
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright ©20072012, Texas Instruments Incorporated 11
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 2.8 V (ISO7241C only)(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
Quiescent VI= VCC or 0 V 3.9 6.8
All channels, no load,
ICC1 ISO7241C mA
EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 6.2 10.5
Quiescent VI= VCC or 0 V 6.9 12
All channels, no load,
ICC2 ISO7241C mA
EN1at 3 V, EN2at 3 V
25 Mbps 12.5 MHz Input Clock Signal 9.4 16
ELECTRICAL CHARACTERISTICS
IOFF Sleep mode output current EN1at 0 V, single channel 0 μA
IOH =4 mA, See Figure 1 VCC0.6
VOH High-level output voltage V
IOH =20 μA, See Figure 1 VCC0.1
IOL = 4 mA, See Figure 1 0.6
VOL Low-level output voltage V
IOL = 20 μA, See Figure 1 0.1
VI(HYS) Input voltage hysteresis 150 mV
IIH High-level input current 10
IN from 0 V or VCC μA
IIL Low-level input current 10
CIInput capacitance to ground IN at VCC, VI= 0.4 sin (4E6πt) 2 pF
CMTI Common-mode transient immunity VI= VCC or 0 V, See Figure 5 10 45 kV/μs
(1) For the 2.8-V operation, VCC1 or VCC2 is specified at 2.8-V.
2.8-V operation is only guaranteed for ISO7241C with production screening starting in January 2012. The first two digits of the Lot Trace
Code (YMLLLLS) written on top of each device can be used to identify year and month of production respectively.
12 Copyright ©20072012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 2.8-V OPERATION (ISO7241C only)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay 25 70
ISO7241C See Figure 1 ns
PWD Pulse-width distortion |tPHL tPLH|(1) 5
tsk(pp) Part-to-part skew (2) ISO7241C 12 ns
tsk(o) Channel-to-channel output skew (3) ISO7241C 5 ns
trOutput signal rise time 2 ns
See Figure 1
tfOutput signal fall time 2 ns
tPHZ Propagation delay, high-level-to-high-impedance output 15 25
tPZH Propagation delay, high-impedance-to-high-level output 15 25
See Figure 2 ns
tPLZ Propagation delay, low-level-to-high-impedance output 15 25
tPZL Propagation delay, high-impedance-to-low-level output 15 25
tfs Failsafe output delay time from input power loss See Figure 3 7μs
twake Wake time from input disable See Figure 4 12 μs
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright ©20072012, Texas Instruments Incorporated 13
IN OUT
VOCL
Input
Generator 50 W
VI
NOTE A NOTE B
V /2
CC
tf
tr
10%
90%
50%
0 V
50%
VI
tPLH tPHL
VOH
VOL
ISOLATION BARRIER
VO
V /2
CC
VCC
Input
Generator 50 W
OUT
EN
VO
VI
IN
0V
ISOLATION BARRIER
CL
NOTE A
NOTE
B
Vcc
Input
Generator
OUT
R = 1 k ±1%
LW
EN
VO
VI
IN
3V
ISOLATION BARRIER
CL
NOTE A
NOTE
B
0 V
0 V
VI
50% 0.5 V
tPHZ
tPZH
VO
VCC
0 V
tPLZ
t
VO
VI
0.5 V
VOL
50%
PZL
R = 1 k ±1%
LW
50 W
VCC/2
VOH
VCC/2
VCC/2
VCC
VCC/2
VCC
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
A. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr3
ns, tf3 ns, ZO= 50.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr3
ns, tf3 ns, ZO= 50.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
14 Copyright ©20072012, Texas Instruments Incorporated
tfs
IN OUT
ISOLATION BARRIER
0 V
or
V 1
CC
VCC
VI
CL
NOTE A
VO
VI
VO50%
VCC
0 V
VOH
VOL
2.7 V
fs low
VO
Input
Generator 50 W
OUT
DISABLE
VI
IN
0V
VO
VI
50 %
50 %
twake
VO
Input
Generator 50 W
OUT
DISABLE
VO
VI
IN
0 V
CL
wake
t
(Note A)
(Note A )
CL
(Note B )
(Note B )
VCC2
0 V
0 V
0 V
0 V
VI
CTRL
3 V
CTRL
3 V
ISOLATION BARRIER
ISOLATION BARRIER
VCC
VCC
V /2
CC
VCC
V /2
CC
NOTE: Which ever test yields the longest time is used in this data sheet
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
PARAMETER MEASUREMENT INFORMATION (continued)
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr3
ns, tf3 ns, ZO= 50.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Wake Time From Input Disable Test Circuit and Voltage Waveforms
Copyright ©20072012, Texas Instruments Incorporated 15
VCM
IN OUT
GND1
NOTE B
S1
V or V
OH OL
ISOLATION BARRIER
VCC1 VCC2
C = 0.1 F± 1%mC = 0.1 F± 1%m
GND2
Pass-fail criteria:
Output must
remain stable
OUT
Tektronix
HFS9009
PATTERN
GENERATOR
IN
DUT
Tektronix
784D
VCC
0 V
V / 2
C C
Jitter
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr3
ns, tf3 ns, ZO= 50.
Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
NOTE: PRBS bit pattern run length is 216 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 8.34 mm
Shortest terminal-to-terminal distance across the
L(I02) Minimum external tracking (Creepage) 8.1 mm
package surface
Tracking resistance (comparative
CTI DIN IEC 60112/VDE 0303 Part 1 400 V
tracking index)
Minimum Internal Gap (Internal Distance through the insulation 0.008 mm
Clearance) Input to output, VIO = 500 V, all pins on each side of the
RIO Isolation resistance >1012
barrier tied together creating a two-terminal device
CIO Barrier capacitance Input to output VI= 0.4 sin (4E6πt) 2 pF
CIInput capacitance to ground VI= 0.4 sin (4E6πt) 2 pF
IEC 60664-1 RATINGS TABLE
PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group II
Rated mains voltage 150 VRMS I-IV
Installation classification Rated mains voltage 300 VRMS I-III
16 Copyright ©20072012, Texas Instruments Incorporated
OUT
8W
13 W
VCC
Output
IN
VCC
VCC
ISO7240CF
Input
1MW
VCC
500 W
VCC
EN
Enable
500 W
VCC
1MW
IN
VCC
VCC
VCC
Input
1MW
500 W
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
spacer
REGULATORY INFORMATION
VDE CSA UL
Certified according to IEC Approved under CSA Component Recognized under 1577
60747-5-2 Acceptance Notice 5A Component Recognition Program
Basic Insulation
Maximum Transient Overvoltage, Basic insulation per CSA
4000 VPK 60950-1-07 and IEC 60950-1
Maximum Surge Votlage, 4000 (2nd Ed), 395 VRMS maximum Single protection, 2500 VRMS(1)
VPK working voltage, 4000 VPK
Maximum Working Voltage, 560 maximum isolation rating
VPK
File Number: 40016131 File Number: 220991 File Number: E181974
(1) Production tested 3000 VRMS for 1 second in accordance with UL 1577.
spacer
DEVICE I/O SCHEMATICS
Copyright ©20072012, Texas Instruments Incorporated 17
0
5
10
15
20
25
30
35
40
45
0 25 50 75 100 125 150
SignalingRate-Mbps
I -SupplyCurrent-mA/RMS
CC
T =25°C,
Load=15pF,
AllChannels
A
5-VICC2
3.3-VICC2
3.3-VICC1
5-VICC1
0
5
10
15
20
25
30
35
40
45
0 25 50 75 100 125 150
SignalingRate-Mbps
I -SupplyCurrent-mA/RMS
CC
T =25°C,
Load=15pF,
AllChannels
A
5-VICC1,ICC2
3.3-VICC1,ICC2
0
5
10
15
20
25
30
35
40
45
-40 -25 -10 5 20 35 50 65 80 95 110 125
T -Free-AirTemperature- C
A°
PropagationDelay-ns
T =25°C,
Load=15pF,
AllChannels
A
C3.3-V ,tpHL
tpLH
M3.3-V ,tpHL
tpLH
C5-V ,tpHL
tpLH
M5-V ,tpHL
tpLH
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-K Thermal Resistance(1) 168
θJA Junction-to-air °C/W
High-K Thermal Resistance 96.1
θJB Junction-to-Board Thermal Resistance 61 °C/W
θJC Junction-to-Case Thermal Resistance 48 °C/W
VCC1 = VCC2 = 5.5 V, TJ= 150°C, CL= 15 pF,
PDDevice Power Dissipation 220 mW
Input a 50% duty cycle square wave
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
spacer TYPICAL CHARACTERISTIC CURVES
ISO7240C/M RMS SUPPLY CURRENT ISO7241C/M RMS SUPPLY CURRENT
vs vs
SIGNALING RATE SIGNALING RATE
Figure 7. Figure 8.
ISO7242C/M RMS SUPPLY CURRENT PROPAGATION DELAY
vs vs
SIGNALING RATE FREE-AIR TEMPERATURE
Figure 9. Figure 10.
18 Copyright ©20072012, Texas Instruments Incorporated
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
-40 -25 -10 5 20 35 50 65 80 95 110 125
InputVoltageThreshold-V
T -Free-AirTemperature- C
A
°
5VVth+
3.3VVth+
5VVth-
3.3VVth-
AirFlowat7cf/m,
Low_KBoard
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
-40 -25 -10 5 20 35 50 65 80 95 110 125
T - Free-Air Temperature - C
A
°
V - V
CC - Undervoltage Threshold
V Rising
CC
V Falling
CC
0
5
10
15
20
25
30
35
40
45
50
012 3 4 5
I -OutputCurrent-mA
O
V -OutputVoltage-V
O
V =5V
CC
V =3.3V
CC
Load=15pF,
T =25 C
A
°
0
10
20
30
40
50
024 6
I -OutputCurrent-mA
O
V -OutputVoltage-V
O
V =5V
CC
V =3.3V
CC
Load=15pF,
T =25 C
A
°
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
TYPICAL CHARACTERISTIC CURVES (continued)
INPUT VOLTAGE THRESHOLD VCC UNDERVOLTAGE THRESHOLD
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 11. Figure 12.
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
vs vs
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
Figure 13. Figure 14.
Copyright ©20072012, Texas Instruments Incorporated 19
1
2
3
4
5
6
7
8
ISO7240x
9
10
11
12
13
14
15
16
NC
IN A
GND1
GND1
GND2
GND2
IN B
IN C
OUT A
OUT C
OUT B
IN DOUT D
EN
0.1 Fm
VCC1
2mm
max.from
VCC1
2mm
max.from
VCC2
VCC2
0.1 Fm
1
2
3
4
5
6
7
8
ISO7240CF
9
10
11
12
13
14
15
16
DISABLE
IN A
GND1
GND1
GND 2
GND2
IN B
IN C
OUT A
OUT C
OUT B
IN DOUT D
CTRL
0.1 Fm
VCC1
2mm
max.from
VCC1
2mm
max.from
VCC2
VCC2
0.1 Fm
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
APPLICATION INFORMATION
Figure 15. Typical ISO7240x Application Circuit
Figure 16. Typical ISO7240CF Failsafe-Low Application Circuit
20 Copyright ©20072012, Texas Instruments Incorporated
10
100
0 250 500 750 1000
WORKINGVOLTAGE(VIORM)--V
WORKINGLIFE-- YEARS
VIORM at560-V
28 Years
880
120
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
LIFE EXPECTANCY vs. WORKING VOLTAGE
Figure 17. Time-Dependant Dielectric Breakdown Testing Results
REVISION HISTORY
Changes from Original (September 2007) to Revision A Page
Deleted Product Preview note .............................................................................................................................................. 2
Changed VCC Supply Voltage in the ROC Table From: 3.6 To: 3.45 ................................................................................... 3
Changed VCC Supply Voltage in the ROC Table From: 3 To: 3.15 ...................................................................................... 3
Changed TBDs to actual values. .......................................................................................................................................... 4
Changed CI- typ value From: 1 To: 2 .................................................................................................................................. 4
Changed Propagation delay max From: 22 To: 23 .............................................................................................................. 5
Changed CI- typ value From: 1 To: 2 .................................................................................................................................. 6
Changed Propagation delay max From: 46 To: 50 .............................................................................................................. 7
Changed Propagation delay max From: 28 To: 29 .............................................................................................................. 7
Changed ISO724xA/C max value From: 2.5 To: 3 ............................................................................................................... 7
Changed CI- typ value From: 1 To: 2 .................................................................................................................................. 8
Changed Propagation delay max From: 26 To: 30 .............................................................................................................. 9
Changed typ value From: 1 To: 2 ....................................................................................................................................... 10
Changed Propagation delay max From: 32 To: 34 ............................................................................................................ 11
Changed ISO724xA/C max value From: 3 To: 3.5 ............................................................................................................. 11
Changed CIO - typ value From: 1 To: 2 .............................................................................................................................. 16
Changed CI- typ value From: 1 To: 2 ................................................................................................................................ 16
Changed the REGULATORY INFORMATION Table ......................................................................................................... 17
Changed Figure 7,Figure 8, and Figure 10. Added Figure 9. ........................................................................................... 18
Changes from Revision A (December 2007) to Revision B Page
Changed VCC Supply Voltage in the ROC Table From: 3.45 To: 3.6 ................................................................................... 3
Changes from Revision B (August 2008) to Revision C Page
Deleted Min = 4.5 V and max = 5.5 V for Supply Voltage of the ROC Table. ..................................................................... 3
Changed VCC Supply Voltage in the ROC Table From: 3.6 To: 5.5 ..................................................................................... 3
Copyright ©20072012, Texas Instruments Incorporated 21
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
www.ti.com
Changes from Revision C (April 2008) to Revision D Page
Changed Feature Bullet 4000-Vpeak Isolation ........................................................................................................................ 1
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 5
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 7
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 9
Added tsk(pp) Part-to-part skew ............................................................................................................................................ 11
Changed Typical ISO724x Application Circuit Figure 15 .................................................................................................... 20
Changes from Revision D (April 2008) to Revision E Page
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. .............................................. 3
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V ............................................... 6
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V ............................................... 8
Added Table Note (1): For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V ............................................. 10
Changes from Revision E (May 2008) to Revision F Page
Changed Title From: QUAD DIGITAL ISOLATORS To: HIGH SPEED QUAD DIGITAL ISOLATORS ............................... 1
Deleted ISO724xA devices. See SLLS905 for the ISO7240A, ISO7241A, and ISO7242A. ................................................ 1
Changed Feature Low Jitter Content - From: 1, 25, and 150-Mbps Signaling Rate Options To: 25, and 150-Mbps
Signaling Rate Options ......................................................................................................................................................... 1
Added tsk(pp) footnote. ............................................................................................................................................................ 5
Added tsk(o) footnote. ............................................................................................................................................................. 5
Added tsk(pp) footnote. .......................................................................................................................................................... 11
Added tsk(o) footnote. ........................................................................................................................................................... 11
Changes from Revision F (May 2008) to Revision G Page
Changed the PACKAGE CHARACTERISTICS table, line , L(IO1) MIN value from7.7mm to 8.34mm ................................ 16
Changes from Revision G (July 2008) to Revision H Page
Added Device number ISO7240CF. ..................................................................................................................................... 1
Added Features Bullet: Selectable Failsafe Output (ISO7240CF) ....................................................................................... 1
Changed description paragraph 4 text. ................................................................................................................................. 1
Added for device number ISO7240CF. ................................................................................................................................. 2
Changed VIin the Abs Max Table From: Voltage at IN, OUT, EN To: Voltage at IN, OUT, EN, DISABLE, CTRL ............. 3
Added twake, Wake time from input disable ........................................................................................................................... 5
Added twake, Wake time from input disable ........................................................................................................................... 7
Added twake, Wake time from input disable ........................................................................................................................... 9
Added twake, Wake time from input disable ......................................................................................................................... 11
Changes from Revision H (October 2008) to Revision I Page
Added information to the Features bullet to include CSA and IEC 60950-1 certification ..................................................... 1
22 Copyright ©20072012, Texas Instruments Incorporated
ISO7240CF, ISO7240C, ISO7240M
ISO7241C, ISO7241M
ISO7242C, ISO7242M
www.ti.com
SLLS868N SEPTEMBER 2007REVISED JANUARY 2012
Changes from Revision I (December 2008) to Revision J Page
Changed ICC1 for Quiescent and 1Mbps From: 10mA To: 11mA ......................................................................................... 4
Changed ICC1 for Quiescent and 1Mbps From: 10mA To: 11mA ......................................................................................... 6
Changes from Revision J (April 2009) to Revision K Page
Changed the Input circuit in the DEVICE I/O SCHEMATICS illustration ............................................................................ 17
Changes from Revision K (Decemberl 2009) to Revision L Page
Added the IEC 60747-5-2 INSULATION CHARACTERISTIC table ..................................................................................... 3
Added CTI - Tracking resistance (comparative tracking index to the PACKAGE CHARACTERISTICS table .................. 16
Added the IEC 60664-1 RATINGS TABLE ......................................................................................................................... 16
Changes from Revision L (January 2010) to Revision M Page
Changed Figure 1,Figure 3, and Figure 4 ......................................................................................................................... 14
Changed the CSA File Number From: 1698195 To: 220991 ............................................................................................. 17
Changes from Revision M (January 2011) to Revision N Page
Changed Feature From: 4000-Vpeak Isolation, 560-Vpeak VIORM To: 4000-Vpeak VIOTM, 560-Vpeak VIORM per IEC
60747-5-2 (VDE 0884, Rev 2) .............................................................................................................................................. 1
Changed Feature From: Operates 3.3-V or 5-V Supplies To: Operates With 2.8-V (ISO7241C), 3.3-V or 5-V
Supplies ................................................................................................................................................................................ 1
Added device options to VCC in the RECOMMENDED OPERATING CONDITIONS table .................................................. 3
Changed Table Note (1) ....................................................................................................................................................... 3
Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 5-V table ............................................................................. 4
Changed Table Note (1) ....................................................................................................................................................... 4
Changed ICC1 and ICC2 test conditions in the VCC1 at 5-V, VCC2 at 3.3-V table ...................................................................... 6
Changed Table Note (1) ....................................................................................................................................................... 6
Changed ICC1 and ICC2 test conditions in the VCC1 at 3.3-V, VCC2 at 5-V table ...................................................................... 8
Changed Table Note (1) ....................................................................................................................................................... 8
Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 3.3 V table ........................................................................ 10
Changed Table Note (1) ..................................................................................................................................................... 10
Added ELECTRICAL and Switching CHARACTERISTICS tables forVCC1 and VCC2 at 2.8V (ISO722xC-only) ................. 12
Changed the CTI MIN value From: 175 V To:400 V ...................................................................................................... 16
Changed the REGULATORY INFORMATION Table ......................................................................................................... 17
Changed Figure 12 From VCC1 Failsafe Threshold To: VCC Undervoltage Threshold ........................................................ 19
Copyright ©20072012, Texas Instruments Incorporated 23
PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ISO7240CDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240CDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240CFDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240CFDWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240CFDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240CFDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240MDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240MDWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240MDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7240MDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7241CDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7241CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7241CDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7241CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7241MDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ISO7241MDWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7241MDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7241MDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7242CDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7242CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7242CDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7242CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7242MDW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7242MDWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7242MDWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO7242MDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Aug-2012
Addendum-Page 3
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7240CF, ISO7241C, ISO7242C :
Automotive: ISO7240CF-Q1, ISO7241C-Q1, ISO7242C-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO7240CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7240CFDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7241CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7241MDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7242CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO7242MDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7240CDWR SOIC DW 16 2000 533.4 186.0 36.0
ISO7240CFDWR SOIC DW 16 2000 533.4 186.0 36.0
ISO7241CDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7241MDWR SOIC DW 16 2000 533.4 186.0 36.0
ISO7242CDWR SOIC DW 16 2000 367.0 367.0 38.0
ISO7242MDWR SOIC DW 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Aug-2012
Pack Materials-Page 2
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