TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Piccolo Microcontrollers
Check for Samples: TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066,
TMS320F28065,TMS320F28064,TMS320F28063,TMS320F28062
1 TMS320F2806x ( Piccolo™) MCUs
1.1 Features
123
• High-Efficiency 32-Bit CPU (TMS320C28x™) • Clocking
– 90 MHz (11.11-ns Cycle Time) – Two Internal Zero-pin Oscillators
– 16 x 16 and 32 x 32 MAC Operations – On-Chip Crystal Oscillator/External Clock
Input
– 16 x 16 Dual MAC – Dynamic PLL Ratio Changes Supported
– Harvard Bus Architecture – Watchdog Timer Module
– Atomic Operations – Missing Clock Detection Circuitry
– Fast Interrupt Response and Processing • Peripheral Interrupt Expansion (PIE) Block That
– Unified Memory Programming Model Supports All Peripheral Interrupts
– Code-Efficient (in C/C++ and Assembly) • Three 32-Bit CPU Timers
• Floating-Point Unit • Advanced Control Peripherals
– Native Single-Precision Floating-Point • Up to 8 Enhanced Pulse Width Modulator
Operations (ePWM) Modules
• Programmable Control Law Accelerator (CLA) – 16 PWM Channels Total (8 HRPWM-Capable)
– 32-Bit Floating-Point Math Accelerator – Independent 16-Bit Timer in Each Module
– Executes Code Independently of the Main • Three Input Capture (eCAP) Modules
CPU • Up to 4 High-Resolution Input Capture (HRCAP)
• Viterbi, Complex Math, CRC Unit (VCU) Modules
– Extends C28x™ Instruction Set to Support • Up to 2 Quadrature Encoder (eQEP) Modules
Complex Multiply, Viterbi Operations, and
Cyclic Redundency Check (CRC) • 12-Bit ADC, Dual Sample-and-Hold
• Embedded Memory – Up to 3.46 MSPS
– Up to 256KB Flash – Up to 16 Channels
– Up to 100KB RAM • On-Chip Temperature Sensor
– 2KB OTP ROM • 128-Bit Security Key/Lock
• 6-Channel DMA – Protects Secure Memory Blocks
• Low Device and System Cost – Prevents Firmware Reverse Engineering
– Single 3.3-V Supply • Serial Port Peripherals
– No Power Sequencing Requirement – Two Serial Communications Interface (SCI)
[UART] Modules
– Integrated Power-on Reset and Brown-out
Reset – Two Serial Peripheral Interface (SPI)
Modules
– Low-Power Operating Modes – One Inter-Integrated-Circuit (I2C) Bus
– No Analog Support Pin – One Multichannel Buffered Serial Port
• Endianness: Little Endian (McBSP) Bus
– One Enhanced Controller Area Network
(eCAN)
– One Universal Serial Bus (USB) 2.0 Module
(Available on TMS320F2806xU Devices Only)
• Full-Speed Device Mode
• Full-/Low-Speed Host Mode
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Piccolo, PowerPAD, C28x, TMS320C2000, C2000, ControlSUITE, Code Composer Studio, XDS510, XDS560, TMS320C28x,
TMS320C54x, TMS320C55x are trademarks of Texas Instruments.
3All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information Copyright © 2010–2012, Texas Instruments Incorporated
current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include
testing of all parameters.
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
• Up to 54 Individually Programmable, • 2806x Packages
Multiplexed GPIO Pins With Input Filtering – 80-Pin PFP and 100-Pin PZP PowerPAD™
• Advanced Emulation Features Thermally Enhanced Thin Quad Flatpacks
(HTQFPs)
– Analysis and Breakpoint Functions – 80-Pin PN and 100-Pin PZ Low-Profile Quad
– Real-Time Debug via Hardware Flatpacks (LQFPs)
1.2 Description
The F2806x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law
Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family
is code-compatible with previous C28x-based code, as well as providing a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the
HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal
10-bit references have been added and can be routed directly to control the PWM outputs. The ADC
converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The
ADC interface has been optimized for low overhead/latency.
2TMS320F2806x ( Piccolo™) MCUs Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
CLA Bus
GPIO Mux
DMA Bus
DMA Bus
16-bit Peripheral Bus 32-bit Peripheral Bus
(CLA accessible)
32-bit Peripheral
Bus
32-bit Peripheral
Bus
32-bit
Peripheral Bus
(CLA accessible)
SCITXDx
SCIRXDx
SPISIMOx
SPISOMIx
SPICLKx
SPISTEx
SDAx
SCLx
TZx
EPWMxA
EPWMxB
MFSRA
MDRA
MCLKRA
MFSXA
MDXA
MCLKXA
ECAPx
EQEPxA
EQEPxB
EQEPxI
EQEPxS
HRCAPx
CANRXx
CANTXx
SCI-A/B
(4L FIFO)
SPI-A/B
(4L FIFO) I2C-A
(4L FIFO)
ePWM1 to ePWM8
HRPWM (8ch) McBSP-A eCAP-
1/2/3
eQEP-
1/2
HRCAP-
1/2/3/4
eCAN-A
(32-mbox)
Memory Bus
A7:0
B7:0
Memory Bus
Memory Bus
DMA Bus
CLA Bus
DMA Bus
GPIO Mux
AIO Mux
32-bit Peripheral Bus
GPIO
Mux
GPIO
Mux
ADC
0-wait
Result
Regs
ADC
COMP
+
DAC
COMP1OUT
COMP2OUT
COMP3OUT
COMP1A
COMP2A
COMP3A
COMP1B
COMP2B
COMP3B
Boot-ROM
(32Kx16)
(0-wait,
Non-Secure)
CLA +
Message
RAMs
DMA
6-ch
C28x 32-bit CPU
FPU
VCU
OSC1, OSC2,
Ext, PLLs,
LPM, WD,
CPU Timers
0/1/2. PIE
TRST
TCK, TDI, TMS
TDO
XCLKIN
LPM Wakeup
3 Ext. Interrupts
X1
X2
XRS
PSWD
M0 SARAM (1Kx16)
(0-wait, Non-Secure)
M1 SARAM (1Kx16)
(0-wait, Non-Secure)
L5 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM0
L6 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM1
L7 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM2
L8 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM3
L0 DPSARAM (2Kx16)
(0-wait, Secure)
CLA Data RAM2
L1 DPSARAM (1Kx16)
(0-wait, Secure)
CLA Data RAM0
L2 DPSARAM (1Kx16)
(0-wait, Secure)
CLA Data RAM1
L3 DPSARAM (4Kx16)
(0-wait, Secure)
CLA Program RAM
L4 SARAM (8Kx16)
(0-wait, Secure)
Code
Security
Module
(CSM)
OTP 1Kx16
Secure
FLASH
64K/128Kx16
8 equal sectors
Secure
PUMP
OTP/Flash
Wrapper
32-bit Peripheral
Bus
USB0DP
USB0DM
USB-0
EPWMSYNCI
EPWMSYNCO
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
1.3 Functional Block Diagram
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
Copyright © 2010–2012, Texas Instruments Incorporated TMS320F2806x ( Piccolo™) MCUs 3
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10-bit
DAC
Analog
Comparators
CMP1-Out
CMP2-Out
CMP3-Out
Trip Zone
Temp
Sensor
ADC
(DMA-
accessible)
12-bit
3.46-MSPS
Dual-S/H
SOC-
based
VREF
CLA Core
90-MHz Floating-Point
(Accelerator)
(DMA-accessible)
10-bit
DAC
10-bit
DAC
A0
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A1
6
eQEP x 2
HRCAP x 4
eCAP x 3
System
Vreg
Int-Osc-1
POR/BOR
Int-Osc-2
On-chip Osc
WD
PLL
CLKSEL
Timers 32-bit
Timer-0
Timer-1
Timer-2
GPIO
Control
COMMS
X1
X2
VREFLO
VREFHI
C28x
Core
(90-MHz)
FPU
VCU
Flash Memory
RAM
RAM
(Dual-Access)
eQEP
8
HRCAP
4
eCAP
3
4
8
2
2
6
PWM-1A
PWM-1B
PWM-2A
PWM-2B
PWM-3A
PWM-3B
PWM-4A
PWM-4B
PWM-5A
PWM-5B
PWM-6A
PWM-6B
PWM-7A
PWM-7B
PWM-8A
PWM-8B
TZ1
TZ2
TZ3
CMP1-out
CMP2-out
CMP3-out
PWM1
(DMA-accessible)
PWM5
(DMA-accessible)
PWM8
(DMA-accessible)
PWM7
(DMA-accessible)
PWM6
(DMA-accessible)
PWM4
(DMA-accessible)
PWM3
(DMA-accessible)
PWM2
(DMA-accessible)
UART x 2
SPI x 2
I2C
CAN
McBSP
(DMA-accessible)
2
USB
(DMA-accessible)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
1.4 System Device Diagram
Figure 1-2. Peripheral Blocks
4TMS320F2806x ( Piccolo™) MCUs Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
1 TMS320F2806x ( Piccolo™) MCUs .................. 15.4 Clock Requirements and Characteristics ........... 65
1.1 Features ............................................. 15.5 Power Sequencing ................................. 66
1.2 Description ........................................... 25.6 Current Consumption ............................... 69
5.7 Emulator Connection Without Signal Buffering for
1.3 Functional Block Diagram ........................... 3the MCU ............................................ 72
1.4 System Device Diagram ............................. 45.8 Interrupts ............................................ 73
2 Device Overview ........................................ 65.9 Control Law Accelerator (CLA) Overview .......... 78
2.1 Device Characteristics ............................... 65.10 Analog Block ........................................ 81
2.2 Memory Maps ........................................ 95.11 Detailed Descriptions ............................... 95
2.3 Pin Assignments .................................... 19 5.12 Serial Peripheral Interface (SPI) Module ........... 96
2.4 Signal Descriptions ................................. 21 5.13 Serial Communications Interface (SCI) Module .. 105
2.5 Brief Descriptions ................................... 30 5.14 Multichannel Buffered Serial Port (McBSP) Module
2.6 Register Map ....................................... 40 ..................................................... 108
2.7 Device Emulation Registers ........................ 42 5.15 Enhanced Controller Area Network (eCAN) Module
2.8 VREG/BOR/POR ................................... 44 ..................................................... 118
2.9 System Control ..................................... 46 5.16 Inter-Integrated Circuit (I2C) ...................... 122
2.10 Low-power Modes Block ........................... 55 5.17 Enhanced Pulse Width Modulator (ePWM) Modules
(ePWM1/2/3/4/5/6/7/8) ............................ 125
3 Device and Documentation Support ............... 56 5.18 High-Resolution PWM (HRPWM) ................. 132
3.1 Getting Started ..................................... 56 5.19 Enhanced Capture Module (eCAP1) .............. 133
3.2 Development Support .............................. 56 5.20 High-Resolution Capture Modules (HRCAP1/2/3/4)
3.3 Device and Development Support Tool ..................................................... 135
Nomenclature ....................................... 56 5.21 Enhanced Quadrature Encoder Modules (eQEP1/2)
3.4 Documentation Support ............................ 58 ..................................................... 137
3.5 Community Resources ............................. 59 5.22 JTAG Port ......................................... 140
4 Device Operating Conditions ....................... 60 5.23 General-Purpose Input/Output (GPIO) MUX ...... 141
4.1 Absolute Maximum Ratings ........................ 60 5.24 Universal Serial Bus (USB) ....................... 153
4.2 Recommended Operating Conditions .............. 60 5.25 Flash Timing ...................................... 154
4.3 Electrical Characteristics ........................... 61 6 Revision History ..................................... 156
5 Peripheral and Electrical Specifications .......... 62 7 Mechanical Packaging and Orderable
5.1 Parameter Information .............................. 62 Information ............................................ 163
5.2 Test Load Circuit ................................... 62 7.1 Thermal Data ...................................... 163
5.3 Device Clock Table ................................. 63 7.2 Packaging Information ............................ 164
Copyright © 2010–2012, Texas Instruments Incorporated Contents 5
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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2 Device Overview
2.1 Device Characteristics
Table 2-1 lists the features of the TMS320F2806x devices.
6Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Table 2-1. Hardware Features
28069, 28068, 28067, 28066, 28065, 28064, 28063, 28062,
FEATURE TYPE(1) 28069U(2) 28068U(2) 28067U(2) 28066U(2) 28065U(2) 28064U(2) 28063U(2) 28062U(2)
(90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz)
Package Type 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin
(PFP and PZP are HTQFPs. PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP
PN and PZ are LQFPs.)
Instruction cycle – 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns
Floating-Point Unit (FPU) Yes Yes Yes Yes Yes Yes Yes Yes
Viterbi, Complex Math, CRC Unit (VCU) Yes Yes No No Yes Yes No No
Control Law Accelerator (CLA) 0 Yes No No No Yes No No No
6-Channel DMA 0 Yes Yes Yes Yes Yes Yes Yes Yes
On-chip Flash (16-bit word) – 128K 128K 128K 128K 64K 64K 64K 64K
On-chip SARAM (16-bit word) – 50K 50K 50K 34K 50K 50K 34K 26K
Code security for on-chip – Yes Yes Yes Yes Yes Yes Yes Yes
flash/SARAM/OTP blocks
Boot ROM (32K x 16) – Yes Yes Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM – 1K 1K 1K 1K 1K 1K 1K 1K
(16-bit word)
ePWM outputs 1 19 15 19 15 19 15 19 15 19 15 19 15 19 15 19 15
High-resolution ePWM Channels 1 8 6 8 6 8 6 8 6 8 6 8 6 8 6 8 6
eCAP inputs 0 3 3 3 3 3 3 3 3
High-resolution capture modules 04141414141414141
(HRCAP)
eQEP modules 0 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
Watchdog timer – Yes Yes Yes Yes Yes Yes Yes Yes
MSPS 3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46
Conversion Time 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns
12-Bit ADC Channels 3 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12
Temperature Sensor Yes Yes Yes Yes Yes Yes Yes Yes
Dual Sample-and-Hold Yes Yes Yes Yes Yes Yes Yes Yes
32-Bit CPU timers – 3 3 3 3 3 3 3 3
Comparators with Integrated DACs 0 3 3 3 3 3 3 3 3
Inter-integrated circuit (I2C) 0 1 1 1 1 1 1 1 1
Multichannel Buffered Serial Port 1 1 1 1 1 1 1 1 1
(McBSP)
Enhanced Controller Area Network 0 1 1 1 1 1 1 1 1
(eCAN)
Serial Peripheral Interface (SPI) 1 2 2 2 2 2 2 2 2
Serial Communications Interface (SCI) 0 2 2 2 2 2 2 2 2
Universal Serial Bus (USB) 0 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the
peripheral reference guides.
(2) USB is present only in TMS320F2806xUdevices.
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 7
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Table 2-1. Hardware Features (continued)
28069, 28068, 28067, 28066, 28065, 28064, 28063, 28062,
FEATURE TYPE(1) 28069U(2) 28068U(2) 28067U(2) 28066U(2) 28065U(2) 28064U(2) 28063U(2) 28062U(2)
(90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz)
Package Type 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin
(PFP and PZP are HTQFPs. PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP
PN and PZ are LQFPs.)
2-pin Oscillator 1 1 1 1 1 1 1 1
0-pin Oscillator 2 2 2 2 2 2 2 2
GPIO – 54 40 54 40 54 40 54 40 54 40 54 40 54 40 54 40
I/O pins
(shared) AIO – 6 6 6 6 6 6 6 6
External interrupts – 3 3 3 3 3 3 3 3
Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
T: –40°C to 105°C – PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN
Temperature S: –40°C to 125°C – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP
options Q: –40°C to 125°C(3) – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP
TMS (28069) TMS (28068) TMS (28067) TMS (28066) TMS (28065) TMS (28064) TMS (28063) TMS (28062)
Product status(4) –TMX (28069U)TMX (28068U)TMX (28067U)TMX (28066U)TMX (28065U)TMX (28064U)TMX (28063U)TMX (28062U)
(3) "Q" refers to Q100 qualification for automotive applications.
(4) The "TMS" product status denotes a fully qualified production device. The "TMX" product status denotes an experimental device that is not necessarily representative of the final device's
electrical specifications. See Section 3.3, Device and Development Support Tool Nomenclature, for descriptions of device stages.
8Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
2.2 Memory Maps
In Figure 2-1 through Figure 2-7, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps
are restricted to data memory only. A user program cannot access these memory maps in program
space.
•Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline
order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
• Locations 0x3D 7C80–0x3D 7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.
• All devices with USB have 2K x16 RAM from 0x40000 to 0x40800. When the clock to the USB module
is enabled, this RAM is connected to the USB controller and acts as the FIFO RAM. When the clock to
the USB module is disabled, this RAM is remapped to the CPU-accessible address space and can be
used as general-purpose RAM.
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 9
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TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
0x00 2000 Reserved
Peripheral Frame 0
0x00 0800
0x00 1580
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 1400
0x00 0E00
0x00 1500
0x00 1480
CPU-to-CLA Message RAM
CLA-to-CPU Message RAM
CLA Registers
Peripheral Frame 0
Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x00 5000
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM2)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, CLA Program RAM)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L8 DPSARAM (8K x 16)
(0-Wait, DMA RAM 3)
L7 DPSARAM (8K x 16)
(0-Wait, DMA RAM 2)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
0x01 0000
0x01 2000
Peripheral Frame 1
(4K x 16, Protected)
0x00 6000
Reserved
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x01 4000 Reserved
0x3D 7BFA Reserved
FLASH
(128K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3D 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
Reserved
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Figure 2-1. 28069 Memory Map
10 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L8 DPSARAM (8K x 16)
(0-Wait, DMA RAM 3)
L7 DPSARAM (8K x 16)
(0-Wait, DMA RAM 2)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
0x01 0000
0x01 2000
Peripheral Frame 1
(4K x 16, Protected)
0x00 6000
Reserved
0x01 4000 Reserved
Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x00 5000
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(128K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3D 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Figure 2-2. 28068/28067 Memory Map
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 11
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
Reserved
0x01 0000 Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(128K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3D 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Figure 2-3. 28066 Memory Map
12 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
0x00 2000 Reserved
Peripheral Frame 0
0x00 0800
0x00 1580
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 1400
0x00 0E00
0x00 1500
0x00 1480
CPU-to-CLA Message RAM
CLA-to-CPU Message RAM
CLA Registers
Peripheral Frame 0
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM2)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, CLA Program RAM)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L8 DPSARAM (8K x 16)
(0-Wait, DMA RAM 3)
L7 DPSARAM (8K x 16)
(0-Wait, DMA RAM 2)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
0x01 0000
0x01 2000
Reserved
0x01 4000 Reserved
Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(64K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3E 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Figure 2-4. 28065 Memory Map
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 13
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TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L8 DPSARAM (8K x 16)
(0-Wait, DMA RAM 3)
L7 DPSARAM (8K x 16)
(0-Wait, DMA RAM 2)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
0x01 0000
0x01 2000
Reserved
0x01 4000 Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(64K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3E 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Figure 2-5. 28064 Memory Map
14 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
Reserved
0x01 0000 Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(64K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3E 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Figure 2-6. 28063 Memory Map
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 15
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
Reserved
0x00 E000 Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(64K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3E 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Figure 2-7. 28062 Memory Map
16 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Table 2-2. Addresses of Flash Sectors in F28069/28068/28067/28066
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3D 8000 – 0x3D BFFF Sector H (16K x 16)
0x3D C000 – 0x3D FFFF Sector G (16K x 16)
0x3E 0000 – 0x3E 3FFF Sector F (16K x 16)
0x3E 4000 – 0x3E 7FFF Sector E (16K x 16)
0x3E 8000 – 0x3E BFFF Sector D (16K x 16)
0x3E C000 – 0x3E FFFF Sector C (16K x 16)
0x3F 0000 – 0x3F 3FFF Sector B (16K x 16)
0x3F 4000 – 0x3F 7FF5 Sector A (16K x 16)
Boot-to-Flash Entry Point
0x3F 7FF6 – 0x3F 7FF7 (program branch instruction here)
Security Password (128-Bit)
0x3F 7FF8 – 0x3F 7FFF (Do not program to all zeros)
Table 2-3. Addresses of Flash Sectors in F28065/28064/28063/28062
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3E 8000 – 0x3E 9FFF Sector H (8K x 16)
0x3E A000 – 0x3E BFFF Sector G (8K x 16)
0x3E C000 – 0x3E DFFF Sector F (8K x 16)
0x3E E000 – 0x3E FFFF Sector E (8K x 16)
0x3F 0000 – 0x3F 1FFF Sector D (8K x 16)
0x3F 2000 – 0x3F 3FFF Sector C (8K x 16)
0x3F 4000 – 0x3F 5FFF Sector B (8K x 16)
0x3F 6000 – 0x3F 7FF5 Sector A (8K x 16)
Boot-to-Flash Entry Point
0x3F 7FF6 – 0x3F 7FF7 (program branch instruction here)
Security Password (128-Bit)
0x3F 7FF8 – 0x3F 7FFF (Do not program to all zeros)
NOTE
Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and should not contain program
code.
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 17
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read
peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as
written. Because of the pipeline, a write immediately followed by a read to different memory locations, will
appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block
protection mode where a region of memory can be protected so that operations occur as written (the
penalty is extra cycles are added to align the operations). This mode is programmable and by default, it
protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 2-4.
Table 2-4. Wait-States
AREA WAIT-STATES (CPU) COMMENTS
M0 and M1 SARAMs 0-wait Fixed
Peripheral Frame 0 0-wait
Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral-generated ready.
2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
Peripheral Frame 3 0-wait (writes) Assumes no conflict between CPU and CLA/DMA cycles. The wait
states can be extended by peripheral-generated ready.
2-wait (reads)
L0–L8 SARAM 0-wait data and program Assumes no CPU conflicts
OTP Programmable Programmed via the Flash registers.
1-wait minimum 1-wait is minimum number of wait states allowed.
FLASH Programmable Programmed via the Flash registers.
0-wait Paged min
1-wait Random min
Random ≥Paged
FLASH Password 16-wait fixed Wait states of password locations are fixed.
Boot-ROM 0-wait
18 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
60
59
58
57
56
55
54
53
52
51
50
49
48
47
40
39
38
37
36
35
34
33
32
31
30
29
28
27
61
62
63
64
65
66
67
68
69
70
71
72
73
74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
46
45
44
43
42
41
15
16
17
18
19
20
75
76
77
78
79
80
26
25
24
23
22
21
GPIO23/EQEP1I/MFSXA/SCIRXDB
VDD
VDD
VSS
VDDIO
GPIO20/EQEP1A/MDXA/COMP1OUT
GPIO21/EQEP1B/MDRA/COMP2OUT
GPIO4/EPWM3A
GPIO5/EPWM3B/SPISIMOA/ECAP1
XRS
TRST
VSS
VDDIO
ADCINA6/COMP3A/AIO6
ADCINA5
ADCINA4/COMP2A/AIO4
ADCINA2/COMP1A/AIO2
ADCINA1
ADCINA0, VREFHI
VDDA
GPIO10/EPWM6A/ADCSOCBO
GPIO11/EPWM6B/SCIRXDB/ECAP1
GPIO36/TMS
GPIO35/TDI
GPIO37/TDO
GPIO34/COMP2OUT/COMP3OUT
GPIO38/XCLKIN/TCK
GPIO39
GPIO19/XCLKIN/ /SCIRXDB/ECAP1SPISTEA
VDD
VSS
VDDIO
X1
X2
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO7/EPWM4B/SCIRXDA/ECAP2
GPIO16/SPISIMOA/TZ2
GPIO8/EPWM5A/ADCSOCAO
GPIO17/SPISOMIA/TZ3
GPIO18/SPICLKA/SCITXDB/XCLKOUT
GPIO26/ECAP3/SPICLKB/USB0DP
GPIO27/HRCAP2/SPISTEB/USB0DM
VDDIO
VSS
VDD
GPIO3/EPWM2B/SPISOMIA/COMP2OUT
GPIO2/EPWM2A
GPIO1/EPWM1B/COMP1OUT
GPIO0/EPWM1A
GPIO15/ECAP2/SCIRXDB/SPISTEB
VREGENZ
VDD
VSS
VDDIO
GPIO13/ /SPISOMIBTZ2
GPIO14/ /SCITXDB/SPICLKBTZ3
GPIO24/ECAP1/SPISIMOB
GPIO22/EQEP1S/MCLKXA/SCITXDB
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO29/SCITXDA/SCLA/TZ3
GPIO12/ /SCITXDA/SPISIMOBTZ1
TEST2
VDD3VFL
VSS
GPIO9/EPWM5B/SCITXDB/ECAP3
GPIO28/SCIRXDA/SDAA/TZ2
GPIO30/CANRXA/EPWM7A
GPIO31/CANTXA/EPWM8A
GPIO25/ECAP2/SPISOMIB
VDD
VSS
VDDIO
ADCINB6/COMP3B/AIO14
ADCINB5
ADCINB4/COMP2B/AIO12
ADCINB2/COMP1B/AIO10
ADCINB1
ADCINB0
V , V
REFLO SSA
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
2.3 Pin Assignments
Figure 2-8 shows the 80-pin PN/PFP pin assignments. Figure 2-9 shows the 100-pin PZ/PZP pin
assignments.
A. Pin 19: VREFHI and ADCINA0 share the same pin on the 80-pin PN/PFP device and their use is mutually exclusive to
one another.
Pin 21: VREFLO is always connected to VSSA on the 80-pin PN/PFP device.
Figure 2-8. 80-Pin PN/PFP (Top View)
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 19
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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Figure 2-9. 100-Pin PZ/PZP (Top View)
20 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
2.4 Signal Descriptions
Table 2-5 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate
functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs
are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM
pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do
not have an internal pullup.
NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38
pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be supplied
externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if
the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-V
transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power
up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring that
the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
Table 2-5. Terminal Functions(1)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system
control of the operations of the device. If this signal is not connected or driven low, the
device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active-high test pin and must be maintained low at all times during
TRST 12 10 I normal device operation. An external pull-down resistor is required on this pin. The
value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩresistor generally offers adequate protection. Since
this is application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application. (↓)
TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup. (↑)
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control
TMS See GPIO36 I input is clocked into the TAP controller on the rising edge of TCK. (↑)
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the
TDI See GPIO35 I selected register (instruction or data) on a rising edge of TCK. (↑)
See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected
TDO See GPIO37 O/Z register (instruction or data) are shifted out of TDO on the falling edge of TCK.
(8-mA drive)
FLASH
VDD3VFL 46 37 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
TEST2 45 36 I/O Test Pin. Reserved for TI. Must be left unconnected.
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑= Pullup, ↓= Pulldown
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Table 2-5. Terminal Functions(1) (continued)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same
frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is
controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
XCLKOUT See GPIO18 O/Z SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3.
The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate
to the pin.
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection.
This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if
available, must be tied to GND and the on-chip crystal oscillator must be disabled via
bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be
See GPIO19 and
XCLKIN I disabled by bit 13 in the CLKCTL register.
GPIO38 NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for
normal device operation may need to incorporate some hooks to disable this path
during debug using the JTAG connector. This is to prevent contention with the TCK
signal, which is active during JTAG debug sessions. The zero-pin internal oscillators
may be used during this time to clock the device.
On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic
resonator must be connected across X1 and X2. In this case, the XCLKIN path must
X1 60 48 I be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to
GND.
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be
X2 59 47 O connected across X1 and X2. If X2 is not used, it must be left unconnected.
RESET
Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on-
reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is
needed to generate a reset pulse. During a power-on or brown-out condition, this pin is
driven low by the device. See Section 4.3, Electrical Characteristics, for thresholds of
the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset
occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset
duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin
XRS 11 9 I/O to assert a device reset. In this case, it is recommended that this pin be driven by an
open-drain device. An R-C circuit must be connected to this pin for noise immunity
reasons. Regardless of the source, a device reset causes the device to terminate
execution. The program counter points to the address contained at the location
0x3FFFC0. When reset is deactivated, execution begins at the location designated by
the program counter. The output buffer of this pin is an open-drain with an internal
pullup.
ADC, COMPARATOR, ANALOG I/O
ADCINA7 16 – I ADC Group A, Channel 7 input
ADCINA6 17 14 I ADC Group A, Channel 6 input
COMP3A I Comparator Input 3A
AIO6 I/O Digital AIO 6
ADCINA5 18 15 I ADC Group A, Channel 5 input
ADCINA4 19 16 I ADC Group A, Channel 4 input
COMP2A I Comparator Input 2A
AIO4 I/O Digital AIO 4
ADCINA3 20 – I ADC Group A, Channel 3 input
ADCINA2 21 17 I ADC Group A, Channel 2 input
COMP1A I Comparator Input 1A
AIO2 I/O Digital AIO 2
ADCINA1 22 18 I ADC Group A, Channel 1 input
ADC Group A, Channel 0 input.
ADCINA0 23 19 I NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN/PFP device and
their use is mutually exclusive to one another.
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Table 2-5. Terminal Functions(1) (continued)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
ADC External Reference – only used when in ADC external reference mode. See
Section 5.10.1, Analog-to-Digital Converter (ADC).
VREFHI 24 19 NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN/PFP device and
their use is mutually exclusive to one another.
ADCINB7 35 – I ADC Group B, Channel 7 input
ADCINB6 34 27 I ADC Group B, Channel 6 input
COMP3B I Comparator Input 3B
AIO14 I/O Digital AIO 14
ADCINB5 33 26 I ADC Group B, Channel 5 input
ADCINB4 32 25 I ADC Group B, Channel 4 input
COMP2B I Comparator Input 2B
AIO12 I/O Digital AIO12
ADCINB3 31 – I ADC Group B, Channel 3 input
ADCINB2 30 24 I ADC Group B, Channel 2 input
COMP1B I Comparator Input 1B
AIO10 I/O Digital AIO 10
ADCINB1 29 23 I ADC Group B, Channel 1 input
ADCINB0 28 22 I ADC Group B, Channel 0 input
VREFLO 27 21 NOTE: VREFLO is always connected to VSSA on the 80-pin PN/PFP device.
CPU AND I/O POWER
VDDA 25 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
Analog Ground Pin.
VSSA 26 21 NOTE: VREFLO is always connected to VSSA on the 80-pin PN/PFP device.
VDD 3 2
VDD 14 12 CPU and Logic Digital Power Pins – no supply source needed when using internal
VDD 37 29 VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when
using internal VREG. Higher value capacitors may be used, but could impact supply-
VDD 63 51 rail ramp-up time.
VDD 81 65
VDD 91 72
VDDIO 5 4
VDDIO 13 11
VDDIO 38 30 Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled.
VDDIO 61 49
VDDIO 79 63
VDDIO 93 74
VSS 4 3
VSS 15 13
VSS 36 28
VSS 47 38 Digital Ground Pins
VSS 62 50
VSS 80 64
VSS 92 73
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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Table 2-5. Terminal Functions(1) (continued)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ 90 71 I Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG.
GPIO AND PERIPHERAL SIGNALS (1)
GPIO0 87 69 I/O/Z General-purpose input/output 0
EPWM1A O Enhanced PWM1 Output A and HRPWM channel
GPIO1 86 68 I/O/Z General-purpose input/output 1
EPWM1B O Enhanced PWM1 Output B
COMP1OUT O Direct output of Comparator 1
GPIO2 84 67 I/O/Z General-purpose input/output 2
EPWM2A O Enhanced PWM2 Output A and HRPWM channel
GPIO3 83 66 I/O/Z General-purpose input/output 3
EPWM2B O Enhanced PWM2 Output B
SPISOMIA I/O SPI-A slave out, master in
COMP2OUT O Direct output of Comparator 2
GPIO4 9 7 I/O/Z General-purpose input/output 4
EPWM3A O Enhanced PWM3 output A and HRPWM channel
GPIO5 10 8 I/O/Z General-purpose input/output 5
EPWM3B O Enhanced PWM3 output B
SPISIMOA I/O SPI-A slave in, master out
ECAP1 I/O Enhanced Capture input/output 1
GPIO6 58 46 I/O/Z General-purpose input/output 6
EPWM4A O Enhanced PWM4 output A and HRPWM channel
EPWMSYNCI I External ePWM sync pulse input
EPWMSYNCO O External ePWM sync pulse output
GPIO7 57 45 I/O/Z General-purpose input/output 7
EPWM4B O Enhanced PWM4 output B
SCIRXDA I SCI-A receive data
ECAP2 I/O Enhanced Capture input/output 2
GPIO8 54 43 I/O/Z General-purpose input/output 8
EPWM5A O Enhanced PWM5 output A and HRPWM channel
Reserved – Reserved
ADCSOCAO O ADC start-of-conversion A
(1) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.
For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the
GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the "Systems
Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18).
24 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Table 2-5. Terminal Functions(1) (continued)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
GPIO9 49 39 I/O/Z General-purpose input/output 9
EPWM5B O Enhanced PWM5 output B
SCITXDB O SCI-B transmit data
ECAP3 I/O Enhanced Capture input/output 3
GPIO10 74 60 I/O/Z General-purpose input/output 10
EPWM6A O Enhanced PWM6 output A and HRPWM channel
Reserved – Reserved
ADCSOCBO O ADC start-of-conversion B
GPIO11 73 59 I/O/Z General-purpose input/output 11
EPWM6B O Enhanced PWM6 output B
SCIRXDB I SCI-B receive data
ECAP1 I/O Enhanced Capture input/output 1
GPIO12 44 35 I/O/Z General-purpose input/output 12
TZ1 I Trip Zone input 1
SCITXDA O SCI-A transmit data
SPISIMOB I/O SPI-B slave in, master out
GPIO13 95 75 I/O/Z General-purpose input/output 13
TZ2 I Trip Zone input 2
Reserved – Reserved
SPISOMIB I/O SPI-B slave out, master in
GPIO14 96 76 I/O/Z General-purpose input/output 14
TZ3 I Trip zone input 3
SCITXDB O SCI-B transmit data
SPICLKB I/O SPI-B clock input/output
GPIO15 88 70 I/O/Z General-purpose input/output 15
ECAP2 I/O Enhanced Capture input/output 2
SCIRXDB I SCI-B receive data
SPISTEB I/O SPI-B slave transmit enable input/output
GPIO16 55 44 I/O/Z General-purpose input/output 16
SPISIMOA I/O SPI-A slave in, master out
Reserved – Reserved
TZ2 I Trip Zone input 2
GPIO17 52 42 I/O/Z General-purpose input/output 17
SPISOMIA I/O SPI-A slave out, master in
Reserved – Reserved
TZ3 I Trip zone input 3
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Table 2-5. Terminal Functions(1) (continued)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
GPIO18 51 41 I/O/Z General-purpose input/output 18
SPICLKA I/O SPI-A clock input/output
SCITXDB O SCI-B transmit data
XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-
half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by
bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4.
The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control
for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
GPIO19 64 52 I/O/Z General-purpose input/output 19
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the
mux function of this pin. Care must be taken not to enable this path for clocking if it is
being used for the other peripheral functions.
SPISTEA I/O SPI-A slave transmit enable input/output
SCIRXDB I SCI-B receive data
ECAP1 I/O Enhanced Capture input/output 1
GPIO20 6 5 I/O/Z General-purpose input/output 20
EQEP1A I Enhanced QEP1 input A
MDXA O McBSP transmit serial data
COMP1OUT O Direct output of Comparator 1
GPIO21 7 6 I/O/Z General-purpose input/output 21
EQEP1B I Enhanced QEP1 input B
MDRA I McBSP receive serial data
COMP2OUT O Direct output of Comparator 2
GPIO22 98 78 I/O/Z General-purpose input/output 22
EQEP1S I/O Enhanced QEP1 strobe
MCLKXA I/O McBSP transmit clock
SCITXDB O SCI-B transmit data
GPIO23 2 1 I/O/Z General-purpose input/output 23
EQEP1I I/O Enhanced QEP1 index
MFSXA I/O McBSP transmit frame synch
SCIRXDB I SCI-B receive data
GPIO24 97 77 I/O/Z General-purpose input/output 24
ECAP1 I/O Enhanced Capture input/output 1
EQEP2A I Enhanced QEP2 input A.
NOTE: eQEP2 is only available in the PZ and PZP packages.
SPISIMOB I/O SPI-B slave in, master out
GPIO25 39 31 I/O/Z General-purpose input/output 25
ECAP2 I/O Enhanced Capture input/output 2
Enhanced QEP2 input B.
EQEP2B I NOTE: eQEP2 is only available in the PZ and PZP packages.
SPISOMIB I/O SPI-B slave out, master in
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Table 2-5. Terminal Functions(1) (continued)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
GPIO26 78 62 I/O/Z General-purpose input/output 26
ECAP3 I/O Enhanced Capture input/output 3
Enhanced QEP2 index.
EQEP2I I/O NOTE: eQEP2 is only available in the PZ and PZP packages.
SPICLKB I/O SPI-B clock input/output
Positive Differential half of USB signal. To enable USB functionality on this pin, set the
USB0DP(1) I/O USBIOEN bit in the GPACTRL2 register.
GPIO27 77 61 I/O/Z General-purpose input/output 27
HRCAP2 I High-Resolution Input Capture 2
Enhanced QEP2 strobe.
EQEP2S I/O NOTE: eQEP2 is only available in the PZ and PZP packages.
SPISTEB I/O SPI-B slave transmit enable input/output
Negative Differential half of USB signal. To enable USB functionality on this pin, set the
USB0DM(1) I/O USBIOEN bit in the GPACTRL2 register.
GPIO28 50 40 I/O/Z General-purpose input/output 28
SCIRXDA I SCI-A receive data
SDAA I/OD I2C data open-drain bidirectional port
TZ2 I Trip zone input 2
GPIO29 43 34 I/O/Z General-purpose input/output 29
SCITXDA O SCI-A transmit data
SCLA I/OD I2C clock open-drain bidirectional port
TZ3 I Trip zone input 3
GPIO30 41 33 I/O/Z General-purpose input/output 30
CANRXA I CAN receive
Enhanced QEP2 index.
EQEP2I I/O NOTE: eQEP2 is only available in the PZ and PZP packages.
EPWM7A O Enhanced PWM7 Output A and HRPWM channel
GPIO31 40 32 I/O/Z General-purpose input/output 31
CANTXA O CAN transmit
Enhanced QEP2 strobe.
EQEP2S I/O NOTE: eQEP2 is only available in the PZ and PZP packages.
EPWM8A O Enhanced PWM8 Output A and HRPWM channel
GPIO32 99 79 I/O/Z General-purpose input/output 32
SDAA I/OD I2C data open-drain bidirectional port
EPWMSYNCI I Enhanced PWM external sync pulse input
ADCSOCAO O ADC start-of-conversion A
GPIO33 100 80 I/O/Z General-purpose input/output 33
SCLA I/OD I2C clock open-drain bidirectional port
EPWMSYNCO O Enhanced PWM external synch pulse output
ADCSOCBO O ADC start-of-conversion B
GPIO34 68 55 I/O/Z General-purpose input/output 34
COMP2OUT O Direct output of Comparator 2
COMP3OUT O Direct output of Comparator 3
(1) Depending on your USB application, additional pins may be required to maintain compliance with the USB 2.0 Specification. For more
information, see the "Universal Serial Bus (USB) Controller" chapter of the TMS320x2806x Piccolo Technical Reference Manual
(literature number SPRUH18).
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Table 2-5. Terminal Functions(1) (continued)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
GPIO35 71 57 I/O/Z General-purpose input/output 35
TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
GPIO36 72 58 I/O/Z General-purpose input/output 36
TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked
into the TAP controller on the rising edge of TCK.
GPIO37 70 56 I/O/Z General-purpose input/output 37
TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive).
GPIO38 67 54 I/O/Z General-purpose input/output 38
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the
mux function of this pin. Care must be taken to not enable this path for clocking if it is
being used for the other functions.
TCK I JTAG test clock with internal pullup
GPIO39 66 53 I/O/Z General-purpose input/output 39
GPIO40 82 – I/O/Z General-purpose input/output 40
EPWM7A O Enhanced PWM7 output A and HRPWM channel
SCITXDB O SCI-B transmit data
GPIO41 76 – I/O/Z General-purpose input/output 41
EPWM7B O Enhanced PWM7 output B
SCIRXDB I SCI-B receive data
GPIO42 1 – I/O/Z General-purpose input/output 42
EPWM8A O Enhanced PWM8 output A and HRPWM channel
TZ1 I Trip zone input 1
COMP1OUT O Direct output of Comparator 1
GPIO43 8 – I/O/Z General-purpose input/output 43
EPWM8B O Enhanced PWM8 output B
TZ2 I Trip zone input 2
COMP2OUT O Direct output of Comparator 2
GPIO44 56 – I/O/Z General-purpose input/output 44
MFSRA I/O McBSP receive frame synch
SCIRXDB I SCI-B receive data
EPWM7B O Enhanced PWM7 output B
GPIO50 42 – I/O/Z General-purpose input/output 50
EQEP1A I Enhanced QEP1 input A
MDXA O McBSP transmit serial data
TZ1 I Trip zone input 1
GPIO51 48 – I/O/Z General-purpose input/output 51
EQEP1B I Enhanced QEP1 input B
MDRA I McBSP receive serial data
TZ2 I Trip zone input 2
GPIO52 53 – I/O/Z General-purpose input/output 52
EQEP1S I/O Enhanced QEP1 strobe
MCLKXA I/O McBSP transmit clock
TZ3 I Trip zone input 3
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Table 2-5. Terminal Functions(1) (continued)
TERMINAL I/O/Z DESCRIPTION
PZ/PZP PN/PFP
NAME PIN # PIN #
GPIO53 65 – I/O/Z General-purpose input/output 53
EQEP1I I/O Enhanced QEP1 index
MFSXA I/O McBSP transmit frame synch
GPIO54 69 – I/O/Z General-purpose input/output 54
SPISIMOA I/O SPI-A slave in, master out
EQEP2A I Enhanced QEP2 input A
HRCAP1 I High-Resolution Input Capture 1
GPIO55 75 – I/O/Z General-purpose input/output 55
SPISOMIA I/O SPI-A slave out, master in
EQEP2B I Enhanced QEP2 input B
HRCAP2 I High-Resolution Input Capture 2
GPIO56 85 – I/O/Z General-purpose input/output 56
SPICLKA I/O SPI-A clock input/output
EQEP2I I/O Enhanced QEP2 index
HRCAP3 I High-Resolution Input Capture 3
GPIO57 89 – I/O/Z General-purpose input/output 57
SPISTEA I/O SPI-A slave transmit enable input/output
EQEP2S I/O Enhanced QEP2 strobe
HRCAP4 I High-Resolution Input Capture 4
GPIO58 94 – I/O/Z General-purpose input/output 58
MCLKRA I/O McBSP receive clock
SCITXDB O SCI-B transmit data
EPWM7A O Enhanced PWM7 output A and HRPWM channel
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2.5 Brief Descriptions
2.5.1 CPU
The 2806x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-
based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very
efficient C/C++ engine, enabling users to develop not only their system control software in a high-level
language, but also enabling development of math algorithms using C/C++. The device is as efficient at
MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This
efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit
processing capabilities enable the controller to handle higher numerical resolution problems efficiently.
Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-
deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high
speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.
2.5.2 Control Law Accelerator (CLA)
The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the
capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its
own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be
specified. Each task is started by software or a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU
Timer 0. The CLA executes one task at a time to completion. When a task completes the main CPU is
notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task.
The CLA can directly access the ADC Result registers, ePWM+HRPWM, eCAP, and eQEP registers.
Dedicated message RAMs provide a method to pass additional data between the main CPU and the CLA.
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2.5.3 Viterbi, Complex Math, CRC Unit (VCU)
The C28x VCU enhances the processing power of C2000™ devices by adding additional assembly
instructions to target complex math, Viterbi decode, and CRC calculations. The VCU instructions
accelerate many applications, including the following:
• Orthogonal frequency-division multiplex (OFDM) used in the PRIME and G3 standards for power line
communications
• Short-range radar complex math calculations
• Power calculations
• Memory and data communication packet checks (CRC)
The VCU features include:
• Instructions to support Cyclic Redundancy Checks (CRCs), which is a polynomial code checksum.
– CRC8
– CRC16
– CRC32
• Instructions to support a flexible software implementation of a Viterbi decoder
– Branch metric calculations for a code rate of 1/2 or 1/3
– Add-Compare Select or Viterbi Butterfly in 5 cycles per butterfly
– Traceback in 3 cycles per stage
– Easily supports a constraint length of K = 7 used in PRIME and G3 standards
• Complex math arithmetic unit
– Single-cycle Add or Subtract
– 2-cycle multiply
– 2-cycle multiply and accumulate (MAC)
– Single-cycle repeat MAC
• Independent register space
2.5.4 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and
data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus
accesses can be summarized as follows:
Highest: Data Writes (Simultaneous data and program writes cannot occur on the
memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the
memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the
memory bus.)
Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the
memory bus.)
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2.5.5 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the
devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various busses that make up the processor Memory Bus into a single bus consisting of 16 address
lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are
supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1).
2.5.6 Real-Time JTAG and Analysis
The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug.
Additionally, the devices support real-time mode of operation allowing modification of the contents of
memory, peripheral, and register locations while the processor is running and executing code and
servicing interrupts. The user can also single step through non-time-critical code while enabling time-
critical interrupts to be serviced without interference. The device implements the real-time mode in
hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software
monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or
data/address watch-points and generating various user-selectable break events when a match occurs.
These devices do not support boundary scan; however, IDCODE and BYPASS features are available if
the following considerations are taken into account. The IDCODE does not come by default. The user
needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For
BYPASS instruction, the first shifted DR value would be 1.
2.5.7 Flash
The F28069/68/67/66 devices contain 128K x 16 of embedded flash memory, segregated into eight
16K x 16 sectors. The F28065/64/63/62 devices contain 64K x 16 of embedded flash memory, segregated
into eight 8K x 16 sectors. All devices also contain a single 1K x 16 of OTP memory at address range
0x3D 7800 – 0x3D 7BF9. The user can individually erase, program, and validate a flash sector while
leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to
execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to
enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and
data space; therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 –
0x3F 7FF5 are reserved for data variables and should not contain program code.
NOTE
The Flash and OTP wait-states can be configured by the application. This allows applications
running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical
Reference Manual (literature number SPRUH18).
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
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2.5.8 M0, M1 SARAMs
All devices contain these two blocks of single-access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a
unified memory map to the programmer. This makes for easier programming in high-level languages.
2.5.9 L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
The device contains up to 48K x 16 of single-access RAM. To ascertain the exact size for a given device,
see the device-specific memory map figures in Section 2.2. This block is mapped to both program and
data space. L0 is 2K in size. L1 and L2 are each 1K in size. L3 is 4K in size. L4, L5, L6, L7, and L8 are
each 8K in size. L0, L1, and L2 are shared with the CLA, which can utilize these blocks for its data space.
L3 is shared with the CLA, which can utilize this block for its program space. L5, L6, L7, and L8 are
shared with the DMA, which can utilize these blocks for its data space. DPSARAM refers to the dual-port
configuration of these blocks.
2.5.10 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math-related algorithms.
Table 2-6. Boot Mode Selection
GPIO34/COMP2OUT/
MODE GPIO37/TDO TRST MODE
COMP3OUT
3 1 1 0 GetMode
2 1 0 0 Wait (see Section 2.5.11 for description)
1 0 1 0 SCI
0 0 0 0 Parallel IO
EMU x x 1 Emulation Boot
2.5.10.1 Emulation Boot
When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this
case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM
locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,
then the Wait boot option is used. All boot mode options can be accessed in emulation boot.
2.5.10.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another
boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then
boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP.
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2.5.10.3 Peripheral Pins Used by the Bootloader
Table 2-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table
to see if these conflict with any of the peripherals you would like to use in your application.
Table 2-7. Peripheral Bootload Pins
BOOTLOADER PERIPHERAL LOADER PINS
SCI SCIRXDA (GPIO28)
SCITXDA (GPIO29)
Parallel Boot Data (GPIO31,30,5:0)
28x Control (AIO6)
Host Control (AIO12)
SPI SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
I2C SDAA (GPIO32)
SCLA (GPIO33)
CAN CANRXA (GPIO30)
CANTXA (GPIO31)
2.5.11 Security
The devices support high levels of security to protect the user firmware from being reverse-engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks.
The security feature prevents unauthorized users from examining the memory contents via the JTAG port,
executing code from external memory or trying to boot-load some undesirable software that would export
the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-
bit KEY value that matches the value stored in the password locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent
unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0
memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow
emulation of secure code, while maintaining the CSM protection against secure memory reads, the user
must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in
the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the
password in the flash must still be performed. If the lower 64 bits of the password locations are all ones
(unprogrammed), then the KEY value does not need to match.
When initially debugging a device with the password locations in flash programmed (that is, secured), the
CPU will start running and may execute an instruction that performs an access to a protected ECSL area.
If this happens, the ECSL will trip and cause the emulator connection to be cut.
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The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an
emulator to be connected without tripping security. Piccolo devices do not support a hardware wait-in-
reset mode.
NOTE
• When the code-security passwords are programmed, all addresses between 0x3F 7F80
and 0x3F 7FF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
• If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may
be used for code or data. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and
should not contain program code.
The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing
so would permanently lock the device.
Disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY
(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN
ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO
TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR
THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
2.5.12 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2806x, 72 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of
12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
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2.5.13 External Interrupts (XINT1–XINT3)
The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be
selected for negative, positive, or both negative and positive edge triggering and can also be
enabled/disabled. These interrupts also contain a 16-bit free-running up counter, which is reset to zero
when a valid interrupt edge is detected. This counter can be used to accurately time-stamp the interrupt.
There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept
inputs from GPIO0–GPIO31 pins.
2.5.14 Internal Zero Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a
crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 16 input-clock-scaling
ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating
frequency if lower power operation is desired. Refer to Section 4, Electrical Specifications, for timing
details. The PLL block can be set in bypass mode. A second PLL (PLL2) feeds the HRCAP module.
2.5.15 Watchdog
Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a
missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a
certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog
can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either
generate an interrupt or a device reset.
2.5.16 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled
relative to the CPU clock.
2.5.17 Low-power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE: Places CPU in low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT: This mode basically shuts down the device and places it in the lowest possible power-
consumption mode. If the internal zero-pin oscillators are used as the clock source,
the HALT mode turns them off, by default. To keep these oscillators from shutting
down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin
oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip
crystal oscillator is used as the clock source, it is shut down in this mode. A reset or
an external signal (through a GPIO pin) or the CPU-watchdog can wake the device
from this mode.
The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put
the device into HALT or STANDBY.
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2.5.18 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash: Flash Waitstate Registers
Timers: CPU-Timers 0, 1, 2 Registers
CSM: Code Security Module KEY Registers
ADC: ADC Result Registers
CLA: Control Law Accelrator Registers and Message RAMs
PF1: GPIO: GPIO MUX Configuration and Control Registers
eCAN: Enhanced Control Area Network Configuration and Control Registers
PF2: SYS: System Control Registers
SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Configuration Registers
I2C: Inter-Integrated Circuit Module and Registers
XINT: External Interrupt Registers
PF3: McBSP: Multichannel Buffered Serial Port Registers
ePWM: Enhanced Pulse Width Modulator Module and Registers
eCAP: Enhanced Capture Module and Registers
eQEP: Enhanced Quadrature Encoder Pulse Module and Registers
Comparators: Comparator Modules
USB: Universal Serial Bus Module and Registers
2.5.19 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
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2.5.20 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use
and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to
INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLKOUT (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTSOC2)
• External clock source
2.5.21 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM: The enhanced PWM peripheral supports independent/complementary PWM
generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the
HRPWM high resolution duty and period features. The type 1 module found on
2806x devices also supports increased dead-band resolution, enhanced SOC and
interrupt generation, and advanced triggering including trip functions based on
comparator outputs.
eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit
timer. This peripheral has a watchdog timer to detect motor stall and input error
detection logic to identify simultaneous edge transition in QEP signals.
ADC: The ADC block is a 12-bit converter. It has up to 16 single-ended channels pinned
out, depending on the device. It contains two sample-and-hold units for
simultaneous sampling.
Comparator: Each comparator block consists of one analog comparator along with an internal
10-bit reference for supplying one input of the comparator.
HRCAP: The high-resolution capture peripheral operates in normal capture mode via a 16-
bit counter clocked off of the HCCAPCLK or in high-resolution capture mode by
utilizing built-in calibration logic in conjunction with a TI-supplied calibration library.
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2.5.22 Serial Port Peripherals
The devices support the following serial communication peripherals:
SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream
of programmed length (one to sixteen bits) to be shifted into and out of the device
at a programmable bit-transfer rate. Normally, the SPI is used for communications
between the MCU and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multi-device communications are
supported by the master/slave operation of the SPI. The SPI contains a 4-level
receive and transmit FIFO for reducing interrupt servicing overhead.
SCI: The serial communications interface is a two-wire asynchronous serial port,
commonly known as UART. The SCI contains a 4-level receive and transmit FIFO
for reducing interrupt servicing overhead.
I2C: The inter-integrated circuit (I2C) module provides an interface between a MCU
and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)
specification version 2.1 and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit/receive up to 8-bit data
to/from the MCU through the I2C module. The I2C contains a 4-level receive-and-
transmit FIFO for reducing interrupt servicing overhead.
eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
McBSP: The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-
quality codecs for modem applications or high-quality stereo audio DAC devices.
The McBSP receive and transmit registers are supported by the DMA to
significantly reduce the overhead for servicing this peripheral. Each McBSP
module can be configured as an SPI as required.
USB: The USB peripheral, which is conformant to the USB 2.0 specification, may be
used as either a full-speed (12-Mbps) device controller or a full-/low-speed
(12-Mbps/1.5-Mbps) host controller. The controller supports a total of six user-
configurable endpoints—all of which can be accessed via DMA, in addition to a
dedicated control endpoint for endpoint zero. All packets transmitted or received
are buffered in 4KB of dedicated endpoint memory. The USB peripheral supports
all four transfer types: Control, Interrupt, Bulk, and Isochronous. Because of the
complexity of the USB peripheral and the associated protocol overhead, a full
software library with application examples is provided within ControlSUITE™.
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2.6 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 2-8.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 2-9.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 2-10.
Peripheral Frame 3: McBSP registers are mapped to this. See Table 2-11.
Table 2-8. Peripheral Frame 0 Registers(1)
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED(2)
Device Emulation Registers 0x00 0880 – 0x00 0984 261 Yes
System Power Control Registers 0x00 0985 – 0x00 0987 3 Yes
FLASH Registers(3) 0x00 0A80 – 0x00 0ADF 96 Yes
Code Security Module Registers 0x00 0AE0 – 0x00 0AEF 16 Yes
ADC registers 0x00 0B00 – 0x00 0B0F 16 No
(0 wait read only)
CPU–TIMER0/1/2 Registers 0x00 0C00 – 0x00 0C3F 64 No
PIE Registers 0x00 0CE0 – 0x00 0CFF 32 No
PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 No
DMA Registers 0x00 1000 – 0x00 11FF 512 Yes
CLA Registers 0x00 1400 – 0x00 147F 128 Yes
CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 – 0x00 14FF 128 NA
CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 – 0x00 157F 128 NA
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
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Table 2-9. Peripheral Frame 1 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
eCAN-A registers 0x00 6000 – 0x00 61FF 512 (1)
HRCAP1 registers 0x00 6AC0 – 0x00 6ADF 32 (1)
HRCAP2 registers 0x00 6AE0 – 0x00 6AFF 32 (1)
HRCAP3 registers 0x00 6C80 – 0x00 6C9F 32 (1)
HRCAP4 registers 0x00 6CA0 – 0x00 6CBF 32 (1)
GPIO registers 0x00 6F80 – 0x00 6FFF 128 (1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 2-10. Peripheral Frame 2 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
System Control Registers 0x00 7010 – 0x00 702F 32 Yes
SPI-A Registers 0x00 7040 – 0x00 704F 16 No
SCI-A Registers 0x00 7050 – 0x00 705F 16 No
NMI Watchdog Interrupt Registers 0x00 7060 – 0x00 706F 16 Yes
External Interrupt Registers 0x00 7070 – 0x00 707F 16 Yes
ADC Registers 0x00 7100 – 0x00 717F 128 (1)
SPI-B Registers 0x00 7740 – 0x00 774F 16 No
SCI-B Registers 0x00 7750 – 0x00 775F 16 No
I2C-A Registers 0x00 7900 – 0x00 793F 64 (1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 2-11. Peripheral Frame 3 Registers
NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
USB0 Registers 0x00 4000 – 0x00 4FFF 4096 No
McBSP-A Registers 0x00 5000 – 0x00 503F 64 No
Comparator 1 registers 0x00 6400 – 0x00 641F 32 (1)
Comparator 2 registers 0x00 6420 – 0x00 643F 32 (1)
Comparator 3 registers 0x00 6440 – 0x00 645F 32 (1)
ePWM1 + HRPWM1 registers 0x00 6800 – 0x00 683F 64 (1)
ePWM2 + HRPWM2 registers 0x00 6840 – 0x00 687F 64 (1)
ePWM3 + HRPWM3 registers 0x00 6880 – 0x00 68BF 64 (1)
ePWM4 + HRPWM4 registers 0x00 68C0 – 0x00 68FF 64 (1)
ePWM5 + HRPWM5 registers 0x00 6900 – 0x00 693F 64 (1)
ePWM6 + HRPWM6 registers 0x00 6940 – 0x00 697F 64 (1)
ePWM7 + HRPWM7 registers 0x00 6980 – 0x00 69BF 64 (1)
ePWM8 + HRPWM8 registers 0x00 69C0 – 0x00 69FF 64 (1)
eCAP1 registers 0x00 6A00 – 0x00 6A1F 32 No
eCAP2 registers 0x00 6A20 – 0x00 6A3F 32 No
eCAP3 registers 0x00 6A40 – 0x00 6A57 32 No
eQEP1 registers 0x00 6B00 – 0x00 6B3F 64 (1)
eQEP2 registers 0x00 6B40 – 0x00 6B7F 64 (1)
(1) Some registers are EALLOW protected. See the module reference guide for more information.
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2.7 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 2-12.
Table 2-12. Device Emulation Registers
ADDRESS EALLOW
NAME SIZE (x16) DESCRIPTION
RANGE PROTECTED
0x0880–
DEVICECNF 2 Device Configuration Register Yes
0x0881
PARTID(1) 0x3D 7E80 1 Part ID Register TMS320F28069PZP/PZ 0x009E
TMS320F28069UPZP/PZ 0x009F
TMS320F28069PFP/PN 0x009C
TMS320F28069UPFP/PN 0x009D
TMS320F28068PZP/PZ 0x008E
TMS320F28068UPZP/PZ 0x008F
TMS320F28068PFP/PN 0x008C
TMS320F28068UPFP/PN 0x008D
TMS320F28067PZP/PZ 0x008A
TMS320F28067UPZP/PZ 0x008B
TMS320F28067PFP/PN 0x0088
TMS320F28067UPFP/PN 0x0089
TMS320F28066PZP/PZ 0x0086
TMS320F28066UPZP/PZ 0x0087
TMS320F28066PFP/PN 0x0084
TMS320F28066UPFP/PN 0x0085 No
TMS320F28065PZP/PZ 0x007E
TMS320F28065UPZP/PZ 0x007F
TMS320F28065PFP/PN 0x007C
TMS320F28065UPFP/PN 0x007D
TMS320F28064PZP/PZ 0x006E
TMS320F28064UPZP/PZ 0x006F
TMS320F28064PFP/PN 0x006C
TMS320F28064UPFP/PN 0x006D
TMS320F28063PZP/PZ 0x006A
TMS320F28063UPZP/PZ 0x006B
TMS320F28063PFP/PN 0x0068
TMS320F28063UPFP/PN 0x0069
TMS320F28062PZP/PZ 0x0066
TMS320F28062UPZP/PZ 0x0067
TMS320F28062PFP/PN 0x0064
TMS320F28062UPFP/PN 0x0065
(1) For TMS320F28069Udevices, the PARTID/CLASSID numbers are also used for TMX devices. In the case of TMX320F28069UPFPA
and TMX320F28069UPZPA devices, the temperature rating is "A" instead of "T".
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Table 2-12. Device Emulation Registers (continued)
ADDRESS EALLOW
NAME SIZE (x16) DESCRIPTION
RANGE PROTECTED
CLASSID(1) 0x0882 1 Class ID Register TMS320F28069 0x009F
TMS320F28069U0x009F
TMS320F28068 0x008F
TMS320F28068U0x008F
TMS320F28067 0x008F
TMS320F28067U0x008F
TMS320F28066 0x008F
TMS320F28066U0x008F No
TMS320F28065 0x007F
TMS320F28065U0x007F
TMS320F28064 0x006F
TMS320F28064U0x006F
TMS320F28063 0x006F
TMS320F28063U0x006F
TMS320F28062 0x006F
TMS320F28062U0x006F
REVID 0x0883 1 Revision ID Register 0x0000 - Silicon Rev. 0 - TMX No
0x0001 - Silicon Rev. A - TMS
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2.8 VREG/BOR/POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and
space of a second external regulator on an application board. Additionally, internal power-on reset (POR)
and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.
2.8.1 On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors
are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
2.8.1.1 Using the On-chip VREG
To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended
operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by
the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum)
capacitance for proper regulation of the VREG. These capacitors should be located as close as possible
to the VDD pins.
2.8.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied
high.
2.8.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the
burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is
to create a clean reset throughout the device during the entire power-up procedure. The trip point is a
looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device
operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-
up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled
(VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their
respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage
protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 4 for the various trip
points as well as the delay time for the device to release the XRS pin after the under/over-voltage
condition is removed. Figure 2-10 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO
BOR functions, a bit is provided in the BORCFG register. See the "Systems Control and Interrupts"
chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for
details.
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I/O Pin
In
Out
DIR (0 = Input, 1 = Output)
(Force Hi-Z When High)
SYSRS
C28
Core
Sync RS
XRS
PLL
+
Clocking
Logic
MCLKRS
VREGHALT
Deglitch
Filter
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
POR/BOR
Generating
Module
XRS
Pin
SYSCLKOUT
WDRST(A)
JTAG
TCK
Detect
Logic
PBRS(B)
Internal
Weak PU
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A. WDRST is the reset signal from the CPU-watchdog.
B. PBRS is the reset signal from the POR/BOR module.
Figure 2-10. VREG + POR + BOR + Reset Signal Connectivity
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2.9 System Control
This section describes the oscillator and clocking mechanisms, the watchdog function and the low power
modes.
Table 2-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME ADDRESS SIZE (x16) DESCRIPTION(1)
BORCFG 0x00 0985 1 BOR Configuration Register
XCLK 0x00 7010 1 XCLKOUT Control
PLLSTS 0x00 7011 1 PLL Status Register
CLKCTL 0x00 7012 1 Clock Control Register
PLLLOCKPRD 0x00 7013 1 PLL Lock Period
INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register
INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register
PCLKCR2 0x00 7019 1 Peripheral Clock Control Register 2
LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register
PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0
PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1
LPMCR0 0x00 701E 1 Low Power Mode Control Register 0
PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3
PLLCR 0x00 7021 1 PLL Control Register
SCSR 0x00 7022 1 System Control and Status Register
WDCNTR 0x00 7023 1 Watchdog Counter Register
WDKEY 0x00 7025 1 Watchdog Reset Key Register
WDCR 0x00 7029 1 Watchdog Control Register
JTAGDEBUG 0x00 702A 1 JTAG Port Debug Register
PLL2CTL 0x00 7030 1 PLL2 Configuration Register
PLL2MULT 0x00 7032 1 PLL2 Multiplier Register
PLL2STS 0x00 7034 1 PLL2 Lock Status Register
SYSCLK2CNTR 0x00 7036 1 SYSCLK2 Clock Counter Register
EPWMCFG 0x00 703A 1 ePWM DMA/CLA Configuration Register
(1) All registers in this table are EALLOW protected.
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LOSPCP
(System Ctrl Regs)
Peripheral
Registers
SPI-A, SPI-B, SCI-A, SCI-B PF2
LSPCLK
SYSCLKOUT
C28x Core CLKIN
Peripheral
Registers
USB PF3
GPIO
Mux
LOSPCP
(System Ctrl Regs)
Peripheral
Registers
McBSP PF3
LSPCLK
Peripheral
Registers
eCAN-A PF1
Peripheral
Registers
eCAP1, eCAP2, eCAP3
eQEP1, eQEP2 PF3
Peripheral
Registers
ePWM1, ePWM2,
ePWM3, ePWM4, ePWM5,
ePWM6, ePWM7, ePWM8 PF3
Peripheral
Registers
I2C-A
PF2
Peripheral
Registers
HRCAP1, HRCAP2,
HRCAP3, HRCAP4 PF1
ADC
Registers
12-Bit ADC
16 Ch PF2
PF0
COMP
Registers
COMP1/2/3 PF3
6
Analog
GPIO
Mux
/2
PCLKCR0/1/2/3
(System Ctrl Regs)
Clock Enables
Clock Enables
Clock Enables
Clock Enables
Clock Enables
Clock Enables
Clock Enables
Clock Enables
Clock Enables
Clock Enables
PLL2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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Figure 2-11 shows the various clock domains that are discussed. Figure 2-12 shows the various clock
sources (both internal and external) that can provide a clock for device operation.
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 2-11. Clock and Reset Domains
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INTOSC1TRIM Reg(A)
Internal
OSC 1
(10 MHz)
OSCE
CLKCTL[INTOSC1OFF]
WAKEOSC
CLKCTL[INTOSC1HALT]
INTOSC2TRIM Reg(A) Internal
OSC 2
(10 MHz)
OSCE
CLKCTL[INTOSC2OFF]
CLKCTL[INTOSC2HALT]
1 = Turn OSC Off
1 = Ignore HALT
1 = Turn OSC Off
1 = Ignore HALT
XCLK[XCLKINSEL] 0 = GPIO38
1 = GPIO19
GPIO19
or
GPIO38
CLKCTL[XCLKINOFF]
0
0
1
(Crystal)
OSC
XCLKIN
X1
X2
CLKCTL[XTALOSCOFF] 0 = OSC on (default on reset)
1 = Turn OSC off
0
1
0
1
OSC1CLK
OSCCLKSRC1 WDCLK
OSC2CLK 0
1
CLKCTL[WDCLKSRCSEL]
(OSC1CLK on reset)XRS
CLKCTL[OSCCLKSRCSEL]
CLKCTL[TRM2CLKPRESCALE]
CLKCTL[TMR2CLKSRCSEL]
OSCCLKSRC2
11
Prescale
/1, /2, /4,
/8, /16
00
01, 10, 11
CPUTMR2CLK
SYNC
Edge
Detect
10
01
CLKCTL[OSCCLKSRC2SEL]
SYSCLKOUT
WAKEOSC
(Oscillators enabled when this signal is high)
EXTCLK
XTAL
XCLKIN
(OSC1CLK on reset)XRS
OSCCLK PLL
Missing-Clock-Detect Circuit(B)
CPU-Watchdog
PLL2CTL.PLL2CLKSRCSEL
PLL2CTL.PLL2EN
SYSCLK2 to
USB and
HRCAP Blocks
PLL2
/2
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A. Register loaded from TI OTP-based calibration function.
B. See Section 2.9.5 for details on missing clock detection.
Figure 2-12. Clock Tree
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External Clock Signal
(Toggling 0−VDDIO)
XCLKIN/GPIO19/38 X2
NC
X1
X2X1
Crystal
XCLKIN/GPIO19/38
Turn off
XCLKIN path
in CLKCTL
register
Rd
CL1 CL2
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2.9.1 Internal Zero Pin Oscillators
The F2806x devices contain two independent internal zero pin oscillators. By default both oscillators are
turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings,
unused oscillators may be powered down by the user. The center frequency of these oscillators is
determined by their respective oscillator trim registers, written to in the calibration routine as part of the
boot ROM execution. See Section 5, Peripheral and Electrical Specifications, for more information on
these oscillators.
2.9.2 Crystal Oscillator Option
The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in
Table 2-14. Furthermore, ESR range = 30 to 150 Ω.
Table 2-14. Typical Specifications for External Quartz Crystal(1)
FREQUENCY (MHz) Rd(Ω) CL1 (pF) CL2 (pF)
5 2200 18 18
10 470 15 15
15 0 15 15
20 0 12 12
(1) Cshunt should be less than or equal to 5 pF.
Figure 2-13. Using the On-chip Crystal Oscillator
NOTE
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the
IC and crystal. The value is usually approximately twice the value of the crystal's load
capacitance.
2. The load capacitance of the crystal is described in the crystal specifications of the
manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the
operation of their device with the MCU chip. The resonator/crystal vendor has the
equipment and expertise to tune the tank circuit. The vendor can also advise the
customer regarding the proper tank component values that will produce proper start up
and stability over the entire operating range.
Figure 2-14. Using a 3.3-V External Oscillator
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2.9.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of
the PLL (VCOCLK) is at least 50 MHz.
Table 2-15. PLL Settings
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(1) (2) PLLSTS[DIVSEL] = 0 or 1(3) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3
00000 (PLL bypass) OSCCLK/4 (Default)(1) OSCCLK/2 OSCCLK
00001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1
00010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 (OSCCLK * 2)/1
00011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 (OSCCLK * 3)/1
00100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 (OSCCLK * 4)/1
00101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 (OSCCLK * 5)/1
00110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 (OSCCLK * 6)/1
00111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 (OSCCLK * 7)/1
01000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 (OSCCLK * 8)/1
01001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 (OSCCLK * 9)/1
01010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 (OSCCLK * 10)/1
01011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 (OSCCLK * 11)/1
01100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 (OSCCLK * 12)/1
01101 (OSCCLK * 13)/4 (OSCCLK * 13)/2 (OSCCLK * 13)/1
01110 (OSCCLK * 14)/4 (OSCCLK * 14)/2 (OSCCLK * 14)/1
01111 (OSCCLK * 15)/4 (OSCCLK * 15)/2 (OSCCLK * 15)/1
10000 (OSCCLK * 16)/4 (OSCCLK * 16)/2 (OSCCLK * 16)/1
(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(2) This register is EALLOW protected. See the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical
Reference Manual (literature number SPRUH18) for more information.
(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
Table 2-16. CLKIN Divide Options
PLLSTS [DIVSEL] CLKIN DIVIDE
0 /4
1 /4
2 /2
3 /1
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The PLL-based clock module provides four modes of operation:
• INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide
the clock for the Watchdog block, core and CPU-Timer 2
•INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide
the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be
independently chosen for the Watchdog block, core and CPU-Timer 2.
•Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external
crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to
the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 2-5 for details.
•External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to
be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin.
Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected
as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit
disables this clock input (forced low). If the clock source is not used or the respective pins are used as
GPIOs, the user should disable at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that
clock source must be disabled (using the CLKCTL register) before switching clocks.
Table 2-17. Possible PLL Configuration Modes
CLKIN AND
PLL MODE REMARKS PLLSTS[DIVSEL] SYSCLKOUT
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low 0, 1 OSCCLK/4
PLL Off power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) 2 OSCCLK/2
before entering this mode. The CPU clock (CLKIN) is derived directly from the 3 OSCCLK/1
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external 0, 1 OSCCLK/4
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
PLL Bypass 2 OSCCLK/2
while the PLL locks to a new frequency after the PLLCR register has been 3 OSCCLK/1
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. 0, 1 OSCCLK * n/4
PLL Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the 2 OSCCLK * n/2
Enable(1) PLLCR the device will switch to PLL Bypass mode until the PLL locks. 3 OSCCLK * n/1
(1) PLLSTS[DIVSEL] should not be set to /1 mode while the PLL is enabled.
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2.9.4 USB and HRCAP PLL Module (PLL2)
In addition to the main system PLL, these devices also contain a second PLL (PLL2) which can be used to
clock the USB and HRCAP peripherals. The PLL supports multipliers of 1 to 15 and has a fixed divide-by-
two on its output.
PLL2 may be clocked from the following three sources by modifying the PLL2CLKSRCSEL bits
appropriately in the PLL2CTL register:
• INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1 and provides a 10-
MHz clock. If used as a clock source for HRCAP, the oscillator compensation routine should be called
frequently. Because of accuracy requirements, INTOSC1 cannot be used as a clock source for the
USB.
• Crystal/Resonator Operation: The (crystal) oscillator enables the use of an external crystal or resonator
attached to the device to provide the time base. The crystal or resonator is connected to the X1/X2
pins.
• External Clock Source Operation: This mode allows the reference clock to be derived from an external
single-ended clock source connected to either GPIO19 or GPIO38. The XCLKINSEL bit in the XCLK
register should be set appropriately to enable the selected GPIO to drive XCLKIN.
NOTE
For proper operation of the USB module, PLL2 should be configured to generate a 120-MHz
clock. This will be divided by two to yield the desired 60 MHz for the USB peripheral.
HRCAP supports a maximum clock input frequency of 120 MHz.
52 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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NMIFLG[NMINT]
1
0
Generate
Interrupt
Pulse
When
Input = 1
NMINT
Latch
Clear
Set Clear
NMIFLGCLR[NMINT]
XRS
0
NMICFG[CLOCKFAIL]
Latch
Clear
Set
Clear
XRS
NMIFLG[CLOCKFAIL]
NMI Watchdog
SYSCLKOUT
SYSRS
NMIRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
NMIFLGCLR[CLOCKFAIL]
SYNC?
NMIFLGFRC[CLOCKFAIL]
SYSCLKOUT
See System
Control Section
CLOCKFAIL
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
2.9.5 Loss of Input Clock (NMI Watchdog Function)
The 2806x devices may be clocked from either one of the internal zero-pin oscillators
(INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the
clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will
issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at
a typical frequency of 1–5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired
immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the
Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect
the input clock failure and initiate necessary corrective action such as switching over to an alternative
clock source (if available) or initiate a shut-down procedure for the system.
If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a
preprogrammed time interval. Figure 2-15 shows the interrupt mechanisms involved.
Figure 2-15. NMI-Watchdog
2.9.6 CPU-Watchdog Module
The CPU-watchdog module on the 2806x device is similar to the one used on the 281x/280x/283xx
devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter
or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets
the watchdog counter. Figure 2-16 shows the various functional blocks within the watchdog module.
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/512
WDCLK
WDCR (WDPS[2:0])
WDCLK
WDCNTR(7:0)
WDKEY(7:0)
Good Key
101
WDCR (WDCHK[2:0])
Bad
WDCHK
Key
WDCR (WDDIS)
Clear Counter
SCSR (WDENINT)
Watchdog
Prescaler
Generate
Output Pulse
(512 OSCCLKs)
8-Bit
Watchdog
Counter
CLR
WDRST
WDINT
Watchdog
55 + AA
Key Detector
XRS
Core-reset
WDRST(A)
Internal
Pullup
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-
watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog
counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).
NOTE
The CPU-watchdog is different from the NMI watchdog. It is the legacy watchdog that is
present in all 28x devices.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the MCU will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the flash memory.
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 2-16. CPU-Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM
block so that it can wake the device from STANDBY (if enabled). See Section 2.10, Low-power Modes
Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.
54 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
2.10 Low-power Modes Block
Table 2-18 summarizes the various modes.
Table 2-18. Low-power Modes
MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT(1)
XRS, CPU-watchdog interrupt, any
IDLE 00 On On On enabled interrupt
On XRS, CPU-watchdog interrupt, GPIO
STANDBY 01 Off Off
(CPU-watchdog still running) Port A signal, debugger(2)
Off
(on-chip crystal oscillator and XRS, GPIO Port A signal, debugger(2),
HALT(3) 1X PLL turned off, zero-pin oscillator Off Off CPU-watchdog
and CPU-watchdog state
dependent on user code.)
(1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power
mode will not be exited and the device will go back into the indicated low power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:
IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the
processor. The LPM block performs no tasks during this mode as long as
the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.
HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake
the device from HALT mode. The user selects the signal in the
GPIOLPMSEL register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included). They
will be in whatever state the code left them in when the IDLE instruction was executed. See
the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical
Reference Manual (literature number SPRUH18) for more details.
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3 Device and Documentation Support
3.1 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more
detail on each of these steps, see the following:
•Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0).
•C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
• TMS320F28x MCU Development and Experimenter's Kits (http://www.ti.com/f28xkits)
3.2 Development Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of 2806x-based applications:
Software Development Tools
• Code Composer Studio™ Integrated Development Environment (IDE)
– C/C++ Compiler
– Code generation tools
– Assembler/Linker
– Cycle Accurate Simulator
• Application algorithms
• Sample applications code
Hardware Development Tools
• Development and evaluation boards
• JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100
• Flash programming tools
• Power supply
• Documentation and cables
3.3 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F28069). Texas Instruments recommends two of
three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully
qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
TMS Fully qualified production device
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PREFIX
TMS
TMX = experimental device
TMP = prototype device
TMS = qualified device
320
DEVICE FAMILY
320 = TMS320 MCU Family
F
TECHNOLOGY
F = Flash
28069
DEVICE(A)
28069
28068
28067
28066
28065
28064
28063
28062
28069U
28068U
28067U
28066U
28065U
28064U
28063U
28062U
PZP
PACKAGE TYPE
80-Pin PN Low-Profile Quad Flatpack (LQFP)
10
80-Pin PFP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP)
0-Pin PZ Low-Profile Quad Flatpack (LQFP)
100-Pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP)
TM
TM
TEMPERATURE RANGE
S
−40°C to 105°C
−40°C to 125°C
−40°C to 125°C
(Q refers to Q100 qualification for automotive applications.)
T
S
Q
=
=
=
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, S). Figure 3-1 provides a legend
for reading the complete device name for any family member.
A. USB is available only on 2806xUdevices.
Figure 3-1. Device Nomenclature
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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3.4 Documentation Support
Extensive documentation supports all of the TMS320™ MCU family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications.
See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) for more
information on types of peripherals. See the TMS320x2806x Piccolo Technical Reference Manual
(literature number SPRUH18) for more information about each peripheral.
The following documents can be downloaded from the TI website (www.ti.com):
Data Manual/Errata
SPRS698 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065,
TMS320F28064, TMS320F28063, TMS320F28062 Piccolo Microcontrollers Data Manual
contains the pinout, signal descriptions, as well as electrical and timing specifications for the
2806x devices.
SPRZ342 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065,
TMS320F28064, TMS320F28063, TMS320F28062 Piccolo MCU Silicon Errata describes
known advisories on silicon and provides workarounds.
CPU User's Guides
SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing
unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital
signal processors (DSPs). It also describes emulation features available on these DSPs.
Peripheral Guides and Technical Reference Manuals
SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
SPRUH18 TMS320x2806x Piccolo Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral
and subsystem in the device.
Tools Guides
SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly
language tools (assembler and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives
for the TMS320C28x device.
SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the
TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code
and produces TMS320 DSP assembly language source code for the TMS320C28x device.
SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x™ core.
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
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3.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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4 Device Operating Conditions
4.1 Absolute Maximum Ratings(1) (2)
Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V
Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V
Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V
Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V
Output voltage range, VO–0.3 V to 4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO)(3) ±20 mA
Output clamp current, IOK (VO< 0 or VO> VDDIO) ±20 mA
Junction temperature range, TJ(4) –40°C to 150°C
Storage temperature range, Tstg (4) –65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ± 2 mA.
(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).
4.2 Recommended Operating Conditions
MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO(1) 2.97 3.3 3.63 V
Device supply voltage CPU, VDD (When internal 1.71 1.8 1.995 V
VREG is disabled and 1.8 V is supplied externally)
Supply ground, VSS 0 V
Analog supply voltage, VDDA(1) 2.97 3.3 3.63 V
Analog ground, VSSA 0 V
Device clock frequency (system clock) 2 90 MHz
High-level input voltage, VIH (3.3 V) 2 VDDIO + 0.3 V
Low-level input voltage, VIL (3.3 V) VSS – 0.3 0.8 V
High-level output source current, VOH = VOH(MIN) , IOH All GPIO/AIO pins –4 mA
Group 2(2) –8 mA
Low-level output sink current, VOL = VOL(MAX), IOL All GPIO/AIO pins 4 mA
Group 2(2) 8 mA
Junction temperature, TJT version –40 105 °C
S version –40 125
Ambient temperature, TAQ version (Q100 qualification) –40 125 °C
Junction temperature, TJ–40 150
(1) VDDIO and VDDA should be maintained within ~0.3 V of each other.
(2) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37.
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4.3 Electrical Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = IOH MAX 2.4
VOH High-level output voltage V
IOH = 50 μA VDDIO – 0.2
VOL Low-level output voltage IOL = IOL MAX 0.4 V
All GPIO –80 –140 –205
Pin with pullup VDDIO = 3.3 V, VIN = 0 V
enabled
Input current XRS pin –230 –300 –375
IIL μA
(low level) Pin with pulldown VDDIO = 3.3 V, VIN = 0 V ±2
enabled
Pin with pullup VDDIO = 3.3 V, VIN = VDDIO ±2
enabled
Input current
IIH μA
(high level) Pin with pulldown VDDIO = 3.3 V, VIN = VDDIO 28 50 80
enabled
Output current, pullup or
IOZ VO= VDDIO or 0 V ±2 μA
pulldown disabled
CIInput capacitance 2 pF
VDDIO BOR trip point Falling VDDIO 2.50 2.78 2.96 V
VDDIO BOR hysteresis 35 mV
Supervisor reset release delay Time after BOR/POR/OVR event is removed to XRS 400 800 μs
time release
VREG VDD output Internal VREG on 1.9 V
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(VDD) go out of range.
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Transmission Line
4.0 pF 1.85 pF
Z0 = 50 W(A)
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
42 W3.5 nH
Device Pin(B)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5 Peripheral and Electrical Specifications
5.1 Parameter Information
5.1.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their Letters and symbols and their
meanings: meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
Unknown, changing, or don't care
f fall time X level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
5.1.2 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
5.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 5-1. 3.3-V Test Load Circuit
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5.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2806x MCUs. Table 5-1 lists the cycle times of various clocks.
Table 5-1. 2806x Clock Table and Nomenclature (90-MHz Devices)
MIN NOM MAX UNIT
tc(SCO), Cycle time 11.11 500 ns
SYSCLKOUT Frequency 2 90 MHz
tc(LCO), Cycle time 11.11 44.4(2) ns
LSPCLK(1) Frequency 22.5(2) 90 MHz
tc(ADCCLK), Cycle time 22.22 ns
ADC clock Frequency 45 MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 90 MHz.
Table 5-2. Device Clocking Requirements/Characteristics
MIN NOM MAX UNIT
tc(OSC), Cycle time 50 200 ns
On-chip oscillator (X1/X2 pins)
(Crystal/Resonator) Frequency 5 20 MHz
tc(CI), Cycle time (C8) 33.3 200 ns
External oscillator/clock source
(XCLKIN pin) — PLL Enabled Frequency 5 30 MHz
tc(CI), Cycle time (C8) 33.33 250 ns
External oscillator/clock source
(XCLKIN pin) — PLL Disabled Frequency 4 30 MHz
Limp mode SYSCLKOUT Frequency range 1 to 5 MHz
(with /2 enabled) tc(XCO), Cycle time (C1) 50 2000 ns
XCLKOUT Frequency 0.5 20 MHz
PLL lock time(1) tp1 ms
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
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Zero-Pin Oscillator Frequency Movement With Temperature
9.6
9.7
9.8
9.9
10
10.1
10.2
10.3
10.4
10.5
10.6
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
Temperature (°C)
Output Frequency (MHz)
Typical
Max
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Table 5-3. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
PARAMETER MIN TYP MAX UNIT
Internal zero-pin oscillator 1 (INTOSC1) at 30°C(1)(2) Frequency 10.000 MHz
Internal zero-pin oscillator 2 (INTOSC2) at 30°C(1)(2) Frequency 10.000 MHz
Step size (coarse trim) 55 kHz
Step size (fine trim) 14 kHz
Temperature drift(3) 3.03 4.85 kHz/°C
Voltage (VDD) drift(3) 175 Hz/mV
(1) In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, refer to the Oscillator Compensation Guide
Application Report (literature number SPRAB84).
(2) Frequency range ensured only when VREG is enabled, VREGENZ = VSS.
(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For
example:
• Increase in temperature will cause the output frequency to increase per the temperature coefficient.
• Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient.
Figure 5-2. Zero-Pin Oscillator Frequency Movement With Temperature
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C4
C3
XCLKOUT(B)
XCLKIN(A)
C5
C9
C10
C1
C8
C6
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.4 Clock Requirements and Characteristics
Table 5-4. XCLKIN Timing Requirements - PLL Enabled
NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN 6 ns
C10 tr(CI) Rise time, XCLKIN 6 ns
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 %
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 %
Table 5-5. XCLKIN Timing Requirements - PLL Disabled
NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN Up to 20 MHz 6 ns
20 MHz to 30 MHz 2
C10 tr(CI) Rise time, XCLKIN Up to 20 MHz 6 ns
20 MHz to 30 MHz 2
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 %
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 %
The possible configuration modes are shown in Table 2-17.
Table 5-6. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN TYP MAX UNIT
C3 tf(XCO) Fall time, XCLKOUT ns
C4 tr(XCO) Rise time, XCLKOUT ns
C5 tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns
C6 tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 5-3. Clock Timing
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tw(RSL1)
th(boot-mode)(C)
V V
(3.3 V)
DDIO DDA
,
INTOSC1
X1/X2
XRS(D)
Boot-Mode
Pins
V (1.8 V)
DD
XCLKOUT
User-code dependent
User-code dependent
Boot-ROM execution starts Peripheral/GPIO function
Based on boot code
GPIO pins as input
tOSCST
Address/Data/
Control
(Internal)
Address/data valid, internal boot-ROM code execution phase
User-code execution phase
td(EX)
tINTOSCST
(A)
(B)
I/O Pins GPIO pins as input (state depends on internal PU/PD)
User-code dependent
(E)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.5 Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset
or to prevent the I/Os from glitching during power up/down (GPIO19, GPIO26–27, GPIO34–38 do not
have glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any
digital pin (for analog pins, it is 0.7 V above VDDA) prior to powering up the device. Furthermore, VDDIO and
VDDA should always be within 0.3 V of each other. Voltages applied to pins on an unpowered device can
bias internal p-n junctions in unintended ways and produce unpredictable results.
A. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this
phase.
B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that
XCLKOUT will not be visible at the pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.
E. The internal pullup/pulldown will take effect when BOR is driven high.
Figure 5-4. Power-on Reset
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th(boot-mode)(A)
tw(RSL2)
INTOSC1
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input Peripheral/GPIO Function
td(EX)
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Table 5-7. Reset (XRS) Timing Requirements
MIN NOM MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1000tc(SCO) cycles
tw(RSL2) Pulse duration, XRS low on warm reset 32tc(OSCCLK) cycles
Table 5-8. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tw(RSL1) Pulse duration, XRS driven by device 600 μs
Pulse duration, reset pulse generated by
tw(WDRS) 512tc(OSCCLK) cycles
watchdog
td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles
tINTOSCST Start up time, internal zero-pin oscillator 3 μs
tOSCST(1) On-chip crystal-oscillator start-up time 1 10 ms
(1) Dependent on crystal/resonator and board design.
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 5-5. Warm Reset
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OSCCLK
SYSCLKOUT
Write to PLLCR
OSCCLK * 2
(Current CPU
Frequency)
OSCCLK/2
(CPU frequency while PLL is stabilizing
with the desired frequency. This period
(PLL lock-up time t ) is 1 ms long.)
p
OSCCLK * 4
(Changed CPU frequency)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Figure 5-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
Figure 5-6. Example of Effect of Writing Into PLLCR Register
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5.6 Current Consumption
Table 5-9. TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
VREG ENABLED VREG DISABLED
MODE TEST CONDITIONS IDDIO(1) IDDA(2) IDD3VFL IDD IDDIO(1) IDDA(2) IDD3VFL
TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX
The following peripheral
clocks are enabled:
• ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6,
ePWM7, ePWM8
• eCAP1/2/3
• eQEP1/2
• eCAN
• CLA
• HRPWM
• SCI-A/B
Operational • SPI-A/B 185 mA(6) 245 mA(6) 16 mA 22 mA 35 mA 40 mA 165 mA(6) 220 mA(6) 15 mA 20 mA 16 mA 22 mA 35 mA 40 mA
(Flash) • ADC
• I2C
• COMP1/2/3
• CPU-TIMER0/1/2
• McBSP
• USB
All PWM pins are toggled
at 90 kHz.
All I/O pins are left
unconnected.(4) (5)
Code is running out of
flash with 3 wait-states.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
IDLE 22 mA 27 mA 15 µA 25 µA 5 µA 10 µA 21 mA 26 mA 120 µA 400 µA 15 µA 25 µA 5 µA 10 µA
All peripheral clocks are
turned off.
Flash is powered down.
STANDBY 9 mA 11 mA 15 µA 25 µA 5 µA 10 µA 8 mA 10 mA 120 µA 400 µA 15 µA 25 µA 5 µA 10 µA
Peripheral clocks are off.
Flash is powered down.
HALT Peripheral clocks are off. 75 µA 15 µA 25 µA 5 µA 10 µA 25 µA(8) 40 µA 15 µA 25 µA 5 µA 10 µA
Input clock is disabled.(7)
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by
writing to the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
• Data is continuously transmitted out of SPI-A/B, SCI-A, eCAN-A, McBSP-A, and I2C ports.
• The hardware multiplier is exercised.
• Watchdog is reset.
• ADC is performing continuous conversion.
• COMP1/2 are continuously switching voltages.
• GPIO17 is toggled.
(5) CLA is continuously performing polynomial calculations.
(6) For F2806x devices that do not have CLA, subtract the IDD current number for CLA (see Table 5-10) from the IDD (VREG disabled)/IDDIO
(VREG enabled) current numbers shown in Table 5-9 for operational mode.
(7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
(8) To realize the IDD number shown for HALT mode, the following must be done:
• PLL2 must be shut down by clearing bit 2 of the PLLCTL register.
• A value of 0x00FF must be written to address 0x6822.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may
share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the
same time, although such a configuration is not useful. If this is done, the current drawn by
the device will be more than the numbers specified in the current consumption tables.
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5.6.1 Reducing Current Consumption
The 2806x devices incorporate a method to reduce the device current consumption. Since each peripheral
unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by
turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one
of the three low-power modes could be taken advantage of to reduce the current consumption even
further. Table 5-10 indicates the typical reduction in current consumption achieved by turning off the
clocks.
Table 5-10. Typical Current Consumption by Various
Peripherals (at 90 MHz)(1)
PERIPHERAL IDD CURRENT
MODULE(2) REDUCTION (mA)
ADC 2(3)
I2C 3
ePWM 2
eCAP 2
eQEP 2
SCI 2
SPI 2
COMP/DAC 1
HRPWM 3
HRCAP 3
USB 12
CPU-TIMER 1
Internal zero-pin oscillator 0.5
CAN 2.5
CLA 20
McBSP 6
(1) All peripheral clocks (except CPU Timer clock) are disabled upon
reset. Writing to/reading from peripheral registers is possible only
after the peripheral clocks are turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for one
ePWM module.
(3) This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the ADC
(IDDA) as well.
NOTE
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
NOTE
The baseline IDD current (current when the core is executing a dummy loop with no
peripherals enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the
current-drawn by the peripherals (enabled by that application) must be added to the baseline
IDD current.
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0
100
200
300
400
500
600
700
800
900
10 20 30 40 50 60 70 80 90
Operational Power (mW)
SYSCLKOUT (MHz)
Operational Power vs Frequency (Internal VREG)
0
50
100
150
200
250
10 20 30 40 50 60 70 80 90
Operational Current (mA)
SYSCLKOUT (MHz)
Operational Current (Flash) vs Frequency (Internal VREG)
IDDIO
IDDA
IDD3VFL
Total
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Following are other methods to reduce power consumption further:
• The flash module may be powered down if code is run off SARAM. This results in a current reduction
of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
• Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
5.6.2 Current Consumption Graphs (VREG Enabled)
Figure 5-7. Typical Operational Current Versus Frequency
Figure 5-8. Typical Operational Power Versus Frequency
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TRST
TMS
TDI
TDO
TCK
VDDIO
MCU
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
TCK_RET
13
14
2
1
3
7
11
9
6 inches or less
PD
GND
GND
GND
GND
GND
5
4
6
8
10
12
JTAG Header
VDDIO
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.7 Emulator Connection Without Signal Buffering for the MCU
Figure 5-9 shows the connection between the MCU and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 5-9 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see Section 2.4, Signal
Descriptions.
A. See Figure 5-48 for JTAG/GPIO multiplexing.
Figure 5-9. Emulator Connection Without Signal Buffering for the MCU
NOTE
The 2806x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header
on-board, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ
(typical) resistor.
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Watchdog
Peripherals
XINT1
Interrupt Control
XINT1
XINT1CR[15:0]
Interrupt Control
XINT2
XINT2CR[15:0]
GPIO
MUX
WDINT
INT1
to
INT12
NMI
XINT1CTR[15:0]
XINT2CTR[15:0]
XINT3CTR[15:0]
Low-Power Modes
LPMINT
WAKEINT Sync
SYSCLKOUT
M
U
X
XINT2 M
U
X
XINT3
ADC XINT2SOC
GPIOXINT1SEL[4:0]
GPIOXINT2SEL[4:0]
M
U
X
Interrupt Control
XINT3
XINT3CR[15:0]
System Control
(See the System Control section.)
INT14
INT13
GPIO0.int
GPIO31.int
DMA clear
DMA
PIE
Up to 96 Interrupts
DMA
DMA
TOUT1
CPU TIMER 2
CPU TIMER 0
TINT0
CPU TIMER 1
TINT2
TINT1 Flash Wrapper
GPIOXINT3SEL[4:0]
M
U
X
NMI Interrupt With Watchdog Function
(See the NMI Watchdog section.) NMIRS
GPIO0.int
GPIO31.int
CLOCKFAIL
CPUTMR2CLK
DMA
C28x
Core
(SPI, SCI, McBSP, I2C, eCAN, ePWM, eCAP, eQEP,
HRCAP, ADC, CLA)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.8 Interrupts
Figure 5-10 shows how the various interrupt sources are multiplexed.
Figure 5-10. External and PIE Interrupt Sources
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INT12
MUX
INT11
INT2
INT1
CPU
(Enable)(Flag)
INTx
INTx.8
PIEIERx[8:1] PIEIFRx[8:1]
MUX
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
From
Peripherals
or
External
Interrupts
(Enable) (Flag)
IER[12:1]IFR[12:1]
Global
Enable
INTM
1
0
PIEACKx
(Enable/Flag)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. Table 5-11 shows the interrupts used by 2806x
devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
Figure 5-11. Multiplexing of Interrupts Using the PIE Block
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Table 5-11. PIE MUXed Peripheral Interrupt Vector Table(1)
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1
(LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC)
0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40
INT2.y EPWM8_TZINT EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
(ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50
INT3.y EPWM8_INT EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT
(ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60
INT4.y HRCAP2_INT HRCAP1_INT Reserved Reserved Reserved ECAP3_INT ECAP2_INT ECAP1_INT
(HRCAP2) (HRCAP1) – – – (eCAP3) (eCAP2) (eCAP1)
0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70
INT5.y USB0_INT Reserved Reserved HRCAP4_INT HRCAP3_INT Reserved EQEP2_INT EQEP1_INT
– – – (HRCAP4) (HRCAP3) – (eQEP2) (eQEP1)
0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80
INT6.y Reserved Reserved MXINTA MRINTA SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA
– – (McBSP-A) (McBSP-A) (SPI-B) (SPI-B) (SPI-A) (SPI-A)
0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90
INT7.y Reserved Reserved DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1
– – (DMA) (DMA) (DMA) (DMA) (DMA) (DMA)
0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0
INT8.y Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A
– – – – – – (I2C-A) (I2C-A)
0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0
INT9.y Reserved Reserved ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA
– – (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) (SCI-A)
0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0
INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1
(ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC)
0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0
INT11.y CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1
(CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA)
0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0
INT12.y LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3
(CLA) (CLA) – – – – – Ext. Int. 3
0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be
used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
• No peripheral within the group is asserting interrupts.
• No peripheral interrupts are assigned to the group (for example, PIE group 7).
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Table 5-12. PIE Configuration and Control Registers
NAME ADDRESS SIZE (x16) DESCRIPTION(1)
PIECTRL 0x0CE0 1 PIE, Control Register
PIEACK 0x0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register
PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register
PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register
PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register
PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register
PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register
PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register
PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register
PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register
PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register
PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register
PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register
PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register
PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register
PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register
PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register
Reserved 0x0CFA – 6 Reserved
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
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XINT1, XINT2, XINT3
tw(INT)
Interrupt Vector
td(INT)
Address bus
(internal)
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5.8.1 External Interrupts
Table 5-13. External Interrupt Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
XINT1CR 0x00 7070 1 XINT1 configuration register
XINT2CR 0x00 7071 1 XINT2 configuration register
XINT3CR 0x00 7072 1 XINT3 configuration register
XINT1CTR 0x00 7078 1 XINT1 counter register
XINT2CTR 0x00 7079 1 XINT2 counter register
XINT3CTR 0x00 707A 1 XINT3 counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the "Systems Control and Interrupts" chapter of the
TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18).
5.8.1.1 External Interrupt Electrical Data/Timing
Table 5-14. External Interrupt Timing Requirements(1)
TEST CONDITIONS MIN MAX UNIT
tw(INT)(2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles
With qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 5-69.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 5-15. External Interrupt Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles
(1) For an explanation of the input qualifier parameters, see Table 5-69.
Figure 5-12. External Interrupt Timing
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5.9 Control Law Accelerator (CLA) Overview
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-
critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA
enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks
frees up the main CPU to perform other system and communication functions concurently. The following is
a list of major features of the CLA.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program address bus and program data bus
• Data address bus, data read bus, and data write bus
– Independent eight-stage pipeline.
– 12-bit program counter (MPC)
– Four 32-bit result registers (MR0–MR3)
– Two 16-bit auxillary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the CLA program memory space.
– One task is serviced at a time through to completion. There is no nesting of tasks.
– Upon task completion, a task-specific interrupt is flagged within the PIE.
– When a task finishes, the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU via the IACK instruction
– Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example:
• Task1: ADCINT1 or EPWM1_INT
• Task2: ADCINT2 or EPWM2_INT
• Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT
• Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT
– Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– The CLA has direct access to the ADC Result registers, comparator registers, and the eCAP,
eQEP, and ePWM+HRPWM registers.
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CLA_INT1 to CLA_INT8
MVECT1
MVECT2
MPERINT1
to
MPERINT8
PIE
Main
28x
CPU
CLA
Program
Memory
MMEMCFG
MCTL
MIFR
MIER
MIFRC
MIRUN
MIOVF
MICLR
MICLROVF
MPISRCSEL1
MVECT3
MVECT4
MVECT5
MVECT6
MVECT7
MVECT8
ain CPU BUS
INT11
INT12
Peripheral Interrupts
ADCINT1 to ADCINT8
ECAP1_INT to ECAP3_INT
EQEP1_INT and EQEP2_INT
EPWM1_INT to EPWM8_INT
CPU Timer 0
Map to CLA or
CPU Space
CLA
Data
Memory
Comparator
Registers
eCAP
Registers
eQEP
Registers
ePWM
and
HRPWM
Registers
ADC
Result
Registers
CLA
Shared
Message
RAMs
Main CPU Read/Write Data Bus
CLA Program Address Bus
CLA Program Data Bus
Map to CLA or
CPU Space
CLA Data Bus
Main CPU Bus
MR0(32)
MPC(12)
MR1(32)
MR3(32)
MAR0(32)
MSTF(32)
MR2(32)
MAR1(32)
CLA Data Read Address Bus
CLA Data Write Data Bus
CLA Data Write Address Bus
CLA Data Read Data Bus
MEALLOW
Main CPU Read Data Bus
CLA Execution
Registers
CLA Control
Registers
SYSCLKOUT
CLAENCLK
SYSRS
LVF
LUF
IACK
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Figure 5-13. CLA Block Diagram
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Table 5-16. CLA Control Registers
CLA1 EALLOW
REGISTER NAME SIZE (x16) DESCRIPTION(1)
ADDRESS PROTECTED
MVECT1 0x1400 1 Yes CLA Interrupt/Task 1 Start Address
MVECT2 0x1401 1 Yes CLA Interrupt/Task 2 Start Address
MVECT3 0x1402 1 Yes CLA Interrupt/Task 3 Start Address
MVECT4 0x1403 1 Yes CLA Interrupt/Task 4 Start Address
MVECT5 0x1404 1 Yes CLA Interrupt/Task 5 Start Address
MVECT6 0x1405 1 Yes CLA Interrupt/Task 6 Start Address
MVECT7 0x1406 1 Yes CLA Interrupt/Task 7 Start Address
MVECT8 0x1407 1 Yes CLA Interrupt/Task 8 Start Address
MCTL 0x1410 1 Yes CLA Control Register
MMEMCFG 0x1411 1 Yes CLA Memory Configure Register
MPISRCSEL1 0x1414 2 Yes Peripheral Interrupt Source Select Register 1
MIFR 0x1420 1 Yes Interrupt Flag Register
MIOVF 0x1421 1 Yes Interrupt Overflow Register
MIFRC 0x1422 1 Yes Interrupt Force Register
MICLR 0x1423 1 Yes Interrupt Clear Register
MICLROVF 0x1424 1 Yes Interrupt Overflow Clear Register
MIER 0x1425 1 Yes Interrupt Enable Register
MIRUN 0x1426 1 Yes Interrupt RUN Register
MIPCTL 0x1427 1 Yes Interrupt Priority Control Register
MPC(2) 0x1428 1 – CLA Program Counter
MAR0(2) 0x142A 1 – CLA Aux Register 0
MAR1(2) 0x142B 1 – CLA Aux Register 1
MSTF(2) 0x142E 2 – CLA STF Register
MR0(2) 0x1430 2 – CLA R0H Register
MR1(2) 0x1434 2 – CLA R1H Register
MR2(2) 0x1438 2 – CLA R2H Register
MR3(2) 0x143C 2 – CLA R3H Register
(1) All registers in this table are CSM protected
(2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes
to this register.
Table 5-17. CLA Message RAM
ADDRESS RANGE SIZE (x16) DESCRIPTION
0x1480 – 0x14FF 128 CLA to CPU Message RAM
0x1500 – 0x157F 128 CPU to CLA Message RAM
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100-Pin
80-Pin
VDDA VDDA
VREFLO
Tied To
VSSA
VSSA
VREFLO
VREFHI
A0
VREFHI
Tied To
A0
A1
A2
A1
A2
A3
A4 A4
A5
A6 A6
A7
B0 B0
B1
B1
B2 B2
B3
B4 B4
B5
B6 B6
B7
(3.3 V) VDDA
(Agnd) VSSA
VREFLO
Diff
Interface Reference
Comp1
VREFHI
A0
B0
AIO2
AIO10
A1
B1
10-Bit
DAC
A2
B2
COMP1OUT
A3
B3
AIO4
AIO12
A4
B4
Comp2
10-Bit
DAC
COMP2OUT
Comp3
10-Bit
DAC
COMP3OUT
ADC
B5
A5
AIO6
AIO14
A6
B6
A7
B7
Simultaneous Sampling Channels
Signal Pinout
Temperature Sensor
A5
B5
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5.10 Analog Block
A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x.
The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the
timing control of start of conversions. Figure 5-14 shows the interaction of the analog module with the rest
of the F2806x system.
Figure 5-14. Analog Pin Configurations
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0,ValueDigital =
V0inputwhen £
VV
V
VoltageAnalogInput
4096ValueDigital
REFLOREFHI
REFLO
-
-
´=
V
inputV0when REFHI
<<
4095,ValueDigital =
V
inputwhen REFHI
³
0,ValueDigital =
V0inputwhen £
3.3
V
VoltageAnalogInput
4096ValueDigital REFLO
-
´=
V3.3inputV0when <<
4095,ValueDigital =
V3.3inputwhen ³
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5.10.1 Analog-to-Digital Converter (ADC)
5.10.1.1 Features
The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-
and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to
16 analog input channels. The converter can be configured to run with an internal bandgap reference to
create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to
create ratiometric-based conversions.
Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a
series of conversions from a single trigger. However, the basic principle of operation is centered around
the configurations of individual conversions, called SOCs, or Start-Of-Conversions.
Functions of the ADC module include:
• 12-bit ADC core with built-in dual sample-and-hold (S/H)
• Simultaneous sampling or sequential sampling modes
• Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input
analog voltage is derived by:
– Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or
external reference modes.)
– External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA
when using either internal or external reference modes.)
• Runs at full system clock, no prescaling required
• Up to 16-channel, multiplexed inputs
• 16 SOCs, configurable for trigger, sample window, and channel
• 16 result registers (individually addressable) to store conversion values
• Multiple trigger sources
– S/W – software immediate start
– ePWM 1–8
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
• 9 flexible PIE interrupts, can configure interrupt request after any conversion
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Table 5-18. ADC Configuration and Control Registers
SIZE EALLOW
REGISTER NAME ADDRESS DESCRIPTION
(x16) PROTECTED
ADCCTL1 0x7100 1 Yes Control 1 Register
ADCCTL2 0x7101 1 Yes Control 2 Register
ADCINTFLG 0x7104 1 No Interrupt Flag Register
ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register
ADCINTOVF 0x7106 1 No Interrupt Overflow Register
ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register
INTSEL1N2 0x7108 1 Yes Interrupt 1 and 2 Selection Register
INTSEL3N4 0x7109 1 Yes Interrupt 3 and 4 Selection Register
INTSEL5N6 0x710A 1 Yes Interrupt 5 and 6 Selection Register
INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register
INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection)
SOCPRICTL 0x7110 1 Yes SOC Priority Control Register
ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register
ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels)
ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels)
ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels)
ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels)
ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels)
ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels)
ADCSOC0CTL to 0x7120 – 1 Yes SOC0 Control Register to SOC15 Control Register
ADCSOC15CTL 0x712F
ADCREFTRIM 0x7140 1 Yes Reference Trim Register
ADCOFFTRIM 0x7141 1 Yes Offset Trim Register
COMPHYSTCTL 0x714C 1 Yes Comparator Hysteresis Control Register
ADCREV 0x714F 1 No Revision Register
Table 5-19. ADC Result Registers (Mapped to PF0)
SIZE EALLOW
REGISTER NAME ADDRESS DESCRIPTION
(x16) PROTECTED
ADCRESULT0 to 0xB00 – 1 No ADC Result 0 Register to ADC Result 15 Register
ADCRESULT15 0xB0F
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PF0 (CPU)
PF2 (CPU)
SYSCLKOUT
ADCENCLK
AIO
MUX
ADC
Channels
ADC
Core
12-Bit
0-Wait
Result
Registers
ADCINT 1
ADCINT 9
ADCTRIG 1 TINT 0
PIE
CPUTIMER 0
ADCTRIG 2 TINT 1 CPUTIMER 1
ADCTRIG 3 TINT 2 CPUTIMER 2
ADCTRIG 4 XINT 2SOC XINT 2
ADCTRIG 5 SOCA 1
EPWM 1
ADCTRIG 6 SOCB 1
ADCTRIG 7 SOCA 2
EPWM 2
ADCTRIG 8 SOCB 2
ADCTRIG 9 SOCA 3
EPWM 3
ADCTRIG 10 SOCB 3
ADCTRIG 11 SOCA 4
EPWM 4
ADCTRIG 12 SOCB 4
ADCTRIG 13 SOCA 5
EPWM 5
ADCTRIG 14 SOCB 5
ADCTRIG 15 SOCA 6
EPWM 6
ADCTRIG 16 SOCB 6
ADCTRIG 17 SOCA 7
EPWM 7
ADCTRIG 18 SOCB 7
ADCTRIG 19 SOCA 8
EPWM 8
ADCTRIG 20 SOCB 8
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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Figure 5-15. ADC Connections
ADC Connections if the ADC is Not Used
It is recommended that the connections for the analog power pins be kept, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:
• VDDA – Connect to VDDIO
• VSSA – Connect to VSS
• VREFLO – Connect to VSS
• ADCINAn, ADCINBn, VREFHI – Connect to VSSA
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSSA).
NOTE: Unused ADCIN pins that are multiplexed with AIO function should not be directly connected to
analog ground. They should be grounded through a 1-kΩresistor. This is to prevent an errant code from
configuring these pins as AIO outputs and driving grounded pins to a logic-high state.
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.
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ADCSOCAO
ADCSOCBO
or
tw(ADCSOCL)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.10.1.2 ADC Start-of-Conversion Electrical Data/Timing
Table 5-20. External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO ) cycles
Figure 5-16. ADCSOCAO or ADCSOCBO Timing
5.10.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
Table 5-21. ADC Electrical Characteristics
PARAMETER MIN TYP MAX UNIT
DC SPECIFICATIONS
Resolution 12 Bits
ADC clock 90-MHz device 0.001 45 MHz
Sample Window 7 64 ADC
Clocks
ACCURACY
INL (Integral nonlinearity)(1) –4 4 LSB
DNL (Differential nonlinearity), no missing codes –1 1.5 LSB
Offset error (2) Executing a single self- –20 20 LSB
recalibration(3)
Executing periodic self- –4 4
recalibration(4)
Overall gain error with internal reference –60 60 LSB
Overall gain error with external reference –40 40 LSB
Channel-to-channel offset variation –4 4 LSB
Channel-to-channel gain variation –4 4 LSB
ADC temperature coefficient with internal reference –50 ppm/°C
ADC temperature coefficient with external reference –20 ppm/°C
VREFLO –100 µA
VREFHI 100 µA
ANALOG INPUT
Analog input voltage with internal reference 0 3.3 V
Analog input voltage with external reference VREFLO VREFHI V
VREFLO input voltage(5) VSSA 0.66 V
VREFHI input voltage(6) 2.64 VDDA V
with VREFLO = VSSA 1.98 VDDA
Input capacitance 5 pF
Input leakage current ±2 μA
(1) INL will degrade when the ADC input voltage goes above VDDA.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) For more details, see the TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064,
TMS320F28063, TMS320F28062 Piccolo MCU Silicon Errata (literature number SPRZ342).
(4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error.
(5) VREFLO is always connected to VSSA on the 80-pin PN/PFP device.
(6) VREFHI must not exceed VDDA when using either internal or external reference modes. Since VREFHI is tied to ADCINA0 on the 80-pin
PN/PFP device, the input signal on ADCINA0 must not exceed VDDA.
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ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE
Request for ADC
Conversion
td(PWD)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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Table 5-22. ADC Power Modes
ADC OPERATING MODE CONDITIONS IDDA UNITS
Mode A – Operating Mode ADC Clock Enabled 16 mA
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 1)
Mode B – Quick Wake Mode ADC Clock Enabled 4 mA
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 0)
Mode C – Comparator-Only Mode ADC Clock Enabled 1.5 mA
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
Mode D – Off Mode ADC Clock Enabled 0.075 mA
Bandgap On (ADCBGPWD = 0)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
5.10.1.3.1 Internal Temperature Sensor
Table 5-23. Temperature Sensor Coefficient
PARAMETER(1) MIN TYP MAX UNIT
TSLOPE Degrees C of temperature movement per measured ADC LSB change 0.18(2)(3) °C/LSB
of the temperature sensor
TOFFSET ADC output at 0°C of the temperature sensor 1750 LSB
(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
(2) ADC temperature coeffieicient is accounted for in this specification
(3) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
5.10.1.3.2 ADC Power-Up Control Bit Timing
Table 5-24. ADC Power-Up Delays
PARAMETER(1) MIN TYP MAX UNIT
td(PWD) Delay time for the ADC to be stable after power up 1 ms
(1) Timings maintain compatibility to the ADC module. The 2806x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
Figure 5-17. ADC Conversion Timing
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ac
RsADCIN
C
5 pF
pC
1.6 pF
h
Switch
Typical Values of the Input Circuit Components:
Switch Resistance (R ): 3.4 k
on W
Sampling Capacitor (C ): 1.6 pF
h
Parasitic Capacitance (C ): 5 pF
p
Source Resistance (R ): 50
sW
28x DSP
Source
Signal
3.4 kW
Ron
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Figure 5-18. ADC Input Impedance Model
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SOC0
ADCCLK
ADCRESULT 0
S/H Window Pulse to Core
ADCCTL 1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCINTFLG.ADCINTx
SOC1 SOC2
9 15 22 24 3720
Result 0 Latched
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
Conversion 0
13 ADC Clocks
Minimum
7 ADCCLKs
6
ADCCLKs
Conversion 1
13 ADC Clocks
Minimum
7 ADCCLKs
2 ADCCLKs
1 ADCCLK
Analog Input
SOC1 Sample
Window
SOC0 Sample
Window
SOC2 Sample
Window
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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5.10.1.3.3 ADC Sequential and Simultaneous Timings
Figure 5-19. Timing Example for Sequential Mode / Late Interrupt Pulse
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Conversion 0
13 ADC Clocks
Minimum
7 ADCCLKs
SOC0
ADCCLK
ADCRESULT 0
S/H Window Pulse to Core
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCINTFLG.ADCINTx
SOC1 SOC2
9 15 22 24 37
6
ADCCLKs
20
Result 0 Latched
Conversion 1
13 ADC Clocks
Minimum
7 ADCCLKs
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
2 ADCCLKs
Analog Input
SOC1 Sample
Window
SOC0 Sample
Window
SOC2 Sample
Window
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Figure 5-20. Timing Example for Sequential Mode / Early Interrupt Pulse
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Conversion 0 (A)
13 ADC Clocks
Minimum
7 ADCCLKs
SOC0 (A/B)
ADCCLK
ADCRESULT 0
S/H Window Pulse to Core
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCINTFLG .ADCINTx
SOC2 (A/B)
9 22 24 37
19
ADCCLKs
20
Result 0 (A) Latched
Conversion 0 (B)
13 ADC Clocks
Minimum
7 ADCCLKs
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
ADCRESULT 1 Result 0 (B) Latched
Conversion 1 (A)
13 ADC Clocks
ADCRESULT 2
50
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
1 ADCCLK
2 ADCCLKs
2 ADCCLKs
Analog Input B
SOC0 Sample
B Window
SOC2 Sample
B Window
Analog Input A
SOC0 Sample
A Window
SOC2 Sample
A Window
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Figure 5-21. Timing Example for Simultaneous Mode / Late Interrupt Pulse
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ADCCLK
2
0 9
SOC0 Sample
B Window
Analog Input B
Analog Input A
SOC0 Sample
A Window
37 50
SOC2 Sample
B Window
SOC2 Sample
A Window
2422
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B)
ADCRESULT 0 Result 0 (A) Latched
2 ADCCLKs
Result 0 (B) Latched
ADCRESULT 1
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
Minimum
7 ADCCLKs
Conversion 0 (A)
13 ADC Clocks 2 ADCCLKs
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
ADCINTFLG.ADCINTx
19
ADCCLKs
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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Figure 5-22. Timing Example for Simultaneous Mode / Early Interrupt Pulse
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To COMPy A or B input
To ADC Channel X
1
0
AIOx Pin
AIOxIN
AIOxINE
SYNC
SYSCLK
Logic implemented in GPIO MUX block
AIODAT Reg
(Read)
AIODAT Reg
(Latch)
AIOSET,
AIOCLEAR,
AIOTOGGLE
Regs
AIOMUX 1 Reg
1
0
AIOxDIR
(1 = Input,
0 = Output)
(0 = Input, 1 = Output)
AIODIR Reg
(Latch)
0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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5.10.2 ADC MUX
Figure 5-23. AIOx Pin Multiplexing
The ADC channel and Comparator functions are always available. The digital I/O function is available only
when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects
the actual pin state.
The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode,
reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer
is disabled to prevent analog signals from generating noise.
On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO
function disabled for that pin.
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AIO
MUX
COMP x A
COMP x B
COMP x
+
DAC x
Wrapper
DAC
Core
10-Bit
+
-
COMP
COMPxOUT
GPIO
MUX
TZ1/2/3
ePWM
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.10.3 Comparator Block
Figure 5-24 shows the interaction of the Comparator modules with the rest of the system.
Figure 5-24. Comparator Block Diagram
Table 5-25. Comparator Control Registers
REGISTER COMP1 COMP2 COMP3 SIZE EALLOW DESCRIPTION
NAME ADDRESS ADDRESS ADDRESS (x16) PROTECTED
COMPCTL 0x6400 0x6420 0x6440 1 Yes Comparator Control Register
COMPSTS 0x6402 0x6422 0x6442 1 No Comparator Status Register
DACCTL 0x6404 0x6424 0x6444 1 Yes DAC Control Register
DACVAL 0x6406 0x6426 0x6446 1 No DAC Value Register
RAMPMAXREF_ 0x6408 0x6428 0x6448 1 No Ramp Generator Maximum Reference
ACTIVE (Active) Register
RAMPMAXREF_ 0x640A 0x642A 0x644A 1 No Ramp Generator Maximum Reference
SHDW (Shadow) Register
RAMPDECVAL_ 0x640C 0x642C 0x644C 1 No Ramp Generator Decrement Value (Active)
ACTIVE Register
RAMPDECVAL_ 0x640E 0x642E 0x644E 1 No Ramp Generator Decrement Value
SHDW (Shadow) Register
RAMPSTS 0x6410 0x6430 0x6450 1 No Ramp Generator Status Register
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Settling Time (ns)
0
100
200
300
400
500
600
700
800
900
1000
1100
0 50 100 150 200 250 300 350 400 450 500
DAC Step Size (Codes)
15 Codes 7 Codes 3 Codes 1 Code
DAC Accuracy
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.10.3.1 On-Chip Comparator/DAC Electrical Data/Timing
Table 5-26. Electrical Characteristics of the Comparator/DAC
CHARACTERISTIC MIN TYP MAX UNITS
Comparator
Comparator Input Range VSSA – VDDA V
Comparator response time to PWM Trip Zone (Async) 30 ns
Input Offset ±5 mV
Input Hysteresis(1) 35 mV
DAC
DAC Output Range VSSA – VDDA V
DAC resolution 10 bits
DAC settling time See Figure 5-
25
DAC Gain –1.5 %
DAC Offset 10 mV
Monotonic Yes
INL ±3 LSB
(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩfeedback
resistance between the output of the comparator and the non-inverting input of the comparator.
Figure 5-25. DAC Settling Time
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6.02
1.76)(SINAD
N-
=
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.11 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following
formula, it is possible to get a measure of performance expressed as N, the effective
number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency
can be calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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1)(SPIBRR
LSPCLK
rateBaud +
=
127to3SPIBRRwhen =
4
LSPCLK
rateBaud =
21,0,SPIBRRwhen =
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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5.12 Serial Peripheral Interface (SPI) Module
The device includes the four-pin serial peripheral interface (SPI) module. Up to two SPI modules are
available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-
transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or
another processor. Typical applications include external I/O or peripheral expansion through devices such
as shift registers, display drivers, and ADCs. Multidevice communications are supported by the
master/slave operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO if the SPI module is not used.
• Two operational modes: master and slave
Baud rate: 125 different programmable rates.
• Data word length: one to sixteen data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
• Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
• 4-level transmit/receive FIFO
• Delayed transmit control
• Bi-directional 3 wire SPI mode support
• Audio data receive support via SPISTE inversion
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The SPI port operation is configured and controlled by the registers listed in Table 5-27 and Table 5-28.
Table 5-27. SPI-A Registers
NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1)
SPICCR 0x7040 1 No SPI-A Configuration Control Register
SPICTL 0x7041 1 No SPI-A Operation Control Register
SPISTS 0x7042 1 No SPI-A Status Register
SPIBRR 0x7044 1 No SPI-A Baud Rate Register
SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register
SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register
SPIDAT 0x7049 1 No SPI-A Serial Data Register
SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register
SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register
SPIFFCT 0x704C 1 No SPI-A FIFO Control Register
SPIPRI 0x704F 1 No SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 5-28. SPI-B Registers
NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1)
SPICCR 0x7740 1 No SPI-B Configuration Control Register
SPICTL 0x7741 1 No SPI-B Operation Control Register
SPISTS 0x7742 1 No SPI-B Status Register
SPIBRR 0x7744 1 No SPI-B Baud Rate Register
SPIRXEMU 0x7746 1 No SPI-B Receive Emulation Buffer Register
SPIRXBUF 0x7747 1 No SPI-B Serial Input Buffer Register
SPITXBUF 0x7748 1 No SPI-B Serial Output Buffer Register
SPIDAT 0x7749 1 No SPI-B Serial Data Register
SPIFFTX 0x774A 1 No SPI-B FIFO Transmit Register
SPIFFRX 0x774B 1 No SPI-B FIFO Receive Register
SPIFFCT 0x774C 1 No SPI-B FIFO Control Register
SPIPRI 0x774F 1 No SPI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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S
SPICTL.0
SPI INT FLAG
SPI INT
ENA
SPISTS.6
S
Clock
Polarity
Talk
LSPCLK
SPI Bit Rate
State Control
Clock
Phase
Receiver
Overrun Flag
SPICTL.4
Overrun
INT ENA
SPICCR.3 - 0
SPIBRR.6 - 0 SPICCR.6 SPICTL.3
SPIDAT.15 - 0
SPICTL.1
M
S
M
Master/Slave
SPISTS.7
SPIDAT
Data Register
M
S
SPICTL.2
SPI Char
SPISIMO
SPISOMI
SPICLK
SW2
S
M
M
S
SW3
To CPU
M
SW1
RX FIFO _0
RX FIFO _1
-----
RX FIFO _3
TX FIFO Registers
TX FIFO _0
TX FIFO _1
-----
TX FIFO _3
RX FIFO Registers
16
16
16
TX Interrupt
Logic
RX Interrupt
Logic
SPIINT
SPITX
SPIFFOVF
FLAG
SPIFFRX.15
TX FIFO Interrupt
RX FIFO Interrupt
SPIRXBUF
SPITXBUF
SPIFFTX.14
SPIFFENA
SPISTE
16
0
12
3
0
12
3
4
5
6
TW
TW
TW
SPIPRI.0
TRIWIRE
SPIPRI.1
STEINV
STEINV
SPIRXBUF
Buffer Register
SPITXBUF
Buffer Register
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
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Figure 5-26 is a block diagram of the SPI in slave mode.
A. SPISTE is driven low by the master for a slave device.
Figure 5-26. SPI Module Block Diagram (Slave Mode)
5.12.1 Serial Peripheral Interface (SPI) Master Mode Electrical Data/ Timing
Table 5-29 lists the master mode timing (clock phase = 0) and Table 5-30 lists the master mode timing
(clock phase = 1). Figure 5-27 and Figure 5-28 show the timing waveforms.
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Table 5-29. SPI Master Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD
SPIBRR = 0 OR 2 AND SPIBRR > 3
NO. UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns
2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns
(clock polarity = 0)
tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO)
(clock polarity = 1)
3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns
(clock polarity = 0)
tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO)
(clock polarity = 1)
4 td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO 10 10 ns
valid (clock polarity = 0)
td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO 10 10
valid (clock polarity = 1)
5 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 ns
SPICLK low (clock polarity = 0)
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10
SPICLK high (clock polarity = 1)
8 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK 26 26 ns
low (clock polarity = 0)
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK 26 26
high (clock polarity = 1)
9 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 ns
SPICLK low (clock polarity = 0)
tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10
SPICLK high (clock polarity = 1)
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
Master Out Data Is Valid
SPISTE(A)
1
2
3
5
8
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A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing
end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit,
except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 5-27. SPI Master Mode External Timing (Clock Phase = 0)
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Table 5-30. SPI Master Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)(5)
SPI WHEN (SPIBRR + 1) IS EVEN SPI WHEN (SPIBRR + 1) IS ODD
OR SPIBRR = 0 OR 2 AND SPIBRR > 3
NO. UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns
2 tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns
(clock polarity = 0)
tw(SPCL))M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO
(clock polarity = 1)
3 tw(SPCL)M Pulse duration, SPICLK low 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) ns
(clock polarity = 0)
tw(SPCH)M Pulse duration, SPICLK high 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO)
(clock polarity = 1)
6 tsu(SIMO-SPCH)M Setup time, SPISIMO data valid 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns
before SPICLK high
(clock polarity = 0)
tsu(SIMO-SPCL)M Setup time, SPISIMO data valid 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10
before SPICLK low
(clock polarity = 1)
7 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 ns
SPICLK high (clock polarity = 0)
tv(SPCL-SIMO)M Valid time, SPISIMO data valid after 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10
SPICLK low (clock polarity = 1)
10 tsu(SOMI-SPCH)M Setup time, SPISOMI before 26 26 ns
SPICLK high (clock polarity = 0)
tsu(SOMI-SPCL)M Setup time, SPISOMI before 26 26
SPICLK low (clock polarity = 1)
11 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 ns
SPICLK high (clock polarity = 0)
tv(SPCL-SOMI)M Valid time, SPISOMI data valid after 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10
SPICLK low (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master in data
must be valid
Master out data Is valid
1
7
6
10
3
2
SPISTE(A)
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B. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing
end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit,
except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 5-28. SPI Master Mode External Timing (Clock Phase = 1)
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20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO data
must be valid
SPISOMI data Is valid
19
16
14
13
12
SPISTE(A)
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5.12.2 Serial Peripheral Interface (SPI) Slave Mode Electrical Data/ Timing
Table 5-31 lists the slave mode external timing (clock phase = 0) and Table 5-32 lists the slave mode
external timing (clock phase = 1). Figure 5-29 and Figure 5-30 show the timing waveforms.
Table 5-31. SPI Slave Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(LCO) ns
13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S
14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S
15 td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 21 ns
td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 21
16 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S ns
tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S
19 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 26 ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 26
20 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 ns
tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
C. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 5-29. SPI Slave Mode External Timing (Clock Phase = 0)
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Data Valid
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO data
must be valid
SPISOMI data is valid
21
12
18
17
14
13
SPISTE(A)
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Table 5-32. SPI Slave Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)(5)
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 8tc(LCO) ns
13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC) S
14 tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC) S ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S
17 tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S ns
tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S
18 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low 0.75tc(SPC)S ns
(clock polarity = 1)
tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high 0.75tc(SPC) S
(clock polarity = 0)
21 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 26 ns
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 26
22 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high 0.5tc(SPC)S – 10 ns
(clock polarity = 0)
tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low 0.5tc(SPC)S – 10
(clock polarity = 1)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 5-30. SPI Slave Mode External Timing (Clock Phase = 1)
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8*1)(BRR
LSPCLK
rateBaud +
=
0BRRwhen ¹
16
LSPCLK
rateBaud =
0BRRwhen =
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5.13 Serial Communications Interface (SCI) Module
The devices include two serial communications interface (SCI) modules (SCI-A, SCI-B). The SCI module
supports digital communications between the CPU and other asynchronous peripherals that use the
standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each
has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in
the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,
overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit
baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
• Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ (non-return-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 4-level transmit/receive FIFO
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The SCI port operation is configured and controlled by the registers listed in Table 5-33 and Table 5-34.
Table 5-33. SCI-A Registers(1)
EALLOW
NAME ADDRESS SIZE (x16) DESCRIPTION
PROTECTED
SCICCRA 0x7050 1 No SCI-A Communications Control Register
SCICTL1A 0x7051 1 No SCI-A Control Register 1
SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits
SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits
SCICTL2A 0x7054 1 No SCI-A Control Register 2
SCIRXSTA 0x7055 1 No SCI-A Receive Status Register
SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register
SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register
SCIFFTXA(2) 0x705A 1 No SCI-A FIFO Transmit Register
SCIFFRXA(2) 0x705B 1 No SCI-A FIFO Receive Register
SCIFFCTA(2) 0x705C 1 No SCI-A FIFO Control Register
SCIPRIA 0x705F 1 No SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 5-34. SCI-B Registers(1)
NAME ADDRESS SIZE (x16) DESCRIPTION
SCICCRB 0x7750 1 SCI-B Communications Control Register
SCICTL1B 0x7751 1 SCI-B Control Register 1
SCIHBAUDB 0x7752 1 SCI-B Baud Register, High Bits
SCILBAUDB 0x7753 1 SCI-B Baud Register, Low Bits
SCICTL2B 0x7754 1 SCI-B Control Register 2
SCIRXSTB 0x7755 1 SCI-B Receive Status Register
SCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer Register
SCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer Register
SCIFFTXB(2) 0x775A 1 SCI-B FIFO Transmit Register
SCIFFRXB(2) 0x775B 1 SCI-B FIFO Receive Register
SCIFFCTB(2) 0x775C 1 SCI-B FIFO Control Register
SCIPRIB 0x775F 1 SCI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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TX FIFO _0
LSPCLK
WUT
Frame Format and Mode
Even/Odd Enable
Parity
SCI RX Interrupt select logic
BRKDT
RXRDY
SCIRXST.6
SCICTL1.3
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt select logic
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
SCICCR.6 SCICCR.5
SCITXBUF.7-0
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 - 0
Transmitter-Data
Buffer Register
8SCICTL2.6
SCICTL2.7
Baud Rate
LSbyte
Register
RXSHF
Register
TXSHF
Register
SCIRXST.5
1TX FIFO _1
-----
TX FIFO _3
8
TX FIFO registers
TX FIFO
TX Interrupt
Logic
TXINT
SCIFFTX.14
RX FIFO _3
SCIRXBUF.7-0
Receive Data
Buffer register
SCIRXBUF.7-0
-----
RX FIFO_1
RX FIFO _0
8
RX FIFO registers
SCICTL1.0
RX Interrupt
Logic
RXINT
RX FIFO
SCIFFRX.15
RXFFOVF
RX Error
SCIRXST.7
PEFE OE
RX Error
SCIRXST.4 - 2
To CPU
To CPU
AutoBaud Detect logic
SCICTL1.1
SCIFFENA
Interrupts
Interrupts
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Figure 5-31 shows the SCI module block diagram.
Figure 5-31. Serial Communications Interface (SCI) Module Block Diagram
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( )
CLKSRG
CLKG = 1+ CLKGDV
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5.14 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
• Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices
• Full-duplex communication
• Double-buffered data registers that allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
• 8-bit data transfers with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
• Works with SPI-compatible devices
• The following application interfaces can be supported on the McBSP:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
– IIS-compliant devices
– SPI
• McBSP clock rate,
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit.
NOTE
See Section 5 for maximum I/O pin toggling speed.
NOTE
On the 80-pin package, only the clock-stop mode (SPI) of the McBSP is supported.
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16
McBSP Receive
Interrupt Select Logic
MDXx
MDRx
Expand Logic
DRR1 Receive Buffer
RX
Interrupt
DRR2 Receive Buffer
RBR1 RegisterRBR2 Register
MCLKXx
MFSXx
MCLKRx
MFSRx
16
Compand Logic
DXR2 Transmit Buffer
RSR1
XSR2 XSR1
Peripheral Read Bus
16
16 16
16
16
RSR2
DXR1 Transmit Buffer
LSPCLK
MRINT
To CPU
RX Interrupt Logic
McBSP Transmit
Interrupt Select Logic
TX
Interrupt
MXINT
To CPU TX Interrupt Logic
16
16 16
Bridge
DMA Bus
Peripheral Bus
Peripheral Write Bus
CPU
CPU
CPU
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Figure 5-32 shows the block diagram of the McBSP module.
Figure 5-32. McBSP Module
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Table 5-35 provides a summary of the McBSP registers.
Table 5-35. McBSP Register Summary
McBSP-A
NAME TYPE RESET VALUE DESCRIPTION
ADDRESS
Data Registers, Receive, Transmit
DRR2 0x5000 R 0x0000 McBSP Data Receive Register 2
DRR1 0x5001 R 0x0000 McBSP Data Receive Register 1
DXR2 0x5002 W 0x0000 McBSP Data Transmit Register 2
DXR1 0x5003 W 0x0000 McBSP Data Transmit Register 1
McBSP Control Registers
SPCR2 0x5004 R/W 0x0000 McBSP Serial Port Control Register 2
SPCR1 0x5005 R/W 0x0000 McBSP Serial Port Control Register 1
RCR2 0x5006 R/W 0x0000 McBSP Receive Control Register 2
RCR1 0x5007 R/W 0x0000 McBSP Receive Control Register 1
XCR2 0x5008 R/W 0x0000 McBSP Transmit Control Register 2
XCR1 0x5009 R/W 0x0000 McBSP Transmit Control Register 1
SRGR2 0x500A R/W 0x0000 McBSP Sample Rate Generator Register 2
SRGR1 0x500B R/W 0x0000 McBSP Sample Rate Generator Register 1
Multichannel Control Registers
MCR2 0x500C R/W 0x0000 McBSP Multichannel Register 2
MCR1 0x500D R/W 0x0000 McBSP Multichannel Register 1
RCERA 0x500E R/W 0x0000 McBSP Receive Channel Enable Register Partition A
RCERB 0x500F R/W 0x0000 McBSP Receive Channel Enable Register Partition B
XCERA 0x5010 R/W 0x0000 McBSP Transmit Channel Enable Register Partition A
XCERB 0x5011 R/W 0x0000 McBSP Transmit Channel Enable Register Partition B
PCR 0x5012 R/W 0x0000 McBSP Pin Control Register
RCERC 0x5013 R/W 0x0000 McBSP Receive Channel Enable Register Partition C
RCERD 0x5014 R/W 0x0000 McBSP Receive Channel Enable Register Partition D
XCERC 0x5015 R/W 0x0000 McBSP Transmit Channel Enable Register Partition C
XCERD 0x5016 R/W 0x0000 McBSP Transmit Channel Enable Register Partition D
RCERE 0x5017 R/W 0x0000 McBSP Receive Channel Enable Register Partition E
RCERF 0x5018 R/W 0x0000 McBSP Receive Channel Enable Register Partition F
XCERE 0x5019 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E
XCERF 0x501A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F
RCERG 0x501B R/W 0x0000 McBSP Receive Channel Enable Register Partition G
RCERH 0x501C R/W 0x0000 McBSP Receive Channel Enable Register Partition H
XCERG 0x501D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G
XCERH 0x501E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H
MFFINT 0x5023 R/W 0x0000 McBSP Interrupt Enable Register
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
5.14.1 Multichannel Buffered Serial Port (McBSP) Electrical Data/Timing
5.14.1.1 McBSP Transmit and Receive Timing
Table 5-36. McBSP Timing Requirements(1)(2)
NO. MIN MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range 1 kHz
20(3)(4) MHz
McBSP module cycle time (CLKG, CLKX, CLKR) range 50(4) ns
1 ms
M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns
M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 7 ns
M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns
M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns
M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 18 ns
CLKR ext 2
M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 0 ns
CLKR ext 6
M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR int 18 ns
CLKR ext 2
M18 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR int 0 ns
CLKR ext 6
M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX int 18 ns
CLKX ext 2
M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX int 0 ns
CLKX ext 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤(SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (20 MHz).
(4) Maximum McBSP module clock frequency decreases to 10 MHz for internal CLKR.
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Table 5-37. McBSP Switching Characteristics(1)(2)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns
M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D – 5(3) D + 5(3) ns
M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C – 5(3) C + 5(3) ns
M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int 0 4 ns
CLKR ext 3 27
M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int 0 4 ns
CLKX ext 3 27
M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance CLKX int 8 ns
following last data bit CLKX ext 14
M7 td(CKXH-DXV) Delay time, CLKX high to DX valid. CLKX int 9 ns
This applies to all bits except the first bit transmitted. CLKX ext 28
Delay time, CLKX high to DX valid DXENA = 0 CLKX int 8
CLKX ext 14
Only applies to first bit transmitted when DXENA = 1 CLKX int P + 8
in Data Delay 1 or 2 (XDATDLY=01b or CLKX ext P + 14
10b) modes
M8 ten(CKXH-DX) Enable time, CLKX high to DX driven DXENA = 0 CLKX int 0 ns
CLKX ext 6
Only applies to first bit transmitted when DXENA = 1 CLKX int P
in Data Delay 1 or 2 (XDATDLY=01b or CLKX ext P + 6
10b) modes
M9 td(FXH-DXV) Delay time, FSX high to DX valid DXENA = 0 FSX int 8 ns
FSX ext 14
Only applies to first bit transmitted when DXENA = 1 FSX int P + 8
in Data Delay 0 (XDATDLY=00b) mode. FSX ext P + 14
M10 ten(FXH-DX) Enable time, FSX high to DX driven DXENA = 0 FSX int 0 ns
FSX ext 6
Only applies to first bit transmitted when DXENA = 1 FSX int P
in Data Delay 0 (XDATDLY=00b) mode FSX ext P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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M8
M7
M7
M8
M6
M7
M9
M10
(XDATDLY=10b)
DX
(XDATDLY=01b)
DX
(XDATDLY=00b)
DX
(n−2)Bit (n−1)Bit 0
(n−4)Bit (n−1) (n−3)(n−2)Bit 0
(n−3)(n−2)Bit (n−1)
Bit 0
M20
M14
M13
M3, M12
M1, M11
M2, M12
FSX (ext)
FSX (int)
CLKX
M5
M5
M19
(n−2)Bit (n−1)
(n−3)(n−2)Bit (n−1)
(n−4)(n−3)(n−2)Bit (n−1)
M18
M17
M18
M17
M17 M18
M16
M15
M4
M4 M14
M13
M3, M12
M1, M11
M2, M12
(RDATDLY=10b)
DR
(RDATDLY=01b)
DR
(RDATDLY=00b)
DR
FSR (ext)
FSR (int)
CLKR
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Figure 5-33. McBSP Receive Timing
Figure 5-34. McBSP Transmit Timing
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Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
M30 M31
DR
M28
M24
M29
M25
LSB MSB
M32 M33
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5.14.1.2 McBSP as SPI Master or Slave Timing
Table 5-38. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns
M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns
M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P + 10 ns
M33 tc(CKX) Cycle time, CLKX 2P(1) 16P ns
(1) 2P = 1/CLKG
Table 5-39. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
over recommended operating conditions (unless otherwise noted) MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M24 th(CKXL-FXL) Hold time, FSX low after CLKX low 2P(1) ns
M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P ns
M28 tdis(FXH-DXHZ) Disable time, DX high impedance following 6 6P + 6 ns
last data bit from FSX high
M29 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 90 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 5.625 MHz and P = 11.11 ns.
Figure 5-35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M35
M37
M40
M39
M38
M34
LSB MSB
M41 M42
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Table 5-40. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns
M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns
M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P + 10 ns
M42 tc(CKX) Cycle time, CLKX 2P(1) 16P ns
(1) 2P = 1/CLKG
Table 5-41. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
over recommended operating conditions (unless otherwise noted) MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M34 th(CKXL-FXL) Hold time, FSX low after CLKX low P ns
M35 td(FXL-CKXH) Delay time, FSX low to CLKX high 2P(1) ns
M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit P + 6 7P + 6 ns
from CLKX low
M38 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 90 MHz, CLKX maximum
frequency is LSPCLK/16; that is, 5.625 MHz and P = 11.11 ns.
Figure 5-36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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M51
M50
M47
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M44
M48
M49
M43
LSB MSB M52
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Table 5-42. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns
M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns
M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P + 10 ns
M52 tc(CKX) Cycle time, CLKX 2P(1) 16P ns
(1) 2P = 1/CLKG
Table 5-43. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
over recommended operating conditions (unless otherwise noted) MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M43 th(CKXH-FXL) Hold time, FSX low after CLKX high 2P(1) ns
M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P ns
M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from 6 6P + 6 ns
FSX high
M48 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 90 MHz, CLKX maximum frequency
is LSPCLK/16; that is, 5.625 MHz and P = 11.11 ns.
Figure 5-37. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M54
M58
M56
M53
M55
M59
M57
LSB MSB
M60 M61
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Table 5-44. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns
M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns
M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P + 10 ns
M61 tc(CKX) Cycle time, CLKX 2P(1) 16P ns
(1) 2P = 1/CLKG
Table 5-45. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1)
over recommended operating conditions (unless otherwise noted) MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M53 th(CKXH-FXL) Hold time, FSX low after CLKX high P ns
M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P(1) ns
M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid –2 0 3P + 6 5P + 20 ns
M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last P + 6 7P + 6 ns
data bit from CLKX high
M57 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 90 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 5.625 MHz and P = 11.11 ns.
Figure 5-38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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5.15 Enhanced Controller Area Network (eCAN) Module
The CAN module (eCAN-A) has the following features:
• Fully compliant with CAN protocol, version 2.0B
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
• Low-power mode
• Programmable wake-up on bus activity
• Automatic reply to a remote request message
• Automatic retransmission of a frame in case of loss of arbitration or error
• 32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 90 MHz, the smallest bit rate possible is 6.25 kbps.
The F2806x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
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Mailbox RAM
(512 Bytes)
32-Message Mailbox
of 4 x 32-Bit Words
Memory Management
Unit
CPU Interface,
Receive Control Unit,
Timer Management Unit
eCAN Memory
(512 Bytes)
Registers and
Message Objects Control
Message Controller
32 32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
Enhanced CAN Controller 32
Controls Address Data
eCAN1INTeCAN0INT
32
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
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Figure 5-39. eCAN Block Diagram and Interface Circuit
Table 5-46. 3.3-V eCAN Transceivers
SUPPLY LOW-POWER SLOPE
PART NUMBER VREF OTHER TA
VOLTAGE MODE CONTROL
SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C
SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C
SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C
SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C
SN65HVD232 3.3 V None None None – –40°C to 85°C
SN65HVD232Q 3.3 V None None None – –40°C to 125°C
SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C
SN65HVD234 3.3 V Standby and Sleep Adjustable None – –40°C to 125°C
SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C
ISO1050 3–5.5 V None None None Built-in Isolation –55°C to 105°C
Low Prop Delay
Thermal Shutdown
Failsafe Operation
Dominant Time-Out
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Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
Master Control - CANMC
Bit-Timing Configuration - CANBTC
Error and Status - CANES
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Global Interrupt Flag 1 - CANGIF1
Time-Out Control - CANTOC
Time-Out Status - CANTOS
Reserved
eCAN-A Control and Status Registers
Message Identifier - MSGID
61E8h-61E9h
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
Message Mailbox (16 Bytes)
Control and Status Registers
6000h
603Fh
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
6040h
607Fh
6080h
60BFh
60C0h
60FFh
eCAN-A Memory (512 Bytes)
Message Object Time Stamps (MOTS)
(32 x 32-Bit RAM)
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Mailbox 06100h-6107h
Mailbox 1
6108h-610Fh
Mailbox 2
6110h-6117h
Mailbox 3
6118h-611Fh
eCAN-A Memory RAM (512 Bytes)
Mailbox 4
6120h-6127h
Mailbox 28
61E0h-61E7h
Mailbox 2961E8h-61EFh
Mailbox 3061F0h-61F7h
Mailbox 31
61F8h-61FFh
61EAh-61EBh
61ECh-61EDh
61EEh-61EFh
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Figure 5-40. eCAN-A Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO,
and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be
enabled for this.
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
The CAN registers listed in Table 5-47 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 5-47. CAN Register Map(1)
eCAN-A
REGISTER NAME SIZE (x32) DESCRIPTION
ADDRESS
CANME 0x6000 1 Mailbox enable
CANMD 0x6002 1 Mailbox direction
CANTRS 0x6004 1 Transmit request set
CANTRR 0x6006 1 Transmit request reset
CANTA 0x6008 1 Transmission acknowledge
CANAA 0x600A 1 Abort acknowledge
CANRMP 0x600C 1 Receive message pending
CANRML 0x600E 1 Receive message lost
CANRFP 0x6010 1 Remote frame pending
CANGAM 0x6012 1 Global acceptance mask
CANMC 0x6014 1 Master control
CANBTC 0x6016 1 Bit-timing configuration
CANES 0x6018 1 Error and status
CANTEC 0x601A 1 Transmit error counter
CANREC 0x601C 1 Receive error counter
CANGIF0 0x601E 1 Global interrupt flag 0
CANGIM 0x6020 1 Global interrupt mask
CANGIF1 0x6022 1 Global interrupt flag 1
CANMIM 0x6024 1 Mailbox interrupt mask
CANMIL 0x6026 1 Mailbox interrupt level
CANOPC 0x6028 1 Overwrite protection control
CANTIOC 0x602A 1 TX I/O control
CANRIOC 0x602C 1 RX I/O control
CANTSC 0x602E 1 Time stamp counter (Reserved in SCC mode)
CANTOC 0x6030 1 Time-out control (Reserved in SCC mode)
CANTOS 0x6032 1 Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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5.16 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 5-41 shows how the I2C peripheral module interfaces
within the device.
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
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I2CXSR I2CDXR
I2CRSR I2CDRR
Clock
Synchronizer
Prescaler
Noise Filters
Arbitrator
I2C INT
Peripheral Bus
Interrupt to
CPU/PIE
SDA
SCL
Control/Status
Registers CPU
I2C Module
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
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A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 5-41. I2C Peripheral Module Interfaces
The registers in Table 5-48 configure and control the I2C port operation.
Table 5-48. I2C-A Registers
EALLOW
NAME ADDRESS DESCRIPTION
PROTECTED
I2COAR 0x7900 No I2C own address register
I2CIER 0x7901 No I2C interrupt enable register
I2CSTR 0x7902 No I2C status register
I2CCLKL 0x7903 No I2C clock low-time divider register
I2CCLKH 0x7904 No I2C clock high-time divider register
I2CCNT 0x7905 No I2C data count register
I2CDRR 0x7906 No I2C data receive register
I2CSAR 0x7907 No I2C slave address register
I2CDXR 0x7908 No I2C data transmit register
I2CMDR 0x7909 No I2C mode register
I2CISRC 0x790A No I2C interrupt source register
I2CPSC 0x790C No I2C prescaler register
I2CFFTX 0x7920 No I2C FIFO transmit register
I2CFFRX 0x7921 No I2C FIFO receive register
I2CRSR – No I2C receive shift register (not accessible to the CPU)
I2CXSR – No I2C transmit shift register (not accessible to the CPU)
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5.16.1 Inter-Integrated Circuit (I2C) Electrical Data/Timing
Table 5-49. I2C Timing
TEST CONDITIONS MIN MAX UNIT
fSCL SCL clock frequency I2C clock module frequency is between 400 kHz
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
vil Low level input voltage 0.3 VDDIO V
Vih High level input voltage 0.7 VDDIO V
Vhys Input hysteresis 0.05 VDDIO V
Vol Low level output voltage 3 mA sink current 0 0.4 V
tLOW Low period of SCL clock I2C clock module frequency is between 1.3 μs
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tHIGH High period of SCL clock I2C clock module frequency is between 0.6 μs
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
lIInput current with an input voltage –10 10 μA
between 0.1 VDDIO and 0.9 VDDIO MAX
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EPWM1TZINT
PIE
EPWM1INT
EPWM2TZINT
EPWM2INT
EPWMxTZINT
EPWMxINT
COMPOUT1
COMPOUT2
COMP
SOCA1
ADC SOCB1
SOCA2
SOCB2
SOCAx
SOCBx
EPWM1SYNCI
EPWM2SYNCI
EPWM1SYNCO
EPWM2SYNCO
EPWM1
Module
EPWM2
Module
EPWMxSYNCI
EPWMx
Module
TZ6
TZ6
TZ1 TZ3to
TZ5 CLOCKFAIL
TZ4 EQEP1ERR(A)
EMUSTOP
TZ5 CLOCKFAIL
TZ4 EQEP1ERR(A)
EMUSTOP
EPWM1ENCLK
TBCLKSYNC
EPWM2ENCLK
TBCLKSYNC
TZ5
TZ6
EPWMxENCLK
TBCLKSYNC
CLOCKFAIL
TZ4 EQEP1ERR(A)
EMUSTOP
EPWM1B
C28x CPU
System Control
eQEP1
TZ1 TZ3to
TZ1 TZ3to
EPWM1SYNCO
EPWM2B
eCAPI
EPWMxB
EQEP1ERR
H
R
P
W
MEPWMxA
EPWM2A
EPWM1A
G
P
I
O
M
U
X
ADCSOCBO
ADCSOCAO
Peripheral Bus
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCA1
SOCA2
SPCAx
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCB1
SOCB2
SPCBx
EPWMSYNCI
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5.17 Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1/2/3/4/5/6/7/8)
The devices contain up to eight enhanced PWM Modules (ePWM). Figure 5-42 shows a block diagram of
multiple ePWM modules. Figure 5-43 shows the signal interconnections with the ePWM.
Table 5-50 and Table 5-51 show the complete ePWM register set per module.
A. This signal exists only on devices with an eQEP1 module.
Figure 5-42. ePWM
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Table 5-50. ePWM1–ePWM4 Control and Status Registers
SIZE (x16) /
NAME ePWM1 ePWM2 ePWM3 ePWM4 DESCRIPTION
#SHADOW
TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register
TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set
TBPRDHR 0x6806 0x6846 0x6886 0x68C6 1 / 1 Time Base Period High Resolution Register(1)
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register
CMPAHR 0x6808 0x6848 0x6888 0x68C8 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register(1)
TZDCSEL 0x6813 0x6853 0x6893 0x68D3 1 / 0 Trip Zone Digital Compare Register
TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register (1)
TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register
ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register
HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1 / 0 HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.
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Table 5-50. ePWM1–ePWM4 Control and Status Registers (continued)
SIZE (x16) /
NAME ePWM1 ePWM2 ePWM3 ePWM4 DESCRIPTION
#SHADOW
HRMSTEP 0x6826 - - - 1 / 0 HRPWM MEP Step Register
HRPCTL 0x6828 0x6868 0x68A8 0x68E8 1 / 0 High resolution Period Control Register(1)
TBPRDHRM 0x682A 0x686A 0x68AA 0x68EA 1 / W(2) Time Base Period HRPWM Register Mirror
TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W(2) Time Base Period Register Mirror
CMPAHRM 0x682C 0x686C 0x68AC 0x68EC 1 / W(2) Compare A HRPWM Register Mirror
CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W(2) Compare A Register Mirror
DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1 / 0 Digital Compare Trip Select Register (1)
DCACTL 0x6831 0x6871 0x68B1 0x68F1 1 / 0 Digital Compare A Control Register(1)
DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1 / 0 Digital Compare B Control Register(1)
DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1 / 0 Digital Compare Filter Control Register(1)
DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1 / 0 Digital Compare Capture Control Register(1)
DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1 / 1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1 / 0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1 / 0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1 / 0 Digital Compare Filter Window Counter Register
DCCAP 0x6839 0x6879 0x68B9 0x68F9 1 / 1 Digital Compare Counter Capture Register
(2) W = Write to shadow register
Table 5-51. ePWM5–ePWM8 Control and Status Registers
SIZE (x16) /
NAME ePWM5 ePWM6 ePWM7 ePWM8 DESCRIPTION
#SHADOW
TBCTL 0x6900 0x6940 0x6980 0x69C0 1 / 0 Time Base Control Register
TBSTS 0x6901 0x6941 0x6981 0x69C1 1 / 0 Time Base Status Register
TBPHSHR 0x6902 0x6942 0x6982 0x69C2 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6903 0x6943 0x6983 0x69C3 1 / 0 Time Base Phase Register
TBCTR 0x6904 0x6944 0x6984 0x69C4 1 / 0 Time Base Counter Register
TBPRD 0x6905 0x6945 0x6985 0x69C5 1 / 1 Time Base Period Register Set
TBPRDHR 0x6906 0x6946 0x6986 0x69C6 1 / 1 Time Base Period High Resolution Register(1)
CMPCTL 0x6907 0x6947 0x6987 0x69C7 1 / 0 Counter Compare Control Register
CMPAHR 0x6908 0x6948 0x6988 0x69C8 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6909 0x6949 0x6989 0x69C9 1 / 1 Counter Compare A Register Set
CMPB 0x690A 0x694A 0x698A 0x69CA 1 / 1 Counter Compare B Register Set
(1) Registers that are EALLOW protected.
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Table 5-51. ePWM5–ePWM8 Control and Status Registers (continued)
SIZE (x16) /
NAME ePWM5 ePWM6 ePWM7 ePWM8 DESCRIPTION
#SHADOW
AQCTLA 0x690B 0x694B 0x698B 0x69CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x690C 0x694C 0x698C 0x69CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x690D 0x694D 0x698D 0x69CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x690E 0x694E 0x698E 0x69CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x690F 0x694F 0x698F 0x69CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6910 0x6950 0x6990 0x69D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6911 0x6951 0x6991 0x69D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6912 0x6952 0x6992 0x69D2 1 / 0 Trip Zone Select Register(1)
TZDCSEL 0x6913 0x6953 0x6993 0x69D3 1 / 0 Trip Zone Digital Compare Register
TZCTL 0x6914 0x6954 0x6994 0x69D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6915 0x6955 0x6995 0x69D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6916 0x6956 0x6996 0x69D6 1 / 0 Trip Zone Flag Register (1)
TZCLR 0x6917 0x6957 0x6997 0x69D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6918 0x6958 0x6998 0x69D8 1 / 0 Trip Zone Force Register(2)
ETSEL 0x6919 0x6959 0x6999 0x69D9 1 / 0 Event Trigger Selection Register
ETPS 0x691A 0x695A 0x699A 0x69DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x691B 0x695B 0x699B 0x69DB 1 / 0 Event Trigger Flag Register
ETCLR 0x691C 0x695C 0x699C 0x69DC 1 / 0 Event Trigger Clear Register
ETFRC 0x691D 0x695D 0x699D 0x69DD 1 / 0 Event Trigger Force Register
PCCTL 0x691E 0x695E 0x699E 0x69DE 1 / 0 PWM Chopper Control Register
HRCNFG 0x6920 0x6960 0x69A0 0x69E0 1 / 0 HRPWM Configuration Register(2)
HRMSTEP - - - - 1 / 0 HRPWM MEP Step Register
HRPCTL 0x6928 0x6968 0x69A8 0x69E8 1 / 0 High resolution Period Control Register(2)
TBPRDHRM 0x692A 0x696A 0x69AA 0x69EA 1 / W(3) Time Base Period HRPWM Register Mirror
TBPRDM 0x692B 0x696B 0x69AB 0x69EB 1 / W(3) Time Base Period Register Mirror
CMPAHRM 0x692C 0x696C 0x69AC 0x69EC 1 / W(3) Compare A HRPWM Register Mirror
CMPAM 0x692D 0x696D 0x69AD 0x69ED 1 / W(3) Compare A Register Mirror
DCTRIPSEL 0x6930 0x6970 0x69B0 0x69F0 1 / 0 Digital Compare Trip Select Register (2)
DCACTL 0x6931 0x6971 0x69B1 0x69F1 1 / 0 Digital Compare A Control Register(2)
DCBCTL 0x6932 0x6972 0x69B2 0x69F2 1 / 0 Digital Compare B Control Register(2)
DCFCTL 0x6933 0x6973 0x69B3 0x69F3 1 / 0 Digital Compare Filter Control Register(2)
(2) Registers that are EALLOW protected.
(3) W = Write to shadow register
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Table 5-51. ePWM5–ePWM8 Control and Status Registers (continued)
SIZE (x16) /
NAME ePWM5 ePWM6 ePWM7 ePWM8 DESCRIPTION
#SHADOW
DCCAPCT 0x6934 0x6974 0x69B4 0x69F4 1 / 0 Digital Compare Capture Control Register(2)
DCFOFFSET 0x6935 0x6975 0x69B5 0x69F5 1 / 1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6936 0x6976 0x69B6 0x69F6 1 / 0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6937 0x6977 0x69B7 0x69F7 1 / 0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6938 0x6978 0x69B8 0x69F8 1 / 0 Digital Compare Filter Window Counter Register
DCCAP 0x6939 0x6979 0x69B9 0x69F9 1 / 1 Digital Compare Counter Capture Register
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TBPRD Shadow (24)
TBPRD Active (24)
Counter
Up/Down
(16 Bit)
TCBNT
Active (16)
TBCTL[PHSEN]
CTR=PRD
16
Phase
Control
8
CTR=ZERO
CTR_Dir
TBPHSHR (8)
TBPRDHR (8)
8
CTR=ZERO
CTR=CMPB
Disabled
TBCTL[SYNCOSEL]
EPWMxSYNCO
Time-Base (TB)
TBPHS Active (24)
Sync
In/Out
Select
Mux
CTR=PRD
CTR=ZERO
CTR=CMPA
CTR=CMPB
CTR_Dir
DCAEVT1.soc(A)
DCBEVT1.soc(A)
Event
Trigger
and
Interrupt
(ET)
EPWMxINT
EPWMxSOCA
EPWMxSOCB
EPWMxSOCA
EPWMxSOCB
ADC
Action
Qualifier
(AQ)
EPWMA
Dead
Band
(DB)
EPWMB
PWM
Chopper
(PC)
Trip
Zone
(TZ)
EPWMxA
EPWMxB
CTR=ZERO
EPWMxTZINT
TZ1 TZ3to
EMUSTOP
CLOCKFAIL
EQEP1ERR(B)
DCAEVT1.force(A)
DCAEVT2.force(A)
DCBEVT1.force(A)
DCBEVT2.force(A)
CTR=CMPA
16
CMPAHR (8)
CTR=CMPB
16
CMPB Active (16)
CMPB Shadow (16)
High-resolution PWM (HRPWM)
CTR=PRD or ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
DCBEVT2.inter
EPWMxSYNCI
TBCTL[SWFSYNC]
(Software Forced
Sync)
DCAEVT1.sync
DCBEVT1.sync
CMPA Active (24)
CMPA Shadow (24)
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A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of
the COMPxOUT and TZ signals.
B. This signal exists only on devices with an eQEP1 module.
Figure 5-43. ePWM Sub-Modules Showing Critical Internal Signal Interconnections
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PWM(B)
TZ
XCLKOUT(A)
tw(TZ)
td(TZ-PWM)HZ
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5.17.1 Enhanced Pulse Width Modulator (ePWM) Electrical Data/Timing
PWM refers to PWM outputs on ePWM1–8. Table 5-52 shows the PWM timing requirements and Table 5-
53, switching characteristics.
Table 5-52. ePWM Timing Requirements(1)
TEST CONDITIONS MIN MAX UNIT
tw(SYCIN) Sync input pulse width Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 5-69.
Table 5-53. ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 33.33 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles
td(PWM)tza Delay time, trip input active to PWM forced high no pin load 25 ns
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns
5.17.2 Trip-Zone Input Timing
Table 5-54. Trip-Zone Input Timing Requirements(1)
MIN MAX UNIT
tw(TZ) Pulse duration, TZx input low Asynchronous 2tc(TBCLK) cycles
Synchronous 2tc(TBCLK) cycles
With input qualifier 2tc(TBCLK) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 5-69.
C. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
D. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 5-44. PWM Hi-Z Characteristics
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5.18 High-Resolution PWM (HRPWM)
This module combines multiple delay lines in a single module and a simplified calibration system by using
a dedicated calibration delay line. For each ePWM module there is one HR delay line.
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be utilized in both single edge (duty cycle and phase-shift control) as well as dual
edge control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and
Phase registers of the ePWM module.
• HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an
ePWM module (that is, on the EPWMxA output). EPWMxB output has conventional PWM capabilities.
NOTE
The minimum SYSCLKOUT frequency allowed for HRPWM is 60 MHz.
NOTE
When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB
channel will have ±1–2 TBCLK cycles of jitter on the output.
5.18.1 High-Resolution PWM (HRPWM) Electrical Data/Timing
Table 5-55 shows the high-resolution PWM switching characteristics.
Table 5-55. High-Resolution PWM Characteristics(1)
MIN TYP MAX UNIT
Micro Edge Positioning (MEP) step size(2) 150 310 ps
(1) The HRPWM operates at a minimum SYSCLKOUT frequency of 60 MHz.
(2) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
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TSCTR
(counter−32 bit)
RST
CAP1
(APRD active) LD
CAP2
(ACMP active) LD
CAP3
(APRD shadow) LD
CAP4
(ACMP shadow) LD
Continuous /
Oneshot
Capture Control
LD1
LD2
LD3
LD4
32
32
PRD [0−31]
CMP [0−31]
CTR [0−31]
eCAPx
Interrupt
Trigger
and
Flag
control
to PIE
CTR=CMP
32
32
32
32
32
ACMP
shadow
Event
Pre-scale
CTRPHS
(phase register−32 bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR [0−31]
PRD [0−31]
CMP [0−31]
CTR=CMP
CTR=PRD
CTR_OVF
OVF
APWM mode
Delta−mode
SYNC
4
Capture events
CEVT[1:4]
APRD
shadow
32
32
MODE SELECT
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5.19 Enhanced Capture Module (eCAP1)
The device contains an enhanced capture (eCAP) module. Figure 5-45 shows a functional block diagram
of a module.
Figure 5-45. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for
low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
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Table 5-56. eCAP Control and Status Registers
EALLOW
NAME eCAP1 eCAP2 eCAP3 SIZE (x16) DESCRIPTION
PROTECTED
TSCTR 0x6A00 0x6A20 0x6A40 2 No Time-Stamp Counter
CTRPHS 0x6A02 0x6A22 0x6A42 2 No Counter Phase Offset Value Register
CAP1 0x6A04 0x6A24 0x6A44 2 No Capture 1 Register
CAP2 0x6A06 0x6A26 0x6A46 2 No Capture 2 Register
CAP3 0x6A08 0x6A28 0x6A48 2 No Capture 3 Register
CAP4 0x6A0A 0x6A2A 0x6A4A 2 No Capture 4 Register
Reserved 0x6A0C – 0x6A2C – 0x6A4C – 8 No Reserved
0x6A12 0x6A32 0x6A52
ECCTL1 0x6A14 0x6A34 0x6A54 1 No Capture Control Register 1
ECCTL2 0x6A15 0x6A35 0x6A55 1 No Capture Control Register 2
ECEINT 0x6A16 0x6A36 0x6A56 1 No Capture Interrupt Enable Register
ECFLG 0x6A17 0x6A37 0x6A57 1 No Capture Interrupt Flag Register
ECCLR 0x6A18 0x6A38 0x6A58 1 No Capture Interrupt Clear Register
ECFRC 0x6A19 0x6A39 0x6A59 1 No Capture Interrupt Force Register
Reserved 0x6A1A – 0x6A3A – 0x6A5A – 6 No Reserved
0x6A1F 0x6A3F 0x6A5F
5.19.1 Enhanced Capture (eCAP) Electrical Data/Timing
Table 5-57 shows the eCAP timing requirement and Table 5-58 shows the eCAP switching characteristics.
Table 5-57. Enhanced Capture (eCAP) Timing Requirement(1)
TEST CONDITIONS MIN MAX UNIT
tw(CAP) Capture input pulse width Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 5-69.
Table 5-58. eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns
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PIE
HRCAPx
SYSCLK2
PLL2CLK
HRCAPxENCLK
HRCAPxINTn
HRCAP Calibration Logic
EPWMxAEPWMx HRPWM
HRCAP Calibration Signal (Internal) GPIO
Mux
HRCAPx
Module
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5.20 High-Resolution Capture Modules (HRCAP1/2/3/4)
The device contains up to four high-resolution capture (HRCAP) modules. The High-Resolution Capture
(HRCAP) module measures the difference between external pulses with a typical resolution of 300 ps.
Uses for the HRCAP include:
• Capactive touch applications
• High-resolution period and duty cycle measurements of pulse train cycles
• Instantaneous speed measurements
• Instantaneous frequency measurements
• Voltage measurements across an isolation boundary
• Distance/sonar measurement and scanning
The HRCAP module features include:
• Pulse width capture in either non-high-resolution or high-resolution modes
• Difference (Delta) mode pulse width capture
• Typical high-resolution capture on the order of 300 ps resolution on each edge
• Interrupt on either falling or rising edge
• Continuous mode capture of pulse widths in 2-deep buffer
• Calibration logic for precision high-resolution capture
• All of the above resources are dedicated to a single input pin
• HRCAP calibration software library supplied by TI is used for both calibration and calculating fractional
pulse widths
The HRCAP module includes one capture channel in addition to a high-resolution calibration block, which
connects internally to ePWM8A HRPWM channel when calibrating.
Each HRCAP channel has the following independent key resources:
• Dedicated input capture pin
• 16-bit HRCAP clock which is either equal to the PLL2 output frequency (asynchronous to SYSCLK2) or
equal to the SYSCLK2 frequency (synchronous to SYSCLK2)
• High-resolution pulse width capture in a 2-deep buffer
Figure 5-46. HRCAP Functional Block Diagram
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Table 5-59. HRCAP Registers
SIZE
NAME HRCAP1 HRCAP2 HRCAP3 HRCAP4 DESCRIPTION
(x16)
HCCTL 0x6AC0 0x6AE0 0x6C80 0x6CA0 1 HRCAP Control Register(1)
HCIFR 0x6AC1 0x6AE1 0x6C81 0x6CA1 1 HRCAP Interrupt Flag Register
HCICLR 0x6AC2 0x6AE2 0x6C82 0x6CA2 1 HRCAP Interrupt Clear Register
HCIFRC 0x6AC3 0x6AE3 0x6C83 0x6CA3 1 HRCAP Interrupt Force Register
HCCOUNTER 0x6AC4 0x6AE4 0x6C84 0x6CA4 1 HRCAP 16-bit Counter Register
HRCAP Capture Counter on
HCCAPCNTRISE0 0x6AD0 0x6AF0 0x6C90 0x6CB0 1 Rising Edge 0 Register
HRCAP Capture Counter on
HCCAPCNTFALL0 0x6AD2 0x6AF2 0x6C92 0x6CB2 1 Falling Edge 0 Register
HRCAP Capture Counter on
HCCAPCNTRISE1 0x6AD8 0x6AF8 0x6C98 0x6CB8 1 Rising Edge 1 Register
HRCAP Capture Counter on
HCCAPCNTFALL1 0x6ADA 0x6AFA 0x6C9A 0x6CBA 1 Falling Edge 1 Register
(1) Registers that are EALLOW-protected.
5.20.1 High-Resolution Capture (HRCAP) Electrical Data/Timing
Table 5-60. High-Resolution Capture (HRCAP) Timing Requirements
MIN NOM MAX UNIT
tc(HCCAPCLK) Cycle time, HRCAP capture clock 8.333 10.204 ns
tw(HRCAP) Pulse width, HRCAP capture 7tc(HCCAPCLK)(1) ns
HRCAP step size(2) 300 ps
(1) The listed minimum pulse width does not take into account the limitation that all relevant HCCAP registers must be read and RISE/FALL
event flags cleared within the pulse width to ensure valid capture data.
(2) HRCAP step size will increase with low voltage and high temperature and decrease with high voltage and low temperature. Applications
that use the HRCAP in high-resolution mode should use the HRCAP calibration functions to dynamically calibrate for varying operating
conditions.
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5.21 Enhanced Quadrature Encoder Modules (eQEP1/2)
The device contains up to two enhanced quadrature encoder (eQEP) modules. Table 5-61 provides a
summary of the eQEP registers.
Table 5-61. eQEP Control and Status Registers
eQEP1
eQEP1 eQEP2
NAME SIZE(x16)/ REGISTER DESCRIPTION
ADDRESS ADDRESS #SHADOW
QPOSCNT 0x6B00 0x6B40 2/0 eQEP Position Counter
QPOSINIT 0x6B02 0x6B42 2/0 eQEP Initialization Position Count
QPOSMAX 0x6B04 0x6B44 2/0 eQEP Maximum Position Count
QPOSCMP 0x6B06 0x6B46 2/1 eQEP Position-compare
QPOSILAT 0x6B08 0x6B48 2/0 eQEP Index Position Latch
QPOSSLAT 0x6B0A 0x6B4A 2/0 eQEP Strobe Position Latch
QPOSLAT 0x6B0C 0x6B4C 2/0 eQEP Position Latch
QUTMR 0x6B0E 0x6B4E 2/0 eQEP Unit Timer
QUPRD 0x6B10 0x6B50 2/0 eQEP Unit Period Register
QWDTMR 0x6B12 0x6B52 1/0 eQEP Watchdog Timer
QWDPRD 0x6B13 0x6B53 1/0 eQEP Watchdog Period Register
QDECCTL 0x6B14 0x6B54 1/0 eQEP Decoder Control Register
QEPCTL 0x6B15 0x6B55 1/0 eQEP Control Register
QCAPCTL 0x6B16 0x6B56 1/0 eQEP Capture Control Register
QPOSCTL 0x6B17 0x6B57 1/0 eQEP Position-compare Control Register
QEINT 0x6B18 0x6B58 1/0 eQEP Interrupt Enable Register
QFLG 0x6B19 0x6B59 1/0 eQEP Interrupt Flag Register
QCLR 0x6B1A 0x6B5A 1/0 eQEP Interrupt Clear Register
QFRC 0x6B1B 0x6B5B 1/0 eQEP Interrupt Force Register
QEPSTS 0x6B1C 0x6B5C 1/0 eQEP Status Register
QCTMR 0x6B1D 0x6B5D 1/0 eQEP Capture Timer
QCPRD 0x6B1E 0x6B5E 1/0 eQEP Capture Period Register
QCTMRLAT 0x6B1F 0x6B5F 1/0 eQEP Capture Timer Latch
QCPRDLAT 0x6B20 0x6B60 1/0 eQEP Capture Period Latch
Reserved 0x6B21 – 0x6B61 – 31/0
0x6B3F 0x6B7F
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QWDTMR
QWDPRD
16
QWDOG
UTIME
QUPRD
QUTMR
32
UTOUT
WDTOUT
Quadrature
Capture
Unit
(QCAP)
QCPRDLAT
QCTMRLAT
16
QFLG
QEPSTS
QEPCTL
Registers
Used by
Multiple Units
QCLK
QDIR
QI
QS
PHE
PCSOUT
Quadrature
Decoder
(QDU)
QDECCTL
16
Position Counter/
Control Unit
(PCCU)
QPOSLAT
QPOSSLAT
16
QPOSILAT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
GPIO
MUX
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxS
EQEPxI
QPOSCMP QEINT
QFRC
32
QCLR
QPOSCTL
1632
QPOSCNT
QPOSMAX
QPOSINIT
PIE EQEPxINT
Enhanced QEP (eQEP) Peripheral
System Control
Registers
QCTMR
QCPRD
1616
QCAPCTL
EQEPxENCLK
SYSCLKOUT
To CPU
Data Bus
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Figure 5-47 shows the block diagram of the eQEP module.
Figure 5-47. eQEP Functional Block Diagram
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5.21.1 Enhanced Quadrature Encoder (eQEP) Electrical Data/Timing
Table 5-62 shows the eQEP timing requirement and Table 5-63 shows the eQEP switching
characteristics.
Table 5-62. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements(1)
TEST CONDITIONS MIN MAX UNIT
tw(QEPP) QEP input period Synchronous 2tc(SCO) cycles
With input qualifier 2[1tc(SCO) + tw(IQSW)] cycles
tw(INDEXH) QEP Index Input High time Synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) +tw(IQSW) cycles
tw(INDEXL) QEP Index Input Low time Synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW) cycles
tw(STROBH) QEP Strobe High time Synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW) cycles
tw(STROBL) QEP Strobe Input Low time Synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) +tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 5-69.
Table 5-63. eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync 6tc(SCO) cycles
output
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TRST
1
0
C28x
Core
TCK/GPIO38
TCK
XCLKIN
GPIO38_in
GPIO38_out
TDO
GPIO37_out
TDO/GPIO37
GPIO37_in
1
0
TMS
TMS/GPIO36
GPIO36_out
GPIO36_in
1
1
0
TDI
TDI/GPIO35
GPIO35_out
GPIO35_in
1
TRST
TRST
= 0: JTAG Disabled (GPIO Mode)
= 1: JTAG Mode
TRST
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5.22 JTAG Port
On the 2806x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS
and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the
pins in Figure 5-48. During emulation/debug, the GPIO function of these pins are not available. If the
GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used
to clock the device during emulation/debug since this pin will be needed for the TCK function.
NOTE
In 2806x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in
the board design to ensure that the circuitry connected to these pins do not affect the
emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should
not prevent the emulator from driving (or being driven by) the JTAG pins for successful
debug.
Figure 5-48. JTAG/GPIO Multiplexing
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5.23 General-Purpose Input/Output (GPIO) MUX
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition
to providing individual pin bit-banging I/O capability.
The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral
Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 5-64 shows the
GPIO register mapping.
Table 5-64. GPIO Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 44)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 44)
GPBQSEL2 0x6F94 2 GPIO B Qualifier Select 2 Register
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 44)
GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO50 to 58)
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 44)
GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 44)
AIOMUX1 0x6FB6 2 Analog, I/O mux 1 register (AIO0 to AIO15)
AIODIR 0x6FBA 2 Analog, I/O Direction Register (AIO0 to AIO15)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 44)
GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 44)
GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 44)
GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 44)
AIODAT 0x6FD8 2 Analog I/O Data Register (AIO0 to AIO15)
AIOSET 0x6FDA 2 Analog I/O Data Set Register (AIO0 to AIO15)
AIOCLEAR 0x6FDC 2 Analog I/O Data Clear Register (AIO0 to AIO15)
AIOTOGGLE 0x6FDE 2 Analog I/O Data Toggle Register (AIO0 to AIO15)
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)
NOTE
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn
and GPxQSELn registers occurs to when the action is valid.
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Table 5-65. GPIOA MUX(1) (2)
DEFAULT AT RESET PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O SELECTION 1 SELECTION 2 SELECTION 3
FUNCTION
GPAMUX1 REGISTER (GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11)
BITS
1-0 GPIO0 EPWM1A (O) Reserved Reserved
3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O)
5-4 GPIO2 EPWM2A (O) Reserved Reserved
7-6 GPIO3 EPWM2B (O) SPISOMIA (I/O) COMP2OUT (O)
9-8 GPIO4 EPWM3A (O) Reserved Reserved
11-10 GPIO5 EPWM3B (O) SPISIMOA (I/O) ECAP1 (I/O)
13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15-14 GPIO7 EPWM4B (O) SCIRXDA (I) ECAP2 (I/O)
17-16 GPIO8 EPWM5A (O) Reserved ADCSOCAO (O)
19-18 GPIO9 EPWM5B (O) SCITXDB (O) ECAP3 (I/O)
21-20 GPIO10 EPWM6A (O) Reserved ADCSOCBO (O)
23-22 GPIO11 EPWM6B (O) SCIRXDB (I) ECAP1 (I/O)
25-24 GPIO12 TZ1 (I) SCITXDA (O) SPISIMOB (I/O)
27-26 GPIO13 TZ2 (I) Reserved SPISOMIB (I/O)
29-28 GPIO14 TZ3 (I) SCITXDB (O) SPICLKB (I/O)
31-30 GPIO15 ECAP2 (I/O) SCIRXDB (I) SPISTEB (I/O)
GPAMUX2 REGISTER (GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11)
BITS
1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I)
3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I)
5-4 GPIO18 SPICLKA (I/O) SCITXDB (O) XCLKOUT (O)
7-6 GPIO19/XCLKIN SPISTEA (I/O) SCIRXDB (I) ECAP1 (I/O)
9-8 GPIO20 EQEP1A (I) MDXA (O) COMP1OUT (O)
11-10 GPIO21 EQEP1B (I) MDRA (I) COMP2OUT (O)
13-12 GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O)
15-14 GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I)
17-16 GPIO24 ECAP1 (I/O) EQEP2A(3) (I) SPISIMOB (I/O)
19-18 GPIO25 ECAP2 (I/O) EQEP2B(3) (I) SPISOMIB (I/O)
21-20 GPIO26 ECAP3 (I/O) EQEP2I(3) (I/O) SPICLKB (I/O)
23-22 GPIO27 HRCAP2 (I) EQEP2S(3) (I/O) SPISTEB (I/O)
25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I)
27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I)
29-28 GPIO30 CANRXA (I) EQEP2I(3) (I/O) EPWM7A (O)
31-30 GPIO31 CANTXA (O) EQEP2S(3) (I/O) EPWM8A (O)
(1) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) The eQEP2 peripheral is not available on the 80-pin PN/PFP package.
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Table 5-66. GPIOB MUX(1)(2)
DEFAULT AT RESET PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O FUNCTION SELECTION 1 SELECTION 2 SELECTION 3
GPBMUX1 REGISTER (GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11)
BITS
1-0 GPIO32 SDAA (I/OD) EPWMSYNCI (I) ADCSOCAO (O)
3-2 GPIO33 SCLA (I/OD) EPWMSYNCO (O) ADCSOCBO (O)
5-4 GPIO34 COMP2OUT (O) Reserved COMP3OUT (O)
7-6 GPIO35 (TDI) Reserved Reserved Reserved
9-8 GPIO36 (TMS) Reserved Reserved Reserved
11-10 GPIO37 (TDO) Reserved Reserved Reserved
13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved
15-14 GPIO39 Reserved Reserved Reserved
17-16 GPIO40(3) EPWM7A (O) SCITXDB (O) Reserved
19-18 GPIO41(3) EPWM7B (O) SCIRXDB (I) Reserved
21-20 GPIO42(3) EPWM8A (O) TZ1 (I) COMP1OUT (O)
23-22 GPIO43(3) EPWM8B (O) TZ2 (I) COMP2OUT (O)
25-24 GPIO44(3) MFSRA (I/O) SCIRXDB (I) EPWM7B (O)
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
GPBMUX2 REGISTER (GPBMUX2 BITS = 00) (GPBMUX2 BITS = 01) (GPBMUX2 BITS = 10) (GPBMUX2 BITS = 11)
BITS
1-0 Reserved Reserved Reserved Reserved
3-2 Reserved Reserved Reserved Reserved
5-4 GPIO50(3) EQEP1A (I) MDXA (O) TZ1 (I)
7-6 GPIO51(3) EQEP1B (I) MDRA (I) TZ2 (I)
9-8 GPIO52(3) EQEP1S (I/O) MCLKXA (I/O) TZ3 (I)
11-10 GPIO53(3) EQEP1I (I/O) MFSXA (I/O) Reserved
13-12 GPIO54(3) SPISIMOA (I/O) EQEP2A (I) HRCAP1 (I)
15-14 GPIO55(3) SPISOMIA (I/O) EQEP2B (I) HRCAP2 (I)
17-16 GPIO56(3) SPICLKA (I/O) EQEP2I (I/O) HRCAP3 (I)
19-18 GPIO57(3) SPISTEA (I/O) EQEP2S (I/O) HRCAP4 (I)
21-20 GPIO58(3) MCLKRA (I/O) SCITXDB (O) EPWM7A (O)
23-22 Reserved Reserved Reserved Reserved
25-24 Reserved Reserved Reserved Reserved
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
(1) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) This pin is not available in the 80-pin PN/PFP package.
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Table 5-67. Analog MUX(1)
DEFAULT AT RESET
PERIPHERAL SELECTION 2 AND
AIOx AND PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I) ADCINA0 (I)
3-2 ADCINA1 (I) ADCINA1 (I)
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
7-6 ADCINA3 (I) ADCINA3 (I)
9-8 AIO4 (I/O) ADCINA4 (I), COMP2A (I)
11-10 ADCINA5 (I) ADCINA5 (I)
13-12 AIO6 (I/O) ADCINA6 (I), COMP3A (I)
15-14 ADCINA7 (I) ADCINA7 (I)
17-16 ADCINB0 (I) ADCINB0 (I)
19-18 ADCINB1 (I) ADCINB1 (I)
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
23-22 ADCINB3 (I) ADCINB3 (I)
25-24 AIO12 (I/O) ADCINB4 (I), COMP2B (I)
27-26 ADCINB5 (I) ADCINB5 (I)
29-28 AIO14 (I/O) ADCINB6 (I), COMP3B (I)
31-30 ADCINB7 (I) ADCINB7 (I)
(1) I = Input, O = Output
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,
after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles
before the input is allowed to change.
• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.
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GPxDAT (read)
Input
Qualification
GPxMUX1/2
High Impedance
Output Control
GPIOx pin
XRS
0 = Input, 1 = Output
Low P ower
Modes Block
GPxDIR (latch)
Peripheral 2 Input
Peripheral 3 Input
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
Peripheral 1 Output Enable
Peripheral 2 Output Enable
Peripheral 3 Output Enable
00
01
10
11
00
01
10
11
00
01
10
11
GPxCTRL
Peripheral 1 Input
N/C
GPxPUD
LPMCR0
Internal
Pullup
GPIOLMPSEL
GPxQSEL1/2
GPxSET
GPxDAT (latch)
GPxCLEAR
GPxTOGGLE
= Default at Reset
PIE
External Interrupt
MUX
Asynchronous
path
Asynchronous path
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
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A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the "Systems
Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number
SPRUH18) for pin-specific variations.
Figure 5-49. GPIO Multiplexing
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GPIO
tr(GPO)
tf(GPO)
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5.23.1 General-Purpose Input/Output (GPIO) Electrical Data/Timing
5.23.1.1 GPIO Output Timing
Table 5-68. General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
tr(GPO) Rise time, GPIO switching low to high All GPIOs 13(1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 13(1) ns
tfGPO Toggling frequency 20 MHz
(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 5-68 are applicable for a 40-pF load on I/O pins.
Figure 5-50. General-Purpose Output Timing
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GPIO Signal
1
Sampling Window
Output From
Qualifier
1 1 1111111110000000 000
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(A)
GPxQSELn = 1,0 (6 samples)
[(SYSCLKOUT cycle * 2 * QUALPRD) * 5 ]
(C)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
(D)
tw(SP)
tw(IQSW)
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5.23.1.2 GPIO Input Timing
Table 5-69. General-Purpose Input Timing Requirements
MIN MAX UNIT
QUALPRD = 0 1tc(SCO) cycles
tw(SP) Sampling period QUALPRD ≠0 2tc(SCO) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
Synchronous mode 2tc(SCO) cycles
tw(GPI) (2) Pulse duration, GPIO low/high With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO) cycles
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active-low signal and VIH to VIH for an active-high signal.
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO
pin will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 5-51. Sampling Mode
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VDDIO
VSS VSS
2 pF
> 1 MS
GPIOxn
XCLKOUT
tw(GPI)
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5.23.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
Figure 5-52. General-Purpose Input Timing
Figure 5-53. Input Resistance Model for a GPIO Pin With an Internal Pull-up
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WAKE INT(A)(B)
XCLKOUT
Address/Data
(internal)
td(WAKE−IDLE)
tw(WAKE−INT)
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5.23.1.4 Low-Power Mode Wakeup Timing
Table 5-70 shows the timing requirements, Table 5-71 shows the switching characteristics, and Figure 5-
54 shows the timing diagram for IDLE mode.
Table 5-70. IDLE Mode Timing Requirements(1)
MIN NOM MAX UNIT
Without input qualifier 2tc(SCO)
tw(WAKE-INT) Pulse duration, external wake-up signal cycles
With input qualifier 5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 5-69.
Table 5-71. IDLE Mode Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Delay time, external wake signal to program execution resume (2) cycles
Without input qualifier 20tc(SCO) cycles
• Wake-up from Flash
– Flash module in active state With input qualifier 20tc(SCO) + tw(IQSW)
td(WAKE-IDLE) Without input qualifier 1050tc(SCO) cycles
• Wake-up from Flash
– Flash module in sleep state With input qualifier 1050tc(SCO) + tw(IQSW)
Without input qualifier 20tc(SCO) cycles
• Wake-up from SARAM With input qualifier 20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 5-69.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake-up) signal involves additional latency.
A. WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5
OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-54. IDLE Entry and Exit Timing
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Table 5-72. STANDBY Mode Timing Requirements
TEST CONDITIONS MIN NOM MAX UNIT
Without input qualification 3tc(OSCCLK)
Pulse duration, external
tw(WAKE-INT) cycles
wake-up signal With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 5-73. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Delay time, IDLE instruction
td(IDLE-XCOL) 32tc(SCO) 45tc(SCO) cycles
executed to XCLKOUT low
Delay time, external wake signal to program execution cycles
resume(1)
Without input qualifier 100tc(SCO)
• Wake up from flash cycles
– Flash module in active With input qualifier 100tc(SCO) + tw(WAKE-INT)
state
td(WAKE-STBY) Without input qualifier 1125tc(SCO)
• Wake up from flash cycles
– Flash module in sleep With input qualifier 1125tc(SCO) + tw(WAKE-INT)
state Without input qualifier 100tc(SCO) cycles
• Wake up from SARAM With input qualifier 100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
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td(IDLE−XCOL)
Wake-up
Signal(H)
X1/X2 or
XCLKIN
XCLKOUT
Flushing Pipeline
(A)
Device
Status STANDBY Normal ExecutionSTANDBY
(G)(B)
(C)
(D)(E)
(F)
tw(WAKE-INT)
td(WAKE-STBY)
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A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the
wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-55. STANDBY Entry and Exit Timing Diagram
Table 5-74. HALT Mode Timing Requirements
MIN NOM MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles
Table 5-75. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
tpPLL lock-up time 1 ms
Delay time, PLL lock to program execution resume 1125tc(SCO) cycles
• Wake up from flash
td(WAKE-HALT) – Flash module in sleep state
35tc(SCO) cycles
• Wake up from SARAM
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td(IDLE−XCOL)
X1/X2 or
XCLKIN
XCLKOUT
HALT HALT
Wake-up Latency
Flushing Pipeline
td(WAKE−HALT
Device
Status
PLL Lock-up Time Normal
Execution
tw(WAKE-GPIO)
GPIOn(I)
Oscillator Start-up Time
(A)
(G)
(C)
(D)(E)
(F)
(B)
(H)
)
tp
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A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the
watchdog alive in HALT mode. This is done by writing to the appropriate bits in the CLKCTL register. After the IDLE
instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be
asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
H. Normal operation resumes.
I. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-56. HALT Wake-Up Using GPIOn
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5.24 Universal Serial Bus (USB)
5.24.1 Universal Serial Bus (USB) Electrical Data/Timing
Table 5-76. USB Input Ports DP and DM Timing Requirements
VCC MIN MAX UNIT
V(CM) Differential input common mode range 0.8 2.5 V
Z(IN) Input impedance 300 kΩ
VCRS Crossover voltage 1.3 2.0 V
VIL Static SE input logic-low level 0.8 V
VIH Static SE input logic-high level 2.0 V
VDI Differential input voltage 0.2 V
Table 5-77. USB Output Ports DP and DM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH D+, D– single-ended USB 2.0 load conditions 2.8 3.6 V
VOL D+, D– single-ended USB 2.0 load conditions 0 0.3 V
Z(DRV) D+, D– impedance 28 44 Ω
trRise time Full speed, differential, CL= 50 pF, 4 20 ns
10%/90%, Rpu on D+
tfFall time Full speed, differential, CL= 50 pF, 4 20 ns
10%/90%, Rpu on D+
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5.25 Flash Timing
Table 5-78. Flash/OTP Endurance for T Temperature Material(1)
ERASE/PROGRAM MIN TYP MAX UNIT
TEMPERATURE
NfFlash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 5-79. Flash/OTP Endurance for S Temperature Material(1)
ERASE/PROGRAM MIN TYP MAX UNIT
TEMPERATURE
NfFlash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 5-80. Flash/OTP Endurance for Q Temperature Material(1)
ERASE/PROGRAM MIN TYP MAX UNIT
TEMPERATURE
NfFlash endurance for the array (write/erase cycles) –40°C to 125°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) –40°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 5-81. Flash Parameters at 90-MHz SYSCLKOUT
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
Program Time 16-Bit Word 50 μs
16K Sector 500 ms
8K Sector 250 ms
4K Sector 125 ms
Erase Time(1) 16K Sector 2 s
8K Sector 2 s
4K Sector 2 s
IDDP (2) VDD current consumption during Erase/Program cycle VREG 80 mA
disabled
IDDIOP (2) VDDIO current consumption during Erase/Program cycle 60
IDDIOP (2) VDDIO current consumption during Erase/Program cycle VREG enabled 120 mA
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off.
Table 5-82. Flash/OTP Access Timing(1)
PARAMETER MIN MAX UNIT
ta(fp) Paged Flash access time 36 ns
ta(fr) Random Flash access time 36 ns
ta(OTP) OTP access time 60 ns
(1) Access time numbers shown in this table are prior to device characterization. Final numbers will be published in the TMS datasheet.
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largeriswhichever1,orinteger,highestnextthetoupround1StateWaitOTP ú
ú
û
ù
ê
ê
ë
é-
÷
÷
ø
ö
ç
ç
è
æ
=t
t
c(SCO)
a(OTP)
largeriswhichever1,orinteger,highestnextthetoupround1StateWaitRandomFlash ú
ú
û
ù
ê
ê
ë
é-
÷
÷
ø
ö
ç
ç
è
æ
=×
t
t
c(SCO)
r)a(f
largeriswhichever1,orinteger,highestnextthetoupround1StateWaitPageFlash ú
ú
û
ù
ê
ê
ë
é-
÷
÷
ø
ö
ç
ç
è
æ
=×
t
t
c(SCO)
p)a(f
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Table 5-83. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT SYSCLKOUT PAGE RANDOM OTP
(MHz) (ns) WAIT-STATE(1) WAIT-STATE(1) WAIT-STATE
90 11.11 3 3 5
80 12.5 2 2 4
70 14.29 2 2 4
60 16.67 2 2 3
55 18.18 1 1 3
50 20 1 1 2
45 22.22 1 1 2
40 25 1 1 2
35 28.57 1 1 2
30 33.33 1 1 1
(1) Page and random wait-state must be ≥1.
The equations to compute the Flash page wait-state and random wait-state in Table 5-83 are as follows:
The equation to compute the OTP wait-state in Table 5-83 is as follows:
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6 Revision History
This data sheet revision history highlights the technical changes made to the SPRS698B device-specific
data sheet to make it an SPRS698C revision.
Scope: The TMS320F2806x devices are now "TMS" devices (fully qualified production devices). The
TMS320F2806xUdevices remain "TMX" devices (experimental device that is not necessarily
representative of the final device's electrical specifications). See Section 3.3 for more
information on device status.
Information/data on TMS320F2806x devices are Production Data. Information/data on
TMS320F2806xUdevices are Advance Information.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of
development. Characteristic data and other specifications are subject to change without notice.
Changed CPU frequency from 80 MHz to 90 MHz.
Changed CPU cycle time from 12.5 ns to 11.11 ns.
Changed ADC MSPS from 3 to 3.46.
Changed ADC conversion time from 325 ns to 289 ns.
Changed ADC clock frequency from 40 MHz to 45 MHz.
Changed ADC cycle time from 25 ns to 22.22 ns.
See table below.
LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS
Global • Changed device status of TMS320F2806x devices from "TMX" to "TMS". Device status of TMS320F2806xU
devices remains "TMX".
• Updated document status of this data manual
• Changed CPU frequency from 80 MHz to 90 MHz. Changed CPU cycle time from 12.5 ns to 11.11 ns.
• Changed ADC MSPS from 3 to 3.46. Changed ADC conversion time from 325 ns to 289 ns. Changed ADC
clock frequency from 40 MHz to 45 MHz. Changed ADC cycle time from 25 ns to 22.22 ns.
Section 1.1 Features:
• Changed "80 MHz (12.5-ns Cycle Time)" to "90 MHz (11.11-ns Cycle Time)"
• Added "Endianness: Little Endian" feature
• Changed "Four High-Resolution Input Capture (HRCAP) Modules" to "Up to 4 High-Resolution Input Capture
(HRCAP) Modules"
• Changed "Two Quadrature Encoder (eQEP) Modules" to "Up to 2 Quadrature Encoder (eQEP) Modules"
• "12-Bit ADC, Dual Sample-and-Hold" feature:
– Changed "Up to 3 MSPS" to "Up to 3.46 MSPS"
Figure 1-1 Functional Block Diagram:
• Changed ESYNCI to EPWMSYNCI
• Changed ESYNCO to EPWMSYNCO
Figure 1-2 Peripheral Blocks:
• Changed "C28x Core (80-MHz)" to "C28x Core (90-MHz)"
• Changed "CLA Core 80-MHz Floating-Point (Accelerator) (DMA-accessible)" to "CLA Core 90-MHz Floating-
Point (Accelerator) (DMA-accessible)"
• Changed "12-bit 3-MSPS Dual-S/H" to "12-bit 3.46-MSPS Dual-S/H"
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LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS
Table 2-1 Hardware Features:
• Changed CPU frequency from 80 MHz to 90 MHz
• Changed Instruction cycle time from 12.5 ns to 11.11 ns
• Modified number of High-resolution capture modules (HRCAP)
• 12-Bit ADC:
– Changed MSPS from 3 to 3.46
– Changed Conversion Time from 325 ns to 289 ns
• Changed Product status of TMS320F2806x devices from TMX to TMS. Product status of TMS320F2806xU
devices remains TMX.
• Updated footnote about device stages
Figure 2-1 28069 Memory Map:
• Changed starting address of "Reserved" space from 0x3D 7C00 to 0x3D 7BFA
Figure 2-2 28068/28067 Memory Map:
• Changed starting address of "Reserved" space from 0x3D 7C00 to 0x3D 7BFA
Figure 2-3 28066 Memory Map:
• Changed starting address of "Reserved" space from 0x3D 7C00 to 0x3D 7BFA
Figure 2-4 28065 Memory Map:
• Changed starting address of "Reserved" space from 0x3D 7C00 to 0x3D 7BFA
Figure 2-5 28064 Memory Map:
• Changed starting address of "Reserved" space from 0x3D 7C00 to 0x3D 7BFA
Figure 2-6 28063 Memory Map:
• Changed starting address of "Reserved" space from 0x3D 7C00 to 0x3D 7BFA
Figure 2-7 28062 Memory Map:
• Changed starting address of "Reserved" space from 0x3D 7C00 to 0x3D 7BFA
Table 2-2 Addresses of Flash Sectors in F28069/28068/28067/28066:
• Changed address range of Sector A from "0x3F 4000 – 0x3F 7F7F" to "0x3F 4000 – 0x3F 7FF5"
• Removed address range 0x3F 7F80 – 0x3F 7FF5
Table 2-3 Addresses of Flash Sectors in F28065/28064/28063/28062:
• Changed address range of Sector A from "0x3F 6000 – 0x3F 7F7F" to "0x3F 6000 – 0x3F 7FF5"
• Removed address range 0x3F 7F80 – 0x3F 7FF5
Revised NOTE that is under Table 2-2 and Table 2-3
Removed "Impact of Using the Code Security Module" table (Table 3-4 in SPRS698B)
Table 2-5 Terminal Functions:
• PZ/PZP pin #78, PN/PFP pin #62: Updated "I/O/Z" column of USB0DP
• PZ/PZP pin #77, PN/PFP pin #61: Updated "I/O/Z" column of USB0DM
Section 2.5.7 Flash:
• Changed OTP memory address range from "0x3D 7800 – 0x3D 7BFF" to "0x3D 7800 – 0x3D 7BF9"
Section 2.5.21 Control Peripherals:
• ADC:
– Changed "It has up to 13 single-ended channels pinned out, ..." to "It has up to 16 single-ended channels
pinned out, ..."
Table 2-12 Device Emulation Registers:
• REVID: Changed DESCRIPTION from "0x0001 - Silicon Rev. A - TMX" to "0x0001 - Silicon Rev. A - TMS"
Section 2.9.4 USB and HRCAP PLL Module (PLL2):
• Updated "INTOSC1 (Internal Zero-pin Oscillator 1)" bulleted item — INTOSC1 cannot be used as a clock
source for the USB
Figure 3-1 Device Nomenclature:
• Changed PREFIX example from "TMX" to "TMS"
Section 4.2 Recommended Operating Conditions:
• Device clock frequency (system clock):
– Changed MAX value from 80 MHz to 90 MHz
• Added Ambient temperature, TAfor "Q version (Q100 qualification)"
• Junction temperature, TJ: Changed MAX TJfor "Q version (Q100 qualification)" from 125ºC to 150ºC
• Removed footnote about TA(Ambient temperature)
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LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS
Section 4.3 Electrical Characteristics:
• IIL, Pin with pullup enabled, TEST CONDITIONS: Changed "All GPIO/AIO" to "All GPIO"
Table 5-1 Changed table title from "2806x Clock Table and Nomenclature (80-MHz Devices)" to "2806x Clock Table and
Nomenclature (90-MHz Devices)"
Table 5-1 2806x Clock Table and Nomenclature (90-MHz Devices):
• SYSCLKOUT:
– tc(SCO), Cycle time: Changed MIN value from 12.5 ns to 11.11 ns
– Frequency: Changed MAX value from 80 MHz to 90 MHz
• LSPCLK:
– tc(LCO), Cycle time:
• Changed MIN value from 12.5 ns to 11.11 ns
• Changed TYP value from 66.67 ns to 44.4 ns
– Frequency:
• Changed TYP value from 15 MHz to 22.5 MHz
• Changed MAX value from 80 MHz to 90 MHz
• ADC clock:
– tc(ADCCLK), Cycle time: Changed MIN value from 25 ns to 22.22 ns
– Frequency: Changed MAX value from 40 MHz to 45 MHz
• Changed "This is the default reset value if SYSCLKOUT = 80 MHz" footnote to "This is the default reset value
if SYSCLKOUT = 90 MHz"
Section 5.5 Power Sequencing:
• Changed "However, it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to
any pin prior to powering up the device" to "No voltage larger than a diode drop (0.7 V) above VDDIO should
be applied to any digital pin (for analog pins, it is 0.7 V above VDDA) prior to powering up the device.
Furthermore, VDDIO and VDDA should always be within 0.3 V of each other."
Figure 5-4 Power-on Reset:
• Updated "I/O Pins" waveform
• Added footnote about internal pullup/pulldown
Table 5-9 Changed title from "TMS320F2806x Current Consumption at 80-MHz SYSCLKOUT" to "TMS320F2806x Current
Consumption at 90-MHz SYSCLKOUT"
158 Revision History Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS
Table 5-9 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT:
• TEST CONDITIONS:
– Changed "All PWM pins are toggled at 60 kHz" to "All PWM pins are toggled at 90 kHz"
– Changed "Code is running out of flash with 2wait-states" to "Code is running out of flash with 3wait-
states"
• Operational (Flash) – VREG ENABLED:
– IDDIO: Changed TYP value from 160 mA to 185 mA
– IDDIO: Added MAX value of 245 mA
– IDDA: Added MAX value of 22 mA
– IDD3VFL: Changed TYP value from 25 mA to 35 mA
– IDD3VFL: Added MAX value of 40 mA
• Operational (Flash) – VREG DISABLED:
– IDD: Changed TYP value from 130 mA to 165 mA
– IDD: Added MAX value of 220 mA
– IDDIO: Changed TYP value from 7 mA to 15 mA
– IDDIO: Added MAX value of 20 mA
– IDDA: Added MAX value of 22 mA
– IDD3VFL: Changed TYP value from 25 mA to 35 mA
– IDD3VFL: Added MAX value of 40 mA
• IDLE – VREG ENABLED:
– IDDIO: Added MAX value of 27 mA
– IDDA: Changed TYP value from 100 µA to 15 µA
– IDDA: Added MAX value of 25 µA
– IDD3VFL: Changed TYP value from 10 µA to 5 µA
– IDD3VFL: Added MAX value of 10 µA
• IDLE – VREG DISABLED:
– IDD: Changed TYP value from 18 mA to 21 mA
– IDD: Added MAX value of 26 mA
– IDDIO: Changed TYP value from 400 µA to 120 µA
– IDDIO: Added MAX value of 400 µA
– IDDA: Changed TYP value from 100 µA to 15 µA
– IDDA: Added MAX value of 25 µA
– IDD3VFL: Changed TYP value from 10 µA to 5 µA
– IDD3VFL: Added MAX value of 10 µA
•(Continued in next row)
Copyright © 2010–2012, Texas Instruments Incorporated Revision History 159
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS
Table 5-9 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT:
(Continued) • STANDBY – VREG ENABLED:
– IDDIO: Changed TYP value from 8 mA to 9 mA
– IDDIO: Added MAX value of 11 mA
– IDDA: Changed TYP value from 100 µA to 15 µA
– IDDA: Added MAX value of 25 µA
– IDD3VFL: Changed TYP value from 10 µA to 5 µA
– IDD3VFL: Added MAX value of 10 µA
• STANDBY – VREG DISABLED:
– IDD: Changed TYP value from 6 mA to 8 mA
– IDD: Added MAX value of 10 mA
– IDDIO: Changed TYP value from 400 µA to 120 µA
– IDDIO: Added MAX value of 400 µA
– IDDA: Changed TYP value from 100 µA to 15 µA
– IDDA: Added MAX value of 25 µA
– IDD3VFL: Changed TYP value from 10 µA to 5 µA
– IDD3VFL: Added MAX value of 10 µA
• HALT – VREG ENABLED:
– IDDIO: Changed TYP value from 3 mA to 75 µA
– IDDA: Changed TYP value from 100 µA to 15 µA
– IDDA: Added MAX value of 25 µA
– IDD3VFL: Changed TYP value from 10 µA to 5 µA
– IDD3VFL: Added MAX value of 10 µA
• HALT – VREG DISABLED:
– IDD: Changed TYP value from 2 mA to 25 µA
– IDDIO: Changed TYP value from 120 µA to 40 µA
– IDDA: Changed TYP value from 100 µA to 15 µA
– IDDA: Added MAX value of 25 µA
– IDD3VFL: Changed TYP value from 10 µA to 5 µA
– IDD3VFL: Added MAX value of 10 µA
Table 5-10 Changed title from "Typical Current Consumption by Various Peripherals (at 80 MHz)" to "Typical Current
Consumption by Various Peripherals (at 90 MHz)"
Figure 5-7 Updated "Typical Operational Current Versus Frequency" graph
Figure 5-8 Updated "Typical Operational Power Versus Frequency" graph
Table 5-18 ADC Configuration and Control Registers:
• Added ADCCTL2
• Changed "ADCINTSEL1AND2" to "INTSEL1N2"
• Changed "ADCINTSEL3AND4" to "INTSEL3N4"
• Changed "ADCINTSEL5AND6" to "INTSEL5N6"
• Changed "ADCINTSEL7AND8" to "INTSEL7N8"
• Changed "ADCINTSEL9AND10" to "INTSEL9N10"
• Changed "ADCSOCPRIORITYCTL" to "SOCPRICTL"
• Added COMPHYSTCTL
160 Revision History Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS
Table 5-21 ADC Electrical Characteristics:
• ADC clock:
– Changed "80-MHz device" to "90-MHz device"
– Changed MAX value from 40 MHz to 45 MHz
• INL (Integral nonlinearity):
– Removed "40-MHz clock (3 MSPS)"
– Added MIN value of –4 LSB
– Removed TYP value of ±2 LSB
– Added MAX value of 4 LSB
• DNL (Differential nonlinearity):
– Appended "no missing codes" to "DNL (Differential nonlinearity)"
– Added MIN value of –1 LSB
– Removed TYP value of ±1 LSB
– Added MAX value of 1.5 LSB
• Offset error:
– Changed "Executing Device_Cal function" to "Executing a single self-recalibration"
– Executing a single self-recalibration:
• Added MIN value of –20 LSB
• Removed TYP value of 10 LSB
• Added MAX value of 20 LSB
• Added footnote referencing SPRZ342
– Executing periodic self-recalibration:
• Added MIN value of –4 LSB
• Removed TYP value of 10 LSB
• Added MAX value of 4 LSB
• Overall gain error with internal reference:
– Added MIN value of –60 LSB
– Removed TYP value of 10 LSB
– Added MAX value of 60 LSB
• Overall gain error with external reference:
– Added MIN value of –40 LSB
– Removed TYP value of 10 LSB
– Added MAX value of 40 LSB
• Channel-to-channel offset variation:
– Added MIN value of –4 LSB
– Removed TYP value of ±4 LSB
– Added MAX value of 4 LSB
• Channel-to-channel gain variation:
– Added MIN value of –4 LSB
– Removed TYP value of ±4 LSB
– Added MAX value of 4 LSB
• Added TYP VREFLO value of –100 µA
• Added TYP VREFHI value of 100 µA
Table 5-22 ADC Power Modes:
• Changed ADCPWRDN to ADCPWDN
• Mode A – Operating Mode:
– Changed IDDA from 13 mA to 16 mA
Figure 5-22 Updated "Timing Example for Simultaneous Mode / Early Interrupt Pulse" figure
Table 5-25 Comparator Control Registers:
• Added DACCTL
• DACVAL: Changed EALLOW PROTECTED value from "Yes" to "No"
• Added RAMPMAXREF_ACTIVE
• Added RAMPMAXREF_SHDW
• Added RAMPDECVAL_ACTIVE
• Added RAMPDECVAL_SHDW
• Added RAMPSTS
Copyright © 2010–2012, Texas Instruments Incorporated Revision History 161
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS
Section 5.14.1.2 McBSP as SPI Master or Slave Timing:
• Changed "With maximum LSPCLK speed of 80 MHz, CLKX maximum frequency is LSPCLK/16 , that is
5 MHz and P = 12.5 ns" to "With maximum LSPCLK speed of 90 MHz, CLKX maximum frequency is
LSPCLK/16 , that is 5.625 MHz and P = 11.11 ns"
Table 5-45 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1):
• Added parameter M55, td(CLKXH-DXV), Delay time, CLKX high to DX valid
Section 5.15 Enhanced Controller Area Network (eCAN) Module:
• Changed NOTE from "For a SYSCLKOUT of 80 MHz, the smallest bit rate possible is 6.25 kbps" to "For a
SYSCLKOUT of 90 MHz, the smallest bit rate possible is 6.25 kbps"
Section 5.20 Changed section title from "High-Resolution Capture (HRCAP) Module" to "High-Resolution Capture Modules
(HRCAP1/2/3/4)"
Section 5.20 High-Resolution Capture Modules (HRCAP1/2/3/4):
• Added "The device contains up to four high-resolution capture (HRCAP) modules" sentence
Table 5-59 HRCAP Registers:
• Added addresses of HRCAP3 registers
• Added addresses of HRCAP4 registers
Table 5-62 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements:
• TEST CONDITIONS: Changed all five instances of "Asynchronous/synchronous" to "Synchronous"
Table 5-64 GPIO Registers:
• Added GPBQSEL2 at 0x6F94
• Added GPBMUX2 at 0x6F98
Table 5-81 Changed title from "Flash Parameters at 80-MHz SYSCLKOUT" to "Flash Parameters at 90-MHz SYSCLKOUT"
Table 5-81 Flash Parameters at 90-MHz SYSCLKOUT:
• Added Program Time for 16K Sector
• Added Erase Time for 16K Sector
• Added footnote about flash memory being in an erased state when the device is shipped
Table 5-83 Minimum Required Flash/OTP Wait-States at Different Frequencies:
• Added values for 90-MHz SYSCLKOUT
162 Revision History Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
7 Mechanical Packaging and Orderable Information
7.1 Thermal Data
Table 7-1 through Table 7-4 show the thermal data. See Section 7.1.1 for more information on thermal
design considerations.
Table 7-1. Thermal Model 100-Pin PZP Results
AIR FLOW
PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm
θJA [°C/W] High k PCB 24.4 15.1 13.9 12.4
ΨJT [°C/W] 0.3 0.4 0.4 0.5
ΨJB 4.5 4.2 4.2 4.2
θJC 9.4
θJB 4.4
Table 7-2. Thermal Model 100-Pin PZ Results
AIR FLOW
PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm
θJA [°C/W] High k PCB 42.2 32.4 30.9 28.7
ΨJT [°C/W] 0.4 0.6 0.7 0.9
ΨJB 19.1 18.2 17.9 14.1
θJC 7.2
θJB 19.6
Table 7-3. Thermal Model 80-Pin PFP Results
AIR FLOW
PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm
θJA [°C/W] High k PCB 25.8 16.3 15.2 13.6
ΨJT [°C/W] 0.3 0.4 0.4 0.5
ΨJB 4.6 4.4 4.3 4.3
θJC 9.4
θJB 4.6
Table 7-4. Thermal Model 80-Pin PN Results
AIR FLOW
PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm
θJA [°C/W] High k PCB 41.1 31.2 29.7 27.5
ΨJT [°C/W] 0.4 0.6 0.7 0.9
ΨJB 15.3 14.6 14.4 14.1
θJC 7.9
θJB 15.6
Copyright © 2010–2012, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 163
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
7.1.1 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require
additional thermal enhancements. Ambient temperature (TA) varies with the end application and product
design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the
ambient temperature. Hence, care should be taken to keep TJwithin the specified limits. Tcase should be
measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of
the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature
number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number
SPRA963) help to understand the thermal metrics and definitions.
7.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
164 Mechanical Packaging and Orderable Information Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PN (S-PQFP-G80) PLASTIC QUAD FLATPACK
4040135 /B 11/96
0,17
0,27
0,13 NOM
40
21
0,25
0,45
0,75
0,05 MIN
Seating Plane
Gage Plane
41
60
61
80
20
SQ
SQ
1
13,80
14,20
12,20
9,50 TYP
11,80
1,45
1,35
1,60 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 11/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
PACKAGE OPTION ADDENDUM
www.ti.com 7-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320F28062PFPQ PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28062PFPS ACTIVE HTQFP PFP 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28062PNT ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28062PZPQ PREVIEW HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28062PZPS ACTIVE HTQFP PZP 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28062PZT ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28062UPFPS PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28062UPNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28062UPZPS ACTIVE HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28062UPZT ACTIVE LQFP PZ 100 90 TBD Call TI Call TI
TMS320F28063PFPQ PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28063PFPS ACTIVE HTQFP PFP 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28063PNT ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28063PZPQ PREVIEW HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28063PZPS ACTIVE HTQFP PZP 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28063PZT ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28063UPFPS ACTIVE HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28063UPNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28063UPZPS ACTIVE HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28063UPZT PREVIEW LQFP PZ 100 TBD Call TI Call TI
TMS320F28064PFPQ ACTIVE HTQFP PFP 80 TBD Call TI Call TI
TMS320F28064PFPS ACTIVE HTQFP PFP 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 7-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320F28064PNT ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28064PZPQ PREVIEW HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28064PZPS ACTIVE HTQFP PZP 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28064PZT ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28064UPFPS ACTIVE HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28064UPNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28064UPZPS ACTIVE HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28064UPZT ACTIVE LQFP PZ 100 90 TBD Call TI Call TI
TMS320F28065PFPQ PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28065PFPS ACTIVE HTQFP PFP 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28065PNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28065PZPQ PREVIEW HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28065PZPS ACTIVE HTQFP PZP 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28065PZT ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28065UPFPS PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28065UPNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28065UPZPS ACTIVE HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28065UPZT ACTIVE LQFP PZ 100 90 TBD Call TI Call TI
TMS320F28066PFPQ PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28066PFPS ACTIVE HTQFP PFP 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28066PNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28066PZPQ PREVIEW HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28066PZPS ACTIVE HTQFP PZP 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28066PZT ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 7-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320F28066UPFPS ACTIVE HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28066UPNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28066UPZPS ACTIVE HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28066UPZT ACTIVE LQFP PZ 100 90 TBD Call TI Call TI
TMS320F28067PFPQ PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28067PFPS ACTIVE HTQFP PFP 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28067PNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28067PZPQ PREVIEW HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28067PZPS ACTIVE HTQFP PZP 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28067PZT ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28067UPFPS ACTIVE HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28067UPNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28067UPZPS ACTIVE HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28067UPZT ACTIVE LQFP PZ 100 90 TBD Call TI Call TI
TMS320F28068PFPQ PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28068PFPS ACTIVE HTQFP PFP 80 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28068PNT ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28068PZPQ PREVIEW HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28068PZPS ACTIVE HTQFP PZP 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28068PZT ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28068UPFPS ACTIVE HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28068UPNT ACTIVE LQFP PN 80 119 TBD Call TI Call TI
TMS320F28068UPZPS ACTIVE HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28068UPZT ACTIVE LQFP PZ 100 90 TBD Call TI Call TI
TMS320F28069PFPQ PREVIEW HTQFP PFP 80 1000 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 7-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320F28069PFPS ACTIVE HTQFP PFP 80 96 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28069PNT ACTIVE LQFP PN 80 119 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28069PZPQ ACTIVE HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28069PZPS ACTIVE HTQFP PZP 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28069PZT ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320F28069UPFPS ACTIVE HTQFP PFP 80 1000 TBD Call TI Call TI
TMS320F28069UPNT PREVIEW LQFP PN 80 119 TBD Call TI Call TI
TMS320F28069UPZPS PREVIEW HTQFP PZP 100 1000 TBD Call TI Call TI
TMS320F28069UPZT PREVIEW LQFP PZ 100 90 TBD Call TI Call TI
TMX320F28069PNA ACTIVE LQFP PN 80 1 TBD Call TI Call TI
TMX320F28069PZA ACTIVE LQFP PZ 100 TBD Call TI Call TI
TMX320F28069UPFPA ACTIVE HTQFP PFP 80 1 TBD Call TI Call TI
TMX320F28069UPZPA ACTIVE HTQFP PZP 100 1 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Aug-2012
Addendum-Page 5
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