TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Piccolo Microcontrollers
Check for Samples: TMS320F28069,TMS320F28068,TMS320F28067,TMS320F28066,
TMS320F28065,TMS320F28064,TMS320F28063,TMS320F28062
1 TMS320F2806x ( Piccolo™) MCUs
1.1 Features
123
• High-Efficiency 32-Bit CPU (TMS320C28x™) • Clocking
– 90 MHz (11.11-ns Cycle Time) – Two Internal Zero-pin Oscillators
– 16 x 16 and 32 x 32 MAC Operations – On-Chip Crystal Oscillator/External Clock
Input
– 16 x 16 Dual MAC – Dynamic PLL Ratio Changes Supported
– Harvard Bus Architecture – Watchdog Timer Module
– Atomic Operations – Missing Clock Detection Circuitry
– Fast Interrupt Response and Processing • Peripheral Interrupt Expansion (PIE) Block That
– Unified Memory Programming Model Supports All Peripheral Interrupts
– Code-Efficient (in C/C++ and Assembly) • Three 32-Bit CPU Timers
• Floating-Point Unit • Advanced Control Peripherals
– Native Single-Precision Floating-Point • Up to 8 Enhanced Pulse Width Modulator
Operations (ePWM) Modules
• Programmable Control Law Accelerator (CLA) – 16 PWM Channels Total (8 HRPWM-Capable)
– 32-Bit Floating-Point Math Accelerator – Independent 16-Bit Timer in Each Module
– Executes Code Independently of the Main • Three Input Capture (eCAP) Modules
CPU • Up to 4 High-Resolution Input Capture (HRCAP)
• Viterbi, Complex Math, CRC Unit (VCU) Modules
– Extends C28x™ Instruction Set to Support • Up to 2 Quadrature Encoder (eQEP) Modules
Complex Multiply, Viterbi Operations, and
Cyclic Redundency Check (CRC) • 12-Bit ADC, Dual Sample-and-Hold
• Embedded Memory – Up to 3.46 MSPS
– Up to 256KB Flash – Up to 16 Channels
– Up to 100KB RAM • On-Chip Temperature Sensor
– 2KB OTP ROM • 128-Bit Security Key/Lock
• 6-Channel DMA – Protects Secure Memory Blocks
• Low Device and System Cost – Prevents Firmware Reverse Engineering
– Single 3.3-V Supply • Serial Port Peripherals
– No Power Sequencing Requirement – Two Serial Communications Interface (SCI)
[UART] Modules
– Integrated Power-on Reset and Brown-out
Reset – Two Serial Peripheral Interface (SPI)
Modules
– Low-Power Operating Modes – One Inter-Integrated-Circuit (I2C) Bus
– No Analog Support Pin – One Multichannel Buffered Serial Port
• Endianness: Little Endian (McBSP) Bus
– One Enhanced Controller Area Network
(eCAN)
– One Universal Serial Bus (USB) 2.0 Module
(Available on TMS320F2806xU Devices Only)
• Full-Speed Device Mode
• Full-/Low-Speed Host Mode
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Piccolo, PowerPAD, C28x, TMS320C2000, C2000, ControlSUITE, Code Composer Studio, XDS510, XDS560, TMS320C28x,
TMS320C54x, TMS320C55x are trademarks of Texas Instruments.
3All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information Copyright © 2010–2012, Texas Instruments Incorporated
current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include
testing of all parameters.
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
• Up to 54 Individually Programmable, • 2806x Packages
Multiplexed GPIO Pins With Input Filtering – 80-Pin PFP and 100-Pin PZP PowerPAD™
• Advanced Emulation Features Thermally Enhanced Thin Quad Flatpacks
(HTQFPs)
– Analysis and Breakpoint Functions – 80-Pin PN and 100-Pin PZ Low-Profile Quad
– Real-Time Debug via Hardware Flatpacks (LQFPs)
1.2 Description
The F2806x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law
Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family
is code-compatible with previous C28x-based code, as well as providing a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the
HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal
10-bit references have been added and can be routed directly to control the PWM outputs. The ADC
converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The
ADC interface has been optimized for low overhead/latency.
2TMS320F2806x ( Piccolo™) MCUs Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
CLA Bus
GPIO Mux
DMA Bus
DMA Bus
16-bit Peripheral Bus 32-bit Peripheral Bus
(CLA accessible)
32-bit Peripheral
Bus
32-bit Peripheral
Bus
32-bit
Peripheral Bus
(CLA accessible)
SCITXDx
SCIRXDx
SPISIMOx
SPISOMIx
SPICLKx
SPISTEx
SDAx
SCLx
TZx
EPWMxA
EPWMxB
MFSRA
MDRA
MCLKRA
MFSXA
MDXA
MCLKXA
ECAPx
EQEPxA
EQEPxB
EQEPxI
EQEPxS
HRCAPx
CANRXx
CANTXx
SCI-A/B
(4L FIFO)
SPI-A/B
(4L FIFO) I2C-A
(4L FIFO)
ePWM1 to ePWM8
HRPWM (8ch) McBSP-A eCAP-
1/2/3
eQEP-
1/2
HRCAP-
1/2/3/4
eCAN-A
(32-mbox)
Memory Bus
A7:0
B7:0
Memory Bus
Memory Bus
DMA Bus
CLA Bus
DMA Bus
GPIO Mux
AIO Mux
32-bit Peripheral Bus
GPIO
Mux
GPIO
Mux
ADC
0-wait
Result
Regs
ADC
COMP
+
DAC
COMP1OUT
COMP2OUT
COMP3OUT
COMP1A
COMP2A
COMP3A
COMP1B
COMP2B
COMP3B
Boot-ROM
(32Kx16)
(0-wait,
Non-Secure)
CLA +
Message
RAMs
DMA
6-ch
C28x 32-bit CPU
FPU
VCU
OSC1, OSC2,
Ext, PLLs,
LPM, WD,
CPU Timers
0/1/2. PIE
TRST
TCK, TDI, TMS
TDO
XCLKIN
LPM Wakeup
3 Ext. Interrupts
X1
X2
XRS
PSWD
M0 SARAM (1Kx16)
(0-wait, Non-Secure)
M1 SARAM (1Kx16)
(0-wait, Non-Secure)
L5 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM0
L6 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM1
L7 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM2
L8 DPSARAM (8Kx16)
(0-wait, Non-Secure)
DMA RAM3
L0 DPSARAM (2Kx16)
(0-wait, Secure)
CLA Data RAM2
L1 DPSARAM (1Kx16)
(0-wait, Secure)
CLA Data RAM0
L2 DPSARAM (1Kx16)
(0-wait, Secure)
CLA Data RAM1
L3 DPSARAM (4Kx16)
(0-wait, Secure)
CLA Program RAM
L4 SARAM (8Kx16)
(0-wait, Secure)
Code
Security
Module
(CSM)
OTP 1Kx16
Secure
FLASH
64K/128Kx16
8 equal sectors
Secure
PUMP
OTP/Flash
Wrapper
32-bit Peripheral
Bus
USB0DP
USB0DM
USB-0
EPWMSYNCI
EPWMSYNCO
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
1.3 Functional Block Diagram
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
Copyright © 2010–2012, Texas Instruments Incorporated TMS320F2806x ( Piccolo™) MCUs 3
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10-bit
DAC
Analog
Comparators
CMP1-Out
CMP2-Out
CMP3-Out
Trip Zone
Temp
Sensor
ADC
(DMA-
accessible)
12-bit
3.46-MSPS
Dual-S/H
SOC-
based
VREF
CLA Core
90-MHz Floating-Point
(Accelerator)
(DMA-accessible)
10-bit
DAC
10-bit
DAC
A0
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A1
6
eQEP x 2
HRCAP x 4
eCAP x 3
System
Vreg
Int-Osc-1
POR/BOR
Int-Osc-2
On-chip Osc
WD
PLL
CLKSEL
Timers 32-bit
Timer-0
Timer-1
Timer-2
GPIO
Control
COMMS
X1
X2
VREFLO
VREFHI
C28x
Core
(90-MHz)
FPU
VCU
Flash Memory
RAM
RAM
(Dual-Access)
eQEP
8
HRCAP
4
eCAP
3
4
8
2
2
6
PWM-1A
PWM-1B
PWM-2A
PWM-2B
PWM-3A
PWM-3B
PWM-4A
PWM-4B
PWM-5A
PWM-5B
PWM-6A
PWM-6B
PWM-7A
PWM-7B
PWM-8A
PWM-8B
TZ1
TZ2
TZ3
CMP1-out
CMP2-out
CMP3-out
PWM1
(DMA-accessible)
PWM5
(DMA-accessible)
PWM8
(DMA-accessible)
PWM7
(DMA-accessible)
PWM6
(DMA-accessible)
PWM4
(DMA-accessible)
PWM3
(DMA-accessible)
PWM2
(DMA-accessible)
UART x 2
SPI x 2
I2C
CAN
McBSP
(DMA-accessible)
2
USB
(DMA-accessible)
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
1.4 System Device Diagram
Figure 1-2. Peripheral Blocks
4TMS320F2806x ( Piccolo™) MCUs Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
1 TMS320F2806x ( Piccolo™) MCUs .................. 15.4 Clock Requirements and Characteristics ........... 65
1.1 Features ............................................. 15.5 Power Sequencing ................................. 66
1.2 Description ........................................... 25.6 Current Consumption ............................... 69
5.7 Emulator Connection Without Signal Buffering for
1.3 Functional Block Diagram ........................... 3the MCU ............................................ 72
1.4 System Device Diagram ............................. 45.8 Interrupts ............................................ 73
2 Device Overview ........................................ 65.9 Control Law Accelerator (CLA) Overview .......... 78
2.1 Device Characteristics ............................... 65.10 Analog Block ........................................ 81
2.2 Memory Maps ........................................ 95.11 Detailed Descriptions ............................... 95
2.3 Pin Assignments .................................... 19 5.12 Serial Peripheral Interface (SPI) Module ........... 96
2.4 Signal Descriptions ................................. 21 5.13 Serial Communications Interface (SCI) Module .. 105
2.5 Brief Descriptions ................................... 30 5.14 Multichannel Buffered Serial Port (McBSP) Module
2.6 Register Map ....................................... 40 ..................................................... 108
2.7 Device Emulation Registers ........................ 42 5.15 Enhanced Controller Area Network (eCAN) Module
2.8 VREG/BOR/POR ................................... 44 ..................................................... 118
2.9 System Control ..................................... 46 5.16 Inter-Integrated Circuit (I2C) ...................... 122
2.10 Low-power Modes Block ........................... 55 5.17 Enhanced Pulse Width Modulator (ePWM) Modules
(ePWM1/2/3/4/5/6/7/8) ............................ 125
3 Device and Documentation Support ............... 56 5.18 High-Resolution PWM (HRPWM) ................. 132
3.1 Getting Started ..................................... 56 5.19 Enhanced Capture Module (eCAP1) .............. 133
3.2 Development Support .............................. 56 5.20 High-Resolution Capture Modules (HRCAP1/2/3/4)
3.3 Device and Development Support Tool ..................................................... 135
Nomenclature ....................................... 56 5.21 Enhanced Quadrature Encoder Modules (eQEP1/2)
3.4 Documentation Support ............................ 58 ..................................................... 137
3.5 Community Resources ............................. 59 5.22 JTAG Port ......................................... 140
4 Device Operating Conditions ....................... 60 5.23 General-Purpose Input/Output (GPIO) MUX ...... 141
4.1 Absolute Maximum Ratings ........................ 60 5.24 Universal Serial Bus (USB) ....................... 153
4.2 Recommended Operating Conditions .............. 60 5.25 Flash Timing ...................................... 154
4.3 Electrical Characteristics ........................... 61 6 Revision History ..................................... 156
5 Peripheral and Electrical Specifications .......... 62 7 Mechanical Packaging and Orderable
5.1 Parameter Information .............................. 62 Information ............................................ 163
5.2 Test Load Circuit ................................... 62 7.1 Thermal Data ...................................... 163
5.3 Device Clock Table ................................. 63 7.2 Packaging Information ............................ 164
Copyright © 2010–2012, Texas Instruments Incorporated Contents 5
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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2 Device Overview
2.1 Device Characteristics
Table 2-1 lists the features of the TMS320F2806x devices.
6Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Table 2-1. Hardware Features
28069, 28068, 28067, 28066, 28065, 28064, 28063, 28062,
FEATURE TYPE(1) 28069U(2) 28068U(2) 28067U(2) 28066U(2) 28065U(2) 28064U(2) 28063U(2) 28062U(2)
(90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz)
Package Type 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin
(PFP and PZP are HTQFPs. PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP
PN and PZ are LQFPs.)
Instruction cycle – 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns
Floating-Point Unit (FPU) Yes Yes Yes Yes Yes Yes Yes Yes
Viterbi, Complex Math, CRC Unit (VCU) Yes Yes No No Yes Yes No No
Control Law Accelerator (CLA) 0 Yes No No No Yes No No No
6-Channel DMA 0 Yes Yes Yes Yes Yes Yes Yes Yes
On-chip Flash (16-bit word) – 128K 128K 128K 128K 64K 64K 64K 64K
On-chip SARAM (16-bit word) – 50K 50K 50K 34K 50K 50K 34K 26K
Code security for on-chip – Yes Yes Yes Yes Yes Yes Yes Yes
flash/SARAM/OTP blocks
Boot ROM (32K x 16) – Yes Yes Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM – 1K 1K 1K 1K 1K 1K 1K 1K
(16-bit word)
ePWM outputs 1 19 15 19 15 19 15 19 15 19 15 19 15 19 15 19 15
High-resolution ePWM Channels 1 8 6 8 6 8 6 8 6 8 6 8 6 8 6 8 6
eCAP inputs 0 3 3 3 3 3 3 3 3
High-resolution capture modules 04141414141414141
(HRCAP)
eQEP modules 0 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
Watchdog timer – Yes Yes Yes Yes Yes Yes Yes Yes
MSPS 3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46
Conversion Time 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns
12-Bit ADC Channels 3 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12
Temperature Sensor Yes Yes Yes Yes Yes Yes Yes Yes
Dual Sample-and-Hold Yes Yes Yes Yes Yes Yes Yes Yes
32-Bit CPU timers – 3 3 3 3 3 3 3 3
Comparators with Integrated DACs 0 3 3 3 3 3 3 3 3
Inter-integrated circuit (I2C) 0 1 1 1 1 1 1 1 1
Multichannel Buffered Serial Port 1 1 1 1 1 1 1 1 1
(McBSP)
Enhanced Controller Area Network 0 1 1 1 1 1 1 1 1
(eCAN)
Serial Peripheral Interface (SPI) 1 2 2 2 2 2 2 2 2
Serial Communications Interface (SCI) 0 2 2 2 2 2 2 2 2
Universal Serial Bus (USB) 0 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the
peripheral reference guides.
(2) USB is present only in TMS320F2806xUdevices.
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 7
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Table 2-1. Hardware Features (continued)
28069, 28068, 28067, 28066, 28065, 28064, 28063, 28062,
FEATURE TYPE(1) 28069U(2) 28068U(2) 28067U(2) 28066U(2) 28065U(2) 28064U(2) 28063U(2) 28062U(2)
(90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz) (90 MHz)
Package Type 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin 100-Pin 80-Pin
(PFP and PZP are HTQFPs. PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP PZ/PZP PN/PFP
PN and PZ are LQFPs.)
2-pin Oscillator 1 1 1 1 1 1 1 1
0-pin Oscillator 2 2 2 2 2 2 2 2
GPIO – 54 40 54 40 54 40 54 40 54 40 54 40 54 40 54 40
I/O pins
(shared) AIO – 6 6 6 6 6 6 6 6
External interrupts – 3 3 3 3 3 3 3 3
Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
T: –40°C to 105°C – PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN
Temperature S: –40°C to 125°C – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP
options Q: –40°C to 125°C(3) – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP
TMS (28069) TMS (28068) TMS (28067) TMS (28066) TMS (28065) TMS (28064) TMS (28063) TMS (28062)
Product status(4) –TMX (28069U)TMX (28068U)TMX (28067U)TMX (28066U)TMX (28065U)TMX (28064U)TMX (28063U)TMX (28062U)
(3) "Q" refers to Q100 qualification for automotive applications.
(4) The "TMS" product status denotes a fully qualified production device. The "TMX" product status denotes an experimental device that is not necessarily representative of the final device's
electrical specifications. See Section 3.3, Device and Development Support Tool Nomenclature, for descriptions of device stages.
8Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
2.2 Memory Maps
In Figure 2-1 through Figure 2-7, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps
are restricted to data memory only. A user program cannot access these memory maps in program
space.
•Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline
order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
• Locations 0x3D 7C80–0x3D 7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.
• All devices with USB have 2K x16 RAM from 0x40000 to 0x40800. When the clock to the USB module
is enabled, this RAM is connected to the USB controller and acts as the FIFO RAM. When the clock to
the USB module is disabled, this RAM is remapped to the CPU-accessible address space and can be
used as general-purpose RAM.
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 9
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TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
0x00 2000 Reserved
Peripheral Frame 0
0x00 0800
0x00 1580
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 1400
0x00 0E00
0x00 1500
0x00 1480
CPU-to-CLA Message RAM
CLA-to-CPU Message RAM
CLA Registers
Peripheral Frame 0
Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x00 5000
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM2)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, CLA Program RAM)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L8 DPSARAM (8K x 16)
(0-Wait, DMA RAM 3)
L7 DPSARAM (8K x 16)
(0-Wait, DMA RAM 2)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
0x01 0000
0x01 2000
Peripheral Frame 1
(4K x 16, Protected)
0x00 6000
Reserved
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x01 4000 Reserved
0x3D 7BFA Reserved
FLASH
(128K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3D 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
Reserved
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Figure 2-1. 28069 Memory Map
10 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L8 DPSARAM (8K x 16)
(0-Wait, DMA RAM 3)
L7 DPSARAM (8K x 16)
(0-Wait, DMA RAM 2)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
0x01 0000
0x01 2000
Peripheral Frame 1
(4K x 16, Protected)
0x00 6000
Reserved
0x01 4000 Reserved
Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x00 5000
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(128K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3D 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Figure 2-2. 28068/28067 Memory Map
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 11
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
Reserved
0x01 0000 Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(128K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3D 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Figure 2-3. 28066 Memory Map
12 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
0x00 2000 Reserved
Peripheral Frame 0
0x00 0800
0x00 1580
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 1400
0x00 0E00
0x00 1500
0x00 1480
CPU-to-CLA Message RAM
CLA-to-CPU Message RAM
CLA Registers
Peripheral Frame 0
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM2)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, CLA Program RAM)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L8 DPSARAM (8K x 16)
(0-Wait, DMA RAM 3)
L7 DPSARAM (8K x 16)
(0-Wait, DMA RAM 2)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
0x01 0000
0x01 2000
Reserved
0x01 4000 Reserved
Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(64K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3E 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Figure 2-4. 28065 Memory Map
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 13
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TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L8 DPSARAM (8K x 16)
(0-Wait, DMA RAM 3)
L7 DPSARAM (8K x 16)
(0-Wait, DMA RAM 2)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
0x01 0000
0x01 2000
Reserved
0x01 4000 Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(64K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3E 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Figure 2-5. 28064 Memory Map
14 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
L6 DPSARAM (8K x 16)
(0-Wait, DMA RAM 1)
0x00 E000
Reserved
0x01 0000 Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(64K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3E 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Figure 2-6. 28063 Memory Map
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 15
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0000
0x00 0040
M1 SARAM (1K x 16, 0-Wait)
0x00 0400
Data Space Prog Space
Reserved
Peripheral Frame 0
0x00 0800
0x00 0D00 PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0
0x00 1400 Reserved
Peripheral Frame 1
(4K x 16, Protected)
Peripheral Frame 2
(4K x 16, Protected)
0x00 7000
0x00 6000
0x00 8000 L0 DPSARAM (2K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8800 L1 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 8C00 L2 DPSARAM (1K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 9000 L3 DPSARAM (4K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 A000 L4 SARAM (8K x 16)
(0-Wait, Secure Zone + ECSL)
0x00 C000 L5 DPSARAM (8K x 16)
(0-Wait, DMA RAM 0)
Reserved
0x00 E000 Reserved
0x00 5000 Peripheral Frame 3
(4K x 16, Protected)
DMA-Accessible
0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C80 Calibration Data
0x3D 7BFA Reserved
FLASH
(64K x 16, 8 Sectors, Secure Zone + ECSL)
128-Bit Password
0x3E 8000
0x3F 7FF8
Boot ROM (32K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
0x3F 8000
0x3F FFC0
0x3D 7CC0 Get_mode function
0x3D 7CD0 Reserved
0x3D 7E80 PARTID
Calibration Data
Reserved
0x3D 7EB0
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Figure 2-7. 28062 Memory Map
16 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698C –NOVEMBER 2010–REVISED MAY 2012
Table 2-2. Addresses of Flash Sectors in F28069/28068/28067/28066
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3D 8000 – 0x3D BFFF Sector H (16K x 16)
0x3D C000 – 0x3D FFFF Sector G (16K x 16)
0x3E 0000 – 0x3E 3FFF Sector F (16K x 16)
0x3E 4000 – 0x3E 7FFF Sector E (16K x 16)
0x3E 8000 – 0x3E BFFF Sector D (16K x 16)
0x3E C000 – 0x3E FFFF Sector C (16K x 16)
0x3F 0000 – 0x3F 3FFF Sector B (16K x 16)
0x3F 4000 – 0x3F 7FF5 Sector A (16K x 16)
Boot-to-Flash Entry Point
0x3F 7FF6 – 0x3F 7FF7 (program branch instruction here)
Security Password (128-Bit)
0x3F 7FF8 – 0x3F 7FFF (Do not program to all zeros)
Table 2-3. Addresses of Flash Sectors in F28065/28064/28063/28062
ADDRESS RANGE PROGRAM AND DATA SPACE
0x3E 8000 – 0x3E 9FFF Sector H (8K x 16)
0x3E A000 – 0x3E BFFF Sector G (8K x 16)
0x3E C000 – 0x3E DFFF Sector F (8K x 16)
0x3E E000 – 0x3E FFFF Sector E (8K x 16)
0x3F 0000 – 0x3F 1FFF Sector D (8K x 16)
0x3F 2000 – 0x3F 3FFF Sector C (8K x 16)
0x3F 4000 – 0x3F 5FFF Sector B (8K x 16)
0x3F 6000 – 0x3F 7FF5 Sector A (8K x 16)
Boot-to-Flash Entry Point
0x3F 7FF6 – 0x3F 7FF7 (program branch instruction here)
Security Password (128-Bit)
0x3F 7FF8 – 0x3F 7FFF (Do not program to all zeros)
NOTE
Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and should not contain program
code.
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 17
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
www.ti.com
Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read
peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as
written. Because of the pipeline, a write immediately followed by a read to different memory locations, will
appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block
protection mode where a region of memory can be protected so that operations occur as written (the
penalty is extra cycles are added to align the operations). This mode is programmable and by default, it
protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 2-4.
Table 2-4. Wait-States
AREA WAIT-STATES (CPU) COMMENTS
M0 and M1 SARAMs 0-wait Fixed
Peripheral Frame 0 0-wait
Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral-generated ready.
2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
Peripheral Frame 3 0-wait (writes) Assumes no conflict between CPU and CLA/DMA cycles. The wait
states can be extended by peripheral-generated ready.
2-wait (reads)
L0–L8 SARAM 0-wait data and program Assumes no CPU conflicts
OTP Programmable Programmed via the Flash registers.
1-wait minimum 1-wait is minimum number of wait states allowed.
FLASH Programmable Programmed via the Flash registers.
0-wait Paged min
1-wait Random min
Random ≥Paged
FLASH Password 16-wait fixed Wait states of password locations are fixed.
Boot-ROM 0-wait
18 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062
60
59
58
57
56
55
54
53
52
51
50
49
48
47
40
39
38
37
36
35
34
33
32
31
30
29
28
27
61
62
63
64
65
66
67
68
69
70
71
72
73
74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
46
45
44
43
42
41
15
16
17
18
19
20
75
76
77
78
79
80
26
25
24
23
22
21
GPIO23/EQEP1I/MFSXA/SCIRXDB
VDD
VDD
VSS
VDDIO
GPIO20/EQEP1A/MDXA/COMP1OUT
GPIO21/EQEP1B/MDRA/COMP2OUT
GPIO4/EPWM3A
GPIO5/EPWM3B/SPISIMOA/ECAP1
XRS
TRST
VSS
VDDIO
ADCINA6/COMP3A/AIO6
ADCINA5
ADCINA4/COMP2A/AIO4
ADCINA2/COMP1A/AIO2
ADCINA1
ADCINA0, VREFHI
VDDA
GPIO10/EPWM6A/ADCSOCBO
GPIO11/EPWM6B/SCIRXDB/ECAP1
GPIO36/TMS
GPIO35/TDI
GPIO37/TDO
GPIO34/COMP2OUT/COMP3OUT
GPIO38/XCLKIN/TCK
GPIO39
GPIO19/XCLKIN/ /SCIRXDB/ECAP1SPISTEA
VDD
VSS
VDDIO
X1
X2
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO7/EPWM4B/SCIRXDA/ECAP2
GPIO16/SPISIMOA/TZ2
GPIO8/EPWM5A/ADCSOCAO
GPIO17/SPISOMIA/TZ3
GPIO18/SPICLKA/SCITXDB/XCLKOUT
GPIO26/ECAP3/SPICLKB/USB0DP
GPIO27/HRCAP2/SPISTEB/USB0DM
VDDIO
VSS
VDD
GPIO3/EPWM2B/SPISOMIA/COMP2OUT
GPIO2/EPWM2A
GPIO1/EPWM1B/COMP1OUT
GPIO0/EPWM1A
GPIO15/ECAP2/SCIRXDB/SPISTEB
VREGENZ
VDD
VSS
VDDIO
GPIO13/ /SPISOMIBTZ2
GPIO14/ /SCITXDB/SPICLKBTZ3
GPIO24/ECAP1/SPISIMOB
GPIO22/EQEP1S/MCLKXA/SCITXDB
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO29/SCITXDA/SCLA/TZ3
GPIO12/ /SCITXDA/SPISIMOBTZ1
TEST2
VDD3VFL
VSS
GPIO9/EPWM5B/SCITXDB/ECAP3
GPIO28/SCIRXDA/SDAA/TZ2
GPIO30/CANRXA/EPWM7A
GPIO31/CANTXA/EPWM8A
GPIO25/ECAP2/SPISOMIB
VDD
VSS
VDDIO
ADCINB6/COMP3B/AIO14
ADCINB5
ADCINB4/COMP2B/AIO12
ADCINB2/COMP1B/AIO10
ADCINB1
ADCINB0
V , V
REFLO SSA
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
2.3 Pin Assignments
Figure 2-8 shows the 80-pin PN/PFP pin assignments. Figure 2-9 shows the 100-pin PZ/PZP pin
assignments.
A. Pin 19: VREFHI and ADCINA0 share the same pin on the 80-pin PN/PFP device and their use is mutually exclusive to
one another.
Pin 21: VREFLO is always connected to VSSA on the 80-pin PN/PFP device.
Figure 2-8. 80-Pin PN/PFP (Top View)
Copyright © 2010–2012, Texas Instruments Incorporated Device Overview 19
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TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
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Figure 2-9. 100-Pin PZ/PZP (Top View)
20 Device Overview Copyright © 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698C –NOVEMBER 2010–REVISED MAY 2012
2.4 Signal Descriptions
Table 2-5 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate
functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs
are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM
pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do
not have an internal pullup.