DATA SHEET
June 1992
Edition 1.0A
1992 by FUJITSU LIMITED and Fujitsu Microelectronics, Inc.
MB40730
1-Channel, 10-Bit ASSP Image Processing
D/A Converter (60 MSPS)
The MB40730 is a low-power consumption, high-speed 10-bit D/A converter . It
is characterized by ECL (10KH) compatible digital inputs, an analog output
voltage ranging from –2 V to 0 V, and a maximum conversion rate of 60 MHz. It
provides reference voltage from a potential divider and band-gap reference, or it
can use external reference voltage. The MB40730 D/A converter is suitable for
use in high-resolution TVs or VTRs.
•Resolution: 10 bits
•Conversion characteristics:
– Maximum conversion rate: 60 MHz minimum
– Linearity error: ±0.1% maximum
– Differential linearity error: ±0.1% maximum
•Input and output:
– Digital input voltage: 10KH ECL levels
– Analog output voltage: 2 Vp-p (–2 V to 0 V)
•Reference voltage:
–V
ROUT1: Potential divider circuit (VEEA x 2/5.2)
–V
ROUT2: Band-gap reference circuit (–2 V)
•Other characteristics:
– Supply voltage: –5.2 V single power supply
– Power dissipation: 180 mW
(typical value at analog output voltage 2 Vp-p)
140 mW
(typical value at analog output voltage 1 Vp-p)
•Package and ordering information:
– 20-pin plastic DIP, order as MB40730P
– 20-pin plastic SOP, order as MB40730PF
ABSOLUTE MAXIMUM RATINGS (VCCA – VCCD = 0 V, TA = +25°C
Parameter Symbol Rating Unit
Analog Power Supply Voltage VCCA –7.0 to 0 V
Digital Power Supply Voltage VCCD –7.0 to 0 V
Power Supply Voltage Difference VEED–VEEA 1.0 V
Digital Signal Input Voltage VID 0 to VEE V
Storage Temperature TSTG –55 to +125 °C
— Note —
Permanent device damage may occur if absolute maximum ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may af fect device reliability.
Plastic SOP
(FPT-20P-M01)
This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields. However , it is advised that
normal precautions be taken to avoid application of any voltage higher
than maximum rated voltages to this high impedance circuit.
Plastic DIP
(DIP-20P-M01)
MB40730
2
PIN ASSIGNMENT
(TOP VIEW)
(DIP–20P–M01)
(FPT–20P–M01)
(MSB) D11 20 CLK
D2219V
CCD
D3318V
CCA
D44 17 A.OUT
D5516V
ROUT2
D6615V
RIN
D7714V
ROUT1
D88 13 COMP
D9912V
EEA
(LSB) D10 10 11 VEED
PIN FUNCTIONS
Pin No. Symbol I/O Description
1 to 10 D1 to D10 IData signal input pin (D1: MSB, D10: LSB)
20 CLK I Clock signal input pin
19 VCCD –Digital ground pin (0V)
18 VCCA –Analog ground pin (0V)
11 VEED –Digital power pin (–5.2V)
12 VEEA –Analog ground pin (–5.2V)
15 VRIN I
Reference voltage input pin
Analog output dynamic range setup pin
(Connect to pin 14 or 16 to use the built-in reference voltage.
When using an external reference voltage, the voltage on this pin must be from
–2.20V to –0.70V.)
14 VROUT1 OReference voltage output pin 1
(The output voltage of the potential divider reference is fixed at VEEA ×2/5.2. When this
pin is connected to pin 15, the analog output voltage ranges from VEEA ×2/5.2 to 0V.)
16 VROUT2 OReference voltage output pin 2
(The output voltage of the band-gap reference is fixed at –2.0V. When the pin is
connected to pin 15, the analog output voltage ranges from –2V to 0V.)
13 COMP – Phase compensation capacitor pin
(Insert a capacitor of 0.1 µF or greater between VEEA and COMP for phase
compensation.)
17 A.OUT O Analog signal output pin
MB40730
3
BLOCK DIAGRAM
CLK
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
(MSB)
(LSB)
Input
Buffer Master-
slave
Flip Flop
Buffer Current
Switch
Reference Resistor
Reference Voltage
1
(Potential Divider
Reference)
Reference Voltage
2
(Band-gap
Reference)
Amplifier
R
2R
2R
2R
2R
2R
2R
R
R
R
R
R
R
R
R
VCCA
A.OUT
VCCD
VCCA
VROUT1 VROUT2 VRIN COMP
10 10 10
VEED
VEEA
MB40730
4
DIGITAL INPUT EQUIVALENT CIRCUIT
VCCD
Threshold voltage = –1.3V
VEED
D1 to D10
CLK
ANALOG OUTPUT EQUIVALENT CIRCUIT
VCCA
RO = 240 Ω
A.OUT
IO
VEEA
REFERENCE VOLTAGE OUTPUT EQUIVALENT CIRCUIT
VCCA
4 kΩ
6 kΩ
VROUT1
VROUT2
RS ∗
VCCA
BGR
–
+
*Overcurrent-prevention resistor (2 kΩ) for a short to GND.
VEEA
MB40730
5
TYPICAL CONNECTION EXAMPLE
VCC
DVCC
A
D1
to
D10
CLK
A. OUT
VROUT2
VRIN
VROUT1
COMP
DATA Input
CLK Input
Connect to VROUT1, VROUT2
or
External Reference Voltage.
0.1 µ
VEE
DVEE
A
2.2 µ47 µ0.01 µ
2.2 µ
47 µ0.01 µ
–5.2 V
RECOMMENDED OPERATING CONDITIONS
(VCCA = VCCD = 0V, TA = 20 °C to +75 °C
Standard Values
Parameter Symbol Min. Typ. Max. Unit
Power
Analog power supply voltage VEEA –5.46 –5.20 –4.94 V
P
ower
supply
voltage
Digital power supply voltage VEED –5.46 –5.20 –4.94 V
supp y
voltage Power supply voltage difference VEEA–VEED –0.2 – 0.2 V
Analog reference voltage VRIN –0.220 –2.00 –0.70 V
–20°C – – –0.88 V
Digital input high voltage VIHD –25°C –1.13 – –0.81 V
Digital input high voltage
VIHD
–75°C – – –0.735 V
–20°C –1.95 – – V
Digital input low voltage VILD –25°C –1.95 – –1.48 V
Digital input low voltage
VILD
–75°C –1.95 – – V
Clock frequency tCLK – – 60 MHz
Setup time tsu 8 – 60 ns
Hold time th2 – – ns
Clock minimum pulse width high tWH 6.5 – – ns
Clock minimum pulse width low tWL 6.5 – – ns
Phase compensation capacitor CCOMP 0.1 – – µF
Operating temperature Top 20 – 75 °C
MB40730
6
DC CHARACTERISTICS
(VEEA=VEED=–5.46 to –4.94V, TA=–20°C to +75°C)
Standard Values
Parameter Symbol Conditions Min. Typ. Max. Unit
Resolution – – – – 10 bit
Linearity error LE
DC accuracy
– – ±0.1 %
Differential linearity error DLE DC accuracy – – ±0.1 %
Digital input current high IIHD – – – 5 µA
Digital input current low IILD ––0.1 – – µA
Reference input current IRIN VRIN = –2.000V – – 10 µA
Potential di-
vider
reference Reference voltage VROUT1 VEEA = –5.20V
VEED = –5.20V –2.100 –2.100 –1.900 V
Band-gap Reference voltage VROUT2 ––2.100 –2.100 –1.900 V
Band
-
gap
reference Temperature coefficient – – – 100 – ppm/°C
Full-scale output voltage VOFS ––20 0 – mV
Zero-scale output voltage VOZS VEEA = –5.20V
VEED = –5.20V
VRIN = –2.000V –2.068 –1.998 –1.928 V
Output resistance ROTA = +25°C192 240 288 Ω
Power dissipation IEE VEEA = –5.46V
VEED = –5.46V
VRIN = VROUT1 –59 –34*– mA
∗VEEA = VEED = –5.20V
AC CHARACTERISTICS
VEEA= VEED=–5.46 to –4.94V, TA=–20°C to +75°C)
Parameter Symbol Conditions Standard Values Unit
Maximum conversion rate FsCL = 15 pF 60 – – MSPS
Output propagation delay time tpd
CL 15 pF
A OUT pin
– 7 – ns
Output rise time trA.OUT pin
terminating
it
– 5 – ns
Output fall time tf
terminating
resistance
= 240 Ω– 5 – ns
Settling time tset
=
240
Ω
– 17.5 – ns
MB40730
7
TIMING CHART
Data input
Clock input
Analog output
VIHD
VILD
VIHD
VILD
VOFS
VOZS
–0.9V
–1.7V
–0.9V
–1.7V
–1.3 V
–1.3V
90%
50%
10%
90%
50%
10%
±1/2LSB
±1/2LSB
tsu th
twH twL
trtf
tsetLH tsetHL
tPLH tPHL
MB40730
8
DAC OUTPUT VOLTAGE CHARACTERISTICS
Input Output
D1 to D10 A.OUT
1023
0
0.000V
0.000V
–1.998V
–2.000V
(VCCA)
VOFS
VOZS
(VRIN)
1 LSB = 2 mV
DAC OUTPUT VOLTAGE FORMULA UNDER IDEAL CONDITIONS
A.OUT = VCCA – × (VCCA – VRIN)
(N : Digital input code from 0 to 1023)
VOFS = VCCA
VOZS = VCCA – × (VCCA – VRIN)
1023 – N
1024
1023
1024
NOTES
1. Preventing Switching Noise
To prevent switching noise in the analog output signal, connect noise limiting capacitors to the VEEA and VEED pins as close to
the VCCA and VCCD pins as possible.
2. Power Pattern
To reduce parasitic impedance, the PC board pattern to the VCCA, VCCD, VEEA and VEED pins should be as wide as possible.
MB40730
9
MB40730 STANDARD CURVES
1. Power Supply Current vs. Ambient Temperature
VEE = –5.46V
VRIN = VROUT1
0
–20
–40
–60
–80
–100
IEE, Power
supply current
(mA)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
2. Linearity Error vs. Ambient Temperature
VEE = –5.20V
VRIN = –2.000V
0.1
0.08
0.06
0.04
0.02
0
LE,
Linearity
error (%)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
4. Output Resistance vs. Ambient Temperature
300
280
260
240
220
200
RO, Output
resistance (Ω)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
VEE = –5.20V
VRIN = –2.000V
–25 0 25 50 75 100
TA, Ambient temperature (°C)
0.1
0.08
0.06
0.04
0.02
0
DLE,
Differential
linearity
error (%)
3. Differential Linearity Error vs. Ambient Temperature
Continued on next page
MB40730
10
VEE = –5.20V
5. Full-Scale Output Voltage
vs. Ambient Temperature
VEE = –5.20V
VRIN = –2.000V
VCC
–10
–20
–30
–40
–50
VOFS,
Full-scale
output voltage
(mV)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
6. Zero-Scale Output Voltage
vs. Ambient Temperature
VEE = –5.20V
VRIN = –2.000V
–1.900
–1.950
–2.000
–2.050
–2.100
VOZS,
Zero-scale
output
voltage (V)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
7. VROUT1 Reference Output Voltage
vs. Ambient Temperature
VROUT1,
Reference
output
voltage (V)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
(Reference)
–1.900
–1.950
–2.000
–2.050
–2.100
VEE = –5.20V
8. VROUT2 Reference Output Voltage
vs. Ambient Temperature
VROUT2,
Reference
output
voltage (V)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
–1.900
–1.950
–2.000
–2.050
–2.100
Continued on next page
MB40730
11
VEE, Power supply voltage (V)
10. Setup Time vs. Ambient Temperature
VEE = –5.20V
10
8
6
4
2
0
tsu,
Setup time
(ns)
–25 0 25 50 75 100
Ta, Ambient temperature (°C)
12. Hold Time vs. Ambient Temperature
VEE = –5.20V
6
4
2
0
–2
–4 –25 0 25 50 75 100
Ta, Ambient temperature (°C)
11. Setup Time vs. Power Supply Voltage
10
8
6
4
2
0–6.5 –6.0 –5.5 –5.0 –4.5 –4.0
TA = 25 °C
9. VROUT2 Reference Output Voltage
vs. Power Supply Voltage
Reference
output voltage
VROUT2 (V)
–6.5 –6.0 –5.5 –5.0 –4.5 –4.0
VCC, Power supply voltage (V)
–1.900
–1.950
–2.000
–2.050
–2.100
TA = 25 °C
tsu,
Setup time
(ns)
tn,
Hold time
(ns)
Continued on next page
MB40730
12
–6.5 –6.0 –5.5 –5.0 –4.5 –4.0
VEE, Power supply voltage (V)
TA = 25 °C
–6.5 –6.0 –5.5 –5.0 –4.5 –4.0
VEE, Power supply voltage (V)
13. Hold Time vs. Power Supply Voltage
6
4
2
0
–2
–4
tn, Hold time
(ns)
14. Minimum Clock Pulse Width
vs. Ambient Temperature
VEE = –5.20V
10
8
6
4
2
0
twL/twH,
Minimum
clock pulse
width (ns)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
16. Rise Time / Fall Time
vs. Ambient Temperature
VEE = –5.20V
VRIN = –2.000V
CL = 15 pF
Analog output 240 Ω termination
(1V amplitude)
10
8
6
4
2
0
tr/tf, Rise time
and fall time
(ns)
–25 0 25 50 75 100
TA, Ambient temperature (°C)
15. Minimum Clock Pulse Width
vs. Power Supply Voltage
10
8
6
4
2
0
twL
twH
TA = 25 °C
twL/twH,
Minimum
clock pulse
width (ns) twL
twH
Continued on next page
MB40730
13
–6.5 –6.0 –5.5 –5.0 –4.5 –4.0
VEE, Power supply voltage (V)
18. Quantization Noise
vs. Analog Output Frequency
70
60
50
40
30
20
S/Nq,
Quantization
noise (dB)
0 5 10 15 20 25
fOUT, Analog output frequency (MHz)
17. Rise Time / Fall Time vs. Power Supply Voltage
Ta= 25 °C
VRIN = –2.000V
CL = 15 pF
Analog output 240 Ω termination
(1V amplitude)
10
8
6
4
2
0
tr/tf, Rise time
and fall time
(ns) fCLK = 15 MHz
fCLK = 30 MHz
fCLK = 60 MHz
MB40730
14
PACKAGE DIMENSIONS
Dimensions in
inches (millimeters)
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-20P-M01)
1991 FUJITSU LIMITED D20005S-3C
.970+.008
–.012 (24.64 )
+0.20
–0.30
.034 +.012
–0
(0.86 )
+0.30
–0
.260±.010
(6.60±0.25)
INDEX-1
.100(2.54)
TYP
.050(1.27)
MAX
.018±.003
(0.46±0.08) .020(0.51) MIN
.172(4.36) MAX
.118(3.00) MIN
.010±.002
(0.25±0.05)
.300(7.62)
TYP
15°MAX
.050 +.012
–0
(1.27 )
+0.30
–0
INDEX-2
MB40730
15
PACKAGE DIMENSIONS (Continued)
Dimensions in
inches (millimeters)
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M01)
1991 FUJITSU LIMITED F20003S-5C
.004(0.10)
∅.005(0.13) M
.050(1.27)
TYP
“A”
.018±.004
(0.45±0.10)
.089(2.25) MAX
(MOUNTING HEIGHT)
.002(0.05) MIN
(STAND OFF HEIGHT)
+.016
–.008 +0.40
–0.20
.268 (6.80 )
.020±.008
(0.50±0.20)
+.002
–.001 +0.05
–0.02
.006 (0.15 )
Details of “A” part
.008(0.20)
.020(0.50)
.007(0.18)
MAX
.027(0.68)
MAX
.500
INDEX
.450(11.43) REF
(12.70 )
+0.25
–0.20
+.010
–.008
.209±.012
(5.30±0.30)
.307±.016
(7.80±0.40)
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