Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 AM437x SitaraTM Processors 1 Device Overview 1.1 Features 1 * Highlights - SitaraTM ARM(R) Cortex(R)-A9 32-Bit RISC Processor With Processing Speed up to 1000 MHz * NEONTM SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor * 32KB of Both L1 Instruction and Data Cache * 256KB of L2 Cache or L3 RAM - 32-Bit LPDDR2, DDR3, and DDR3L Support - General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC - SGX530 Graphics Engine - Display Subsystem - Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRUICSS) - Real-Time Clock (RTC) - Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY - 10, 100, and 1000 Ethernet Switch Supporting up to Two Ports - Serial Interfaces: * Two Controller Area Network (CAN) Ports * Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire - Security * Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES) * Secure Boot (Avaliable Only on AM437x High-Security [AM437xHS] Devices) - Two 12-Bit Successive Approximation Register (SAR) ADCs - Up to Three 32-Bit Enhanced Capture (eCAP) Modules - Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules - Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules * MPU Subsystem - ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 1000 MHz - 32KB of Both L1 Instruction and Data Cache - 256KB of L2 Cache (Option to Configure as L3 RAM) - 256KB of On-Chip Boot ROM - 64KB of On-Chip RAM * * * * * - Secure Control Module (SCM) (Avaliable Only on AM437xHS Devices) - Emulation and Debug * JTAG * Embedded Trace Buffer - Interrupt Controller On-Chip Memory (Shared L3 RAM) - 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM - Accessible to All Masters - Supports Retention for Fast Wakeup - Up to 512KB of Total Internal RAM (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM) External Memory Interfaces (EMIFs) - DDR Controllers: * LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate) * DDR3 and DDR3L: 400-MHz Clock (DDR800 Data Rate) * 32-Bit Data Bus * 2GB of Total Addressable Space * Supports One x32, Two x16, or Four x8 Memory Device Configurations General-Purpose Memory Controller (GPMC) - Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM) - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC - Uses Hamming Code to Support 1-Bit ECC Error Locator Module (ELM) - Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm - Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) - Supports Protocols such as EtherCAT(R), PROFIBUS(R), PROFINET(R), and EtherNet/IPTM, EnDat 2.2, and More - Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores Each * Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 * 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity) * 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity) * Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator * Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal - 12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity) - Three 120-Byte Register Banks Accessible by Each PRU - Interrupt Controller Module (INTC) for Handling System Input Events - Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS - Peripherals Inside the PRU-ICSS * One UART Port With Flow Control Pins, Supports up to 12 Mbps * One eCAP Module * Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT * One MDIO Port - Industrial Communication is Supported by Two PRU-ICSS Subsystems * Power, Reset, and Clock Management (PRCM) Module - Controls the Entry and Exit of Deep-Sleep Modes - Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing - Clocks * Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks * Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption * Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], and LCD Pixel Clock) - Power * Two Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP]) 2 Device Overview www.ti.com * Three Switchable Power Domains (MPU Subsystem, SGX530 [GFX], Peripherals and Infrastructure [PER]) * Dynamic Voltage Frequency Scaling (DVFS) * Real-Time Clock (RTC) - Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information - Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO - Independent Power-On-Reset (RTC_PWRONRSTn) Input - Dedicated Input Pin (RTC_WAKEUP) for External Wake Events - Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or CortexA9 for Event Notification - Programmable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power Domains * Peripherals - Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY - Up to Two Industrial Gigabit Ethernet MACs (10, 100, and 1000 Mbps) * Integrated Switch * Each MAC Supports MII, RMII, and RGMII and MDIO Interfaces * Ethernet MACs and Switch Can Operate Independent of Other Functions * IEEE 1588v2 Precision Time Protocol (PTP) - Up to Two CAN Ports * Supports CAN Version 2 Parts A and B - Up to Two Multichannel Audio Serial Ports (McASPs) * Transmit and Receive Clocks up to 50 MHz * Up to Four Serial Data Pins Per McASP Port With Independent TX and RX Clocks * Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats * Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats) * FIFO Buffers for Transmit and Receive (256 Bytes) - Up to Six UARTs * All UARTs Support IrDA and CIR Modes * All UARTs Support RTS and CTS Flow Control * UART1 Supports Full Modem Control - Up to Five Master and Slave McSPIs * McSPI0-McSPI2 Support up to Four Chip Selects Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 * - - - - - - - - - - - - McSPI3 and McSPI4 Support up to Two Chip Selects * Up to 48 MHz One Quad-SPI * Supports eXecute In Place (XIP) from Serial NOR FLASH One Dallas 1-Wire(R) and HDQ Serial Interface Up to Three MMC, SD, and SDIO Ports * 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes * 1.8- or 3.3-V Operation on All Ports * Up to 48-MHz Clock * Supports Card Detect and Write Protect * Complies With MMC4.3 and SD and SDIO 2.0 Specifications Up to Three I2C Master and Slave Interfaces * Standard Mode (up to 100 kHz) * Fast Mode (up to 400 kHz) Up to Six Banks of General-Purpose I/O (GPIO) * 32 GPIOs per Bank (Multiplexed With Other Functional Pins) * GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank) Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs Twelve 32-Bit General-Purpose Timers * DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks * DMTIMER4-DMTIMER7 are Pinned Out One Public Watchdog Timer One Free-Running, High-Resolution 32-kHz Counter (synctimer32K) One Secure Watchdog Timer (Avaliable Only on AM437xHS Devices) SGX530 3D Graphics Engine * Tile-Based Architecture Delivering up to 20M Poly/sec * Universal Scalable Shader Engine is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality * Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0 * Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenVG 1.0 * Fine-Grained Task Switching, Load Balancing, and Power Management * Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction * Programmable High-Quality Image AntiAliasing * Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture Display Subsystem * Display Modes - Programmable Pixel Memory Formats (Palletized: 1-, 2-, 4-, and 8-Bits Per Pixel; RGB 16- and 24-Bits Per Pixel; and YUV 4:2:2) - 256- x 24-Bit Entries Palette in RGB - Up to 2048 x 2048 Resolution * Display Support - Four Types of Displays Are Supported: Passive and Active Colors; Passive and Active Monochromes - 4- and 8-Bit Monochrome Passive Panel Interface Support (15 Grayscale Levels Supported Using Dithering Block) - RGB 8-Bit Color Passive Panel Interface Support (3,375 Colors Supported for Color Panel Using Dithering Block) - RGB 12-, 16-, 18-, and 24-Bit Active Panel Interface Support (Replicated or Dithered Encoded Pixel Values) - Remote Frame Buffer (Embedded in the LCD Panel) Support Through the RFBI Module - Partial Refresh of the Remote Frame Buffer Through the RFBI Module - Partial Display - Multiple Cycles Output Format on 8-, 9-, 12-, and 16-Bit Interface (TDM) * Signal Processing - Overlay and Windowing Support for One Graphics Layer (RGB or CLUT) and Two Video Layers (YUV 4:2:2, RGB16, and RGB24) - RGB 24-Bit Support on the Display Interface, Optionally Dithered to RGB 18Bit Pixel Output Plus 6-Bit Frame Rate Control (Spatial and Temporal) - Transparency Color Key (Source and Destination) - Synchronized Buffer Update - Gamma Curve Support - Multiple-Buffer Support - Cropping Support - Color Phase Rotation - Two 12-Bit SAR ADCs (ADC0, ADC1) * 867K Samples Per Second * Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch * ADC0 Can Be Configured to Operate as a 4, 5-, or 8-Wire Resistive Touch Screen Controller (TSC) - Up to Three 32-Bit eCAP Modules * Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs - Up to Six Enhanced eHRPWM Modules Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Device Overview 3 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls * Configurable as Six Single-Ended, Six DualEdge Symmetric, or Three Dual-Edge Asymmetric Outputs - Up to Three 32-Bit eQEP Modules * Device Identification - Factory Programmable Electrical Fuse Farm (FuseFarm) * Production ID * Device Part Number (Unique JTAG ID) * Device Revision (Readable by Host ARM) * Security Keys (Avaliable Only on AM437xHS Devices) * Feature Identification * Debug Interface Support - JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug - Supports Real-Time Trace Pins (for Cortex-A9) - 64-KB Embedded Trace Buffer (ETB) - Supports Device Boundary Scan - Supports IEEE 1500 * DMA - On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller www.ti.com * 1.2 * * * * 4 * * * * (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels - EDMA is Used for: * Transfers to and from On-Chip Memories * Transfers to and from External Storage (EMIF, GPMC, and Slave Peripherals) InterProcessor Communication (IPC) - Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS Boot Modes - Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin Camera - Dual Port 8- and 10-Bit BT656 Interface - Dual Port 8- and 10-Bit Including External Syncs - Single Port 12-Bit - YUV422/RGB422 and BT656 Input Format - RAW Format - Pixel Clock Rate up to 75 MHz Package - 491-Pin BGA Package (17-mm x 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing Applications Patient Monitoring Navigation Equipment Industrial Automation Portable Data Terminals Device Overview * * * * Bar Code Scanners Point of Service Portable Mobile Radios Test and Measurement Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 1.3 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Description The TI AM437x high-performance processors are based on the ARM Cortex-A9 core. The processors are enhanced with 3D graphics acceleration for rich graphical user interfaces, as well as a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux(R) is available free of charge from TI. Other HLOSs are available from TI's Design Network and ecosystem partners. These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2. The processors contain the subsystems shown in Figure 1-1, and a brief description of each follows. The processor subsystem is based on the ARM Cortex-A9 core, and the PowerVR SGXTM graphics accelerator subsystem provides 3D graphics acceleration to support display and advanced user interfaces. The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC. High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme. One on-chip analog to digital converter (ADC0) can couple with the display subsystem to provide an integrated touch-screen solution. The other ADC (ADC1) can combine with the pulse width module to create a closed-loop motor control solution. The RTC provides a clock reference on a separate power domain. The clock reference enables a batterybacked clock reference. The camera interface offers configuration for a single- or dual-camera parallel port. Cryptographic acceleration is available in every AM437x device. Secure boot is available only on AM437xHS devices for anticloning and illegal software update protection. For more information about secure boot and HS devices, contact your TI sales representative. Table 1-1. Device Information (1) PACKAGE BODY SIZE AM4372ZDN PART NUMBER NFBGA (491) 17.0 mm x 17.0 mm AM4376ZDN NFBGA (491) 17.0 mm x 17.0 mm AM4377ZDN NFBGA (491) 17.0 mm x 17.0 mm AM4378ZDN NFBGA (491) 17.0 mm x 17.0 mm AM4379ZDN NFBGA (491) 17.0 mm x 17.0 mm (1) For more information, see Section 7, Mechanical, Packaging, and Orderable Information. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Device Overview 5 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 1.4 www.ti.com Functional Block Diagram ARM Cortex-A9 Up to 1000 MHz Graphics Display PowerVR SGX 3D GFX 20 MTri/s 24-bit LCDCtrl (WXGA) Touch Screen Controller (TSC) Processing: Overlay, Resizing,Color Space Conversion, and more Quad Core PRU-ICSS 32KB, 32KB L1 256KB L2, L3 RAM 64KB RAM (A) EtherCAT, PROFINET, EtherNet/IP, EnDat and more Crypto 256KB L3 RAM Secure Boot (HS device only) L3 and L4 Interconnect System Interface UART x6 EDMA SPI x5 Timers x12 QSPI WDT 2 RTC I C x3 CAN x2 eHRPWM x6 HDQ, 1-Wire eQEP, eCAP x3 McASP x2 (4ch) GPIO JTAG, ETB ADC0 (8 inputs) (A) 12-bit SAR Simplified Power Sequencing ADC1 (8 inputs) 12-bit SAR Camera Interface (2x Parallel) MMC, SD, SDIO x3 USB 2.0 Dual-Role + PHY x2 EMAC 2-port switch 10, 100, 1G with 1588 (MII, RMII, RGMII and MDIO) Memory Interface 32b LPDDR2, DDR3, DDR3L (B) NAND, NOR, Async (16-bit ECC) Copyright (c) 2016, Texas Instruments Incorporated A. B. Use of TSC limits available ADC0 inputs. Maximum clock: LPDDR2 = 266 MHz; DDR3/DDR3L = 400 MHz. Figure 1-1. Functional Block Diagram 6 Device Overview Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table of Contents 1 2 3 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 4 1.3 Description ............................................ 5 1.4 Functional Block Diagram ............................ 6 5 5.10 Revision History ......................................... 8 Device Comparison ..................................... 9 3.1 4 5.9 Related Products .................................... 10 Terminal Configuration and Functions ............ 11 4.1 Pin Diagrams ........................................ 11 4.2 Pin Attributes ........................................ 21 4.3 Signal Descriptions .................................. 65 ......................................... Absolute Maximum Ratings........................ ESD Ratings ....................................... Power-On Hours (POH) ........................... Operating Performance Points .................... Recommended Operating Conditions ............. Power Consumption Summary .................... DC Electrical Characteristics ...................... Specifications 103 5.1 103 5.2 5.3 5.4 5.5 5.6 5.7 5.8 ADC0: Touch Screen Controller and Analog-to- 6 105 105 106 107 109 110 5.11 Thermal Resistance Characteristics ............... 119 5.12 External Capacitors ................................ 121 5.13 Timing and Switching Characteristics.............. 124 5.14 Emulation and Debug .............................. 254 Device and Documentation Support .............. 255 6.1 Device Nomenclature .............................. 255 6.2 Tools and Software ................................ 256 6.3 Documentation Support ............................ 258 6.4 Related Links 6.5 Community Resources............................. 260 6.6 Trademarks ........................................ 260 6.7 Electrostatic Discharge Caution 6.8 7 Digital Subsystem Electrical Parameters .......... 113 ADC1: Analog-to-Digital Subsystem Electrical Parameters ......................................... 115 VPP Specifications for One-Time Programmable (OTP) eFuses ...................................... 118 ...................................... ................... Glossary............................................ 260 260 260 Mechanical, Packaging, and Orderable Information ............................................. 261 7.1 Via Channel ........................................ 261 7.2 Packaging Information ............................. 261 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Table of Contents 7 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2015) to Revision D * * * * * * * 8 Page Added AM4372 device information to document ................................................................................. 1 Added AM4372ZDN Part Number to Table 1-1, Device Information .......................................................... 5 Added Table 3-1, Device Features Comparison ................................................................................. 9 Added AM4372 Device and 600-MHz Device Speed Range to Figure 6-1, Device Nomenclature .................... 256 Updated Design Kits and Evaluation Modules list in Section 6.2, Tools and Software................................... 256 Updated notification alert paragraph in Section 6.3, Documentation Support ............................................. 258 Added AM4372 part number information to Table 6-1, Related Links ...................................................... 260 Revision History Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 3 Device Comparison Table 3-1 shows the features supported across different AM437x devices. Table 3-1. Device Features Comparison FUNCTION ARM Cortex-A9 Frequency MIPS AM4372 AM4376 AM4377 AM4378 AM4379 Yes Yes Yes Yes Yes 600 MHz 800 MHz 300 MHz 800 MHz 1000 MHz 800 MHz 1000 MHz 800 MHz 1000 MHz 800 MHz 1000 MHz 1500 2000 750 2000 2500 2000 2500 2000 2500 2000 2500 On-chip L1 cache 64KB 64KB 64KB 64KB 64KB On-chip L2 cache 256KB 256KB 256KB 256KB 256KB Graphics accelerator (SGX530) Hardware acceleration Programmable real-time unit subsystem and industrial communication subsystem (PRUICSS) On-chip memory Display options General-purpose memory DRAM(1) Universal serial bus (USB) -- -- -- 3D 3D Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator Crypto accelerator -- Features including basic Industrial protocols Features including all Industrial protocols Features including basic Industrial protocols Features including all Industrial protocols 256KB 256KB 256KB 256KB 256KB DSS DSS DSS DSS DSS 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 16-bit (GPMC, NAND flash, NOR flash, SRAM) 1 32-bit (DDR3-800, DDR3L-800, LPDDR2-532) 1 32-bit (DDR3-800, DDR3L-800, LPDDR2-532) 1 32-bit (DDR3-800, DDR3L-800, LPDDR2-532) 1 32-bit (DDR3-800, DDR3L-800, LPDDR2-532) 1 32-bit (DDR3-800, DDR3L-800, LPDDR2-532) 2 ports 2 ports 2 ports 2 ports 2 ports 10/100/1000 2 ports 10/100/1000 2 ports 10/100/1000 2 ports 10/100/1000 2 ports 10/100/1000 2 ports Multimedia card (MMC) 3 3 3 3 3 Controller-area network (CAN) 2 2 2 2 2 Universal asynchronous receiver and transmitter (UART) 6 6 6 6 6 Analog-to-digital converter (ADC) Ethernet media access controller (EMAC) with 2-port switch 2 8-ch 12-bit 2 8-ch 12-bit 2 8-ch 12-bit 2 8-ch 12-bit 2 8-ch 12-bit Enhanced high-resolution PWM modules (eHRPWM) 6 6 6 6 6 Enhanced capture modules (eCAP) 3 3 3 3 3 Enhanced quadrature encoder pulse (eQEP) 3 3 3 3 3 Real-time clock (RTC) 1 1 1 1 1 Inter-integrated circuit (I2C) 3 3 3 3 3 Multichannel audio serial port (McASP) 2 2 2 2 2 Multichannel serial port interface (McSPI) 5 5 5 5 5 Enhanced direct memory access (EDMA) 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch Camera (VPFE) 12-bit 12-bit 12-bit 12-bit 12-bit Sync timer (32K) 1 1 1 1 1 HDQ/1-Wire 1 1 1 1 1 QSPI 1 1 1 1 1 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Device Comparison 9 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 3-1. Device Features Comparison (continued) FUNCTION AM4372 AM4376 AM4377 AM4378 12 12 12 12 12 DEV_FEATURE register value(2) 0x020000EF 0x020000EF 0x020300EF 0x220000EF 0x220300EF Input/output (I/O) supply 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 0 to 90C -40 to 105C 0 to 90C -40 to 105C -40 to 90C -40 to 105C -40 to 90C 0 to 90C -40 to 105C -40 to 90C -40 to 105C Timers Operating temperature range AM4379 (1) DRAM speeds listed are data rates. (2) For more details about the DEV_FEATURE register, see the AM437x Sitara Processors Technical Reference Manual. 3.1 Related Products For information about other devices in this family of products or related products, see the following links: Sitara Processors Scalable processors based on ARM Cortex-A cores with flexible peripherals, connectivity and unified software support - perfect for sensors to servers. Sitara AM437x Processors Scalable ARM Cortex-A9 from 300 MHz up to 1 GHz. 3D graphics option for enhanced user interface. Quad core PRU-ICSS for industrial Ethernet protocols and position feedback control. Dual camera support for barcode scanning, preview and still pictures. Customer programmable secure boot option. Companion Products for AM437x Devices Review products that are frequently used in conjunction with this product. Reference Designs for AM437x Devices TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns. 10 Device Comparison Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4 Terminal Configuration and Functions 4.1 Pin Diagrams NOTE The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 11 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-1. ZDN Ball Map [Section Top Left - Top View] A B C D E F G H 25 VSS XTALOUT XTALIN gpio5_8 gpio5_12 USB1_DRVVBUS EXTINTn uart3_rxd 24 dss_ac_bias_en VSS_OSC xdma_event_intr1 xdma_event_intr0 gpio5_13 gpio5_9 eCAP0_in_PWM0_o ut uart3_txd 23 dss_hsync dss_vsync VDDS_OSC VDDS_CLKOUT gpio5_11 22 dss_pclk dss_data0 21 dss_data1 dss_data2 dss_data3 20 dss_data4 dss_data5 dss_data6 vdd_mpu_mon 19 dss_data8 dss_data9 dss_data12 dss_data13 18 dss_data10 dss_data11 VDDSHV5 VDDS dss_data7 CAP_VBB_MPU mcasp0_axr0 WARMRSTn uart3_ctsn USB0_DRVVBUS Reserved gpio5_10 clkreq Reserved VSS Ball Map Position 12 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-2. ZDN Ball Map [Section Top Middle - Top View] J K L M N P R T 25 uart0_rtsn uart0_rxd uart0_ctsn mcasp0_axr1 spi4_cs0 spi4_sclk spi0_cs1 USB1_VBUS 24 uart0_txd uart3_rtsn mcasp0_ahclkx mcasp0_ahclkr mcasp0_aclkx spi4_d1 spi4_d0 EMU1 23 mcasp0_fsr mcasp0_aclkr EMU0 spi0_sclk spi2_cs0 22 uart1_ctsn uart1_rtsn mcasp0_fsx spi2_d0 spi0_d0 21 uart1_rxd uart1_txd VDDS_PLL_CORE_ LCD VPP spi0_d1 20 VDD_MPU VDD_MPU spi2_sclk spi2_d1 spi0_cs0 19 VDD_MPU VDD_MPU VDDSHV3 VDDS VDD_CORE VDDSHV3 VSS VDDSHV3 VDDSHV3 18 VDDSHV3 VDD_MPU VSS VDD_CORE Ball Map Position 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 13 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-3. ZDN Ball Map [Section Top Right - Top View] U V W Y AA AB AC AD AE 25 USB1_ID USB1_DM USB0_DP nTRST TCK cam1_wen cam1_field cam1_hd VSS 24 USB0_ID USB1_DP USB0_DM TMS TDO I2C0_SDA cam1_data9 cam1_data8 cam1_data7 23 USB0_VBUS VSSA_USB PWRONRSTn VSS cam1_vd cam1_data6 cam1_data5 22 USB1_CE USB0_CE I2C0_SCL cam1_data4 cam1_data3 21 VDDA1P8V_USB1 VDDA1P8V_USB0 cam1_data1 cam1_data2 cam1_pclk 20 VDDA3P3V_USB1 VDDA3P3V_USB0 cam0_pclk cam0_data7 cam0_data6 19 VSS cam0_data5 cam0_data4 18 VSS cam0_vd cam0_data0 VSS VDDSHV3 TDI cam1_data0 VDDS cam0_data9 cam0_data8 cam0_data2 cam0_data3 cam0_data1 cam0_field Ball Map Position 14 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-4. ZDN Ball Map [Section Middle Left - Top View] A B C D E F G H 17 mdio_data mdio_clk dss_data14 dss_data15 VDDS_PLL_MPU mii1_rxd0 VDDSHV6 VDDSHV6 16 rmii1_ref_clk mii1_rxd1 mii1_txd3 mii1_col mii1_rxd2 VDDSHV7 VDDSHV6 VDD_MPU 15 mii1_rx_dv mii1_txd0 14 mii1_txd1 mii1_crs mii1_rxd3 mii1_tx_clk 13 mii1_tx_en mii1_rx_er mii1_txd2 mii1_rx_clk 12 gpmc_clk gpmc_csn3 11 gpmc_ad15 gpmc_ad14 gpmc_ad13 gpmc_ad11 gpmc_ad12 gpmc_ad10 VDDSHV9 VDDSHV9 10 gpmc_ad9 gpmc_ad8 gpmc_be0n_cle gpmc_wen gpmc_oen_ren gpmc_csn2 VDDSHV10 VDDSHV10 VSS CAP_VDD_SRAM_ MPU VDDS_SRAM_MPU _BB VDDSHV8 VDD_MPU CAP_VDD_SRAM_C VDDS_SRAM_COR ORE E_BG VDDSHV8 VDD_MPU VDDS Ball Map Position 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 15 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-5. ZDN Ball Map [Section Middle Middle - Top View] J K L M N P R T 17 VSS VDDSHV3 VSS VDD_MPU VDD_CORE VDD_CORE VSS VSS 16 VDD_MPU VSS VDD_CORE VDD_CORE 15 VSS VSS VSS VSS VSS VSS VSS VSS 14 VDD_MPU VSS VDD_CORE VDD_CORE VSS VSS VDD_CORE VDD_CORE 13 VDD_MPU VSS VSS VSS 12 VSS VSS VDD_CORE VDD_CORE VSS VSS VSS VSS 11 VDD_CORE VSS VSS VSS VSS VSS VDD_CORE VDD_CORE 10 VDD_CORE VSS VSS VSS Ball Map Position 16 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-6. ZDN Ball Map [Section Middle Right - Top View] U V W 17 VSS VDDSHV2 16 VSS VDDSHV2 VDDSHV2 VDDA_ADC1 ADC1_AIN2 ADC1_AIN1 15 VDD_CORE VDD_CORE VDDS ADC1_AIN5 ADC1_AIN4 ADC1_AIN3 14 VSS VSS 13 VSS VSS VDD_CORE ADC0_AIN2 ADC0_AIN3 ADC0_AIN4 12 VSS VSS VDD_CORE ADC0_AIN1 ADC0_AIN0 VDDA_ADC0 11 VSS VSS 10 VSS VSS Reserved Y Reserved AA Reserved AB Reserved AC AD AE cam0_wen cam0_hd ADC1_AIN0 ADC1_AIN7 ADC1_AIN6 VSSA_ADC ADC1_VREFN ADC1_VREFP ADC0_VREFP ADC0_VREFN ADC0_AIN5 ADC0_AIN6 ADC0_AIN7 Reserved VDDS Reserved Reserved Reserved Reserved VSS Reserved Ball Map Position 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 17 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-7. ZDN Ball Map [Section Bottom Left - Top View] A B C 9 gpmc_advn_ale gpmc_csn1 8 gpmc_csn0 gpmc_ad7 7 gpmc_ad5 gpmc_ad4 6 gpmc_ad3 gpmc_ad2 gpmc_a2 5 gpmc_ad1 gpmc_ad0 gpmc_a1 4 gpmc_a3 gpmc_a9 3 gpmc_be1n gpmc_wpn gpmc_a0 2 gpmc_wait0 mmc0_dat2 mmc0_dat1 1 VSS mmc0_dat3 mmc0_dat0 D E F G H VDDSHV11 gpmc_ad6 gpmc_a11 gpmc_a6 VDDS3P3V_IOLDO gpmc_a4 gpmc_a5 gpmc_a8 CAP_VDDS1P8V_IO LDO gpmc_a7 gpmc_a10 VDDSHV11 VDDS VDDS_PLL_DDR ddr_dqm0 ddr_d4 ddr_d0 ddr_d3 ddr_d5 mmc0_cmd ddr_d1 ddr_dqs0 ddr_d6 ddr_dqm1 mmc0_clk ddr_d2 ddr_dqsn0 ddr_d7 ddr_d8 Ball Map Position 18 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-8. ZDN Ball Map [Section Bottom Middle - Top View] J K L M N P R T 9 VSS VSS VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE 8 VDDSHV1 VDDS_DDR VSS VDDS_DDR VDDS_DDR VSS VDDS_DDR VDDS_DDR 7 VDDSHV1 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR 6 ddr_d9 ddr_d13 ddr_a10 ddr_cke1 VDDS_DDR ddr_vref 5 ddr_d10 ddr_d14 ddr_csn0 ddr_a13 ddr_a5 ddr_a11 4 ddr_d11 ddr_d15 ddr_csn1 ddr_wen ddr_a6 ddr_a12 3 ddr_d12 ddr_ba2 ddr_cke0 ddr_casn ddr_a7 ddr_a14 2 ddr_dqs1 ddr_ba1 ddr_a2 ddr_ck ddr_rasn ddr_a3 ddr_a8 ddr_a15 1 ddr_dqsn1 ddr_ba0 ddr_a1 ddr_nck ddr_a0 ddr_a4 ddr_a9 ddr_resetn Ball Map Position 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 19 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-9. ZDN Ball Map [Section Bottom Right - Top View] U V 9 VSS VSS 8 VSS VDDS_DDR W 7 VDDS_DDR 6 ddr_dqm2 ddr_d23 5 ddr_d16 ddr_d22 4 ddr_d17 ddr_d21 3 ddr_d18 Y Reserved AA AB AC AD AE Reserved Reserved Reserved VDD_CORE Reserved VDDS VSS Reserved Reserved Reserved Reserved Reserved VSS Reserved Reserved RTC_PMIC_EN RTC_PWRONRST n Reserved VDDS_RTC RTC_XTALIN VSS_RTC RTC_XTALOUT ddr_vtp CAP_VDD_RTC RTC_WAKEUP ddr_d26 ddr_d25 ddr_d27 2 ddr_odt1 ddr_d19 ddr_dqsn2 ddr_d24 ddr_dqsn3 ddr_d28 ddr_d31 Reserved RTC_KALDO_EN n 1 ddr_odt0 ddr_d20 ddr_dqs2 ddr_dqm3 ddr_dqs3 ddr_d29 ddr_d30 Reserved VSS Ball Map Position 20 1 2 3 4 5 6 7 8 9 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 4.2 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Pin Attributes 1. BALL NUMBER: Package ball numbers associated with each signals. 2. PIN NAME: The name of the package pin. Note: The table does not take into account subsystem terminal multiplexing options. 3. SIGNAL NAME: The signal name for that pin in the mode being used. 4. MODE: Multiplexing mode number. (a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the terminal corresponds to the name of the terminal. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode. Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE column. (b) Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration. 5. TYPE: Signal direction - I = Input - O = Output - IO = Input and Output - D = Open drain - DS = Differential - A = Analog - PWR = Power - GND = Ground Note: In the safe_mode, the buffer is configured in high-impedance. 6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low. - 0: The buffer drives VOL (pulldown or pullup resistor not activated) 0(PD): The buffer drives VOL with an active pulldown resistor - 1: The buffer drives VOH (pulldown or pullup resistor not activated) 1(PU): The buffer drives VOH with an active pullup resistor - Z or OFF: High-impedance - L: High-impedance with an active pulldown resistor - H : High-impedance with an active pullup resistor 7. BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal transitions from low to high. - 0: The buffer drives VOL (pulldown or pullup resistor not activated) 0(PD): The buffer drives VOL with an active pulldown resistor - 1: The buffer drives VOH (pulldown or pullup resistor not activated) 1(PU): The buffer drives VOH with an active pullup resistor - Z or OFF: High-impedance. - L: High-impedance with an active pulldown resistor - H : High-impedance with an active pullup resistor 8. RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal transitions from low to high. 9. POWER: The voltage supply that powers the terminal's IO buffers. 10. HYS: Indicates if the input buffer is with hysteresis. 11. BUFFER STRENGTH: Drive strength of the associated output buffer. 12. PULLUP OR PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. 13. IO CELL: IO cell information. Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 21 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. 22 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] AA12 ADC0_AIN0 ADC0_AIN0 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog Y12 ADC0_AIN1 ADC0_AIN1 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog Y13 ADC0_AIN2 ADC0_AIN2 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog AA13 ADC0_AIN3 ADC0_AIN3 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog AB13 ADC0_AIN4 ADC0_AIN4 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog AC13 ADC0_AIN5 ADC0_AIN5 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog AD13 ADC0_AIN6 ADC0_AIN6 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog AE13 ADC0_AIN7 ADC0_AIN7 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog AE14 ADC0_VREFN ADC0_VREFN 0x0 AP Z Z Mode0 VDDA_ADC0 NA NA NA Analog AD14 ADC0_VREFP ADC0_VREFP 0x0 AP Z Z Mode0 VDDA_ADC0 NA NA NA Analog AC16 ADC1_AIN0 ADC1_AIN0 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog AB16 ADC1_AIN1 ADC1_AIN1 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog AA16 ADC1_AIN2 ADC1_AIN2 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog AB15 ADC1_AIN3 ADC1_AIN3 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog AA15 ADC1_AIN4 ADC1_AIN4 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog Y15 ADC1_AIN5 ADC1_AIN5 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog AE16 ADC1_AIN6 ADC1_AIN6 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog AD16 ADC1_AIN7 ADC1_AIN7 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog AD15 ADC1_VREFN ADC1_VREFN 0x0 AP Z Z Mode0 VDDA_ADC1 NA NA NA Analog AE15 ADC1_VREFP ADC1_VREFP 0x0 AP Z Z Mode0 VDDA_ADC1 NA NA NA Analog AE18 cam0_data0 cam0_data0 0x0 I PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS cam1_data9 0x2 I I2C1_SDA 0x3 IOD pr0_pru1_gpo16 0x4 O pr0_pru1_gpi16 0x5 I ehrpwm0_synco 0x6 O gpio5_19 0x7 IO cam0_data1 0x0 I PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS cam1_data8 0x2 I I2C1_SCL 0x3 IOD pr0_pru1_gpo17 0x4 O pr0_pru1_gpi17 0x5 I ehrpwm3_synco 0x6 O gpio5_20 0x7 IO AB18 cam0_data1 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 23 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] Y18 AA18 AE19 AD19 AE20 AD20 24 PIN NAME [2] cam0_data2 cam0_data3 cam0_data4 cam0_data5 cam0_data6 cam0_data7 SIGNAL NAME [3] MODE [4] TYPE [5] cam0_data2 0x0 I mmc1_clk 0x1 IO cam1_data10 0x2 I qspi_clk 0x3 IO gpio4_24 0x7 IO cam0_data3 0x0 I mmc1_cmd 0x1 IO cam1_data11 0x2 I qspi_csn 0x3 O gpio4_25 0x7 IO cam0_data4 0x0 I mmc1_dat0 0x1 IO cam1_wen 0x2 I qspi_d0 0x3 IO ehrpwm3A 0x6 O gpio4_26 0x7 IO cam0_data5 0x0 I mmc1_dat1 0x1 IO qspi_d1 0x3 I ehrpwm3B 0x6 O gpio4_27 0x7 IO cam0_data6 0x0 I mmc1_dat2 0x1 IO qspi_d2 0x3 I ehrpwm1A 0x6 O gpio4_28 0x7 IO cam0_data7 0x0 I mmc1_dat3 0x1 IO qspi_d3 0x3 I ehrpwm1B 0x6 O gpio4_29 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] AB19 AA19 AC18 AE17 AC20 PIN NAME [2] cam0_data8 cam0_data9 cam0_field cam0_hd cam0_pclk SIGNAL NAME [3] MODE [4] TYPE [5] cam0_data8 0x0 I dss_data18 0x2 O pr0_pru0_gpo15 0x3 O spi2_cs2 0x4 IO pr0_pru0_gpi15 0x5 I EMU7 0x6 IO gpio4_5 0x7 IO I2C2_SCL 0x8 IOD cam0_data9 0x0 I dss_data17 0x2 O pr0_pru0_gpo16 0x3 O spi2_cs3 0x4 IO pr0_pru0_gpi16 0x5 I EMU8 0x6 IO gpio4_6 0x7 IO cam0_field 0x0 IO dss_data21 0x2 O cam0_data10 0x3 I spi2_sclk 0x4 IO cam1_data10 0x5 I EMU4 0x6 IO gpio4_2 0x7 IO cam0_hd 0x0 IO dss_data23 0x2 O pr1_edio_sof 0x3 O spi2_cs1 0x4 IO EMU10 0x5 IO EMU2 0x6 IO gpio4_0 0x7 IO cam0_pclk 0x0 I dss_data19 0x2 O pr0_pru0_gpo14 0x3 O spi2_cs0 0x4 IO pr0_pru0_gpi14 0x5 I EMU6 0x6 IO gpio4_4 0x7 IO I2C2_SDA 0x8 IOD BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 25 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] AD18 AD17 AB20 AC21 AD21 26 PIN NAME [2] cam0_vd cam0_wen cam1_data0 cam1_data1 cam1_data2 SIGNAL NAME [3] MODE [4] TYPE [5] cam0_vd 0x0 IO dss_data22 0x2 O pr1_edio_outvalid 0x3 O spi2_d1 0x4 IO EMU11 0x5 IO EMU3 0x6 IO gpio4_1 0x7 IO cam0_wen 0x0 I dss_data20 0x2 O cam0_data11 0x3 I spi2_d0 0x4 IO cam1_data11 0x5 I EMU5 0x6 IO gpio4_3 0x7 IO cam1_data0 0x0 I uart1_rxd 0x1 IO spi3_d0 0x2 IO I2C2_SDA 0x3 IOD ehrpwm0_tripzone_input 0x6 I gpio4_14 0x7 IO cam1_data1 0x0 I uart1_txd 0x1 IO spi3_d1 0x2 IO I2C2_SCL 0x3 IOD ehrpwm0_synci 0x6 I gpio4_15 0x7 IO cam1_data2 0x0 I uart1_ctsn 0x1 IO spi3_cs0 0x2 IO mmc2_clk 0x3 IO pr0_pru1_gpo10 0x4 O pr0_pru1_gpi10 0x5 I ehrpwm1_tripzone_input 0x6 I gpio4_16 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] AE22 AD22 AE23 AD23 PIN NAME [2] cam1_data3 cam1_data4 cam1_data5 cam1_data6 SIGNAL NAME [3] MODE [4] TYPE [5] cam1_data3 0x0 I uart1_rtsn 0x1 O spi3_sclk 0x2 IO mmc2_cmd 0x3 IO pr0_pru1_gpo11 0x4 O pr0_pru1_gpi11 0x5 I pr1_edc_latch0_in 0x6 I gpio4_17 0x7 IO cam1_data4 0x0 I uart1_rin 0x1 I uart2_rxd 0x2 IO mmc2_dat0 0x3 IO pr0_pru1_gpo12 0x4 O pr0_pru1_gpi12 0x5 I pr1_edc_latch1_in 0x6 I gpio4_18 0x7 IO uart0_dcdn 0x8 I cam1_data5 0x0 I uart1_dsrn 0x1 I uart2_txd 0x2 IO mmc2_dat1 0x3 IO pr0_pru1_gpo13 0x4 O pr0_pru1_gpi13 0x5 I pr1_edio_latch_in 0x6 I gpio4_19 0x7 IO cam1_data6 0x0 I uart1_dcdn 0x1 I uart2_ctsn 0x2 IO mmc2_dat2 0x3 IO pr0_pru1_gpo14 0x4 O pr0_pru1_gpi14 0x5 I pr1_edio_data_in0 0x6 I gpio4_20 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 27 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] AE24 AD24 AC24 AC25 28 PIN NAME [2] cam1_data7 cam1_data8 cam1_data9 cam1_field SIGNAL NAME [3] MODE [4] TYPE [5] cam1_data7 0x0 I uart1_dtrn 0x1 O uart2_rtsn 0x2 O mmc2_dat3 0x3 IO pr0_pru1_gpo15 0x4 O pr0_pru1_gpi15 0x5 I pr1_edio_data_in1 0x6 I gpio4_21 0x7 IO cam1_data8 0x0 I xdma_event_intr3 0x1 I spi0_cs2 0x2 IO pr0_pru1_gpo0 0x3 O spi2_d0 0x4 IO pr0_pru1_gpi0 0x5 I EMU10 0x6 IO gpio4_8 0x7 IO uart0_rtsn 0x8 O cam1_data9 0x0 I dss_data16 0x2 O pr0_pru0_gpo17 0x3 O spi2_cs3 0x4 IO pr0_pru0_gpi17 0x5 I EMU9 0x6 IO gpio4_7 0x7 IO uart0_ctsn 0x8 I cam1_field 0x0 IO xdma_event_intr7 0x1 I ext_hw_trigger 0x2 I cam0_data10 0x3 I spi2_cs1 0x4 IO cam1_data10 0x5 I ehrpwm1B 0x6 O gpio4_12 0x7 IO ehrpwm3A 0x8 O BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] AD25 AE21 AC23 AB25 PIN NAME [2] cam1_hd cam1_pclk cam1_vd cam1_wen SIGNAL NAME [3] MODE [4] TYPE [5] cam1_hd 0x0 IO xdma_event_intr4 0x1 I spi0_cs3 0x2 IO pr0_pru1_gpo1 0x3 O spi2_cs0 0x4 IO pr0_pru1_gpi1 0x5 I ehrpwm0A 0x6 O gpio4_9 0x7 IO cam1_pclk 0x0 I xdma_event_intr6 0x1 I spi1_cs3 0x2 IO pr0_pru1_gpo3 0x3 O spi2_sclk 0x4 IO pr0_pru1_gpi3 0x5 I ehrpwm1A 0x6 O gpio4_11 0x7 IO cam1_vd 0x0 IO xdma_event_intr5 0x1 I spi1_cs2 0x2 IO pr0_pru1_gpo2 0x3 O spi2_cs2 0x4 IO pr0_pru1_gpi2 0x5 I ehrpwm0B 0x6 O gpio4_10 0x7 IO cam1_wen 0x0 I xdma_event_intr8 0x1 I pr1_edio_sof 0x2 O cam0_data11 0x3 I spi2_d1 0x4 IO cam1_data11 0x5 I EMU11 0x6 IO gpio4_13 0x7 IO ehrpwm3B 0x8 O BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] F19 CAP_VBB_MPU CAP_VBB_MPU NA A NA NA NA NA NA NA NA NA D6 CAP_VDDS1P8V_IOLDO CAP_VDDS1P8V_IOLDO NA POWER NA NA NA NA NA NA NA NA AD3 CAP_VDD_RTC CAP_VDD_RTC NA A NA NA NA NA NA NA NA NA E13 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A NA NA NA NA NA NA NA NA E14 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A NA NA NA NA NA NA NA NA Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 29 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] H20 PIN NAME [2] clkreq SIGNAL NAME [3] MODE [4] TYPE [5] clkreq 0x0 O gpio0_24 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PU POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS N1 ddr_a0 ddr_a0 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 L1 ddr_a1 ddr_a1 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 L2 ddr_a2 ddr_a2 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 P2 ddr_a3 ddr_a3 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 P1 ddr_a4 ddr_a4 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 R5 ddr_a5 ddr_a5 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 R4 ddr_a6 ddr_a6 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 R3 ddr_a7 ddr_a7 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 R2 ddr_a8 ddr_a8 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 R1 ddr_a9 ddr_a9 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 M6 ddr_a10 ddr_a10 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 T5 ddr_a11 ddr_a11 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 T4 ddr_a12 ddr_a12 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 N5 ddr_a13 ddr_a13 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 T3 ddr_a14 ddr_a14 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 T2 ddr_a15 ddr_a15 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 K1 ddr_ba0 ddr_ba0 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 K2 ddr_ba1 ddr_ba1 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 K3 ddr_ba2 ddr_ba2 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 N3 ddr_casn ddr_casn 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 M2 ddr_ck ddr_ck 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 M3 ddr_cke0 ddr_cke0 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 30 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] N6 ddr_cke1 ddr_cke1 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 M5 ddr_csn0 ddr_csn0 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 M4 ddr_csn1 ddr_csn1 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 E3 ddr_d0 ddr_d0 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 E2 ddr_d1 ddr_d1 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 E1 ddr_d2 ddr_d2 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 F3 ddr_d3 ddr_d3 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 G4 ddr_d4 ddr_d4 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 G3 ddr_d5 ddr_d5 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 G2 ddr_d6 ddr_d6 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 G1 ddr_d7 ddr_d7 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 H1 ddr_d8 ddr_d8 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 J6 ddr_d9 ddr_d9 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 J5 ddr_d10 ddr_d10 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 J4 ddr_d11 ddr_d11 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 J3 ddr_d12 ddr_d12 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 K6 ddr_d13 ddr_d13 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 K5 ddr_d14 ddr_d14 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 K4 ddr_d15 ddr_d15 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 V5 ddr_d16 ddr_d16 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 V4 ddr_d17 ddr_d17 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 V3 ddr_d18 ddr_d18 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 V2 ddr_d19 ddr_d19 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 31 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] V1 ddr_d20 ddr_d20 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 W4 ddr_d21 ddr_d21 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 W5 ddr_d22 ddr_d22 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 W6 ddr_d23 ddr_d23 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 Y2 ddr_d24 ddr_d24 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 Y3 ddr_d25 ddr_d25 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 Y4 ddr_d26 ddr_d26 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 AA3 ddr_d27 ddr_d27 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 AB2 ddr_d28 ddr_d28 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 AB1 ddr_d29 ddr_d29 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 AC1 ddr_d30 ddr_d30 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 AC2 ddr_d31 ddr_d31 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 F4 ddr_dqm0 ddr_dqm0 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 H2 ddr_dqm1 ddr_dqm1 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 V6 ddr_dqm2 ddr_dqm2 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 Y1 ddr_dqm3 ddr_dqm3 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 F2 ddr_dqs0 ddr_dqs0 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 J2 ddr_dqs1 ddr_dqs1 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 W1 ddr_dqs2 ddr_dqs2 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 AA1 ddr_dqs3 ddr_dqs3 0x0 IO PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 F1 ddr_dqsn0 ddr_dqsn0 0x0 IO PU Mode0 VDDS_DDR Yes 8 PU/PD LVCMOS/HST L/HSUL_12 J1 ddr_dqsn1 ddr_dqsn1 0x0 IO PU Mode0 VDDS_DDR Yes 8 PU/PD LVCMOS/HST L/HSUL_12 W2 ddr_dqsn2 ddr_dqsn2 0x0 IO PU Mode0 VDDS_DDR Yes 8 PU/PD LVCMOS/HST L/HSUL_12 32 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] AA2 ddr_dqsn3 ddr_dqsn3 0x0 IO PU Mode0 VDDS_DDR Yes 8 PU/PD LVCMOS/HST L/HSUL_12 M1 ddr_nck ddr_nck 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 U1 ddr_odt0 ddr_odt0 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 U2 ddr_odt1 ddr_odt1 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 N2 ddr_rasn ddr_rasn 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 T1 ddr_resetn ddr_resetn 0x0 O PD Mode0 VDDS_DDR YES 8 PU/PD LVCMOS T6 ddr_vref ddr_vref 0x0 AP (19) NA NA Mode0 VDDS_DDR NA NA NA Analog AC3 ddr_vtp ddr_vtp 0x0 I (20) NA NA Mode0 VDDS_DDR NA NA NA Analog N4 ddr_wen ddr_wen 0x0 O PU Mode0 VDDS_DDR YES 8 PU/PD LVCMOS/HST L/HSUL_12 A24 dss_ac_bias_en dss_ac_bias_en 0x0 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS gpmc_a11 0x1 O gpmc_a4 0x2 O pr1_edio_data_in5 0x3 I pr1_edio_data_out5 0x4 O pr0_pru1_gpo9 0x5 O pr0_pru1_gpi9 0x6 I gpio2_25 0x7 IO dss_data0 0x0 IO OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS gpmc_a0 0x1 O pr1_mii_mt0_clk 0x2 I ehrpwm2A 0x3 O pr1_pru0_gpo0 0x5 O pr1_pru0_gpi0 0x6 I gpio2_6 0x7 IO dss_data1 0x0 IO OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS gpmc_a1 0x1 O pr1_mii0_txen 0x2 O ehrpwm2B 0x3 O pr1_pru0_gpo1 0x5 O pr1_pru0_gpi1 0x6 I gpio2_7 0x7 IO B22 A21 dss_data0 (4) dss_data1 (4) Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 33 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] B21 C21 A20 B20 C20 34 PIN NAME [2] dss_data2 (4) dss_data3 (4) dss_data4 (4) dss_data5 (4) dss_data6 (4) SIGNAL NAME [3] MODE [4] TYPE [5] dss_data2 0x0 IO gpmc_a2 0x1 O pr1_mii0_txd3 0x2 O ehrpwm2_tripzone_input 0x3 I pr1_pru0_gpo2 0x5 O pr1_pru0_gpi2 0x6 I gpio2_8 0x7 IO dss_data3 0x0 IO gpmc_a3 0x1 O pr1_mii0_txd2 0x2 O ehrpwm0_synco 0x3 O pr1_pru0_gpo3 0x5 O pr1_pru0_gpi3 0x6 I gpio2_9 0x7 IO dss_data4 0x0 IO gpmc_a4 0x1 O pr1_mii0_txd1 0x2 O eQEP2A_in 0x3 I pr1_pru0_gpo4 0x5 O pr1_pru0_gpi4 0x6 I gpio2_10 0x7 IO dss_data5 0x0 IO gpmc_a5 0x1 O pr1_mii0_txd0 0x2 O eQEP2B_in 0x3 I pr1_pru0_gpo5 0x5 O pr1_pru0_gpi5 0x6 I gpio2_11 0x7 IO dss_data6 0x0 IO gpmc_a6 0x1 O pr1_edio_data_in6 0x2 I eQEP2_index 0x3 IO pr1_edio_data_out6 0x4 O pr1_pru0_gpo6 0x5 O pr1_pru0_gpi6 0x6 I gpio2_12 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] E19 A19 B19 A18 PIN NAME [2] dss_data7 (4) dss_data8 (4) dss_data9 (4) dss_data10 (4) SIGNAL NAME [3] MODE [4] TYPE [5] dss_data7 0x0 IO gpmc_a7 0x1 O pr1_edio_data_in7 0x2 I eQEP2_strobe 0x3 IO pr1_edio_data_out7 0x4 O pr1_pru0_gpo7 0x5 O pr1_pru0_gpi7 0x6 I gpio2_13 0x7 IO dss_data8 0x0 IO gpmc_a12 0x1 O ehrpwm1_tripzone_input 0x2 I mcasp0_aclkx 0x3 IO uart5_txd 0x4 O pr1_mii0_rxd3 0x5 I uart2_ctsn 0x6 IO gpio2_14 0x7 IO dss_data9 0x0 IO gpmc_a13 0x1 O ehrpwm0_synco 0x2 O mcasp0_fsx 0x3 IO uart5_rxd 0x4 I pr1_mii0_rxd2 0x5 I uart2_rtsn 0x6 O gpio2_15 0x7 IO dss_data10 0x0 IO gpmc_a14 0x1 O ehrpwm1A 0x2 O mcasp0_axr0 0x3 IO pr1_mii0_rxd1 0x5 I uart3_ctsn 0x6 IO gpio2_16 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 35 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] B18 C19 D19 C17 36 PIN NAME [2] dss_data11 (4) dss_data12 (4) dss_data13 (4) dss_data14 (4) SIGNAL NAME [3] MODE [4] TYPE [5] dss_data11 0x0 IO gpmc_a15 0x1 O ehrpwm1B 0x2 O mcasp0_ahclkr 0x3 IO mcasp0_axr2 0x4 IO pr1_mii0_rxd0 0x5 I uart3_rtsn 0x6 O gpio2_17 0x7 IO spi3_cs1 0x8 IO dss_data12 0x0 IO gpmc_a16 0x1 O eQEP1A_in 0x2 I mcasp0_aclkr 0x3 IO mcasp0_axr2 0x4 IO pr1_mii0_rxlink 0x5 I uart4_ctsn 0x6 I gpio0_8 0x7 IO spi3_sclk 0x8 IO dss_data13 0x0 IO gpmc_a17 0x1 O eQEP1B_in 0x2 I mcasp0_fsr 0x3 IO mcasp0_axr3 0x4 IO pr1_mii0_rxer 0x5 I uart4_rtsn 0x6 O gpio0_9 0x7 IO spi3_d0 0x8 IO dss_data14 0x0 IO gpmc_a18 0x1 O eQEP1_index 0x2 IO mcasp0_axr1 0x3 IO uart5_rxd 0x4 I pr1_mii_mr0_clk 0x5 I uart5_ctsn 0x6 I gpio0_10 0x7 IO spi3_d1 0x8 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] D17 A23 A22 B23 PIN NAME [2] dss_data15 (4) dss_hsync (5) dss_pclk dss_vsync (6) SIGNAL NAME [3] MODE [4] TYPE [5] dss_data15 0x0 IO gpmc_a19 0x1 O eQEP1_strobe 0x2 IO mcasp0_ahclkx 0x3 IO mcasp0_axr3 0x4 IO pr1_mii0_rxdv 0x5 I uart5_rtsn 0x6 O gpio0_11 0x7 IO spi3_cs0 0x8 IO dss_hsync 0x0 O gpmc_a9 0x1 O gpmc_a2 0x2 O pr1_edio_data_in3 0x3 I pr1_edio_data_out3 0x4 O pr0_pru1_gpo7 0x5 O pr0_pru1_gpi7 0x6 I gpio2_23 0x7 IO dss_pclk 0x0 O gpmc_a10 0x1 O gpmc_a3 0x2 O pr1_edio_data_in4 0x3 I pr1_edio_data_out4 0x4 O pr0_pru1_gpo8 0x5 O pr0_pru1_gpi8 0x6 I gpio2_24 0x7 IO dss_vsync 0x0 O gpmc_a8 0x1 O gpmc_a1 0x2 O pr1_edio_data_in2 0x3 I pr1_edio_data_out2 0x4 O pr0_pru1_gpo6 0x5 O pr0_pru1_gpi6 0x6 I gpio2_22 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 37 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] G24 N23 T24 PIN NAME [2] eCAP0_in_PWM0_out EMU0 EMU1 SIGNAL NAME [3] MODE [4] TYPE [5] eCAP0_in_PWM0_out 0x0 IO uart3_txd 0x1 IO spi1_cs1 0x2 IO pr1_ecap0_ecap_capin_apwm_o 0x3 IO spi1_sclk 0x4 IO mmc0_sdwp 0x5 I xdma_event_intr2 0x6 I gpio0_7 0x7 IO ehrpwm2B 0x8 O timer1 0x9 IO EMU0 0x0 IO gpio3_7 0x7 IO EMU1 0x0 IO gpio3_8 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS PU PU Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS PU PU Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] G25 EXTINTn nNMI 0x0 I OFF PU Mode0 VDDSHV3 Yes NA PU/PD LVCMOS D25 gpio5_8 pr1_mii0_col 0x5 I OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS gpio5_8 0x7 IO pr1_mii1_col 0x5 I OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS gpio5_9 0x7 IO I2C1_SCL 0x1 IOD OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS pr1_mii0_crs 0x5 I gpio5_10 0x7 IO pr1_mii1_crs 0x5 I OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS gpio5_11 0x7 IO I2C1_SDA 0x1 IOD OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS pr1_mii0_rxlink 0x5 I gpio5_12 0x7 IO pr1_mii1_rxlink 0x5 I OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS gpio5_13 0x7 IO gpmc_a0 0x0 O PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS gmii2_txen 0x1 O rgmii2_tctl 0x2 O rmii2_txen 0x3 O gpmc_a16 0x4 O pr1_mii1_txen 0x5 O ehrpwm1_tripzone_input 0x6 I gpio1_16 0x7 IO F24 G20 F23 E25 E24 C3 38 gpio5_9 gpio5_10 gpio5_11 gpio5_12 gpio5_13 gpmc_a0 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] C5 C6 A4 D7 PIN NAME [2] gpmc_a1 gpmc_a2 gpmc_a3 gpmc_a4 SIGNAL NAME [3] MODE [4] TYPE [5] gpmc_a1 0x0 O gmii2_rxdv 0x1 I rgmii2_rctl 0x2 I mmc2_dat0 0x3 IO gpmc_a17 0x4 O pr1_mii1_rxdv 0x5 I ehrpwm0_synco 0x6 O gpio1_17 0x7 IO gpmc_a2 0x0 O gmii2_txd3 0x1 O rgmii2_td3 0x2 O mmc2_dat1 0x3 IO gpmc_a18 0x4 O pr1_mii1_txd3 0x5 O ehrpwm1A 0x6 O gpio1_18 0x7 IO gpmc_a3 0x0 O gmii2_txd2 0x1 O rgmii2_td2 0x2 O mmc2_dat2 0x3 IO gpmc_a19 0x4 O pr1_mii1_txd2 0x5 O ehrpwm1B 0x6 O gpio1_19 0x7 IO gpmc_a4 0x0 O gmii2_txd1 0x1 O rgmii2_td1 0x2 O rmii2_txd1 0x3 O gpmc_a20 0x4 O pr1_mii1_txd1 0x5 O eQEP1A_in 0x6 I gpio1_20 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 39 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] E7 E8 F6 F7 40 PIN NAME [2] gpmc_a5 gpmc_a6 gpmc_a7 gpmc_a8 SIGNAL NAME [3] MODE [4] TYPE [5] gpmc_a5 0x0 O gmii2_txd0 0x1 O rgmii2_td0 0x2 O rmii2_txd0 0x3 O gpmc_a21 0x4 O pr1_mii1_txd0 0x5 O eQEP1B_in 0x6 I gpio1_21 0x7 IO gpmc_a6 0x0 O gmii2_txclk 0x1 I rgmii2_tclk 0x2 O mmc2_dat4 0x3 IO gpmc_a22 0x4 O pr1_mii_mt1_clk 0x5 I eQEP1_index 0x6 IO gpio1_22 0x7 IO gpmc_a7 0x0 O gmii2_rxclk 0x1 I rgmii2_rclk 0x2 I mmc2_dat5 0x3 IO gpmc_a23 0x4 O pr1_mii_mr1_clk 0x5 I eQEP1_strobe 0x6 IO gpio1_23 0x7 IO gpmc_a8 0x0 O gmii2_rxd3 0x1 I rgmii2_rd3 0x2 I mmc2_dat6 0x3 IO gpmc_a24 0x4 O pr1_mii1_rxd3 0x5 I mcasp0_aclkx 0x6 IO gpio1_24 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] B4 G8 D8 B5 A5 B6 A6 PIN NAME [2] gpmc_a9 gpmc_a10 gpmc_a11 gpmc_ad0 gpmc_ad1 gpmc_ad2 gpmc_ad3 SIGNAL NAME [3] MODE [4] TYPE [5] gpmc_a9 0x0 O gmii2_rxd2 0x1 I rgmii2_rd2 0x2 I mmc2_dat7 0x3 IO gpmc_a25 0x4 O pr1_mii1_rxd2 0x5 I mcasp0_fsx 0x6 IO gpio1_25 0x7 IO rmii2_crs_dv 0x8 I gpmc_a10 0x0 O gmii2_rxd1 0x1 I rgmii2_rd1 0x2 I rmii2_rxd1 0x3 I gpmc_a26 0x4 O pr1_mii1_rxd1 0x5 I mcasp0_axr0 0x6 IO gpio1_26 0x7 IO gpmc_a11 0x0 O gmii2_rxd0 0x1 I rgmii2_rd0 0x2 I rmii2_rxd0 0x3 I gpmc_a27 0x4 O pr1_mii1_rxd0 0x5 I mcasp0_axr1 0x6 IO gpio1_27 0x7 IO gpmc_ad0 0x0 IO mmc1_dat0 0x1 IO gpio1_0 0x7 IO gpmc_ad1 0x0 IO mmc1_dat1 0x1 IO gpio1_1 0x7 IO gpmc_ad2 0x0 IO mmc1_dat2 0x1 IO gpio1_2 0x7 IO gpmc_ad3 0x0 IO mmc1_dat3 0x1 IO gpio1_3 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 41 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] B7 A7 C8 B8 B10 A10 42 PIN NAME [2] gpmc_ad4 gpmc_ad5 gpmc_ad6 gpmc_ad7 gpmc_ad8 gpmc_ad9 SIGNAL NAME [3] MODE [4] TYPE [5] gpmc_ad4 0x0 IO mmc1_dat4 0x1 IO gpio1_4 0x7 IO gpmc_ad5 0x0 IO mmc1_dat5 0x1 IO gpio1_5 0x7 IO gpmc_ad6 0x0 IO mmc1_dat6 0x1 IO gpio1_6 0x7 IO gpmc_ad7 0x0 IO mmc1_dat7 0x1 IO gpio1_7 0x7 IO gpmc_ad8 0x0 IO dss_data23 0x1 O mmc1_dat0 0x2 IO mmc2_dat4 0x3 IO ehrpwm2A 0x4 O pr1_mii_mt0_clk 0x5 I spi3_sclk 0x6 IO gpio0_22 0x7 IO spi3_cs1 0x8 IO gpio5_26 0x9 IO gpmc_ad9 0x0 IO dss_data22 0x1 O mmc1_dat1 0x2 IO mmc2_dat5 0x3 IO ehrpwm2B 0x4 O pr1_mii0_col 0x5 I spi3_d0 0x6 IO gpio0_23 0x7 IO gpio5_25 0x9 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] F11 D11 E11 C11 PIN NAME [2] gpmc_ad10 gpmc_ad11 gpmc_ad12 gpmc_ad13 SIGNAL NAME [3] MODE [4] TYPE [5] gpmc_ad10 0x0 IO dss_data21 0x1 O mmc1_dat2 0x2 IO mmc2_dat6 0x3 IO ehrpwm2_tripzone_input 0x4 I pr1_mii0_txen 0x5 O spi3_d1 0x6 IO gpio0_26 0x7 IO gpio5_24 0x9 IO gpmc_ad11 0x0 IO dss_data20 0x1 O mmc1_dat3 0x2 IO mmc2_dat7 0x3 IO ehrpwm0_synco 0x4 O pr1_mii0_txd3 0x5 O spi3_cs0 0x6 IO gpio0_27 0x7 IO gpio5_23 0x9 IO gpmc_ad12 0x0 IO dss_data19 0x1 O mmc1_dat4 0x2 IO mmc2_dat0 0x3 IO eQEP2A_in 0x4 I pr1_mii0_txd2 0x5 O pr1_pru0_gpi10 0x6 I gpio1_12 0x7 IO mcasp0_aclkx 0x8 IO pr1_pru0_gpo10 0x9 O gpmc_ad13 0x0 IO dss_data18 0x1 O mmc1_dat5 0x2 IO mmc2_dat1 0x3 IO eQEP2B_in 0x4 I pr1_mii0_txd1 0x5 O pr1_pru0_gpi11 0x6 I gpio1_13 0x7 IO mcasp0_fsx 0x8 IO pr1_pru0_gpo11 0x9 O BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 43 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] B11 A11 A9 C10 44 PIN NAME [2] gpmc_ad14 gpmc_ad15 gpmc_advn_ale gpmc_be0n_cle SIGNAL NAME [3] MODE [4] TYPE [5] gpmc_ad14 0x0 IO dss_data17 0x1 O mmc1_dat6 0x2 IO mmc2_dat2 0x3 IO eQEP2_index 0x4 IO pr1_mii0_txd0 0x5 O pr1_pru0_gpi16 0x6 I gpio1_14 0x7 IO mcasp0_axr0 0x8 IO gpmc_ad15 0x0 IO dss_data16 0x1 O mmc1_dat7 0x2 IO mmc2_dat3 0x3 IO eQEP2_strobe 0x4 IO pr1_ecap0_ecap_capin_apwm_o 0x5 IO gpio1_15 0x7 IO mcasp0_axr1 0x8 IO spi3_cs1 0x9 IO gpmc_advn_ale 0x0 O spi0_cs3 0x1 IO timer4 0x2 IO qspi_d0 0x3 IO gpio2_2 0x7 IO gpmc_be0n_cle 0x0 O spi1_cs3 0x1 IO timer5 0x2 IO qspi_d3 0x3 I pr1_mii1_rxlink 0x4 I gpmc_a5 0x5 O spi3_cs1 0x6 IO gpio2_5 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] A3 A12 A8 B9 F10 PIN NAME [2] gpmc_be1n gpmc_clk gpmc_csn0 gpmc_csn1 gpmc_csn2 SIGNAL NAME [3] MODE [4] TYPE [5] gpmc_be1n 0x0 O gmii2_col 0x1 I gpmc_csn6 0x2 O mmc2_dat3 0x3 IO gpmc_dir 0x4 O pr1_mii1_col 0x5 I mcasp0_aclkr 0x6 IO gpio1_28 0x7 IO gpmc_clk 0x0 IO gpmc_wait1 0x2 I mmc2_clk 0x3 IO pr1_mii1_crs 0x4 I pr1_mdio_mdclk 0x5 O mcasp0_fsr 0x6 IO gpio2_1 0x7 IO gpio0_4 0x9 IO gpmc_csn0 0x0 O qspi_csn 0x3 O gpio1_29 0x7 IO gpmc_csn1 0x0 O gpmc_clk 0x1 IO mmc1_clk 0x2 IO pr1_edio_data_in6 0x3 I pr1_edio_data_out6 0x4 O pr1_pru0_gpo8 0x5 O pr1_pru0_gpi8 0x6 I gpio1_30 0x7 IO gpmc_csn2 0x0 O gpmc_be1n 0x1 O mmc1_cmd 0x2 IO pr1_edio_data_in7 0x3 I pr1_edio_data_out7 0x4 O pr1_pru0_gpo9 0x5 O pr1_pru0_gpi9 0x6 I gpio1_31 0x7 IO gmii2_crs 0x8 I rmii2_crs_dv 0x9 I BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PU PU Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 45 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] B12 E10 A2 D10 B3 46 PIN NAME [2] gpmc_csn3 gpmc_oen_ren gpmc_wait0 gpmc_wen gpmc_wpn SIGNAL NAME [3] MODE [4] TYPE [5] gpmc_csn3 0x0 O gpmc_wait0 0x1 I qspi_clk 0x2 IO mmc2_cmd 0x3 IO pr1_mii0_crs 0x4 I pr1_mdio_data 0x5 IO EMU4 0x6 IO gpio2_0 0x7 IO gmii2_crs 0x8 I rmii2_crs_dv 0x9 I gpmc_oen_ren 0x0 O spi0_cs2 0x1 IO timer7 0x2 IO qspi_d1 0x3 I gpio2_3 0x7 IO gpmc_wait0 0x0 I gmii2_crs 0x1 I gpmc_csn4 0x2 O rmii2_crs_dv 0x3 I mmc1_sdcd 0x4 I pr1_mii1_crs 0x5 I uart4_rxd 0x6 I gpio0_30 0x7 IO gpio5_30 0x9 IO gpmc_wen 0x0 O spi1_cs2 0x1 IO timer6 0x2 IO qspi_d2 0x3 I gpio2_4 0x7 IO gpmc_wpn 0x0 O gmii2_rxer 0x1 I gpmc_csn5 0x2 O rmii2_rxer 0x3 I mmc2_sdcd 0x4 I pr1_mii1_rxer 0x5 I uart4_txd 0x6 O gpio0_31 0x7 IO gpio5_31 0x9 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PU PU Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] Y22 AB24 L23 N24 M24 PIN NAME [2] I2C0_SCL I2C0_SDA mcasp0_aclkr mcasp0_aclkx mcasp0_ahclkr SIGNAL NAME [3] MODE [4] TYPE [5] I2C0_SCL 0x0 IOD timer7 0x1 IO uart2_rtsn 0x2 O eCAP1_in_PWM1_out 0x3 IO gpio3_6 0x7 IO I2C0_SDA 0x0 IOD timer4 0x1 IO uart2_ctsn 0x2 IO eCAP2_in_PWM2_out 0x3 IO gpio3_5 0x7 IO mcasp0_aclkr 0x0 IO eQEP0A_in 0x1 I mcasp0_axr2 0x2 IO mcasp1_aclkx 0x3 IO mmc0_sdwp 0x4 I pr0_pru0_gpo4 0x5 O pr0_pru0_gpi4 0x6 I gpio3_18 0x7 IO gpio0_18 0x9 IO mcasp0_aclkx 0x0 IO ehrpwm0A 0x1 O spi0_cs3 0x2 IO spi1_sclk 0x3 IO mmc0_sdcd 0x4 I pr0_pru0_gpo0 0x5 O pr0_pru0_gpi0 0x6 I gpio3_14 0x7 IO mcasp0_ahclkr 0x0 IO ehrpwm0_synci 0x1 I mcasp0_axr2 0x2 IO spi1_cs0 0x3 IO eCAP2_in_PWM2_out 0x4 IO pr0_pru0_gpo3 0x5 O pr0_pru0_gpi3 0x6 I gpio3_17 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 47 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] L24 H23 M25 K23 48 PIN NAME [2] mcasp0_ahclkx mcasp0_axr0 mcasp0_axr1 mcasp0_fsr SIGNAL NAME [3] MODE [4] TYPE [5] mcasp0_ahclkx 0x0 IO eQEP0_strobe 0x1 IO mcasp0_axr3 0x2 IO mcasp1_axr1 0x3 IO EMU4 0x4 IO pr0_pru0_gpo7 0x5 O pr0_pru0_gpi7 0x6 I gpio3_21 0x7 IO gpio0_3 0x9 IO mcasp0_axr0 0x0 IO ehrpwm0_tripzone_input 0x1 I spi1_cs3 0x2 IO spi1_d1 0x3 IO mmc2_sdcd 0x4 I pr0_pru0_gpo2 0x5 O pr0_pru0_gpi2 0x6 I gpio3_16 0x7 IO mcasp0_axr1 0x0 IO eQEP0_index 0x1 IO mcasp1_axr0 0x3 IO EMU3 0x4 IO pr0_pru0_gpo6 0x5 O pr0_pru0_gpi6 0x6 I gpio3_20 0x7 IO gpio0_2 0x9 IO mcasp0_fsr 0x0 IO eQEP0B_in 0x1 I mcasp0_axr3 0x2 IO mcasp1_fsx 0x3 IO EMU2 0x4 IO pr0_pru0_gpo5 0x5 O pr0_pru0_gpi5 0x6 I gpio3_19 0x7 IO gpio0_19 0x9 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] N22 B17 A17 D16 PIN NAME [2] mcasp0_fsx mdio_clk mdio_data mii1_col SIGNAL NAME [3] MODE [4] TYPE [5] mcasp0_fsx 0x0 IO ehrpwm0B 0x1 O spi1_cs2 0x2 IO spi1_d0 0x3 IO mmc1_sdcd 0x4 I pr0_pru0_gpo1 0x5 O pr0_pru0_gpi1 0x6 I gpio3_15 0x7 IO mdio_clk 0x0 O timer5 0x1 IO uart5_txd 0x2 O uart3_rtsn 0x3 O mmc0_sdwp 0x4 I mmc1_clk 0x5 IO mmc2_clk 0x6 IO gpio0_1 0x7 IO pr1_mdio_mdclk 0x8 O mdio_data 0x0 IO timer6 0x1 IO uart5_rxd 0x2 I uart3_ctsn 0x3 IO mmc0_sdcd 0x4 I mmc1_cmd 0x5 IO mmc2_cmd 0x6 IO gpio0_0 0x7 IO pr1_mdio_data 0x8 IO gmii1_col 0x0 I rmii2_refclk 0x1 IO spi1_sclk 0x2 IO uart5_rxd 0x3 I mcasp1_axr2 0x4 IO mmc2_dat3 0x5 IO mcasp0_axr2 0x6 IO gpio3_0 0x7 IO gpio0_0 0x9 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV7 Yes 6 PU/PD LVCMOS PU PU Mode7 VDDSHV7 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 49 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] B14 F17 B16 E16 50 PIN NAME [2] mii1_crs mii1_rxd0 mii1_rxd1 mii1_rxd2 SIGNAL NAME [3] MODE [4] TYPE [5] gmii1_crs 0x0 I rmii1_crs_dv 0x1 I spi1_d0 0x2 IO I2C1_SDA 0x3 IOD mcasp1_aclkx 0x4 IO uart5_ctsn 0x5 I uart2_rxd 0x6 IO gpio3_1 0x7 IO gmii1_rxd0 0x0 I rmii1_rxd0 0x1 I rgmii1_rd0 0x2 I mcasp1_ahclkx 0x3 IO mcasp1_ahclkr 0x4 IO mcasp1_aclkr 0x5 IO mcasp0_axr3 0x6 IO gpio2_21 0x7 IO gmii1_rxd1 0x0 I rmii1_rxd1 0x1 I rgmii1_rd1 0x2 I mcasp1_axr3 0x3 IO mcasp1_fsr 0x4 IO eQEP0_strobe 0x5 IO mmc2_clk 0x6 IO gpio2_20 0x7 IO gmii1_rxd2 0x0 I uart3_txd 0x1 IO rgmii1_rd2 0x2 I mmc0_dat4 0x3 IO mmc1_dat3 0x4 IO uart1_rin 0x5 I mcasp0_axr1 0x6 IO gpio2_19 0x7 IO gpio0_11 0x9 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] C14 D13 A15 B13 PIN NAME [2] mii1_rxd3 mii1_rx_clk mii1_rx_dv mii1_rx_er SIGNAL NAME [3] MODE [4] TYPE [5] gmii1_rxd3 0x0 I uart3_rxd 0x1 IO rgmii1_rd3 0x2 I mmc0_dat5 0x3 IO mmc1_dat2 0x4 IO uart1_dtrn 0x5 O mcasp0_axr0 0x6 IO gpio2_18 0x7 IO gpio0_10 0x9 IO gmii1_rxclk 0x0 I uart2_txd 0x1 IO rgmii1_rclk 0x2 I mmc0_dat6 0x3 IO mmc1_dat1 0x4 IO uart1_dsrn 0x5 I mcasp0_fsx 0x6 IO gpio3_10 0x7 IO gpio0_9 0x9 IO gmii1_rxdv 0x0 I rgmii1_rctl 0x2 I uart5_txd 0x3 O mcasp1_aclkx 0x4 IO mmc2_dat0 0x5 IO mcasp0_aclkr 0x6 IO gpio3_4 0x7 IO gpio0_1 0x9 IO gmii1_rxer 0x0 I rmii1_rxer 0x1 I spi1_d1 0x2 IO I2C1_SCL 0x3 IOD mcasp1_fsx 0x4 IO uart5_rtsn 0x5 O uart2_txd 0x6 IO gpio3_2 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 51 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] B15 A14 C13 C16 52 PIN NAME [2] mii1_txd0 mii1_txd1 mii1_txd2 mii1_txd3 SIGNAL NAME [3] MODE [4] TYPE [5] gmii1_txd0 0x0 O rmii1_txd0 0x1 O rgmii1_td0 0x2 O mcasp1_axr2 0x3 IO mcasp1_aclkr 0x4 IO eQEP0B_in 0x5 I mmc1_clk 0x6 IO gpio0_28 0x7 IO gmii1_txd1 0x0 O rmii1_txd1 0x1 O rgmii1_td1 0x2 O mcasp1_fsr 0x3 IO mcasp1_axr1 0x4 IO eQEP0A_in 0x5 I mmc1_cmd 0x6 IO gpio0_21 0x7 IO gmii1_txd2 0x0 O dcan0_rx 0x1 I rgmii1_td2 0x2 O uart4_txd 0x3 O mcasp1_axr0 0x4 IO mmc2_dat2 0x5 IO mcasp0_ahclkx 0x6 IO gpio0_17 0x7 IO gpio3_12 0x9 IO gmii1_txd3 0x0 O dcan0_tx 0x1 O rgmii1_td3 0x2 O uart4_rxd 0x3 I mcasp1_fsx 0x4 IO mmc2_dat1 0x5 IO mcasp0_fsr 0x6 IO gpio0_16 0x7 IO gpio3_11 0x9 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] D14 A13 D1 D2 PIN NAME [2] mii1_tx_clk mii1_tx_en mmc0_clk mmc0_cmd SIGNAL NAME [3] MODE [4] TYPE [5] gmii1_txclk 0x0 I uart2_rxd 0x1 IO rgmii1_tclk 0x2 O mmc0_dat7 0x3 IO mmc1_dat0 0x4 IO uart1_dcdn 0x5 I mcasp0_aclkx 0x6 IO gpio3_9 0x7 IO gpio0_8 0x9 IO gmii1_txen 0x0 O rmii1_txen 0x1 O rgmii1_tctl 0x2 O timer4 0x3 IO mcasp1_axr0 0x4 IO eQEP0_index 0x5 IO mmc2_cmd 0x6 IO gpio3_3 0x7 IO mmc0_clk 0x0 IO gpmc_a24 0x1 O uart3_ctsn 0x2 IO uart2_rxd 0x3 IO dcan1_tx 0x4 O pr0_pru0_gpo12 0x5 O pr0_pru0_gpi12 0x6 I gpio2_30 0x7 IO mmc0_cmd 0x0 IO gpmc_a25 0x1 O uart3_rtsn 0x2 O uart2_txd 0x3 IO dcan1_rx 0x4 I pr0_pru0_gpo13 0x5 O pr0_pru0_gpi13 0x6 I gpio2_31 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 53 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] C1 C2 B2 B1 PIN NAME [2] mmc0_dat0 mmc0_dat1 mmc0_dat2 mmc0_dat3 SIGNAL NAME [3] MODE [4] TYPE [5] mmc0_dat0 0x0 IO gpmc_a23 0x1 O uart5_rtsn 0x2 O uart3_txd 0x3 IO uart1_rin 0x4 I pr0_pru0_gpo11 0x5 O pr0_pru0_gpi11 0x6 I gpio2_29 0x7 IO mmc0_dat1 0x0 IO gpmc_a22 0x1 O uart5_ctsn 0x2 I uart3_rxd 0x3 IO uart1_dtrn 0x4 O pr0_pru0_gpo10 0x5 O pr0_pru0_gpi10 0x6 I gpio2_28 0x7 IO mmc0_dat2 0x0 IO gpmc_a21 0x1 O uart4_rtsn 0x2 O timer6 0x3 IO uart1_dsrn 0x4 I pr0_pru0_gpo9 0x5 O pr0_pru0_gpi9 0x6 I gpio2_27 0x7 IO mmc0_dat3 0x0 IO gpmc_a20 0x1 O uart4_ctsn 0x2 I timer5 0x3 IO uart1_dcdn 0x4 I pr0_pru0_gpo8 0x5 O pr0_pru0_gpi8 0x6 I gpio2_26 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Y25 nTRST nTRST 0x0 I PD PD Mode0 VDDSHV3 Yes NA PU/PD LVCMOS Y23 PWRONRSTn porz 0x0 I Z Z Mode0 VDDSHV3 (13) Yes NA NA LVCMOS 54 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] AA10, AA7, AA9, AB10, AB6, AB7, AB9, AC10, AC12, AC5, AC6, AC7, AC9, AD1, AD10, AD11, AD2, AD7, AE11, AE12, AE9, H19, H21, W10, Y10, Y6, Y7 Reserved Reserved (7) NA NA NA NA NA NA NA NA NA NA A16 rmii1_ref_clk rmii1_refclk 0x0 IO PD PD Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS xdma_event_intr2 0x1 I spi1_cs0 0x2 IO uart5_txd 0x3 O mcasp1_axr3 0x4 IO mmc0_pow 0x5 O mcasp1_ahclkx 0x6 IO gpio0_29 0x7 IO AE2 RTC_KALDO_ENn RTC_KALDO_ENn 0x0 I Z Z Mode0 VDDS_RTC NA NA NA Analog AD6 RTC_PMIC_EN RTC_PMIC_EN 0x0 O PU 1 Mode0 VDDS_RTC NA 6 NA LVCMOS AE6 RTC_PWRONRSTn RTC_PORz 0x0 I Z Z Mode0 VDDS_RTC Yes NA NA LVCMOS AE3 RTC_WAKEUP RTC_WAKEUP 0x0 I PD Z Mode0 VDDS_RTC Yes NA NA LVCMOS AE5 RTC_XTALIN OSC1_IN 0x0 I H H Mode0 VDDS_RTC Yes NA PU (2) LVCMOS AE4 RTC_XTALOUT OSC1_OUT 0x0 O Z Z (24) Mode0 VDDS_RTC NA NA (14) NA LVCMOS T20 spi0_cs0 spi0_cs0 0x0 IO OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS mmc2_sdwp 0x1 I I2C1_SCL 0x2 IOD ehrpwm0_synci 0x3 I pr1_uart0_txd 0x4 O pr0_uart0_txd 0x5 O pr1_edio_data_out1 0x6 O gpio0_5 0x7 IO ehrpwm1B 0x8 O Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 55 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] R25 T22 T21 P23 56 PIN NAME [2] spi0_cs1 spi0_d0 spi0_d1 spi0_sclk SIGNAL NAME [3] MODE [4] TYPE [5] spi0_cs1 0x0 IO uart3_rxd 0x1 IO eCAP1_in_PWM1_out 0x2 IO mmc0_pow 0x3 O xdma_event_intr2 0x4 I mmc0_sdcd 0x5 I EMU4 0x6 IO gpio0_6 0x7 IO ehrpwm2A 0x8 O timer0 0x9 IO spi0_d0 0x0 IO uart2_txd 0x1 IO I2C2_SCL 0x2 IOD ehrpwm0B 0x3 O pr1_uart0_rts_n 0x4 O pr0_uart0_rts_n 0x5 O EMU3 0x6 IO gpio0_3 0x7 IO spi0_d1 0x0 IO mmc1_sdwp 0x1 I I2C1_SDA 0x2 IOD ehrpwm0_tripzone_input 0x3 I pr1_uart0_rxd 0x4 I pr0_uart0_rxd 0x5 I pr1_edio_data_out0 0x6 O gpio0_4 0x7 IO ehrpwm1A 0x8 O spi0_sclk 0x0 IO uart2_rxd 0x1 IO I2C2_SDA 0x2 IOD ehrpwm0A 0x3 O pr1_uart0_cts_n 0x4 I pr0_uart0_cts_n 0x5 I EMU2 0x6 IO gpio0_2 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] T23 P22 P20 N20 N25 R24 P24 P25 PIN NAME [2] spi2_cs0 spi2_d0 spi2_d1 spi2_sclk spi4_cs0 spi4_d0 spi4_d1 spi4_sclk SIGNAL NAME [3] MODE [4] TYPE [5] spi2_cs0 0x0 IO I2C1_SDA 0x1 IOD ehrpwm2_tripzone_input 0x6 I gpio3_25 0x7 IO gpio0_23 0x9 IO spi2_d0 0x0 IO ehrpwm5_tripzone_input 0x6 I gpio3_22 0x7 IO gpio0_20 0x9 IO spi2_d1 0x0 IO ehrpwm1_tripzone_input 0x6 I gpio3_23 0x7 IO gpio0_21 0x9 IO spi2_sclk 0x0 IO I2C1_SCL 0x1 IOD ehrpwm4_tripzone_input 0x6 I gpio3_24 0x7 IO gpio0_22 0x9 IO spi4_cs0 0x0 IO ehrpwm3_tripzone_input 0x6 I gpio5_7 0x7 IO spi4_d0 0x0 IO ehrpwm3_synci 0x6 I gpio5_5 0x7 IO spi4_d1 0x0 IO ehrpwm0_tripzone_input 0x6 I gpio5_6 0x7 IO spi4_sclk 0x0 IO ehrpwm0_synci 0x6 I BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] gpio5_4 0x7 IO AA25 TCK TCK 0x0 I PU PU Mode0 VDDSHV3 Yes NA PU/PD LVCMOS Y20 TDI TDI 0x0 I PU PU Mode0 VDDSHV3 Yes NA PU/PD LVCMOS AA24 TDO TDO 0x0 O PU PU Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS Y24 TMS TMS 0x0 I PU PU Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 57 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] L25 J25 K25 J24 58 PIN NAME [2] uart0_ctsn uart0_rtsn uart0_rxd uart0_txd SIGNAL NAME [3] MODE [4] TYPE [5] uart0_ctsn 0x0 I uart4_rxd 0x1 I dcan1_tx 0x2 O I2C1_SDA 0x3 IOD spi1_d0 0x4 IO timer7 0x5 IO pr1_edc_sync0_out 0x6 O gpio1_8 0x7 IO uart0_rtsn 0x0 O uart4_txd 0x1 O dcan1_rx 0x2 I I2C1_SCL 0x3 IOD spi1_d1 0x4 IO spi1_cs0 0x5 IO pr1_edc_sync1_out 0x6 O gpio1_9 0x7 IO uart0_rxd 0x0 I spi1_cs0 0x1 IO dcan0_tx 0x2 O I2C2_SDA 0x3 IOD eCAP2_in_PWM2_out 0x4 IO pr0_pru1_gpo4 0x5 O pr0_pru1_gpi4 0x6 I gpio1_10 0x7 IO uart0_txd 0x0 O spi1_cs1 0x1 IO dcan0_rx 0x2 I I2C2_SCL 0x3 IOD eCAP1_in_PWM1_out 0x4 IO pr0_pru1_gpo5 0x5 O pr0_pru1_gpi5 0x6 I gpio1_11 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS POWER [9] Terminal Configuration and Functions HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] K22 L22 K21 L21 H22 PIN NAME [2] uart1_ctsn uart1_rtsn uart1_rxd uart1_txd uart3_ctsn SIGNAL NAME [3] MODE [4] TYPE [5] uart1_ctsn 0x0 IO timer6 0x1 IO dcan0_tx 0x2 O I2C2_SDA 0x3 IOD spi1_cs0 0x4 IO pr1_uart0_cts_n 0x5 I pr1_edc_latch0_in 0x6 I gpio0_12 0x7 IO uart1_rtsn 0x0 O timer5 0x1 IO dcan0_rx 0x2 I I2C2_SCL 0x3 IOD spi1_cs1 0x4 IO pr1_uart0_rts_n 0x5 O pr1_edc_latch1_in 0x6 I gpio0_13 0x7 IO uart1_rxd 0x0 IO mmc1_sdwp 0x1 I dcan1_tx 0x2 O I2C1_SDA 0x3 IOD pr1_uart0_rxd 0x5 I pr1_pru0_gpi16 0x6 I gpio0_14 0x7 IO uart1_txd 0x0 IO mmc2_sdwp 0x1 I dcan1_rx 0x2 I I2C1_SCL 0x3 IOD pr1_uart0_txd 0x5 O pr1_pru0_gpi16 0x6 I gpio0_15 0x7 IO uart3_ctsn 0x0 IO spi4_cs1 0x2 IO pr0_pru1_gpo18 0x4 O pr0_pru1_gpi18 0x5 I ehrpwm5A 0x6 O gpio5_0 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 59 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] K24 H25 H24 PIN NAME [2] uart3_rtsn uart3_rxd uart3_txd SIGNAL NAME [3] MODE [4] TYPE [5] uart3_rtsn 0x0 O hdq_sio 0x1 IOD pr0_pru1_gpo19 0x4 O pr0_pru1_gpi19 0x5 I ehrpwm5B 0x6 O gpio5_1 0x7 IO uart3_rxd 0x0 IO pr0_pru0_gpo18 0x4 O pr0_pru0_gpi18 0x5 I ehrpwm4A 0x6 O gpio5_2 0x7 IO uart3_txd 0x0 IO pr0_pru0_gpo19 0x4 O pr0_pru0_gpi19 0x5 I ehrpwm4B 0x6 O gpio5_3 0x7 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS OFF PU Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] W22 USB0_CE USB0_CE 0x0 A Z Z Mode0 VDDA3P3V_USB0/V DDA1P8V_USB0 NA NA NA Analog W24 USB0_DM USB0_DM 0x0 A Z Z Mode0 VDDA3P3V_USB0/V DDA1P8V_USB0 NA (15) 8 (15) NA Analog W25 USB0_DP USB0_DP 0x0 A Z Z Mode0 VDDA3P3V_USB0/V DDA1P8V_USB0 NA (15) 8 (15) NA Analog G21 USB0_DRVVBUS USB0_DRVVBUS 0x0 O PD PD Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS gpio0_18 0x7 IO gpio5_27 0x9 IO U24 USB0_ID USB0_ID 0x0 A Z Z Mode0 VDDA3P3V_USB0/V DDA1P8V_USB0 NA NA NA Analog U23 USB0_VBUS USB0_VBUS 0x0 A Z Z Mode0 VDDA3P3V_USB0/V DDA1P8V_USB0 NA NA NA Analog U22 USB1_CE USB1_CE 0x0 A Z Z Mode0 VDDA3P3V_USB1/V DDA1P8V_USB1 NA NA NA Analog V25 USB1_DM USB1_DM 0x0 A Z Z Mode0 VDDA3P3V_USB1/V DDA1P8V_USB1 NA (16) 8 (16) NA Analog V24 USB1_DP USB1_DP 0x0 A Z Z Mode0 VDDA3P3V_USB1/V DDA1P8V_USB1 NA (16) 8 (16) NA Analog F25 USB1_DRVVBUS USB1_DRVVBUS 0x0 O PD PD Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS gpio3_13 0x7 IO gpio0_25 0x9 IO USB1_ID 0x0 A Z Z Mode0 VDDA3P3V_USB1/V DDA1P8V_USB1 NA NA NA Analog U25 60 USB1_ID Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] T25 USB1_VBUS USB1_VBUS 0x0 A Z Z Mode0 VDDA3P3V_USB1/V DDA1P8V_USB1 NA NA NA Analog W21 VDDA1P8V_USB0 VDDA1P8V_USB0 NA POWER NA NA NA NA NA NA NA NA U21 VDDA1P8V_USB1 VDDA1P8V_USB1 NA POWER NA NA NA NA NA NA NA NA W20 VDDA3P3V_USB0 VDDA3P3V_USB0 NA POWER NA NA NA NA NA NA NA NA U20 VDDA3P3V_USB1 VDDA3P3V_USB1 NA POWER NA NA NA NA NA NA NA NA AB12 VDDA_ADC0 VDDA_ADC0 NA POWER NA NA NA NA NA NA NA NA Y16 VDDA_ADC1 VDDA_ADC1 NA POWER NA NA NA NA NA NA NA NA AD12, AD8, VDDS F20, G6, H12, P19, W15, Y19 VDDS (1) NA POWER NA NA NA NA NA NA NA NA F8 VDDS3P3V_IOLDO VDDS3P3V_IOLDO NA POWER NA NA NA NA NA NA NA NA J7, J8 VDDSHV1 VDDSHV1 NA POWER NA NA NA NA NA NA NA NA V16, V17, W16 VDDSHV2 VDDSHV2 NA POWER NA NA NA NA NA NA NA NA J18, K17, K18, N18, N19, P18, W18 VDDSHV3 VDDSHV3 NA POWER NA NA NA NA NA NA NA NA F22 VDDSHV5 VDDSHV5 NA POWER NA NA NA NA NA NA NA NA G16, G17, H17 VDDSHV6 VDDSHV6 NA POWER NA NA NA NA NA NA NA NA F16 VDDSHV7 VDDSHV7 NA POWER NA NA NA NA NA NA NA NA G13, G14 VDDSHV8 VDDSHV8 NA POWER NA NA NA NA NA NA NA NA G11, H11 VDDSHV9 VDDSHV9 NA POWER NA NA NA NA NA NA NA NA G10, H10 VDDSHV10 VDDSHV10 NA POWER NA NA NA NA NA NA NA NA H8, H9 VDDSHV11 VDDSHV11 NA POWER NA NA NA NA NA NA NA NA E23 VDDS_CLKOUT VDDS_CLKOUT NA POWER NA NA NA NA NA NA NA NA K7, K8, M7, M8, N7, N8, R6, R7, R8, T7, T8, V7, V8 VDDS_DDR VDDS_DDR NA POWER NA NA NA NA NA NA NA NA C23 VDDS_OSC VDDS_OSC NA POWER NA NA NA NA NA NA NA NA N21 VDDS_PLL_CORE_LCD VDDS_PLL_CORE_LCD NA POWER NA NA NA NA NA NA NA NA G5 VDDS_PLL_DDR VDDS_PLL_DDR NA POWER NA NA NA NA NA NA NA NA E17 VDDS_PLL_MPU VDDS_PLL_MPU NA POWER NA NA NA NA NA NA NA NA AD5 VDDS_RTC VDDS_RTC NA POWER NA NA NA NA NA NA NA NA F13 VDDS_SRAM_CORE_BG VDDS_SRAM_CORE_BG NA POWER NA NA NA NA NA NA NA NA F14 VDDS_SRAM_MPU_BB VDDS_SRAM_MPU_BB NA POWER NA NA NA NA NA NA NA NA Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 61 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] AD9, J10, VDD_CORE J11, L12, L14, M12, M14, M9, N16, N17, N9, P16, P17, R11, R14, R9, T11, T14, T18, T19, T9, U15, V15, W12, W13 VDD_CORE (11) NA POWER NA NA NA NA NA NA NA NA H13, H14, VDD_MPU H16, J13, J14, J16, K19, K20, L19, L20, M17, M18 VDD_MPU NA POWER NA NA NA NA NA NA NA NA D20 vdd_mpu_mon vdd_mpu_mon (25) NA POWER NA NA NA NA NA NA NA NA P21 VPP VPP (18) NA POWER NA NA NA NA NA NA NA NA A1, A25, VSS AA23, AE1, AE10, AE25, AE7, AE8, H15, H18, J12, J15, J17, J9, K11, K12, K14, K15, K9, L11, L15, L17, L18, L8, L9, M10, M11, M13, M15, M16, N10, N11, N12, N13, N14, N15, P10, P11, P12, P13, P14, P15, P8, P9, R12, R15, R17, R18, T12, T15, T17, U10, U11, U12, U13, U14, U16, U17, U18, U19, U8, U9, V10, V11, V12, V13, V14, V18, V9 VSS (12) NA GROUND NA NA NA NA NA NA NA NA AC15 VSSA_ADC VSSA_ADC NA GROUND NA NA NA NA NA NA NA NA W23 VSSA_USB VSSA_USB NA GROUND NA NA NA NA NA NA NA NA B24 VSS_OSC VSS_OSC (26) NA GROUND NA NA NA NA NA NA NA NA AD4 VSS_RTC VSS_RTC (27) NA GROUND NA NA NA NA NA NA NA NA G22 WARMRSTn nRESETIN_OUT 0x0 IOD (9) OFF PU (17) Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS 62 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-10. Pin Attributes (ZDN Package) (continued) BALL NUMBER [1] D24 C24 PIN NAME [2] xdma_event_intr0 xdma_event_intr1 SIGNAL NAME [3] MODE [4] TYPE [5] xdma_event_intr0 0x0 I ext_hw_trigger 0x1 I timer4 0x2 IO clkout1 0x3 O spi1_cs1 0x4 IO pr1_pru0_gpi16 0x5 I EMU2 0x6 IO gpio0_19 0x7 IO pr1_mdio_data 0x8 IO gpio5_28 0x9 IO xdma_event_intr1 0x0 I spi0_cs2 0x1 IO tclkin 0x2 I clkout2 0x3 O timer7 0x4 IO pr1_pru0_gpi16 0x5 I EMU3 0x6 IO gpio0_20 0x7 IO pr1_mdio_mdclk 0x8 O gpio5_29 0x9 IO BALL RESET STATE [6] BALL BALL RESET RESET REL. MODE REL. [8] STATE [7] OFF PD (8) Mode7 VDDSHV5 Yes 6 PU/PD LVCMOS OFF PD Mode7 VDDSHV5 Yes 6 PU/PD LVCMOS POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13] C25 XTALIN OSC0_IN 0x0 (3) I Z Z Mode0 VDDS_OSC Yes NA PD LVCMOS B25 XTALOUT OSC0_OUT 0x0 O Z Z Mode0 VDDS_OSC NA NA (14) NA LVCMOS (1) AD12 and AD8 are not connected to VDDS in the device, but they are required to be connected to 1.8-V VDDS on the board. (2) An internal 10-k pullup is turned on when the oscillator is disabled. The oscillator is disabled by default after power is applied. (3) An internal 15-k pulldown is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied. (4) DSS_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn. (5) DSS_HSYNC terminal is SYSBOOT[17] input, latched on the rising edge of PWRONRSTn. (6) DSS_VSYNC terminal is SYSBOOT[16] input, latched on the rising edge of PWRONRSTn. (7) Do not connect any signal, test point, or board trace to reserved signals. (8) If sysboot[17] is low on the rising edge of PWRONRSTn, this terminal has an internal pulldown turned on after reset is released. If sysboot[17] is high on the rising edge or PWRONRSTn, this terminal will initially be driven low after reset is released then it begins to toggle at the same frequency of the OSC0_IN terminal. (9) See the External Warm Reset section of the Technical Reference Manual for more information related to the operation of this terminal. (10) Reset Release Mode = 7 if sysboot[17] is low. Mode = 3 if sysboot[17] is high. (11) Terminal AD9 is not connected to VDD_CORE in the device, but it is required to be connected to VDD_CORE on the board. (12) Terminals AA23, AE10, AE7, AE8 are not connected to VSS in the device, but they are required to be connected to board ground. Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 63 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com (13) The input voltage thresholds for this input are not a function of VDDSHV3. See the DC Electrical Characteristics section for details related to electrical parameters associated with this input terminal. (14) This output should only be used to source the recommended crystal circuit. (15) This parameter only applies when this USB PHY terminal is operating in UART2 mode. (16) This parameter only applies when this USB PHY terminal is operating in UART3 mode. (17) This pin is configured as open-drain and, hence, is expected to have an external pullup resistor. However, there is also an internal PU resistor by default enabled after reset is deasserted. (18) This signal is valid only for High-Security (AM437xHS) devices. For more details, see the VPP Specification for One-Time Programmable (OTP) eFUSEs section. This signal is reserved for AM437x devices and, thus, do not connect any signal, test point, or board trace to this signal for AM437x devices. (19) This terminal is an analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2). (20) This terminal is an analog passive signal that connects to an external 49.9 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers. (21) This terminal is analog input that may also be configured as an open-drain output. (22) This terminal is analog input that may also be configured as an open-source or open-drain output. (23) This terminal is analog input that may also be configured as an open-source output. (24) This terminal is high-Z when the oscillator is disabled. This terminal is driven high if RTC_XTALIN is less than VIL, driven low if RTC_XTALIN is greater than VIH, and driven to a unknown value if RTC_XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is disabled by default after power is applied. (25) This terminal provides a Kelvin connection to VDD_MPU. It can be connected to the power supply feedback input to provide remote sensing which compensates for voltage drop in the PCB power distribution network and package. When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU. (26) This terminal provides a Kelvin ground reference for the external crystal components. If a crystal circuit is connected to the OSC0_IN/OSC0_OUT terminals, the crystal circuit component grounds should be connected to this terminal and also be connected to the PCB ground plane close to this terminal. If an external LVCMOS clock source is connected to the OSC0_IN terminal, this terminal should be connected to VSS. (27) This terminal provides a Kelvin ground reference for the external crystal components. If a crystal circuit is connected to the OSC1_IN/OSC1_OUT terminals, the crystal circuit component grounds should be connected to this terminal and also should be connected to the PCB ground plane close to this terminal. If an external LVCMOS clock source is connected to the OSC1_IN terminal, this terminal should be connected to VSS. 64 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 4.3 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Signal Descriptions The device contains many peripheral interfaces. In order to reduce package size and lower overall system cost while maintaining maximum functionality, many of the terminals can multiplex up to eight signal functions. Although there are many combinations of pin multiplexing that are possible, only a certain number of sets, called IO Sets, are valid due to timing limitations. These valid IO Sets were carefully chosen to provide many possible application scenarios for the user. TI has developed a Windows-based application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their device-based product design. The Pin Mux Utility provides a way to select valid IO Sets of specific peripheral interfaces to ensure the pin-multiplexing configuration selected for a design only uses valid IO Sets supported by the device. (1) SIGNAL NAME: The signal name (2) DESCRIPTION: Description of the signal. (3) TYPE: Ball type for this specific function: - I = Input - O = Output - I/O = Input/Output - D = Open drain - DS = Differential - A = Analog (4) BALL: Package ball location. 4.3.1 ADC Interfaces Table 4-11. ADC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] ADC0_AIN0 Analog Input/Output A AA12 ADC0_AIN1 Analog Input/Output A Y12 ADC0_AIN2 Analog Input/Output A Y13 ADC0_AIN3 Analog Input/Output A AA13 ADC0_AIN4 Analog Input/Output A AB13 ADC0_AIN5 Analog Input/Output A AC13 ADC0_AIN6 Analog Input/Output A AD13 ADC0_AIN7 Analog Input/Output A AE13 ADC0_VREFN Analog Negative Reference Input AP AE14 ADC0_VREFP Analog Positive Reference Input AP AD14 Table 4-12. ADC0/1 Signal Descriptions SIGNAL NAME [1] ext_hw_trigger DESCRIPTION [2] External Hardware Trigger for ADC conversion TYPE [3] ZDN [4] I AC25, D24 TYPE [3] ZDN [4] Table 4-13. ADC1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] ADC1_AIN0 Analog Input/Output A AC16 ADC1_AIN1 Analog Input/Output A AB16 ADC1_AIN2 Analog Input/Output A AA16 ADC1_AIN3 Analog Input/Output A AB15 ADC1_AIN4 Analog Input/Output A AA15 ADC1_AIN5 Analog Input/Output A Y15 ADC1_AIN6 Analog Input/Output A AE16 ADC1_AIN7 Analog Input/Output A AD16 ADC1_VREFN Analog Negative Reference Input AP AD15 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 65 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-13. ADC1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] ADC1_VREFP 66 Analog Positive Reference Input Terminal Configuration and Functions TYPE [3] ZDN [4] AP AE15 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 4.3.2 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 CAN Interfaces Table 4-14. DCAN0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] dcan0_rx DCAN0 Receive Data I C13, J24, L22 dcan0_tx DCAN0 Transmit Data O C16, K22, K25 Table 4-15. DCAN1 Signal Descriptions TYPE [3] ZDN [4] dcan1_rx SIGNAL NAME [1] DCAN1 Receive Data DESCRIPTION [2] I D2, J25, L21 dcan1_tx DCAN1 Transmit Data O D1, K21, L25 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 67 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.3 www.ti.com Camera (VPFE) Interfaces Table 4-16. Camera0 Input Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] cam0_data0 Camera data I AE18 cam0_data1 Camera data I AB18 cam0_data2 Camera data I Y18 cam0_data3 Camera data I AA18 cam0_data4 Camera data I AE19 cam0_data5 Camera data I AD19 cam0_data6 Camera data I AE20 cam0_data7 Camera data I AD20 cam0_data8 Camera data I AB19 cam0_data9 Camera data I AA19 cam0_data10 Camera data I AC18, AC25 cam0_data11 Camera data I AB25, AD17 cam0_field CCD Data Field Indicator IO AC18 cam0_hd CCD Data Horizontal Detect IO AE17 cam0_pclk CCD Data Pixel Clock cam0_vd CCD Data Vertical Detect cam0_wen CCD Data Write Enable I AC20 IO AD18 I AD17 TYPE [3] ZDN [4] Table 4-17. Camera1 Input Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] cam1_data0 Camera data I AB20 cam1_data1 Camera data I AC21 cam1_data2 Camera data I AD21 cam1_data3 Camera data I AE22 cam1_data4 Camera data I AD22 cam1_data5 Camera data I AE23 cam1_data6 Camera data I AD23 cam1_data7 Camera data I AE24 cam1_data8 Camera data I AB18, AD24 cam1_data9 Camera data I AC24, AE18 cam1_data10 Camera data I AC18, AC25, Y18 cam1_data11 Camera data I AA18, AB25, AD17 cam1_field CCD Data Field Indicator IO AC25 cam1_hd CCD Data Horizontal Detect IO AD25 cam1_pclk CCD Data Pixel Clock cam1_vd CCD Data Vertical Detect cam1_wen CCD Data Write Enable 68 Terminal Configuration and Functions I AE21 IO AC23 I AB25, AE19 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 4.3.4 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Debug Subsystem Interface Table 4-18. Debug Subsystem Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] N23 EMU0 MISC EMULATION PIN IO EMU1 MISC EMULATION PIN IO T24 EMU2 MISC EMULATION PIN IO AE17, D24, K23, P23 EMU3 MISC EMULATION PIN IO AD18, C24, M25, T22 EMU4 MISC EMULATION PIN IO AC18, B12, L24, R25 EMU5 MISC EMULATION PIN IO AD17 EMU6 MISC EMULATION PIN IO AC20 EMU7 MISC EMULATION PIN IO AB19 EMU8 MISC EMULATION PIN IO AA19 EMU9 MISC EMULATION PIN IO AC24 EMU10 MISC EMULATION PIN IO AD24, AE17 EMU11 MISC EMULATION PIN IO AB25, AD18 nTRST JTAG TEST RESET (ACTIVE LOW) I Y25 TCK JTAG TEST CLOCK I AA25 TDI JTAG TEST DATA INPUT I Y20 TDO JTAG TEST DATA OUTPUT O AA24 TMS JTAG TEST MODE SELECT I Y24 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 69 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.5 www.ti.com Display Subsystem (DSS) Interface Table 4-19. Display Subsystem (DSS) Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] dss_ac_bias_en DSS data O A24 dss_data0 DSS data IO B22 dss_data1 DSS data IO A21 dss_data2 DSS data IO B21 dss_data3 DSS data IO C21 dss_data4 DSS data IO A20 dss_data5 DSS data IO B20 dss_data6 DSS data IO C20 dss_data7 DSS data IO E19 dss_data8 DSS data IO A19 dss_data9 DSS data IO B19 dss_data10 DSS data IO A18 dss_data11 DSS data IO B18 dss_data12 DSS data IO C19 dss_data13 DSS data IO D19 dss_data14 DSS data IO C17 dss_data15 DSS data IO D17 dss_data16 DSS data O A11, AC24 dss_data17 DSS data O AA19, B11 dss_data18 DSS data O AB19, C11 dss_data19 DSS data O AC20, E11 dss_data20 DSS data O AD17, D11 dss_data21 DSS data O AC18, F11 dss_data22 DSS data O A10, AD18 dss_data23 DSS data O AE17, B10 dss_hsync DSS Horizontal Sync O A23 dss_pclk DSS Pixel Clock O A22 dss_vsync DSS Vertical Sync O B23 70 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 4.3.6 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Ethernet (GEMAC_CPSW) Interfaces Table 4-20. MDIO Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] mdio_clk MDIO Clk O B17 mdio_data MDIO Data IO A17 Table 4-21. MII1 Signal Descriptions TYPE [3] ZDN [4] gmii1_col SIGNAL NAME [1] MII Colision DESCRIPTION [2] I D16 gmii1_crs MII Carrier Sense I B14 gmii1_rxclk MII Receive Clock I D13 gmii1_rxd0 MII Receive Data bit 0 I F17 gmii1_rxd1 MII Receive Data bit 1 I B16 gmii1_rxd2 MII Receive Data bit 2 I E16 gmii1_rxd3 MII Receive Data bit 3 I C14 gmii1_rxdv MII Receive Data Valid I A15 gmii1_rxer MII Receive Data Error I B13 gmii1_txclk MII Transmit Clock I D14 gmii1_txd0 MII Transmit Data bit 0 O B15 gmii1_txd1 MII Transmit Data bit 1 O A14 gmii1_txd2 MII Transmit Data bit 2 O C13 gmii1_txd3 MII Transmit Data bit 3 O C16 gmii1_txen MII Transmit Enable O A13 Table 4-22. MII2 Signal Descriptions TYPE [3] ZDN [4] gmii2_col SIGNAL NAME [1] MII Colision DESCRIPTION [2] I A3 gmii2_crs MII Carrier Sense I A2, B12, F10 gmii2_rxclk MII Receive Clock I F6 gmii2_rxd0 MII Receive Data bit 0 I D8 gmii2_rxd1 MII Receive Data bit 1 I G8 gmii2_rxd2 MII Receive Data bit 2 I B4 gmii2_rxd3 MII Receive Data bit 3 I F7 gmii2_rxdv MII Receive Data Valid I C5 gmii2_rxer MII Receive Data Error I B3 gmii2_txclk MII Transmit Clock I E8 gmii2_txd0 MII Transmit Data bit 0 O E7 gmii2_txd1 MII Transmit Data bit 1 O D7 gmii2_txd2 MII Transmit Data bit 2 O A4 gmii2_txd3 MII Transmit Data bit 3 O C6 gmii2_txen MII Transmit Enable O C3 Table 4-23. RGMII1 Signal Descriptions TYPE [3] ZDN [4] rgmii1_rclk SIGNAL NAME [1] RGMII Receive Clock DESCRIPTION [2] I D13 rgmii1_rctl RGMII Receive Control I A15 rgmii1_rd0 RGMII Receive Data bit 0 I F17 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 71 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-23. RGMII1 Signal Descriptions (continued) TYPE [3] ZDN [4] rgmii1_rd1 SIGNAL NAME [1] RGMII Receive Data bit 1 DESCRIPTION [2] I B16 rgmii1_rd2 RGMII Receive Data bit 2 I E16 rgmii1_rd3 RGMII Receive Data bit 3 I C14 rgmii1_tclk RGMII Transmit Clock O D14 rgmii1_tctl RGMII Transmit Control O A13 rgmii1_td0 RGMII Transmit Data bit 0 O B15 rgmii1_td1 RGMII Transmit Data bit 1 O A14 rgmii1_td2 RGMII Transmit Data bit 2 O C13 rgmii1_td3 RGMII Transmit Data bit 3 O C16 TYPE [3] ZDN [4] Table 4-24. RGMII2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] rgmii2_rclk RGMII Receive Clock I F6 rgmii2_rctl RGMII Receive Control I C5 rgmii2_rd0 RGMII Receive Data bit 0 I D8 rgmii2_rd1 RGMII Receive Data bit 1 I G8 rgmii2_rd2 RGMII Receive Data bit 2 I B4 rgmii2_rd3 RGMII Receive Data bit 3 I F7 rgmii2_tclk RGMII Transmit Clock O E8 rgmii2_tctl RGMII Transmit Control O C3 rgmii2_td0 RGMII Transmit Data bit 0 O E7 rgmii2_td1 RGMII Transmit Data bit 1 O D7 rgmii2_td2 RGMII Transmit Data bit 2 O A4 rgmii2_td3 RGMII Transmit Data bit 3 O C6 TYPE [3] ZDN [4] I B14 IO A16 Table 4-25. RMII1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] rmii1_crs_dv RMII Carrier Sense / Data Valid rmii1_refclk RMII Reference Clock rmii1_rxd0 RMII Receive Data bit 0 I F17 rmii1_rxd1 RMII Receive Data bit 1 I B16 rmii1_rxer RMII Receive Data Error I B13 rmii1_txd0 RMII Transmit Data bit 0 O B15 rmii1_txd1 RMII Transmit Data bit 1 O A14 rmii1_txen RMII Transmit Enable O A13 Table 4-26. RMII2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] I A2, B12, B4, F10 IO D16 I D8 RMII Receive Data bit 1 I G8 RMII Receive Data Error I B3 rmii2_txd0 RMII Transmit Data bit 0 O E7 rmii2_txd1 RMII Transmit Data bit 1 O D7 rmii2_txen RMII Transmit Enable O C3 rmii2_crs_dv RMII Carrier Sense / Data Valid rmii2_refclk RMII Reference Clock rmii2_rxd0 RMII Receive Data bit 0 rmii2_rxd1 rmii2_rxer 72 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 4.3.7 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 External Memory Interfaces Table 4-27. DDR Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] ddr_a0 DDR SDRAM ROW/COLUMN ADDRESS O N1 ddr_a1 DDR SDRAM ROW/COLUMN ADDRESS O L1 ddr_a2 DDR SDRAM ROW/COLUMN ADDRESS O L2 ddr_a3 DDR SDRAM ROW/COLUMN ADDRESS O P2 ddr_a4 DDR SDRAM ROW/COLUMN ADDRESS O P1 ddr_a5 DDR SDRAM ROW/COLUMN ADDRESS O R5 ddr_a6 DDR SDRAM ROW/COLUMN ADDRESS O R4 ddr_a7 DDR SDRAM ROW/COLUMN ADDRESS O R3 ddr_a8 DDR SDRAM ROW/COLUMN ADDRESS O R2 ddr_a9 DDR SDRAM ROW/COLUMN ADDRESS O R1 ddr_a10 DDR SDRAM ROW/COLUMN ADDRESS O M6 ddr_a11 DDR SDRAM ROW/COLUMN ADDRESS O T5 ddr_a12 DDR SDRAM ROW/COLUMN ADDRESS O T4 ddr_a13 DDR SDRAM ROW/COLUMN ADDRESS O N5 ddr_a14 DDR SDRAM ROW/COLUMN ADDRESS O T3 ddr_a15 DDR SDRAM ROW/COLUMN ADDRESS O T2 ddr_ba0 DDR SDRAM BANK ADDRESS O K1 ddr_ba1 DDR SDRAM BANK ADDRESS O K2 ddr_ba2 DDR SDRAM BANK ADDRESS O K3 ddr_casn DDR SDRAM COLUMN ADDRESS STROBE. (ACTIVE LOW) O N3 ddr_ck DDR SDRAM CLOCK (Differential+) O M2 ddr_cke0 DDR SDRAM CLOCK ENABLE O M3 ddr_cke1 DDR SDRAM CLOCK ENABLE1 O N6 ddr_csn0 DDR SDRAM CHIP SELECT0 O M5 ddr_csn1 DDR SDRAM CHIP SELECT1 O M4 ddr_d0 DDR SDRAM DATA IO E3 ddr_d1 DDR SDRAM DATA IO E2 ddr_d2 DDR SDRAM DATA IO E1 ddr_d3 DDR SDRAM DATA IO F3 ddr_d4 DDR SDRAM DATA IO G4 ddr_d5 DDR SDRAM DATA IO G3 ddr_d6 DDR SDRAM DATA IO G2 ddr_d7 DDR SDRAM DATA IO G1 ddr_d8 DDR SDRAM DATA IO H1 ddr_d9 DDR SDRAM DATA IO J6 ddr_d10 DDR SDRAM DATA IO J5 ddr_d11 DDR SDRAM DATA IO J4 ddr_d12 DDR SDRAM DATA IO J3 ddr_d13 DDR SDRAM DATA IO K6 ddr_d14 DDR SDRAM DATA IO K5 ddr_d15 DDR SDRAM DATA IO K4 ddr_d16 DDR SDRAM DATA IO V5 ddr_d17 DDR SDRAM DATA IO V4 ddr_d18 DDR SDRAM DATA IO V3 ddr_d19 DDR SDRAM DATA IO V2 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 73 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-27. DDR Signal Descriptions (continued) TYPE [3] ZDN [4] ddr_d20 SIGNAL NAME [1] DDR SDRAM DATA DESCRIPTION [2] IO V1 ddr_d21 DDR SDRAM DATA IO W4 ddr_d22 DDR SDRAM DATA IO W5 ddr_d23 DDR SDRAM DATA IO W6 ddr_d24 DDR SDRAM DATA IO Y2 ddr_d25 DDR SDRAM DATA IO Y3 ddr_d26 DDR SDRAM DATA IO Y4 ddr_d27 DDR SDRAM DATA IO AA3 ddr_d28 DDR SDRAM DATA IO AB2 ddr_d29 DDR SDRAM DATA IO AB1 ddr_d30 DDR SDRAM DATA IO AC1 ddr_d31 DDR SDRAM DATA IO AC2 ddr_dqm0 DDR WRITE ENABLE / DATA MASK FOR DATA[7:0] O F4 ddr_dqm1 DDR WRITE ENABLE / DATA MASK FOR DATA[15:8] O H2 ddr_dqm2 DDR WRITE ENABLE / DATA MASK FOR DATA[23:16] O V6 ddr_dqm3 DDR WRITE ENABLE / DATA MASK FOR DATA[31:24] O Y1 ddr_dqs0 DDR DATA STROBE FOR DATA[7:0] (Differential+) IO F2 ddr_dqs1 DDR DATA STROBE FOR DATA[15:8] (Differential+) IO J2 ddr_dqs2 DDR DATA STROBE FOR DATA[23:16] (Differential+) IO W1 ddr_dqs3 DDR DATA STROBE FOR DATA[31:24] (Differential+) IO AA1 ddr_dqsn0 DDR DATA STROBE FOR DATA[7:0] (Differential-) IO F1 ddr_dqsn1 DDR DATA STROBE FOR DATA[15:8] (Differential-) IO J1 ddr_dqsn2 DDR DATA STROBE FOR DATA[23:16] (Differential-) IO W2 ddr_dqsn3 DDR DATA STROBE FOR DATA[31:24] (Differential-) IO AA2 ddr_nck DDR SDRAM CLOCK (Differential-) O M1 ddr_odt0 DDR SDRAM ODT0 O U1 ddr_odt1 DDR SDRAM ODT1 O U2 ddr_rasn DDR SDRAM ROW ADDRESS STROBE (ACTIVE LOW) O N2 ddr_resetn DDR SDRAM RESET (only for DDR3) O T1 ddr_vref Voltage Reference ddr_vtp External Resistor for Impedance Training ddr_wen DDR SDRAM WRITE ENABLE (ACTIVE LOW) AP (1) T6 I (2) AC3 O N4 (1) This terminal is an analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2). (2) This terminal is an analog passive signal that connects to an external 49.9 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers. Table 4-28. General Purpose Memory Controller (GPMC) Signal Descriptions TYPE [3] ZDN [4] gpmc_a0 SIGNAL NAME [1] GPMC Address O B22, C3 gpmc_a1 GPMC Address O A21, B23, C5 gpmc_a2 GPMC Address O A23, B21, C6 gpmc_a3 GPMC Address O A22, A4, C21 gpmc_a4 GPMC Address O A20, A24, D7 gpmc_a5 GPMC Address O B20, C10, E7 gpmc_a6 GPMC Address O C20, E8 gpmc_a7 GPMC Address O E19, F6 gpmc_a8 GPMC Address O B23, F7 74 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-28. General Purpose Memory Controller (GPMC) Signal Descriptions (continued) TYPE [3] ZDN [4] gpmc_a9 SIGNAL NAME [1] GPMC Address DESCRIPTION [2] O A23, B4 gpmc_a10 GPMC Address O A22, G8 gpmc_a11 GPMC Address O A24, D8 gpmc_a12 GPMC Address O A19 gpmc_a13 GPMC Address O B19 gpmc_a14 GPMC Address O A18 gpmc_a15 GPMC Address O B18 gpmc_a16 GPMC Address O C19, C3 gpmc_a17 GPMC Address O C5, D19 gpmc_a18 GPMC Address O C17, C6 gpmc_a19 GPMC Address O A4, D17 gpmc_a20 GPMC Address O B1, D7 gpmc_a21 GPMC Address O B2, E7 gpmc_a22 GPMC Address O C2, E8 gpmc_a23 GPMC Address O C1, F6 gpmc_a24 GPMC Address O D1, F7 gpmc_a25 GPMC Address O B4, D2 gpmc_a26 GPMC Address O G8 gpmc_a27 GPMC Address O D8 gpmc_ad0 GPMC Address and Data IO B5 gpmc_ad1 GPMC Address and Data IO A5 gpmc_ad2 GPMC Address and Data IO B6 gpmc_ad3 GPMC Address and Data IO A6 gpmc_ad4 GPMC Address and Data IO B7 gpmc_ad5 GPMC Address and Data IO A7 gpmc_ad6 GPMC Address and Data IO C8 gpmc_ad7 GPMC Address and Data IO B8 gpmc_ad8 GPMC Address and Data IO B10 gpmc_ad9 GPMC Address and Data IO A10 gpmc_ad10 GPMC Address and Data IO F11 gpmc_ad11 GPMC Address and Data IO D11 gpmc_ad12 GPMC Address and Data IO E11 gpmc_ad13 GPMC Address and Data IO C11 gpmc_ad14 GPMC Address and Data IO B11 gpmc_ad15 GPMC Address and Data IO A11 gpmc_advn_ale GPMC Address Valid / Address Latch Enable O A9 gpmc_be0n_cle GPMC Byte Enable 0 / Command Latch Enable O C10 gpmc_be1n GPMC Byte Enable 1 O A3, F10 gpmc_clk GPMC Clock IO A12, B9 gpmc_csn0 GPMC Chip Select O A8 gpmc_csn1 GPMC Chip Select O B9 gpmc_csn2 GPMC Chip Select O F10 gpmc_csn3 GPMC Chip Select O B12 gpmc_csn4 GPMC Chip Select O A2 gpmc_csn5 GPMC Chip Select O B3 gpmc_csn6 GPMC Chip Select O A3 gpmc_dir GPMC Data Direction O A3 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 75 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-28. General Purpose Memory Controller (GPMC) Signal Descriptions (continued) TYPE [3] ZDN [4] gpmc_oen_ren SIGNAL NAME [1] GPMC Output / Read Enable O E10 gpmc_wait0 GPMC Wait 0 I A2, B12 gpmc_wait1 GPMC Wait 1 I A12 gpmc_wen GPMC Write Enable O D10 gpmc_wpn GPMC Write Protect O B3 76 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 4.3.8 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 General Purpose IOs Table 4-29. GPIO0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] A17, D16 gpio0_0 GPIO IO gpio0_1 GPIO IO A15, B17 gpio0_2 GPIO IO M25, P23 gpio0_3 GPIO IO L24, T22 gpio0_4 GPIO IO A12, T21 gpio0_5 GPIO IO T20 gpio0_6 GPIO IO R25 gpio0_7 GPIO IO G24 gpio0_8 GPIO IO C19, D14 gpio0_9 GPIO IO D13, D19 gpio0_10 GPIO IO C14, C17 gpio0_11 GPIO IO D17, E16 gpio0_12 GPIO IO K22 gpio0_13 GPIO IO L22 gpio0_14 GPIO IO K21 gpio0_15 GPIO IO L21 gpio0_16 GPIO IO C16 gpio0_17 GPIO IO C13 gpio0_18 GPIO IO G21, L23 gpio0_19 GPIO IO D24, K23 gpio0_20 GPIO IO C24, P22 gpio0_21 GPIO IO A14, P20 gpio0_22 GPIO IO B10, N20 gpio0_23 GPIO IO A10, T23 gpio0_24 GPIO IO H20 gpio0_25 GPIO IO F25 gpio0_26 GPIO IO F11 gpio0_27 GPIO IO D11 gpio0_28 GPIO IO B15 gpio0_29 GPIO IO A16 gpio0_30 GPIO IO A2 gpio0_31 GPIO IO B3 Table 4-30. GPIO1 Signal Descriptions TYPE [3] ZDN [4] gpio1_0 SIGNAL NAME [1] GPIO DESCRIPTION [2] IO B5 gpio1_1 GPIO IO A5 gpio1_2 GPIO IO B6 gpio1_3 GPIO IO A6 gpio1_4 GPIO IO B7 gpio1_5 GPIO IO A7 gpio1_6 GPIO IO C8 gpio1_7 GPIO IO B8 gpio1_8 GPIO IO L25 gpio1_9 GPIO IO J25 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 77 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-30. GPIO1 Signal Descriptions (continued) TYPE [3] ZDN [4] gpio1_10 SIGNAL NAME [1] GPIO DESCRIPTION [2] IO K25 gpio1_11 GPIO IO J24 gpio1_12 GPIO IO E11 gpio1_13 GPIO IO C11 gpio1_14 GPIO IO B11 gpio1_15 GPIO IO A11 gpio1_16 GPIO IO C3 gpio1_17 GPIO IO C5 gpio1_18 GPIO IO C6 gpio1_19 GPIO IO A4 gpio1_20 GPIO IO D7 gpio1_21 GPIO IO E7 gpio1_22 GPIO IO E8 gpio1_23 GPIO IO F6 gpio1_24 GPIO IO F7 gpio1_25 GPIO IO B4 gpio1_26 GPIO IO G8 gpio1_27 GPIO IO D8 gpio1_28 GPIO IO A3 gpio1_29 GPIO IO A8 gpio1_30 GPIO IO B9 gpio1_31 GPIO IO F10 Table 4-31. GPIO2 Signal Descriptions TYPE [3] ZDN [4] gpio2_0 SIGNAL NAME [1] GPIO IO B12 gpio2_1 GPIO IO A12 gpio2_2 GPIO IO A9 gpio2_3 GPIO IO E10 gpio2_4 GPIO IO D10 gpio2_5 GPIO IO C10 gpio2_6 GPIO IO B22 gpio2_7 GPIO IO A21 gpio2_8 GPIO IO B21 gpio2_9 GPIO IO C21 gpio2_10 GPIO IO A20 gpio2_11 GPIO IO B20 gpio2_12 GPIO IO C20 gpio2_13 GPIO IO E19 gpio2_14 GPIO IO A19 gpio2_15 GPIO IO B19 gpio2_16 GPIO IO A18 gpio2_17 GPIO IO B18 gpio2_18 GPIO IO C14 gpio2_19 GPIO IO E16 gpio2_20 GPIO IO B16 gpio2_21 GPIO IO F17 78 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-31. GPIO2 Signal Descriptions (continued) TYPE [3] ZDN [4] gpio2_22 SIGNAL NAME [1] GPIO DESCRIPTION [2] IO B23 gpio2_23 GPIO IO A23 gpio2_24 GPIO IO A22 gpio2_25 GPIO IO A24 gpio2_26 GPIO IO B1 gpio2_27 GPIO IO B2 gpio2_28 GPIO IO C2 gpio2_29 GPIO IO C1 gpio2_30 GPIO IO D1 gpio2_31 GPIO IO D2 Table 4-32. GPIO3 Signal Descriptions TYPE [3] ZDN [4] gpio3_0 SIGNAL NAME [1] GPIO DESCRIPTION [2] IO D16 gpio3_1 GPIO IO B14 gpio3_2 GPIO IO B13 gpio3_3 GPIO IO A13 gpio3_4 GPIO IO A15 gpio3_5 GPIO IO AB24 gpio3_6 GPIO IO Y22 gpio3_7 GPIO IO N23 gpio3_8 GPIO IO T24 gpio3_9 GPIO IO D14 gpio3_10 GPIO IO D13 gpio3_11 GPIO IO C16 gpio3_12 GPIO IO C13 gpio3_13 GPIO IO F25 gpio3_14 GPIO IO N24 gpio3_15 GPIO IO N22 gpio3_16 GPIO IO H23 gpio3_17 GPIO IO M24 gpio3_18 GPIO IO L23 gpio3_19 GPIO IO K23 gpio3_20 GPIO IO M25 gpio3_21 GPIO IO L24 gpio3_22 GPIO IO P22 gpio3_23 GPIO IO P20 gpio3_24 GPIO IO N20 gpio3_25 GPIO IO T23 TYPE [3] ZDN [4] Table 4-33. GPIO4 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] gpio4_0 GPIO IO AE17 gpio4_1 GPIO IO AD18 gpio4_2 GPIO IO AC18 gpio4_3 GPIO IO AD17 gpio4_4 GPIO IO AC20 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 79 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-33. GPIO4 Signal Descriptions (continued) TYPE [3] ZDN [4] gpio4_5 SIGNAL NAME [1] GPIO DESCRIPTION [2] IO AB19 gpio4_6 GPIO IO AA19 gpio4_7 GPIO IO AC24 gpio4_8 GPIO IO AD24 gpio4_9 GPIO IO AD25 gpio4_10 GPIO IO AC23 gpio4_11 GPIO IO AE21 gpio4_12 GPIO IO AC25 gpio4_13 GPIO IO AB25 gpio4_14 GPIO IO AB20 gpio4_15 GPIO IO AC21 gpio4_16 GPIO IO AD21 gpio4_17 GPIO IO AE22 gpio4_18 GPIO IO AD22 gpio4_19 GPIO IO AE23 gpio4_20 GPIO IO AD23 gpio4_21 GPIO IO AE24 gpio4_24 GPIO IO Y18 gpio4_25 GPIO IO AA18 gpio4_26 GPIO IO AE19 gpio4_27 GPIO IO AD19 gpio4_28 GPIO IO AE20 gpio4_29 GPIO IO AD20 Table 4-34. GPIO5 Signal Descriptions TYPE [3] ZDN [4] gpio5_0 SIGNAL NAME [1] GPIO IO H22 gpio5_1 GPIO IO K24 gpio5_2 GPIO IO H25 gpio5_3 GPIO IO H24 gpio5_4 GPIO IO P25 gpio5_5 GPIO IO R24 gpio5_6 GPIO IO P24 gpio5_7 GPIO IO N25 gpio5_8 GPIO IO D25 gpio5_9 GPIO IO F24 gpio5_10 GPIO IO G20 gpio5_11 GPIO IO F23 gpio5_12 GPIO IO E25 gpio5_13 GPIO IO E24 gpio5_19 GPIO IO AE18 gpio5_20 GPIO IO AB18 gpio5_23 GPIO IO D11 gpio5_24 GPIO IO F11 gpio5_25 GPIO IO A10 gpio5_26 GPIO IO B10 gpio5_27 GPIO IO G21 80 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-34. GPIO5 Signal Descriptions (continued) TYPE [3] ZDN [4] gpio5_28 SIGNAL NAME [1] GPIO DESCRIPTION [2] IO D24 gpio5_29 GPIO IO C24 gpio5_30 GPIO IO A2 gpio5_31 GPIO IO B3 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 81 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.9 www.ti.com HDQ Interface Table 4-35. HDQ Signal Description SIGNAL NAME [1] DESCRIPTION [2] hdq_sio 82 HDQ 1W Data IO Terminal Configuration and Functions TYPE [3] ZDN [4] IOD K24 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.10 I2C Interfaces Table 4-36. I2C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] I2C0_SCL I2C0 Clock IOD Y22 I2C0_SDA I2C0 Data IOD AB24 Table 4-37. I2C1 Signal Descriptions TYPE [3] ZDN [4] I2C1_SCL SIGNAL NAME [1] I2C1 Clock DESCRIPTION [2] IOD AB18, B13, G20, J25, L21, N20, T20 I2C1_SDA I2C1 Data IOD AE18, B14, E25, K21, L25, T21, T23 Table 4-38. I2C2 Signal Descriptions TYPE [3] ZDN [4] I2C2_SCL SIGNAL NAME [1] I2C2 Clock DESCRIPTION [2] IOD AB19, AC21, J24, L22, T22 I2C2_SDA I2C2 Data IOD AB20, AC20, K22, K25, P23 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 83 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4.3.11 McASP Interfaces Table 4-39. McASP0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] mcasp0_aclkr McASP0 Receive Bit Clock IO A15, A3, C19, L23 mcasp0_aclkx McASP0 Transmit Bit Clock IO A19, D14, E11, F7, N24 mcasp0_ahclkr McASP0 Receive Master Clock IO B18, M24 mcasp0_ahclkx McASP0 Transmit Master Clock IO C13, D17, L24 mcasp0_axr0 McASP0 Serial Data (IN/OUT) IO A18, B11, C14, G8, H23 mcasp0_axr1 McASP0 Serial Data (IN/OUT) IO A11, C17, D8, E16, M25 mcasp0_axr2 McASP0 Serial Data (IN/OUT) IO B18, C19, D16, L23, M24 mcasp0_axr3 McASP0 Serial Data (IN/OUT) IO D17, D19, F17, K23, L24 mcasp0_fsr McASP0 Receive Frame Sync IO A12, C16, D19, K23 mcasp0_fsx McASP0 Transmit Frame Sync IO B19, B4, C11, D13, N22 Table 4-40. McASP1 Signal Descriptions TYPE [3] ZDN [4] mcasp1_aclkr SIGNAL NAME [1] McASP1 Receive Bit Clock IO B15, F17 mcasp1_aclkx McASP1 Transmit Bit Clock IO A15, B14, L23 mcasp1_ahclkr McASP1 Receive Master Clock IO F17 mcasp1_ahclkx McASP1 Transmit Master Clock IO A16, F17 mcasp1_axr0 McASP1 Serial Data (IN/OUT) IO A13, C13, M25 mcasp1_axr1 McASP1 Serial Data (IN/OUT) IO A14, L24 mcasp1_axr2 McASP1 Serial Data (IN/OUT) IO B15, D16 mcasp1_axr3 McASP1 Serial Data (IN/OUT) IO A16, B16 mcasp1_fsr McASP1 Receive Frame Sync IO A14, B16 mcasp1_fsx McASP1 Transmit Frame Sync IO B13, C16, K23 84 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.12 Miscellaneous Table 4-41. Miscellaneous Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] clkout1 Clock out1 O D24 clkout2 Clock out2 O C24 clkreq Clock Request Control O H20 nNMI External Interrupt to ARM Cortex A9 core I G25 nRESETIN_OUT Warm Reset Input/Output IOD (1) G22 OSC0_IN High frequency oscillator input I C25 OSC0_OUT High frequency oscillator output O B25 OSC1_IN Low frequency (32.768 KHz) Real Time Clock oscillator input I AE5 OSC1_OUT Low frequency (32.768 KHz) Real Time Clock oscillator output O AE4 porz Power on Reset I Y23 RTC_PORz RTC active low reset input I AE6 tclkin Timer Clock In I C24 xdma_event_intr0 External DMA Event or Interrupt 0 I D24 xdma_event_intr1 External DMA Event or Interrupt 1 I C24 xdma_event_intr2 External DMA Event or Interrupt 2 I A16, G24, R25 xdma_event_intr3 External DMA Event or Interrupt 3 I AD24 xdma_event_intr4 External DMA Event or Interrupt 4 I AD25 xdma_event_intr5 External DMA Event or Interrupt 5 I AC23 xdma_event_intr6 External DMA Event or Interrupt 6 I AE21 xdma_event_intr7 External DMA Event or Interrupt 7 I AC25 xdma_event_intr8 External DMA Event or Interrupt 8 I AB25 (1) Refer to the External Warm Reset section of the Technical Reference Manual for more information related to the operation of this terminal. Table 4-42. Reserved Signals SIGNAL NAME [1] DESCRIPTION [2] Reserved TYPE [3] ZDN [4] NA AA10, AA7, AA9, AB10, AB6, AB7, AB9, AC10, AC12, AC5, AC6, AC7, AC9, AD1, AD10, AD11, AD2, AD7, AE11, AE12, AE9, H19, H21, W10, Y10, Y6, Y7 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 85 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4.3.13 PRU-ICSS0 Interface Table 4-43. PRU-ICSS0-PRU0/General Purpose Inputs Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] pr0_pru0_gpi0 PRU-ICSS0 PRU0 Data In I N24 pr0_pru0_gpi1 PRU-ICSS0 PRU0 Data In I N22 pr0_pru0_gpi2 PRU-ICSS0 PRU0 Data In I H23 pr0_pru0_gpi3 PRU-ICSS0 PRU0 Data In I M24 pr0_pru0_gpi4 PRU-ICSS0 PRU0 Data In I L23 pr0_pru0_gpi5 PRU-ICSS0 PRU0 Data In I K23 pr0_pru0_gpi6 PRU-ICSS0 PRU0 Data In I M25 pr0_pru0_gpi7 PRU-ICSS0 PRU0 Data In I L24 pr0_pru0_gpi8 PRU-ICSS0 PRU0 Data In I B1 pr0_pru0_gpi9 PRU-ICSS0 PRU0 Data In I B2 pr0_pru0_gpi10 PRU-ICSS0 PRU0 Data In I C2 pr0_pru0_gpi11 PRU-ICSS0 PRU0 Data In I C1 pr0_pru0_gpi12 PRU-ICSS0 PRU0 Data In I D1 pr0_pru0_gpi13 PRU-ICSS0 PRU0 Data In I D2 pr0_pru0_gpi14 PRU-ICSS0 PRU0 Data In I AC20 pr0_pru0_gpi15 PRU-ICSS0 PRU0 Data In I AB19 pr0_pru0_gpi16 PRU-ICSS0 PRU0 Data In Capture Enable I AA19 pr0_pru0_gpi17 PRU-ICSS0 PRU0 Data In I AC24 pr0_pru0_gpi18 PRU-ICSS0 PRU0 Data In I H25 pr0_pru0_gpi19 PRU-ICSS0 PRU0 Data In I H24 Table 4-44. PRU-ICSS0-PRU0/General Purpose Outputs Signal Descriptions TYPE [3] ZDN [4] pr0_pru0_gpo0 SIGNAL NAME [1] PRU-ICSS0 PRU0 Data Out O N24 pr0_pru0_gpo1 PRU-ICSS0 PRU0 Data Out O N22 pr0_pru0_gpo2 PRU-ICSS0 PRU0 Data Out O H23 pr0_pru0_gpo3 PRU-ICSS0 PRU0 Data Out O M24 pr0_pru0_gpo4 PRU-ICSS0 PRU0 Data Out O L23 pr0_pru0_gpo5 PRU-ICSS0 PRU0 Data Out O K23 pr0_pru0_gpo6 PRU-ICSS0 PRU0 Data Out O M25 pr0_pru0_gpo7 PRU-ICSS0 PRU0 Data Out O L24 pr0_pru0_gpo8 PRU-ICSS0 PRU0 Data Out O B1 pr0_pru0_gpo9 PRU-ICSS0 PRU0 Data Out O B2 pr0_pru0_gpo10 PRU-ICSS0 PRU0 Data Out O C2 pr0_pru0_gpo11 PRU-ICSS0 PRU0 Data Out O C1 pr0_pru0_gpo12 PRU-ICSS0 PRU0 Data Out O D1 pr0_pru0_gpo13 PRU-ICSS0 PRU0 Data Out O D2 pr0_pru0_gpo14 PRU-ICSS0 PRU0 Data Out O AC20 pr0_pru0_gpo15 PRU-ICSS0 PRU0 Data Out O AB19 pr0_pru0_gpo16 PRU-ICSS0 PRU0 Data Out O AA19 pr0_pru0_gpo17 PRU-ICSS0 PRU0 Data Out O AC24 pr0_pru0_gpo18 PRU-ICSS0 PRU0 Data Out O H25 pr0_pru0_gpo19 PRU-ICSS0 PRU0 Data Out O H24 86 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-45. PRU-ICSS0-PRU1/General Purpose Inputs Signal Descriptions TYPE [3] ZDN [4] pr0_pru1_gpi0 SIGNAL NAME [1] PRU-ICSS0 PRU1 Data In DESCRIPTION [2] I AD24 pr0_pru1_gpi1 PRU-ICSS0 PRU1 Data In I AD25 pr0_pru1_gpi2 PRU-ICSS0 PRU1 Data In I AC23 pr0_pru1_gpi3 PRU-ICSS0 PRU1 Data In I AE21 pr0_pru1_gpi4 PRU-ICSS0 PRU1 Data In I K25 pr0_pru1_gpi5 PRU-ICSS0 PRU1 Data In I J24 pr0_pru1_gpi6 PRU-ICSS0 PRU1 Data In I B23 pr0_pru1_gpi7 PRU-ICSS0 PRU1 Data In I A23 pr0_pru1_gpi8 PRU-ICSS0 PRU1 Data In I A22 pr0_pru1_gpi9 PRU-ICSS0 PRU1 Data In I A24 pr0_pru1_gpi10 PRU-ICSS0 PRU1 Data In I AD21 pr0_pru1_gpi11 PRU-ICSS0 PRU1 Data In I AE22 pr0_pru1_gpi12 PRU-ICSS0 PRU1 Data In I AD22 pr0_pru1_gpi13 PRU-ICSS0 PRU1 Data In I AE23 pr0_pru1_gpi14 PRU-ICSS0 PRU1 Data In I AD23 pr0_pru1_gpi15 PRU-ICSS0 PRU1 Data In I AE24 pr0_pru1_gpi16 PRU-ICSS0 PRU1 Data In Capture Enable I AE18 pr0_pru1_gpi17 PRU-ICSS0 PRU1 Data In I AB18 pr0_pru1_gpi18 PRU-ICSS0 PRU1 Data In I H22 pr0_pru1_gpi19 PRU-ICSS0 PRU1 Data In I K24 Table 4-46. PRU-ICSS0-PRU1/General Purpose Outputs Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] pr0_pru1_gpo0 PRU-ICSS0 PRU1 Data Out O AD24 pr0_pru1_gpo1 PRU-ICSS0 PRU1 Data Out O AD25 pr0_pru1_gpo2 PRU-ICSS0 PRU1 Data Out O AC23 pr0_pru1_gpo3 PRU-ICSS0 PRU1 Data Out O AE21 pr0_pru1_gpo4 PRU-ICSS0 PRU1 Data Out O K25 pr0_pru1_gpo5 PRU-ICSS0 PRU1 Data Out O J24 pr0_pru1_gpo6 PRU-ICSS0 PRU1 Data Out O B23 pr0_pru1_gpo7 PRU-ICSS0 PRU1 Data Out O A23 pr0_pru1_gpo8 PRU-ICSS0 PRU1 Data Out O A22 pr0_pru1_gpo9 PRU-ICSS0 PRU1 Data Out O A24 pr0_pru1_gpo10 PRU-ICSS0 PRU1 Data Out O AD21 pr0_pru1_gpo11 PRU-ICSS0 PRU1 Data Out O AE22 pr0_pru1_gpo12 PRU-ICSS0 PRU1 Data Out O AD22 pr0_pru1_gpo13 PRU-ICSS0 PRU1 Data Out O AE23 pr0_pru1_gpo14 PRU-ICSS0 PRU1 Data Out O AD23 pr0_pru1_gpo15 PRU-ICSS0 PRU1 Data Out O AE24 pr0_pru1_gpo16 PRU-ICSS0 PRU1 Data Out O AE18 pr0_pru1_gpo17 PRU-ICSS0 PRU1 Data Out O AB18 pr0_pru1_gpo18 PRU-ICSS0 PRU1 Data Out O H22 pr0_pru1_gpo19 PRU-ICSS0 PRU1 Data Out O K24 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 87 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-47. PRU-ICSS0/UART0 Signal Descriptions TYPE [3] ZDN [4] pr0_uart0_cts_n SIGNAL NAME [1] UART Clear to Send I P23 pr0_uart0_rts_n UART Request to Send O T22 pr0_uart0_rxd UART Receive Data I T21 pr0_uart0_txd UART Transmit Data O T20 88 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.14 PRU-ICSS1 Interface Table 4-48. PRU-ICSS1-PRU0/General Purpose Inputs Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] pr1_pru0_gpi0 PRU-ICSS1 PRU0 Data In I B22 pr1_pru0_gpi1 PRU-ICSS1 PRU0 Data In I A21 pr1_pru0_gpi2 PRU-ICSS1 PRU0 Data In I B21 pr1_pru0_gpi3 PRU-ICSS1 PRU0 Data In I C21 pr1_pru0_gpi4 PRU-ICSS1 PRU0 Data In I A20 pr1_pru0_gpi5 PRU-ICSS1 PRU0 Data In I B20 pr1_pru0_gpi6 PRU-ICSS1 PRU0 Data In I C20 pr1_pru0_gpi7 PRU-ICSS1 PRU0 Data In I E19 pr1_pru0_gpi8 PRU-ICSS1 PRU0 Data In I B9 pr1_pru0_gpi9 PRU-ICSS1 PRU0 Data In I F10 pr1_pru0_gpi10 PRU-ICSS1 PRU0 Data In I E11 pr1_pru0_gpi11 PRU-ICSS1 PRU0 Data In I C11 pr1_pru0_gpi16 PRU-ICSS1 PRU0 Data In Capture Enable I B11, C24, D24, K21, L21 Table 4-49. PRU-ICSS1-PRU0/General Purpose Outputs Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] pr1_pru0_gpo0 PRU-ICSS1 PRU0 Data Out O B22 pr1_pru0_gpo1 PRU-ICSS1 PRU0 Data Out O A21 pr1_pru0_gpo2 PRU-ICSS1 PRU0 Data Out O B21 pr1_pru0_gpo3 PRU-ICSS1 PRU0 Data Out O C21 pr1_pru0_gpo4 PRU-ICSS1 PRU0 Data Out O A20 pr1_pru0_gpo5 PRU-ICSS1 PRU0 Data Out O B20 pr1_pru0_gpo6 PRU-ICSS1 PRU0 Data Out O C20 pr1_pru0_gpo7 PRU-ICSS1 PRU0 Data Out O E19 pr1_pru0_gpo8 PRU-ICSS1 PRU0 Data Out O B9 pr1_pru0_gpo9 PRU-ICSS1 PRU0 Data Out O F10 pr1_pru0_gpo10 PRU-ICSS1 PRU0 Data Out O E11 pr1_pru0_gpo11 PRU-ICSS1 PRU0 Data Out O C11 Table 4-50. PRU-ICSS1/ECAT Signal Descriptions TYPE [3] ZDN [4] pr1_edc_latch0_in SIGNAL NAME [1] Data In DESCRIPTION [2] I AE22, K22 pr1_edc_latch1_in Data In I AD22, L22 pr1_edc_sync0_out Data Out O L25 pr1_edc_sync1_out Data Out O J25 pr1_edio_data_in0 Data In I AD23 pr1_edio_data_in1 Data In I AE24 pr1_edio_data_in2 Data In I B23 pr1_edio_data_in3 Data In I A23 pr1_edio_data_in4 Data In I A22 pr1_edio_data_in5 Data In I A24 pr1_edio_data_in6 Data In I B9, C20 pr1_edio_data_in7 Data In I E19, F10 pr1_edio_data_out0 Data Out O T21 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 89 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-50. PRU-ICSS1/ECAT Signal Descriptions (continued) TYPE [3] ZDN [4] pr1_edio_data_out1 SIGNAL NAME [1] Data Out DESCRIPTION [2] O T20 pr1_edio_data_out2 Data Out O B23 pr1_edio_data_out3 Data Out O A23 pr1_edio_data_out4 Data Out O A22 pr1_edio_data_out5 Data Out O A24 pr1_edio_data_out6 Data Out O B9, C20 pr1_edio_data_out7 Data Out O E19, F10 pr1_edio_latch_in Latch In I AE23 pr1_edio_outvalid Data Out Valid O AD18 pr1_edio_sof Start of Frame O AB25, AE17 Table 4-51. PRU-ICSS1/MDIO Signal Descriptions TYPE [3] ZDN [4] pr1_mdio_data SIGNAL NAME [1] MDIO Data DESCRIPTION [2] IO A17, B12, D24 pr1_mdio_mdclk MDIO Clk O A12, B17, C24 Table 4-52. PRU-ICSS1/MII0 Signal Descriptions TYPE [3] ZDN [4] pr1_mii0_col SIGNAL NAME [1] MII Collision Detect DESCRIPTION [2] I A10, D25 pr1_mii0_crs MII Carrier Sense I B12, G20 pr1_mii0_rxd0 MII Receive Data bit 0 I B18 pr1_mii0_rxd1 MII Receive Data bit 1 I A18 pr1_mii0_rxd2 MII Receive Data bit 2 I B19 pr1_mii0_rxd3 MII Receive Data bit 3 I A19 pr1_mii0_rxdv MII Receive Data Valid I D17 pr1_mii0_rxer MII Receive Data Error I D19 pr1_mii0_rxlink MII Receive Link I C19, E25 pr1_mii0_txd0 MII Transmit Data bit 0 O B11, B20 pr1_mii0_txd1 MII Transmit Data bit 1 O A20, C11 pr1_mii0_txd2 MII Transmit Data bit 2 O C21, E11 pr1_mii0_txd3 MII Transmit Data bit 3 O B21, D11 pr1_mii0_txen MII Transmit Enable O A21, F11 pr1_mii_mr0_clk MII Receive Clock I C17 pr1_mii_mt0_clk MII Transmit Clock I B10, B22 TYPE [3] ZDN [4] Table 4-53. PRU-ICSS1/MII1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] pr1_mii1_col MII Collision Detect I A3, F24 pr1_mii1_crs MII Carrier Sense I A12, A2, F23 pr1_mii1_rxd0 MII Receive Data bit 0 I D8 pr1_mii1_rxd1 MII Receive Data bit 1 I G8 pr1_mii1_rxd2 MII Receive Data bit 2 I B4 pr1_mii1_rxd3 MII Receive Data bit 3 I F7 pr1_mii1_rxdv MII Receive Data Valid I C5 pr1_mii1_rxer MII Receive Data Error I B3 pr1_mii1_rxlink MII Receive Link I C10, E24 90 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 4-53. PRU-ICSS1/MII1 Signal Descriptions (continued) TYPE [3] ZDN [4] pr1_mii1_txd0 SIGNAL NAME [1] MII Transmit Data bit 0 DESCRIPTION [2] O E7 pr1_mii1_txd1 MII Transmit Data bit 1 O D7 pr1_mii1_txd2 MII Transmit Data bit 2 O A4 pr1_mii1_txd3 MII Transmit Data bit 3 O C6 pr1_mii1_txen MII Transmit Enable O C3 pr1_mii_mr1_clk MII Receive Clock I F6 pr1_mii_mt1_clk MII Transmit Clock I E8 Table 4-54. PRU-ICSS1/UART0 Signal Descriptions TYPE [3] ZDN [4] pr1_uart0_cts_n SIGNAL NAME [1] UART Clear to Send DESCRIPTION [2] I K22, P23 pr1_uart0_rts_n UART Request to Send O L22, T22 pr1_uart0_rxd UART Receive Data I K21, T21 pr1_uart0_txd UART Transmit Data O L21, T20 TYPE [3] ZDN [4] IO A11, G24 Table 4-55. PRU-ICSS1/eCAP Signal Descriptions SIGNAL NAME [1] pr1_ecap0_ecap_capin_apwm_o DESCRIPTION [2] Enhanced capture input or Auxiliary PWM out Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 91 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4.3.15 QSPI Interface Table 4-56. QSPI Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] qspi_clk QSPI Clock IO B12, Y18 qspi_csn QSPI Chip Select O A8, AA18 qspi_d0 QSPI Data IO A9, AE19 qspi_d1 QSPI Data I AD19, E10 qspi_d2 QSPI Data I AE20, D10 qspi_d3 QSPI Data I AD20, C10 92 Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.16 RTC Subsystem Interface Table 4-57. RTC Subsystem Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] RTC_KALDO_ENn Active low enable input for internal CAP_VDD_RTC voltage regulator I AE2 RTC_PMIC_EN PMIC Power Enable output generated from Generic RTCSS O AD6 RTC_WAKEUP External Wakeup Pin when Generic RTC is used I AE3 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 93 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4.3.17 Removable Media Interfaces Table 4-58. MMC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] mmc0_clk MMC/SD/SDIO Clock IO D1 mmc0_cmd MMC/SD/SDIO Command IO D2 mmc0_dat0 MMC/SD/SDIO Data Bus IO C1 mmc0_dat1 MMC/SD/SDIO Data Bus IO C2 mmc0_dat2 MMC/SD/SDIO Data Bus IO B2 mmc0_dat3 MMC/SD/SDIO Data Bus IO B1 mmc0_dat4 MMC/SD/SDIO Data Bus IO E16 mmc0_dat5 MMC/SD/SDIO Data Bus IO C14 mmc0_dat6 MMC/SD/SDIO Data Bus IO D13 mmc0_dat7 MMC/SD/SDIO Data Bus IO D14 mmc0_pow MMC/SD Power Switch Control O A16, R25 mmc0_sdcd SD Card Detect I A17, N24, R25 mmc0_sdwp SD Write Protect I B17, G24, L23 Table 4-59. MMC1 Signal Descriptions TYPE [3] ZDN [4] mmc1_clk SIGNAL NAME [1] MMC/SD/SDIO Clock DESCRIPTION [2] IO B15, B17, B9, Y18 mmc1_cmd MMC/SD/SDIO Command IO A14, A17, AA18, F10 mmc1_dat0 MMC/SD/SDIO Data Bus IO AE19, B10, B5, D14 mmc1_dat1 MMC/SD/SDIO Data Bus IO A10, A5, AD19, D13 mmc1_dat2 MMC/SD/SDIO Data Bus IO AE20, B6, C14, F11 mmc1_dat3 MMC/SD/SDIO Data Bus IO A6, AD20, D11, E16 mmc1_dat4 MMC/SD/SDIO Data Bus IO B7, E11 mmc1_dat5 MMC/SD/SDIO Data Bus IO A7, C11 mmc1_dat6 MMC/SD/SDIO Data Bus IO B11, C8 mmc1_dat7 MMC/SD/SDIO Data Bus IO A11, B8 mmc1_sdcd SD Card Detect I A2, N22 mmc1_sdwp SD Write Protect I K21, T21 Table 4-60. MMC2 Signal Descriptions TYPE [3] ZDN [4] mmc2_clk SIGNAL NAME [1] MMC/SD/SDIO Clock IO A12, AD21, B16, B17 mmc2_cmd MMC/SD/SDIO Command IO A13, A17, AE22, B12 mmc2_dat0 MMC/SD/SDIO Data Bus IO A15, AD22, C5, E11 mmc2_dat1 MMC/SD/SDIO Data Bus IO AE23, C11, C16, C6 mmc2_dat2 MMC/SD/SDIO Data Bus IO A4, AD23, B11, C13 mmc2_dat3 MMC/SD/SDIO Data Bus IO A11, A3, AE24, D16 mmc2_dat4 MMC/SD/SDIO Data Bus IO B10, E8 mmc2_dat5 MMC/SD/SDIO Data Bus IO A10, F6 mmc2_dat6 MMC/SD/SDIO Data Bus IO F11, F7 mmc2_dat7 MMC/SD/SDIO Data Bus IO B4, D11 mmc2_sdcd SD Card Detect I B3, H23 mmc2_sdwp SD Write Protect I L21, T20 94 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.18 SPI Interfaces Table 4-61. SPI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] spi0_cs0 SPI Chip Select IO T20 spi0_cs1 SPI Chip Select IO R25 spi0_cs2 SPI Chip Select IO AD24, C24, E10 spi0_cs3 SPI Chip Select IO A9, AD25, N24 spi0_d0 SPI Data IO T22 spi0_d1 SPI Data IO T21 spi0_sclk SPI Clock IO P23 TYPE [3] ZDN [4] Table 4-62. SPI1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] spi1_cs0 SPI Chip Select IO A16, J25, K22, K25, M24 spi1_cs1 SPI Chip Select IO D24, G24, J24, L22 spi1_cs2 SPI Chip Select IO AC23, D10, N22 spi1_cs3 SPI Chip Select IO AE21, C10, H23 spi1_d0 SPI Data IO B14, L25, N22 spi1_d1 SPI Data IO B13, H23, J25 spi1_sclk SPI Clock IO D16, G24, N24 Table 4-63. SPI2 Signal Descriptions TYPE [3] ZDN [4] spi2_cs0 SIGNAL NAME [1] SPI Chip Select DESCRIPTION [2] IO AC20, AD25, T23 spi2_cs1 SPI Chip Select IO AC25, AE17 spi2_cs2 SPI Chip Select IO AB19, AC23 spi2_cs3 SPI Chip Select IO AA19, AC24 spi2_d0 SPI Data IO AD17, AD24, P22 spi2_d1 SPI Data IO AB25, AD18, P20 spi2_sclk SPI Clock IO AC18, AE21, N20 Table 4-64. SPI3 Signal Descriptions TYPE [3] ZDN [4] spi3_cs0 SIGNAL NAME [1] SPI Chip Select DESCRIPTION [2] IO AD21, D11, D17 spi3_cs1 SPI Chip Select IO A11, B10, B18, C10 spi3_d0 SPI Data IO A10, AB20, D19 spi3_d1 SPI Data IO AC21, C17, F11 spi3_sclk SPI Clock IO AE22, B10, C19 Table 4-65. SPI4 Signal Descriptions TYPE [3] ZDN [4] spi4_cs0 SIGNAL NAME [1] SPI Chip Select DESCRIPTION [2] IO N25 spi4_cs1 SPI Chip Select IO H22 spi4_d0 SPI Data IO R24 spi4_d1 SPI Data IO P24 spi4_sclk SPI Clock IO P25 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 95 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4.3.19 Timer Interfaces Table 4-66. Timer0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] timer0 Timer trigger event / PWM out TYPE [3] ZDN [4] IO R25 TYPE [3] ZDN [4] IO G24 Table 4-67. Timer1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] timer1 Timer trigger event / PWM out Table 4-68. Timer4 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] timer4 Timer trigger event / PWM out TYPE [3] ZDN [4] IO A13, A9, AB24, D24 Table 4-69. Timer5 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] timer5 Timer trigger event / PWM out TYPE [3] ZDN [4] IO B1, B17, C10, L22 Table 4-70. Timer6 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] timer6 Timer trigger event / PWM out TYPE [3] ZDN [4] IO A17, B2, D10, K22 TYPE [3] ZDN [4] IO C24, E10, L25, Y22 Table 4-71. Timer7 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] timer7 96 Timer trigger event / PWM out Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.20 UART Interfaces Table 4-72. UART0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] AC24, L25 uart0_ctsn UART Clear to Send I uart0_dcdn UART Data Carrier Detect I AD22 uart0_rtsn UART Request to Send O AD24, J25 uart0_rxd UART Receive Data I K25 uart0_txd UART Transmit Data O J24 Table 4-73. UART1 Signal Descriptions TYPE [3] ZDN [4] uart1_ctsn SIGNAL NAME [1] UART Clear to Send DESCRIPTION [2] IO AD21, K22 uart1_dcdn UART Clear to Send I AD23, B1, D14 uart1_dsrn UART Request to Send I AE23, B2, D13 uart1_dtrn UART Receive Data O AE24, C14, C2 uart1_rin UART Transmit Data I AD22, C1, E16 uart1_rtsn UART Request to Send O AE22, L22 uart1_rxd UART Receive Data IO AB20, K21 uart1_txd UART Transmit Data IO AC21, L21 Table 4-74. UART2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] IO A19, AB24, AD23 uart2_ctsn UART Clear to Send uart2_rtsn UART Request to Send O AE24, B19, Y22 uart2_rxd UART Receive Data IO AD22, B14, D1, D14, P23 uart2_txd UART Transmit Data IO AE23, B13, D13, D2, T22 Table 4-75. UART3 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] IO A17, A18, D1, H22 uart3_ctsn UART Clear to Send uart3_rtsn UART Request to Send O B17, B18, D2, K24 uart3_rxd UART Receive Data IO C14, C2, H25, R25 uart3_txd UART Transmit Data IO C1, E16, G24, H24 Table 4-76. UART4 Signal Descriptions TYPE [3] ZDN [4] uart4_ctsn SIGNAL NAME [1] UART Clear to Send DESCRIPTION [2] I B1, C19 uart4_rtsn UART Request to Send O B2, D19 uart4_rxd UART Receive Data I A2, C16, L25 uart4_txd UART Transmit Data O B3, C13, J25 Table 4-77. UART5 Signal Descriptions TYPE [3] ZDN [4] uart5_ctsn SIGNAL NAME [1] UART Clear to Send DESCRIPTION [2] I B14, C17, C2 uart5_rtsn UART Request to Send O B13, C1, D17 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 97 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 4-77. UART5 Signal Descriptions (continued) TYPE [3] ZDN [4] uart5_rxd SIGNAL NAME [1] UART Receive Data I A17, B19, C17, D16 uart5_txd UART Transmit Data O A15, A16, A19, B17 98 DESCRIPTION [2] Terminal Configuration and Functions Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.21 USB Interfaces Table 4-78. USB0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] USB0_CE USB0 Active high Charger Enable output A W22 USB0_DM USB0 Data minus A W24 USB0_DP USB0 Data plus A W25 USB0_DRVVBUS USB0 Active high VBUS control output O G21 USB0_ID USB0 ID A U24 USB0_VBUS USB0 VBUS A U23 Table 4-79. USB1 Signal Descriptions TYPE [3] ZDN [4] USB1_CE SIGNAL NAME [1] USB1 Active high Charger Enable output DESCRIPTION [2] A U22 USB1_DM USB1 Data minus A V25 USB1_DP USB1 Data plus A V24 USB1_DRVVBUS USB1 Active high VBUS control output O F25 USB1_ID USB1 ID A U25 USB1_VBUS USB1 VBUS A T25 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 99 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4.3.22 eCAP Interfaces Table 4-80. eCAP0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] eCAP0_in_PWM0_out Enhanced Capture 0 input or Auxiliary PWM0 output TYPE [3] ZDN [4] IO G24 TYPE [3] ZDN [4] IO J24, R25, Y22 Table 4-81. eCAP1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] eCAP1_in_PWM1_out Enhanced Capture 1 input or Auxiliary PWM1 output Table 4-82. eCAP2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] eCAP2_in_PWM2_out 100 Enhanced Capture 2 input or Auxiliary PWM2 output Terminal Configuration and Functions TYPE [3] ZDN [4] IO AB24, K25, M24 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 4.3.23 eHRPWM Interfaces Table 4-83. eHRPWM0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] ehrpwm0_synci Sync input to eHRPWM0 module from an external pin I AC21, M24, P25, T20 ehrpwm0_synco Sync Output from eHRPWM0 module to an external pin O AE18, B19, C21, C5, D11 ehrpwm0_tripzone_input eHRPWM0 trip zone input I AB20, H23, P24, T21 ehrpwm0A eHRPWM0 A output. O AD25, N24, P23 ehrpwm0B eHRPWM0 B output. O AC23, N22, T22 Table 4-84. eHRPWM1 Signal Descriptions TYPE [3] ZDN [4] ehrpwm1_tripzone_input SIGNAL NAME [1] eHRPWM1 trip zone input DESCRIPTION [2] I A19, AD21, C3, P20 ehrpwm1A eHRPWM1 A output. O A18, AE20, AE21, C6, T21 ehrpwm1B eHRPWM1 B output. O A4, AC25, AD20, B18, T20 TYPE [3] ZDN [4] Table 4-85. eHRPWM2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] ehrpwm2_tripzone_input eHRPWM2 trip zone input I B21, F11, T23 ehrpwm2A eHRPWM2 A output. O B10, B22, R25 ehrpwm2B eHRPWM2 B output. O A10, A21, G24 Table 4-86. eHRPWM3 Signal Descriptions TYPE [3] ZDN [4] ehrpwm3_synci SIGNAL NAME [1] Sync input to eHRPWM3 module or sync output to external PWM DESCRIPTION [2] I R24 ehrpwm3_synco Sync input to eHRPWM3 module or sync output to external PWM O AB18 ehrpwm3_tripzone_input eHRPWM3 trip zone input I N25 ehrpwm3A eHRPWM3 A output. O AC25, AE19 ehrpwm3B eHRPWM3 B output. O AB25, AD19 Table 4-87. eHRPWM4 Signal Descriptions TYPE [3] ZDN [4] ehrpwm4_tripzone_input SIGNAL NAME [1] eHRPWM4 trip zone input DESCRIPTION [2] I N20 ehrpwm4A eHRPWM4 A output. O H25 ehrpwm4B eHRPWM4 B output. O H24 TYPE [3] ZDN [4] Table 4-88. eHRPWM5 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] ehrpwm5_tripzone_input eHRPWM5 trip zone input I P22 ehrpwm5A eHRPWM5 A output. O H22 ehrpwm5B eHRPWM5 B output. O K24 Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 101 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4.3.24 eQEP Interfaces Table 4-89. eQEP0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4] eQEP0_index eQEP0 index. IO A13, M25 eQEP0_strobe eQEP0 strobe. IO B16, L24 eQEP0A_in eQEP0A quadrature input I A14, L23 eQEP0B_in eQEP0B quadrature input I B15, K23 TYPE [3] ZDN [4] C17, E8 Table 4-90. eQEP1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] eQEP1_index eQEP1 index. IO eQEP1_strobe eQEP1 strobe. IO D17, F6 eQEP1A_in eQEP1A quadrature input I C19, D7 eQEP1B_in eQEP1B quadrature input I D19, E7 TYPE [3] ZDN [4] Table 4-91. eQEP2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] eQEP2_index eQEP2 index. IO B11, C20 eQEP2_strobe eQEP2 strobe. IO A11, E19 eQEP2A_in eQEP2A quadrature input I A20, E11 eQEP2B_in eQEP2B quadrature input I B20, C11 102 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5 Specifications 5.1 Absolute Maximum Ratings over junction temperature range (unless otherwise noted)(1)(2) MIN MAX VDD_MPU Supply voltage for the MPU domain -0.5 1.5 V VDD_CORE Supply voltage range for the CORE domain -0.5 1.5 V CAP_VDD_RTC(3) Supply voltage range for the RTC domain -0.5 1.5 V VDDS_RTC Supply voltage range for the RTC domain -0.5 2.1 V VDDS_OSC Supply voltage range for the System oscillator -0.5 2.1 V VDDS_SRAM_CORE_BG Supply voltage range for the Core SRAM and Bandgap LDOs -0.5 2.1 V VDDS_SRAM_MPU_BB Supply voltage range for the MPU SRAM and BB LDOs -0.5 2.1 V VDDS_PLL_DDR Supply voltage range for the DPLL DDR -0.5 2.1 V VDDS_PLL_CORE_LCD Supply voltage range for the DPLL CORE, EXTDEV, and LCD -0.5 2.1 V VDDS_PLL_MPU Supply voltage range for the DPLL MPU -0.5 2.1 V VDDS_DDR Supply voltage range for the DDR IO domain -0.5 2.1 V VDDS Supply voltage range for all dual-voltage IO domains -0.5 2.1 V VDDA1P8V_USB0 Supply voltage range for USBPHY and DPLL PER -0.5 2.1 V VDDA1P8V_USB1 Supply voltage range for USBPHY -0.5 2.1 V VDDA_ADC0 Supply voltage range for ADC0 -0.5 2.1 V VDDA_ADC1 Supply voltage range for ADC1 -0.5 2.1 V VDDSHV1 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDSHV2 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDSHV3 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDSHV5 Supply voltage range for the CLKOUT voltage domain -0.5 3.8 V VDDSHV6 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDSHV7 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDSHV8 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDSHV9 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDSHV10 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDSHV11 Supply voltage range for the dual-voltage IO domain -0.5 3.8 V VDDA3P3V_USB0 Supply voltage range for USBPHY -0.5 4 V VDDA3P3V_USB1 Supply voltage range for USBPHY -0.5 4 V VDDS3P3V_IOLDO Supply voltage range for the dual-voltage IO LDO -0.5 3.8 V VDDS_CLKOUT Supply voltage range for CLKOUT domain -0.5 2.1 V USB0_VBUS(4) Supply voltage range for USB VBUS comparator input -0.5 5.25 V USB1_VBUS(4) Supply voltage range for USB VBUS comparator input -0.5 5.25 V DDR_VREF Supply voltage range for the DDR3/DDR3L HSTL, LPDDR2 HSUL_12 reference voltage -0.3 1.1 V Steady State Max. Voltage at all IO pins(5) UNIT -0.5 V to IO supply voltage + 0.3 V USB0_ID(6) Steady state maximum voltage range for the USB ID input -0.5 2.1 V (6) Steady state maximum voltage range for the USB ID input -0.5 2.1 V USB1_ID Transient Overshoot and Undershoot specification at IO terminal Latch-up Performance(7) Tstg(8) 20% of corresponding IO supply voltage for up to 20% of signal period (see Figure 5-1) Class II (105C) Latch-up I-test performance current-pulse injection on each IO pin 100 Latch-up overvoltage performance voltage injection on each IO pin 100 Storage temperature mA -55 155 C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to their associated VSS or VSSA_x. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 103 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Absolute Maximum Ratings (continued) over junction temperature range (unless otherwise noted)(1)(2) (3) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced from an external power supply. (4) This terminal is connected to a fail-safe IO and does not have a dependence on any IO supply voltage. (5) This parameter applies to all IO terminals which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be -0.5 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences. (6) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 or greater than 100 k. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source. (7) For current pulse injection: Pins stressed per JEDEC JESD78D (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage. For overvoltage performance: Supplies stressed per JEDEC JESD78D (Class II) and passed specified voltage injection. (8) For tape and reel the storage temperature range is [-10C; +50C] with a maximum relative humidity of 70%. TI recommends returning to ambient room temperature before usage. Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The USB0_VBUS, USB1_VBUS, and DDR_RESETn are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 5.1. Overshoot = 20% of nominal IO supply voltage Tovershoot Tperiod Tundershoot Undershoot = 20% of nominal IO supply voltage Figure 5-1. Tovershoot + Tundershoot < 20% of Tperiod 104 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 5.2 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 ESD Ratings VALUE VESD Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Electrostatic discharge (ESD) UNIT 1000 Charged device model (CDM), per JESD22-C101(2) V 250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 5.3 Power-On Hours (POH)(1)(2)(3)(4) OPERATING CONDITION COMMERCIAL INDUSTRIAL EXTENDED JUNCTION TEMP (Tj) LIFETIME (POH)(5) JUNCTION TEMP (Tj) LIFETIME (POH)(5) JUNCTION TEMP (Tj) LIFETIME (POH)(5) Nitro 0C to 90C 100K -40C to 90C 100K -40C to 105C 84.4K Turbo 0C to 90C 100K -40C to 90C 100K -40C to 105C 100K OPP120 0C to 90C 100K -40C to 90C 100K -40C to 105C 100K OPP100 0C to 90C 100K -40C to 90C 100K -40C to 105C 100K OPP50 0C to 90C 100K -40C to 90C 100K -40C to 105C 100K (1) The POH information in this table is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. (2) To avoid significant degradation, the device POH must be limited as described in this table. (3) Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. (4) The previous notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms and conditions for TI semiconductor products. (5) POH = Power-on hours when the device is fully functional. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 105 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.4 www.ti.com Operating Performance Points Device operating performance points (OPPs) are defined in Table 5-1, Table 5-2, and Table 5-3. Table 5-1. VDD_CORE OPPs(1) VDD_CORE OPP VDD_CORE DDR3/DDR3L(2) LPDDR2(2) L3 and L4 1.144 V 400 MHz 266 MHz 200 MHz and 100 MHz 1V Not supported 133 MHz 100 MHz and 50 MHz MIN NOM MAX OPP100 1.056 V 1.100 V OPP50 0.912 V 0.950 V (1) Frequencies in this table indicate maximum performance for a given OPP condition. (2) This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table. Table 5-2. VDD_MPU OPPs(1) VDD_MPU OPP VDD_MPU ARM (A9) MIN NOM MAX Nitro 1.272 V 1.325 V 1.378 V 1 GHz Turbo 1.210 V 1.260 V 1.326 V 800 MHz OPP120 1.152 V 1.200 V 1.248 V 720 MHz OPP100 1.056 V 1.100 V 1.144 V 600 MHz OPP50 0.912 V 0.950 V 1.000 V 300 MHz (1) Frequencies in this table indicate maximum performance for a given OPP condition. Table 5-3. Valid Combinations of VDD_CORE and VDD_MPU OPPs(1) VDD_CORE VDD_MPU OPP50 OPP50 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 OPP100 Turbo OPP100 Nitro (1) OPP combinations listed in this table have been tested. Other OPP combinations are not supported. 106 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 5.5 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Recommended Operating Conditions over junction temperature range (unless otherwise noted) SUPPLY NAME DESCRIPTION VDD_CORE VDD_MPU MIN NOM MAX Supply voltage range for core domain; OPP100 1.056 1.100 1.144 Supply voltage range for core domain; OPP50 0.912 0.950 1.000 Supply voltage range for MPU domain, Nitro 1.272 1.325 1.378 Supply voltage range for MPU domain; Turbo 1.210 1.260 1.326 Supply voltage range for MPU domain; OPP120 1.152 1.200 1.248 Supply voltage range for MPU domain; OPP100 1.056 1.100 1.144 UNIT V V Supply voltage range for MPU domain; OPP50 0.912 0.950 1.000 CAP_VDD_RTC(1) Supply voltage range for RTC core domain 0.900 1.100 1.250 V VDDS_RTC Supply voltage range for RTC domain 1.710 1.800 1.890 V Supply voltage range for DDR IO domain (DDR3) 1.425 1.500 1.575 Supply voltage range for DDR IO domain (DDR3L) 1.283 1.350 1.418 Supply voltage range for DDR IO domain (LPDDR2) 1.140 1.200 1.260 VDDS(2) Supply voltage range for all dual-voltage IO domains 1.710 1.800 1.890 V VDDS_SRAM_CORE_BG Supply voltage range for Core SRAM LDOs, Analog 1.710 1.800 1.890 V VDDS_SRAM_MPU_BB Supply voltage range for MPU SRAM LDOs, Analog 1.710 1.800 1.890 V VDDS_PLL_DDR(3) Supply voltage range for DPLL DDR, Analog 1.710 1.800 1.890 V Supply voltage range for DPLL CORE, EXTDEV, and LCD, Analog 1.710 1.800 1.890 V Supply voltage range for DPLL MPU, Analog 1.710 1.800 1.890 V Supply voltage range for system oscillator, Analog 1.710 1.800 1.890 V VDDA1P8V_USB0 Supply voltage range for USBPHY and DPLL PER, Analog, 1.8 V 1.710 1.800 1.890 V VDDA1P8V_USB1 Supply voltage range for USBPHY, Analog, 1.8 V 1.710 1.800 1.890 V VDDA3P3V_USB0 Supply voltage range for USBPHY, Analog, 3.3 V 3.135 3.300 3.465 V VDDA3P3V_USB1 Supply voltage range for USBPHY, Analog, 3.3 V 3.135 3.300 3.465 V VDDA_ADC0 Supply voltage range for ADC0, Analog 1.710 1.800 1.890 V VDDA_ADC1 Supply voltage range for ADC1, Analog 1.710 1.800 1.890 V 1.710 1.800 1.890 VDDS_DDR (3) VDDS_PLL_CORE_LCD VDDS_PLL_MPU (3) VDDS_OSC (3) V VDDSHV1 Supply voltage range for dual-voltage IO domain 1.8-V operation 3.3-V operation 3.135 3.300 3.465 VDDSHV2 Supply voltage range for dual-voltage IO domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 VDDSHV3 Supply voltage range for dual-voltage IO domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 VDDSHV5 Supply voltage range for CLKOUT voltage domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 VDDSHV6 Supply voltage range for dual-voltage IO domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 VDDSHV7 Supply voltage range for dual-voltage IO domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 VDDSHV8 Supply voltage range for dual-voltage IO domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 VDDSHV9 Supply voltage range for dual-voltage IO domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 VDDSHV10 Supply voltage range for dual-voltage IO domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 VDDSHV11 Supply voltage range for dual-voltage IO domain 1.8-V operation 1.710 1.800 1.890 3.3-V operation 3.135 3.300 3.465 DDR_VREF Supply voltage range for the DDR3/DDR3L HSTL, LPDDR2 HSUL_12 reference input 0.49 x VDDS_DDR 0.50 x VDDS_DDR 0.51 x VDDS_DDR V VDDS3P3V_IOLDO Supply voltage range for the dual-voltage IO LDO 3.135 3.3 3.465 V VDDS_CLKOUT Supply voltage range for CLKOUT domain 1.71 1.8 1.89 V Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications V V V V V V V V V V 107 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Recommended Operating Conditions (continued) over junction temperature range (unless otherwise noted) MIN NOM MAX UNIT USB0_VBUS SUPPLY NAME Voltage range for USB VBUS comparator input DESCRIPTION 0.000 5.000 5.250 V USB1_VBUS Voltage range for USB VBUS comparator input 0.000 5.000 5.250 V USB0_ID Voltage range for the USB ID input (4) USB1_ID Voltage range for the USB ID input (4) Commercial Temperature Operating Temperature Range, Tj 0 V V 90 Industrial Temperature -40 90 Extended Temperature -40 105 C (1) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced from an external power supply. (2) VDDS should be supplied irrespective of 1.8-V or 3.3-V mode of operation of the dual-voltage IOs. (3) For more details on power supply requirements, see Section 5.13.2.1.1. (4) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 or greater than 100 k. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source. 108 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 5.6 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Power Consumption Summary Table 5-4 summarizes the maximum power consumption at each power terminal. Note: Data in the Maximum Current Ratings table (Table 5-4) represents worst-case power consumption based on various applications of the device using practical operating conditions. The data primarily benefits the power supply designer trying to understand the worst-case power consumption expected from each power rail. Table 5-4. Maximum Current Ratings at Power Terminals (1) PARAMETER MAX UNIT Maximum current rating for the core domain; OPP100 600 mA Maximum current rating for the core domain; OPP50 400 mA SUPPLY NAME VDD_CORE VDD_MPU DESCRIPTION Maximum current rating for the MPU domain; Nitro at 1 GHz 1000 Maximum current rating for the MPU domain; Turbo at 800 MHz 800 Maximum current rating for the MPU domain; OPP120 at 720 MHz 720 Maximum current rating for the MPU domain; OPP100 at 600 MHz 600 Maximum current rating for the MPU domain; OPP50 at 300 MHz 350 mA CAP_VDD_RTC (2) Maximum current rating for RTC domain and LDO output 2 mA VDDS_RTC Maximum current rating for the RTC domain 5 mA VDDS_DDR Maximum current rating for DDR IO domain; DDR3/DDR3L 300 mA Maximum current rating for DDR IO domain; LPDDR2 150 VDDS Maximum current rating for all dual-voltage IO domains 70 mA VDDS_SRAM_CORE_BG Maximum current rating for core SRAM LDOs 10 mA VDDS_SRAM_MPU_BB Maximum current rating for MPU SRAM LDOs 10 mA VDDS_PLL_DDR Maximum current rating for the DPLL DDR 10 mA VDDS_PLL_CORE_LCD Maximum current rating for the DPLL CORE, EXTDEV, and LCD 20 mA VDDS_PLL_MPU Maximum current rating for the DPLL MPU 10 mA VDDS_OSC Maximum current rating for the system oscillator 5 mA VDDA1P8V_USB0 Maximum current rating for USBPHY 1.8 V and DPLL PER 25 mA VDDA1P8V_USB1 Maximum current rating for USBPHY 1.8 V 25 mA VDDA3P3V_USB0 Maximum current rating for USBPHY 3.3 V 40 mA VDDA3P3V_USB1 Maximum current rating for USBPHY 3.3 V 40 mA VDDS3P3V_IOLDO Maximum current rating for the dual-voltage IO LDO 30 mA VDDA_ADC0 Maximum current rating for ADC0 10 mA VDDA_ADC1 Maximum current rating for ADC1 10 mA VDDSHV1 Maximum current rating for dual-voltage IO domain 30 mA VDDSHV2 Maximum current rating for dual-voltage IO domain 80 mA VDDSHV3 Maximum current rating for dual-voltage IO domain 100 mA VDDSHV5 Maximum current rating for dual-voltage IO domain 10 mA VDDSHV6 Maximum current rating for dual-voltage IO domain 50 mA VDDSHV7 Maximum current rating for dual-voltage IO domain 10 mA VDDSHV8 Maximum current rating for dual-voltage IO domain 50 mA VDDSHV9 Maximum current rating for dual-voltage IO domain 50 mA VDDSHV10 Maximum current rating for dual-voltage IO domain 50 mA VDDSHV11 Maximum current rating for dual-voltage IO domain 50 mA VDDS_CLKOUT Maximum current rating for CLKOUT domain 10 mA (1) (2) Current ratings specified in this table are worst-case estimates. Actual application power supply estimates could be lower. For more information, see AM43xx Power Consumption Summary. This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced from an external power supply. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 109 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.7 www.ti.com DC Electrical Characteristics over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1) PARAMETER MIN TYP MAX UNIT DDR_CSn[1:0], DDR_CKE[1:0], DDR_CK, DDR_CKn, DDR_CASn, DDR_RASn, DDR_WEn, DDR_BA[2:0], DDR_A[15:0], DDR_ODT[1:0], DDR_D[31:0], DDR_DQM[3:0], DDR_DQS[3:0], DDR_DQSn[3:0] pins (DDR3/DDR3L - HSTL mode) VIH High-level input voltage VDDS_DDR = 1.5 V DDR_VREF + 0.1 VDDS_DDR = 1.35 V DDR_VREF + 0.09 VDDS_DDR = 1.5 V DDR_VREF - 0.1 VDDS_DDR = 1.35 V DDR_VREF - 0.09 VIL Low-level input voltage VHYS Hysteresis voltage at an input VOH High-level output voltage, driver enabled, pullup or pulldown disabled IOH = 8 mA VOL Low-level output voltage, driver enabled, pullup or pulldown disabled IOL = 8 mA NA Input leakage current, Receiver disabled, pullup or pulldown inhibited II Input leakage current, Receiver disabled, pullup enabled Input leakage current, Receiver disabled, pulldown enabled IOZ V Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver output is disabled and the pullup or pulldown is inhibited. V V VDDS_DDR - 0.4 V 0.4 -10 10 -240 -40 40 240 -10 10 V A A DDR_CSn[1:0], DDR_CKE[1:0], DDR_CK, DDR_CKn, DDR_CASn, DDR_RASn, DDR_WEn, DDR_BA[2:0], DDR_A[15:0], DDR_D[31:0], DDR_DQM[3:0], DDR_DQS[3:0], DDR_DQSn[3:0] pins (LPDDR2 - HSUL_12 mode)(2) VIH High-level input voltage VDDS_DDR = 1.2 V VIL Low-level input voltage VDDS_DDR = 1.2 V VHYS Hysteresis voltage at an input VOH High-level output voltage, driver enabled, pullup or pulldown disabled IOH = 8 mA VOL Low-level output voltage, driver enabled, pullup or pulldown disabled IOL = 8 mA Input leakage current, Receiver disabled, pullup enabled Input leakage current, Receiver disabled, pulldown enabled IOZ V DDR_VREF - 0.13 NA Input leakage current, Receiver disabled, pullup or pulldown inhibited II DDR_VREF + 0.13 Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver output is disabled and the pullup or pulldown is inhibited. V V VDDS_DDR - 0.4 V 0.4 -10 10 -240 -40 40 240 -10 10 V A A DDR_RESETn(3) VIH High-level input voltage NA VIL Low-level input voltage NA VHYS Hysteresis voltage at an input VOH High-level output voltage, driver enabled, pullup or pulldown disabled IOH = 8 mA VOL Low-level output voltage, driver enabled, pullup or pulldown disabled IOL = 8 mA NA Input leakage current, Receiver disabled, pullup or pulldown inhibited II Input leakage current, Receiver disabled, pullup enabled Input leakage current, Receiver disabled, pulldown enabled 110 Specifications VDDS_DDR - 0.4 V 0.4 -10 10 -240 -24 24 240 V A Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 DC Electrical Characteristics (continued) over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1) PARAMETER IOZ MIN Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver output is disabled and the pullup or pulldown is inhibited. TYP -10 MAX UNIT 10 A RTC_PWRONRSTn VIH High-level input voltage VIL Low-level input voltage VHYS Hysteresis voltage at an input II Input leakage current 0.65 x VDDS_RTC V 0.35 x VDDS_RTC 0.065 V V -1 1 A RTC_PMIC_EN VOH High-level output voltage, driver enabled, pullup or pulldown disabled IOH = 6 mA VOL Low-level output voltage, driver enabled, pullup or pulldown disabled IOL = 6 mA Input leakage current, Receiver disabled, pullup or pulldown inhibited II IOZ VDDS_RTC - 0.45 V 0.45 -1 1 -200 -40 Input leakage current, Receiver disabled, pulldown enabled 40 200 Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver output is disabled and the pullup or pulldown is inhibited. -1 1 Input leakage current, Receiver disabled, pullup enabled V A A RTC_WAKEUP VIH High-level input voltage VIL Low-level input voltage VHYS Hysteresis voltage at an input 0.65 x VDDS_RTC 0.35 x VDDS_RTC 0.15 Input leakage current, Receiver disabled, pullup or pulldown inhibited II V Input leakage current, Receiver disabled, pullup enabled Input leakage current, Receiver disabled, pulldown enabled V V -1 1 -200 -40 40 200 A TCK (VDDSHV3 = 1.8 V) VIH High-level input voltage VIL Low-level input voltage VHYS Hysteresis voltage at an input 0.4 Input leakage current, Receiver disabled, pullup or pulldown inhibited -8 II 1.45 V 0.46 Input leakage current, Receiver disabled, pullup enabled Input leakage current, Receiver disabled, pulldown enabled V V 8 -161 -100 -52 52 100 170 A TCK (VDDSHV3 = 3.3 V) VIH High-level input voltage VIL Low-level input voltage VHYS Hysteresis voltage at an input 0.4 Input leakage current, Receiver disabled, pullup or pulldown inhibited -18 II 2.15 V 0.46 Input leakage current, Receiver disabled, pullup enabled Input leakage current, Receiver disabled, pulldown enabled V V 18 -243 -100 -19 51 110 210 A (4) PWRONRSTn (VDDSHV3 = 1.8 V or 3.3 V) VIH High-level input voltage VIL Low-level input voltage 1.35 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 V 0.5 Specifications V 111 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com DC Electrical Characteristics (continued) over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1) PARAMETER VHYS II MIN Hysteresis voltage at an input Input leakage current TYP MAX 0.07 UNIT V VI = 1.8 V 0.1 VI = 3.3 V 2 A All other LVCMOS pins (VDDSHVx = 1.8 V; x=1-11) VIH VIL High-level input voltage 0.65 x VDDSHVx Low-level input voltage VHYS Hysteresis voltage at an input VOH High-level output voltage, driver enabled, pullup or pulldown disabled IOH = 6 mA VOL Low-level output voltage, driver enabled, pullup or pulldown disabled IOL = 6 mA II 0.35 x VDDSHVx V 0.305 V 0.18 VDDSHVx - 0.45 V 0.45 Input leakage current, Receiver disabled, pullup or pulldown inhibited -8.4 Input leakage current, Receiver disabled, pullup enabled -161 -100 -52 52 100 170 Input leakage current, Receiver disabled, pulldown enabled IOZ V Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver output is disabled and the pullup or pulldown is inhibited. V 8.4 -8.4 A 8.4 A All other LVCMOS pins (VDDSHVx = 3.3 V; x=1-11) VIH High-level input voltage VIL Low-level input voltage 2 VHYS Hysteresis voltage at an input VOH High-level output voltage, driver enabled, pullup or pulldown disabled IOH = 6 mA VOL Low-level output voltage, driver enabled, pullup or pulldown disabled IOL = 6 mA 0.265 Input leakage current, Receiver disabled, pullup or pulldown inhibited II Input leakage current, Receiver disabled, pullup enabled Input leakage current, Receiver disabled, pulldown enabled IOZ V Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver output is disabled and the pullup or pulldown is inhibited. 0.8 V 0.44 V VDDSHVx - 0.45 V 0.45 -18 V 18 -243 -100 -19 51 110 210 -18 A 18 A XTALIN (OSC0) VIH VIL High-level input voltage 0.65 x VDDS_OSC Low-level input voltage V 0.35 x VDDS_OSC V RTC_XTALIN (OSC1) VIH VIL High-level input voltage 0.65 x VDDS_RTC Low-level input voltage V 0.35 x VDDS_RTC V (1) The interfaces or signals described in this table correspond to the interfaces or signals available in multiplexing mode 0. All interfaces or signals multiplexed on the terminals described in this table have the same DC electrical characteristics. (2) For mapping to the LPDDR2 interface terminal name, see the AM437x Sitara Processors Technical Reference Manual. (3) The DDR_RESETn terminal supports fail-safe operation. (4) The input voltage thresholds for this input are not a function of VDDSHV3. 112 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 5.8 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 ADC0: Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters The touch screen controller (TSC) and analog-to-digital converter (ADC) subsystem (ADC0) contains a single-channel ADC connected to an 8:1 analog multiplexer which operates as a general-purpose ADC with optional support for interleaving TSC conversions for 4-wire, 5-wire, or 8-wire resistive panels. The ADC0 subsystem can be configured for use in one of the following applications: * 8 general-purpose ADC channels * 4-wire TSC with 4 general-purpose ADC channels * 5-wire TSC with 3 general-purpose ADC channels * 8-wire TSC Table 5-5 summarizes the ADC0 subsystem electrical parameters. Table 5-5. ADC0 Electrical Parameters PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ANALOG INPUT ADC0_VREFP(1) (0.5 x VDDA_ADC0) + 0.25 VDDA_ADC0 V ADC0_VREFN(1) 0 (0.5 x VDDA_ADC0) - 0.25 V ADC0_VREFP + ADC0_VREFN Full-scale Input Range Differential Nonlinearity (DNL) Integral Nonlinearity (INL) VDDA_ADC0 Internal Voltage Reference V 0 VDDA_ADC0 External Voltage Reference ADC0_VREFN ADC0_VREFP Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V -1 0.5 1 Source impedance = 50 Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V -2 1 2 V LSB LSB Source Impedance = 1 k Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V 1 Gain Error Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V 2 LSB Offset Error Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V 2 LSB Input Sampling Capacitance 5.5 pF Signal-to-Noise Ratio (SNR) Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 70 dB Total Harmonic Distortion (THD) Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 75 dB Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 113 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-5. ADC0 Electrical Parameters (continued) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Spurious Free Dynamic Range Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 80 dB Signal-to-Noise Plus Distortion Internal Voltage Reference: VDDA_ADC0 = 1.8 V External Voltage Reference: VREFP - VREFN = 1.8 V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 69 dB VREFP and VREFN Input Impedance Input Impedance of AIN[7:0](2) f = input frequency 20 k -12 [1/((65.97 x 10 ) x f)] SAMPLING DYNAMICS ADC Clock Frequency 13 Conversion Time 13 Acquisition Time Sampling Rate(3) 2 ADC0 Clock = 13 MHz Channel-to-Channel Isolation MHz ADC0 clock cycles 257 ADC0 clock cycles 867 kSPS 100 dB 2 TOUCH SCREEN SWITCH DRIVERS Pullup and Pulldown Switch ON-Resistance (Ron) Pullup and Pulldown Switch Source impedance = 500 Current Leakage Ileak 0.5 uA Drive Current 25 mA Touch Screen Resistance 6 k Pen Touch Detect 2 k (1) The ADC0_VREFP and ADC0_VREFN terminals should not be allowed to float to prevent noise from coupling into the ADC. If ADC0_VREFN is not used to connect an external negative voltage reference to the ADC, connect it to VSSA_ADC. If ADC0_VREFP is not used to connect an external positive voltage reference to the ADC, connect it to VSSA_ADC or VDDA_ADC0. Connecting ADC0_VREFP to VSSA_ADC in this use case is the preferred option because VDDA_ADC0 may couple more noise into the ADC than VSSA_ADC. (2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input. (3) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2 ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted digital value. 114 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com 5.9 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 ADC1: Analog-to-Digital Subsystem Electrical Parameters The analog-to-digital converter (ADC) subsystem implements a basic general-purpose ADC1. Table 5-6 summarizes the ADC1 subsystem electrical parameters. Table 5-6. ADC1 Electrical Parameters PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ANALOG INPUT ADC1_VREFP Bypass mode (0.5 x VDDA_ADC1) + 0.25 Gain mode (0.5 x VDDA_ADC1) + 0.25 (1) Bypass mode 0 Gain mode 0 VDDA_ADC1 V 1.2(2) (0.5 x VDDA_ADC1) - 0.25 (1) ADC1_VREFN ADC1_VREFP + ADC1_VREFN (0.5 x VDDA_ADC1) - 0.25 VDDA_ADC1 ADC1_VREFN ADC1_VREFP Gain mode, Internal Voltage Reference -(VDDA_ADC1 / Gain) (VDDA_ADC1 / Gain) Gain mode, External Voltage Reference -((ADC1_VREFP - ADC1_VREFN) / Gain) ((ADC1_VREFP - ADC1_VREFN) / Gain) Bypass mode, External Voltage Reference Gain mode (differential) Differential Nonlinearity (DNL) Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V V V 0 Preamp output Preamp Gain 0.5(2) VDDA_ADC1 Bypass mode, Internal Voltage Reference Full-scale Input Range VDDA_ADC1 V 2.4 -1 0.5 GAIN_CTRLx[MSB:LSB] = 00b 12 GAIN_CTRLx[MSB:LSB] = 01b 14 GAIN_CTRLx[MSB:LSB] = 10b 16 GAIN_CTRLx[MSB:LSB] = 11b V 1 LSB 18 Preamp Bandwidth Gain mode 15 50 -2 1 Integral Nonlinearity (INL) Bypass mode Source impedance = 1 k Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V kHz 2 LSB Gain mode Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V 1 Gain Error Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V 2 LSB Offset Error Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V 2 LSB Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 115 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-6. ADC1 Electrical Parameters (continued) PARAMETER Input Capacitance TEST CONDITIONS Bypass mode Gain mode Differential Input Impedance(3) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range Signal-to-Noise Plus Distortion 116 Specifications NOM UNIT pF 2 pF 18 k 70 Gain mode External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.2 V Input Signal: 5 kHz sine wave at Full Scale 70 Bypass mode Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 75 Gain mode External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.2 V Input Signal: 5 kHz sine wave at Full Scale 75 Bypass mode Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 80 Gain mode External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.2 V Input Signal: 5 kHz sine wave at Full Scale 80 Bypass mode Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale 69 Gain mode External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.2 V Input Signal: 5 kHz sine wave at Full Scale 69 f = input frequency MAX 5.5 Bypass mode Internal Voltage Reference: VDDA_ADC1 = 1.8 V External Voltage Reference: ADC1_VREFP - ADC1_VREFN = 1.8 V Input Signal: 30 kHz sine wave at -0.5 dB Full Scale ADC1_VREFP and ADC1_VREFN Input Impedance Input Impedance of ADC1_AIN[7:0](4) MIN dB dB dB dB 20 k [1/((65.97 x 10-12) x f)] Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-6. ADC1 Electrical Parameters (continued) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SAMPLING DYNAMICS ADC Clock Frequency 13 Conversion Time 13 Acquisition Time(5) Sampling Rate(6) MHz ADC clock cycles 2 ADC Clock = 13 MHz 257 ADC clock cycles 867 kSPS (1) The ADC1_VREFP and ADC1_VREFN terminals should not be allowed to float to prevent noise from coupling into the ADC. If ADC1_VREFN is not used to connect an external negative voltage reference to the ADC, connect it to VSSA_ADC. If ADC1_VREFP is not used to connect an external positive voltage reference to the ADC, connect it to VSSA_ADC or VDDA_ADC1. Connecting ADC1_VREFP to VSSA_ADC in this use case is the preferred option because VDDA_ADC1 may couple more noise into the ADC than VSSA_ADC. (2) If the application using ADC1 requires low distortion when operating in Gain mode, the preamplifier output should be limited to 1.2 volts differential. To get the full dynamic range of the ADC for this use case it will be necessary to provide a 0.3 volt reference for ADC1_VREFN and 1.5 volt reference for ADC1_VREFP. (3) The differential input impedance of each preamplifier is biased to VDDA_ADC1 divided by 2 with a 22-k to 50-k source. See the AFE Functional Description section of the device-specific TRM for more information. (4) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input. (5) The maximum sample rate of ADC1 may be reduced when using the internal preamplifiers because the preamplifier outputs require 600 ns to settle. Sample Delay must be configured to provide a minimum acquisition time of 600 ns when using the preamplifiers. An increase in acquisition time may reduce the maximum sample rate because the maximum sample rate is based on a minimum acquisition time of 2 ADC clock cycles. For example, the minimum Sample Delay value should be 6 when the preamplifiers are being used with a 13-MHz ADC clock. A Sample Delay of 6 provides an acquisition time of 8 ADC clock cycles, which reduces the maximum single input sample rate to 619 kSPS when the acquisition time is combined with the conversion time of 13 ADC clock cycles. (6) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2 ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted digital value. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 117 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.10 VPP Specifications for One-Time Programmable (OTP) eFuses This section specifies the operating conditions required for programming the OTP eFuses and is applicable only for high-security (AM437xHS) devices. Table 5-7. Recommended Operating Conditions for OTP eFuse Programming PARAMETER VDD_CORE DESCRIPTION Supply voltage range for the core domain during OTP operation; OPP100 MIN 1.056 Supply voltage range for the eFuse ROM domain during normal operation VPP Supply voltage range for the eFuse ROM domain during OTP programming (1) (2) NOM MAX UNIT 1.1 1.144 V 1.75 V NC 1.65 1.7 0 30 I(VPP) Temperature (ambient) (1) (2) 50 mA 50 C Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70717 from the TLV707x family meet the supply voltage range needed for VPP. During normal operation, no voltage should be applied to VPP. This can be typically achieved by disabling the regulator attached to the VPP terminal. For more details, see TLV707, TLV707P 200-mA, Low-IQ, Low-Noise, Low-Dropout Regulator for Portable Devices. 5.10.1 Hardware Requirements The following hardware requirements must be met when programming keys in the OTP eFuses: * The VPP power supply must be disabled when not programming OTP registers. * The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see Section 5.13.1.2). 5.10.2 Programming Sequence Programming sequence for OTP eFuses: 1. Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during power up and normal operation. 2. Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP software package). 3. Apply the voltage on the VPP terminal according to the specification in Table 5-7. 4. Run the software that programs the OTP registers. 5. After validating the content of the OTP registers, remove the voltage from the VPP terminal. 5.10.3 Impact to Your Hardware Warranty You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a failure may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI device specifications prior to the attempted eFuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY FOR ANY TI DEVICES THAT HAVE BEEN eFUSED. 118 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.11 Thermal Resistance Characteristics Failure to maintain a junction temperature within the range specified in Section 5.5 reduces operating lifetime, reliability, and performance--and may cause irreversible damage to the system. Therefore, the product design cycle should include thermal analysis to verify the maximum operating junction temperature of the device. It is important this thermal analysis is performed using specific system use cases and conditions. TI provides an application report to aid users in overcoming some of the existing challenges of producing a good thermal design. For more information, see AM43xx Thermal Considerations. Table 5-8 provides thermal characteristics for the packages used on this device. NOTE This table provides simulation data and may not represent actual use-case values. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 119 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-8. Thermal Resistance Characteristics (NFBGA Package) [ZDN] over operating free-air temperature range (unless otherwise noted) ZDN (C/W) (1) AIR FLOW (m/s) (1) (3) NAME DESCRIPTION RJC Junction-to-case 7.07 NA RJB Junction-to-board 11.11 NA 23.0 0.0 19.5 0.5 18.5 1.0 17.5 2.0 16.9 3.0 2.10 0.0 2.16 0.5 2.20 1.0 2.27 2.0 2.31 3.0 11.59 0.0 11.18 0.5 11.05 1.0 10.91 2.0 10.80 3.0 RJA PsiJT PsiJB (1) (2) (3) 120 Junction-to-free air Junction-to-package top Junction-to-board (2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards: * JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air) * JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages * JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages * JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements Power dissipation of 2 W and an ambient temperature of 70C is assumed. C/W = degrees Celsius per watt. m/s = meters per second. Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.12 External Capacitors To improve module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to the device, because this minimizes the inductance of the circuit board wiring and interconnects. 5.12.1 Voltage Decoupling Capacitors Table 5-9 summarizes the Core voltage decoupling characteristics. 5.12.1.1 Core Voltage Decoupling Capacitors To improve module performance, decoupling capacitors are required to suppress high-frequency switching noise and to stabilize the supply voltage. A decoupling capacitor is most effective when located close to the device, because this minimizes the inductance of the circuit board wiring and interconnects. Table 5-9. Core Voltage Decoupling Characteristics TYP UNIT CVDD_CORE(1) PARAMETER 10.08 F CVDD_MPU(2) 10.05 F (1) The typical value corresponds to 1 capacitor of 10 F and 8 capacitors of 10 nF. (2) The typical value corresponds to 1 capacitor of 10 F and 5 capacitors of 10 nF. 5.12.1.2 IO and Analog Voltage Decoupling Capacitors Table 5-10 summarizes the power-supply decoupling capacitor recommendations. Table 5-10. Power-Supply Decoupling Capacitor Characteristics PARAMETER TYP UNIT CVDDA_ADC0 10 nF CVDDA_ADC1 10 nF CVDDA1P8V_USB0(1) 2.21 F CCVDDA3P3V_USB0 10 nF CVDDA1P8V_USB1 10 nF CVDDA3P3V_USB1 10 nF 10.04 F CVDDS(2) CVDDS_DDR (3) CVDDS_OSC 10 nF CVDDS_PLL_DDR 10 nF CVDDS_PLL_CORE_LCD 10 nF CVDDS_SRAM_CORE_BG(4) 10.01 F CVDDS_SRAM_MPU_BB(5) 10.01 F CVDDS_PLL_MPU 10 nF CVDDS_RTC 10 nF CVDDS_CLKOUT 10 nF CVDDS3P3V_IOLDO 10 nF (6) 10.02 F CVDDSHV2(7) 10.06 F CVDDSHV3(7) 10.06 F (6) 10.02 F CVDDSHV6(7) 10.06 F CVDDSHV7(6) 10.02 F CVDDSHV1 CVDDSHV5 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 121 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-10. Power-Supply Decoupling Capacitor Characteristics (continued) TYP UNIT CVDDSHV8(6) PARAMETER 10.02 F (6) CVDDSHV9 10.02 F CVDDSHV10(6) 10.02 F CVDDSHV11(6) 10.02 F (1) Typical values consist of 1 capacitor of 10 F and 4 capacitors of 10 nF. (2) Typical values consist of 1 capacitor of 2.2 F and 1 capacitor of 10 nF. (3) For more details on decoupling capacitor requirements for the DDR3 and DDR3L memory interface, see Section 5.13.8.2.1.3.6 and Section 5.13.8.2.1.3.7 when using DDR3 and DDR3L memory devices. (4) VDDS_SRAM_CORE_BG supply powers an internal LDO for SRAM supplies. Inrush currents could cause voltage drop on the VDDS_SRAM_CORE_BG supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_CORE_BG terminals. TI recommends placing a 10-F capacitor close to the terminal and routing it with the widest traces possible to minimize the voltage drop on VDDS_SRAM_CORE_BG terminals. (5) VDDS_SRAM_MPU_BB supply powers an internal LDO for SRAM supplies. Inrush currents could cause voltage drop on the VDDS_SRAM_MPU_BB supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_MPU_BB terminals. TI recommends placing a 10-F capacitor close to the terminal and routing it with the widest traces possible to minimize the voltage drop on VDDS_SRAM_MPU_BB terminals. (6) Typical values consist of 1 capacitor of 10 F and 2 capacitors of 10 nF. (7) Typical values consist of 1 capacitor of 10 F and 6 capacitors of 10 nF. 5.12.2 Output Capacitors Internal low dropout output (LDO) regulators require external capacitors to stabilize their outputs. These capacitors should be placed as close as possible to the respective terminals of the device. Table 5-11 summarizes the LDO output capacitor recommendations. Table 5-11. Output Capacitor Characteristics PARAMETER CCAP_VDD_SRAM_CORE (1) CCAP_VDD_RTC (1) (2) TYP UNIT 1 F 1 F CCAP_VDD_SRAM_MPU (1) 1 F CCAP_VBB_MPU (1) 1 F 2.2 F CCAP_VDDS1P8V_IOLDO (1) (2) (3) 122 (1) (3) LDO regulator outputs should not be used as a power source for any external components. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the RTC_KALDO_ENn terminal is high. The CAP_VDDS1P8V_IOLDO terminal is the output of the IO LDO and required for simplified power sequencing. For more details, see Figure 5-8. If simplified power sequencing is not used, this terminal can be left floating. Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Figure 5-2 shows an example of the external capacitors. Device VDDS_PLL_MPU MPU PLL VDD_MPU CVDDS_PLL_MPU EXTDEV PLL MPU CVDD_MPU VDDS_PLL_CORE_LCD CORE PLL VDD_CORE CORE CVDDS_PLL_CORE_LCD LCD PLL CAP_VBB_MPU CVDD_CORE CCAP_VBB_MPU CVDDS CVDDSHV1 VDDS IO VDDS_SRAM_MPU_BB CVDDS_SRAM_MPU_BB VDDSHV1 IOs MPU SRAM LDO Back Bias LDO CVDDSHV2 CAP_VDD_SRAM_MPU CCAP_VDD_SRAM_MPU VDDSHV2 IOs VDDS_SRAM_CORE_BG CVDDSHV3 VDDSHV3 IOs CVDDS_SRAM_CORE_BG CORE SRAM LDO Band Gap Reference CVDDSHV5 CAP_VDD_SRAM_CORE VDDSHV5 IOs CCAP_VDD_SRAM_CORE VDDA_3P3V_USB0 CVDDSHV6 VDDSHV6 IOs CVDDA_3P3V_USB0 VSSA_USB USBPHY0 CVDDSHV7 VDDSHV7 IOs VDDA_1P8V_USB0 PER PLL CVDDA_1P8V_USB0 VSSA_USB CVDDSHV8 VDDSHV8 IOs VDDA_3P3V_USB1 CVDDA_3P3V_USB1 CVDDSHV9 VDDSHV9 IOs VSSA_USB USBPHY1 VDDA_1P8V_USB1 CVDDA_1P8V_USB1 CVDDSHV10 VDDSHV10 IOs VSSA_USB VDDA_ADC0 CVDDSHV11 VDDSHV11 IOs CVDDA_ADC0 ADC0 VSSA_ADC CVDDS_DDR VDDA_ADC1 VDDS_DDR IOs CVDDA_ADC1 ADC1 VSSA_ADC VDDS_RTC IOs CVDDS_RTC VDDS_OSC CVDDS_OSC VDDS_PLL_DDR CVDDS_PLL_DDR DDR PLL CAP_VDD_RTC RTC CCAP_VDD_RTC VDDS3P3V_ IOLDO A. B. CAP_VDDS1P8V_IOLDO Decoupling capacitors must be placed as closed as possible to the power terminal. Choose the ground closest to the power pin for each decoupling capacitor. In case of interconnecting powers, first insert the decoupling capacitor and then interconnect the powers. The decoupling capacitor value depends on the board characteristics. Figure 5-2. External Capacitors Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 123 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13 Timing and Switching Characteristics The data provided in the following timing requirements and switching characteristics tables assumes the device is operating within the recommended operating conditions defined in Section 5.5, unless otherwise noted. 5.13.1 Power Supply Sequencing 5.13.1.1 Power Supply Slew Rate Requirement To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the maximum slew rate of supplies to be less than 1.0E + 5 V/s. For instance, as shown in Figure 5-3, TI recommends having the supply ramp slew for a 1.8-V supply of more than 18 s. Supply value t slew rate < 1E + 5 V/s slew > (supply value) / (1E + 5V/s) supply value 10 s 0 Figure 5-3. Power Supply Slew and Slew Rate 124 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.1.2 Power-Up Sequencing 1.8V (A) VDDS_RTC 1.8V RTC_PWRONRSTn (B) 1.8V RTC_PMIC_EN 1.8V VDDS, VDDS_CLKOUT 1.8V VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR, VDDS_PLL_CORE_LCD, VDDS_PLL_MPU, VDDS_SRAM_MPU_BB, VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1 (C) 1.2V/1.35V/1.5V VDDS_DDR 3.3V VDDSHVx [x=1-11] VDDA3P3V_USB0/1 1.1V VDD_CORE (D) 1.1V VDD_MPU (D) CLK_32K_RTC CLK_M_OSC 1.8V/3.3V (E) (F) PWRONRSTn A. B. C. D. E. F. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. VDDS_RTC can be ramped independent of other supplies if RTC_PMIC_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE when internal RTC LDO is enabled, there might be a small amount of leakage current on VDD_CORE. RTC_PWRONRSTn should be asserted for at least 1 ms and can be released before the 32-kHz clock is stable. These supplies can be ramped together with VDDS, VDDS_CLKOUT supplies if powered from the same source only. If a USB port is not used, the respective VDDA1P8V_USB may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3V supply, the VDDA3P3V_USB may be connected to ground. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used. PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe. PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However, PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input terminal, see Section 5.7. It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock CLK_M_OSC is stable. Figure 5-4. Power Sequencing With RTC Feature Enabled, All Dual-Voltage IOs Configured as 3.3 V Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 125 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 1.8V (A) VDDS_RTC RTC_PWRONRSTn 1.8V (B) 1.8V RTC_PMIC_EN 1.8V VDDS, VDDSHVx [x=1-11] VDDS_CLKOUT 1.8V VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR, VDDS_PLL_CORE_LCD, VDDS_PLL_MPU, VDDS_SRAM_MPU_BB, VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1 (C) 1.2V/1.35V/1.5V VDDS_DDR 3.3V VDDA3P3V_USB0/1 1.1V VDD_CORE (D) 1.1V VDD_MPU (D) CLK_32K_RTC CLK_M_OSC 1.8V (E) PWRONRSTn A. B. C. D. E. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. RTC_PWRONRSTn should be asserted for at least 1 ms and can be released before the 32-kHz clock is stable. These supplies can be ramped together with the VDDS, VDDSHVx [x=1-11], VDDS_CLKOUT supplies if powered from the same source. If a USB port is not used, the respective VDDA1P8V_USB may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3V supply, the VDDA3P3V_USB may be connected to ground. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used. It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock CLK_M_OSC is stable. Figure 5-5. Power Sequencing With RTC Feature Enabled, All Dual-Voltage IOs Configured as 1.8 V 126 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 1.8V (A) VDDS_RTC 1.8V RTC_PWRONRSTn (B) 1.8V RTC_PMIC_EN 1.8V VDDS, VDDS_CLKOUT VDDSHVx [x=1-11] 1.8V VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR, VDDS_PLL_CORE_LCD, VDDS_PLL_MPU, VDDS_SRAM_MPU_BB, (C) VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1 1.2V/1.35V/1.5V VDDS_DDR 3.3V VDDSHVx [x=1-11] VDDA3P3V_USB0/1 1.1V VDD_CORE (D) 1.1V VDD_MPU (D) CLK_32K_RTC CLK_M_OSC 1.8V/3.3V (E) (F) PWRONRSTn A. B. C. D. E. F. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. RTC_PWRONRSTn should be asserted for at least 1 ms and can be released before the 32-kHz clock is stable. These supplies can be ramped together with the VDDS, VDDSHVx [x=1-11], VDDS_CLKOUT supplies if powered from the same source. If a USB port is not used, the respective VDDA1P8V_USB may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3V supply, the VDDA3P3V_USB may be connected to ground. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used. PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe. PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However, PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input terminal, see Section 5.7. It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock CLK_M_OSC is stable. Figure 5-6. Power Sequencing With RTC Feature Enabled, Dual-Voltage IOs Configured as 1.8 V, 3.3 V Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 127 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 1.8V VDDS, VDDS_CLKOUT VDDSHVx [x=1-11] 1.8V VDDS_RTC, VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR, VDDS_PLL_CORE_LCD, VDDS_PLL_MPU, VDDS_SRAM_MPU_BB, VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1 (A) 1.2V/1.35V/1.5V VDDS_DDR 3.3V VDDSHVx [x=1-11] VDDA3P3V_USB0/1 1.1V VDD_CORE (B) CAP_VDD_RTC , (C) 1.1V VDD_MPU (B) CLK_M_OSC 1.8V/3.3V (D) (E) PWRONRSTn A. B. C. D. E. These supplies can be ramped together with the VDDS, VDDSHVx [x=1-11], VDDS_CLKOUT supplies if powered from the same source. If a USB port is not used, the repsective VDDA1P8V_USB may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3V supply, the VDDA3P3V_USB may be connected to ground. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. VDDS_RTC can be ramped independent of other supplies if RTC_PMIC_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE when internal RTC LDO is enabled, there might be a small amount of leakage current on VDD_CORE. PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe. PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However, PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input terminal, see Section 5.7. It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock CLK_M_OSC is stable. Figure 5-7. Power Sequencing With RTC Feature Disabled, Dual-Voltage IOs Configured as 1.8 V, 3.3 V 128 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 3.3V VDDS3P3V_IOLDO, VDDSHVx [x=1-11] VDDA3P3V_USB0/1 (A) 1.8V VDDS_RTC, VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR, VDDS_PLL_CORE_LCD, VDDS_PLL_MPU, VDDS_SRAM_MPU_BB, VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1 (B) 1.2V/1.35V/1.5V VDDS_DDR 1.1V VDD_CORE CAP_VDD_RTC (C) (D) 1.1V VDD_MPU (C) CLK_M_OSC 1.8V/3.3V (E) (F) PWRONRSTn A. B. C. D. E. F. Power source supplying VDDS3P3V_IOLDO should have a supply slew of >100us. CAP_VDDS1P8V_IOLDO is the 1.8-V output of VDDA3P3V_IOLDO. VDDS, VDDS_CLKOUT terminals are powered by shorting them to CAP_VDDS1P8V_IOLDO on the board. If a USB port is not used, the repsective VDDA1P8V_USB may be connected to any 1.8-V power supply and the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3V supply, the VDDA3P3V_USB may be connected to ground. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. VDDS_RTC can be ramped independent of other supplies if RTC_PMIC_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE when internal RTC LDO is enabled, there might be a small amount of leakage current on VDD_CORE. PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe. PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However, PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input terminal, see Section 5.7. The PWRONRSTn terminal must be held low until all the supplies have ramped and the input clock CLK_M_OSC is stable. Figure 5-8. Simplified Power Sequencing With RTC Feature Disabled, Dual-Voltage IOs Configured as 3.3 V Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 129 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.1.3 Power-Down Sequencing PWRONRSTn input terminal should be taken low, which stops all internal clocks before power supplies are turned off. All other external clocks to the device should be shut off. The preferred way to sequence power down is to have all the power supplies ramped down sequentially in the exact reverse order of the power-up sequencing. In other words, the power supply that has been ramped up first should be the last one that is ramped down. This ensures there would be no spurious current paths during the power-down sequence. The VDDS, VDDS_CLKOUT power supply must ramp down after all 3.3-V VDDSHVx [x=1-11] power supplies. If it is desired to ramp down VDDS, VDDS_CLKOUT and VDDSHVx [x=1-11] simultaneously, it should always be ensured that the difference between VDDS, VDDS_CLKOUT and VDDSHVx [x=1-11] during the entire power-down sequence is <2 V. Any violation of this could cause reliability risks for the device. Further, it is recommended to maintain VDDS, VDDS_CLKOUT 1.5V as all the other supplies fully ramp down to minimize in-rush currents. If none of the VDDSHVx [x=1-11] power supplies are configured as 3.3 V, the VDDS, VDDS_CLKOUT power supply may ramp down along with the VDDSHVx [x=1-11] supplies or after all the VDDSHVx [x=111] supplies have ramped down. TI recommends maintaining VDDS, VDDS_CLKOUT 1.5V as all the other supplies fully ramp down to minimize in-rush currents. When using simplified power-down sequence, there are no power-down requirements between the VDDS, VDDS_CLKOUT and VDDSHVx [x=1-11] supplies and are ramped down together without any reliability concerns. 130 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.2 Clock 5.13.2.1 PLLs 5.13.2.1.1 Digital Phase-Locked Loop Power Supply Requirements The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the device. The device integrates six different DPLLs: * Core DPLL * Per DPLL * Display DPLL * DDR DPLL * MPU DPLL * EXTDEV DPLL Figure 5-9 shows the power supply connectivity implemented in the device. Table 5-12 provides the power supply requirements for the DPLL. MPU PLL PER PLL VDDS_PLL_MPU VDDA1P8V_USB0 CORE PLL DDR PLL EXTDEV PLL VDDS_PLL_DDR VDDS_PLL_CORE_LCD LCD PLL Figure 5-9. DPLL Power Supply Connectivity Table 5-12. DPLL Power Supply Requirements SUPPLY NAME DESCRIPTION MIN NOM MAX UNIT VDDA1P8V_USB0 Supply voltage range for USBPHY and PER DPLL, Analog, 1.8V 1.71 1.8 1.89 V 1.71 1.8 1.89 Max. peak-to-peak supply noise VDDS_PLL_MPU Supply voltage range for DPLL MPU, Analog 50 mV (p-p) Max. peak-to-peak supply noise VDDS_PLL_CORE_LCD Supply voltage range for DPLL CORE, EXTDEV, and LCD, Analog 1.71 1.8 Max. peak-to-peak supply noise VDDS_PLL_DDR Supply voltage range for DPLL DDR, Analog Max. peak-to-peak supply noise Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 V 50 mV (p-p) 1.89 V 50 mV (p-p) 1.71 1.8 1.89 V 50 mV (p-p) Specifications 131 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.2.2 Input Clock Specifications The device has two clock inputs. Each clock input passes through an internal oscillator which can be connected to an external crystal circuit (oscillator mode) or external LVCMOS square-wave digital clock source (bypass mode). The oscillators automatically operate in bypass mode when their input is connected to an external LVCMOS square-wave digital clock source. The oscillator associated with a specific clock input must be enabled when the clock input is being used in either oscillator mode or bypass mode. The OSC1 oscillator provides a 32.768-kHz reference clock to the real-time clock (RTC) and is connected to the RTC_XTALIN and RTC_XTALOUT terminals. This clock source is referred to as the 32K oscillator (CLK_32K_RTC) in the device-specific technical reference manual. OSC1 is disabled by default after power is applied. This clock input is optional and may not be required if the RTC is configured to receive a clock from the internal 32k RC oscillator (CLK_RC32K) or peripheral PLL (CLK_32KHZ) which receives a reference clock from the OSC0 input. The OSC0 oscillator provides a 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz reference clock which is used to clock all non-RTC functions and is connected to the XTALIN and XTALOUT terminals. This clock source is referred to as the master oscillator (CLK_M_OSC) in the device-specific technical reference manual. OSC0 is enabled by default after power is applied. For more information related to recommended circuit topologies and crystal oscillator circuit requirements for these clock inputs, see Section 5.13.2.3. 132 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.2.3 Input Clock Requirements 5.13.2.3.1 OSC0 Internal Oscillator Clock Source Figure 5-10 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0- resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs. The XTALIN terminal has a 15-k to 40-k internal pulldown resistor which is enabled when OSC0 is disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. Device VSS_OSC XTALIN XTALOUT C1 C2 Crystal Optional Rd Optional Rbias Copyright (c) 2016, Texas Instruments Incorporated A. B. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator. The external crystal component grounds should be connected to the VSS_OSC terminal. The VSS_OSC terminal should be connected to the PCB ground plane as close as possible to the device. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components (excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL = [(C1xC2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer plus any mutual capacitance (Cpkg + CPCB) seen across the XTALIN and XTALOUT signals. For recommended values of crystal circuit components, see Table 5-13. Figure 5-10. OSC0 Crystal Circuit Schematic Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 133 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-13. OSC0 Crystal Circuit Requirements NAME DESCRIPTION MIN Crystal parallel resonance frequency Fundamental mode oscillation only TYP MAX 19.2, 24.0, 25.0, or 26.0 fxtal Crystal frequency stability and tolerance UNIT MHz -50.0 50.0 ppm CC1 C1 capacitance 12.0 24.0 pF CC2 C2 capacitance 12.0 24.0 pF Cshunt Shunt capacitance 5.0 pF Crystal effective series resistance ESR fxtal = 19.2 MHz, oscillator has nominal negative resistance of 272 and worstcase negative resistance of 163 54.4 fxtal = 24.0 MHz, oscillator has nominal negative resistance of 240 and worstcase negative resistance of 144 48.0 fxtal = 25.0 MHz, oscillator has nominal negative resistance of 233 and worstcase negative resistance of 140 46.6 fxtal = 26.0 MHz, oscillator has nominal negative resistance of 227 and worstcase negative resistance of 137 45.3 Table 5-14. OSC0 Crystal Circuit Characteristics NAME DESCRIPTION Cpkg Shunt capacitance of package MIN Pxtal The actual values of the ESR, fxtal, and CL should be used to yield a typical crystal power dissipation value. Using the maximum values specified for ESR, fxtal, and CL parameters yields a maximum power dissipation value. tsX Start-up time TYP ZDN package UNIT pF Pxtal = 0.5 ESR (2 fxtal CL VDDS_OSC)2 1.5 VDD_CORE (min.) MAX 0.01 ms VDD_CORE Voltage VSS VDDS_OSC (min.) VSS VDDS_OSC XTALOUT tsX Time Figure 5-11. OSC0 Start-up Time 134 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.2.3.2 OSC0 LVCMOS Digital Clock Source Figure 5-12 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. In this mode of operation, the XTALOUT terminal should not be used to source any external components. The printed circuit board design should provide a mechanism to disconnect the XTALOUT terminal from any external components or signal traces that may couple noise into OSC0 via the XTALOUT terminal. The XTALIN terminal has a 15-k to 40-k internal pulldown resistor which is enabled when OSC0 is disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. Device XTALIN VSS_OSC XTALOUT VDDS_OSC LVCMOS Digital Clock Source Copyright (c) 2016, Texas Instruments Incorporated Figure 5-12. OSC0 LVCMOS Circuit Schematic Table 5-15. OSC0 LVCMOS Reference Clock Requirements NAME f(XTALIN) DESCRIPTION MIN Frequency, LVCMOS reference clock Frequency, LVCMOS reference clock stability and tolerance (1) TYP MAX 19.2, 24, 25, or 26 UNIT MHz -50 50 tdc(XTALIN) Duty cycle, LVCMOS reference clock period 45% 55% tjpp(XTALIN) Jitter peak-to-peak, LVCMOS reference clock period -1% 1% tR(XTALIN) Time, LVCMOS reference clock rise 5 ns tF(XTALIN) Time, LVCMOS reference clock fall 5 ns (1) ppm Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 135 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.2.3.3 OSC1 Internal Oscillator Clock Source Figure 5-13 shows the recommended crystal circuit for OSC1 of the package. It is recommended that preproduction printed circuit board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0- resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs. The RTC_XTALIN terminal has a 10-k to 40-k internal pullup resistor which is enabled when OSC1 is disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. Device RTC_XTALIN VSS_RTC RTC_XTALOUT Optional Rbias Optional Rd Crystal C1 C2 Copyright (c) 2016, Texas Instruments Incorporated A. B. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the package. Parasitic capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled into the oscillator. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components (excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL = [(C1xC2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer plus any mutual capacitance (Cpkg + CPCB) seen across the RTC_XTALIN and RTC_XTALOUT signals. For recommended values of crystal circuit components, see Table 5-16. Figure 5-13. OSC1 Crystal Circuit Schematic Table 5-16. OSC1 Crystal Circuit Requirements NAME fxtal DESCRIPTION MIN TYP MAX Crystal parallel resonance frequency Fundamental mode oscillation only 32.768 Crystal frequency stability and tolerance Maximum RTC error = 10.512 minutes per year -20.0 20.0 Maximum RTC error = 26.28 minutes per year -50.0 50.0 UNIT kHz ppm ppm CC1 C1 capacitance 12.0 24.0 pF CC2 C2 capacitance 12.0 24.0 pF Cshunt Shunt capacitance 1.5 pF ESR Crystal effective series resistance fxtal = 32.768 kHz, oscillator has nominal negative resistance of 725 k and worstcase negative resistance of 250 k 80 k Table 5-17. OSC1 Crystal Circuit Characteristics NAME DESCRIPTION Cpkg Shunt capacitance of package 136 Specifications MIN ZDN package TYP 0.17 MAX UNIT pF Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-17. OSC1 Crystal Circuit Characteristics (continued) NAME DESCRIPTION Pxtal The actual values of the ESR, fxtal, and CL should be used to yield a typical crystal power dissipation value. Using the maximum values specified for ESR, fxtal, and CL parameters yields a maximum power dissipation value. MIN tsX Start-up time TYP MAX 2 CAP_VDD_RTC (min.) UNIT Pxtal = 0.5 ESR (2 fxtal CL VDDS_RTC)2 s CAP_VDD_RTC Voltage VSS_RTC VDDS_RTC (min.) VDDS_RTC RTC_XTALOUT VSS_RTC tsX Time Figure 5-14. OSC1 Start-up Time Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 137 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.2.3.4 OSC1 LVCMOS Digital Clock Source Figure 5-15 shows the recommended oscillator connections when OSC1 of the package is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the RTC_XTALIN terminal. In this mode of operation, the RTC_XTALOUT terminal should not be used to source any external components. The printed circuit board design should provide a mechanism to disconnect the RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1 via the RTC_XTALOUT terminal. The RTC_XTALIN terminal has a 10-k to 40-k internal pullup resistor which is enabled when OSC1 is disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. Device RTC_XTALIN VSS_RTC RTC_XTALOUT VDDS_RTC LVCMOS Digital Clock Source N/C Copyright (c) 2016, Texas Instruments Incorporated Figure 5-15. OSC1 LVCMOS Circuit Schematic Table 5-18. OSC1 LVCMOS Reference Clock Requirements NAME DESCRIPTION MIN Frequency, LVCMOS reference clock f(RTC_XTALIN) Frequency, LVCMOS reference clock stability and tolerance (1) TYP MAX 32.768 UNIT kHz Maximum RTC error = 10.512 minutes/year -20 20 ppm Maximum RTC error = 26.28 minutes/year -50 50 ppm tdc(RTC_XTALIN) Duty cycle, LVCMOS reference clock period 45% 55% tjpp(RTC_XTALIN) Jitter peak-to-peak, LVCMOS reference clock period -1% 1% tR(RTC_XTALIN) Time, LVCMOS reference clock rise 5 ns tF(RTC_XTALIN) Time, LVCMOS reference clock fall 5 ns (1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement. 5.13.2.3.5 OSC1 Not Used Figure 5-16 shows the recommended oscillator connections when OSC1 is not used. An internal 10-k pullup on the RTC_XTALIN terminal is turned on when OSC1 is disabled to prevent this input from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. OSC1 is disabled by default after power is applied. Therefore, both RTC_XTALIN and RTC_XTALOUT terminals should be a no connect (NC) when OSC1 is not used. For more information on disabling OSC1, see the device-specific technical reference manual. 138 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Device RTC_XTALIN VSS_RTC RTC_XTALOUT N/C N/C Copyright (c) 2016, Texas Instruments Incorporated Figure 5-16. OSC1 Not Used Schematic 5.13.2.4 Output Clock Specifications The device has two clock output signals. The CLKOUT1 signal can be configured to output the master oscillator (CLK_M_OSC), EXTDEV_PLL, 32-kHz, or several other internal clocks. See the device-specific TRM for more details. The CLKOUT2 signal can be configured to output the OSC1 input clock, which is referred to as the 32K oscillator (CLK_32K_RTC) in the device-specific technical reference manual, or four other internal clocks. For more information related to configuring these clock output signals, see the CLKOUT Signals section of the device-specific technical reference manual. 5.13.2.5 Output Clock Characteristics 5.13.2.5.1 CLKOUT1 The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one of seven internal signals through configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must be configured for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal. The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level applied to the DSS_HSYNC terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0 multiplexer is configured to Mode 7 if the DSS_HSYNC terminal is low on the rising edge of PWRONRSTn or Mode 3 if the DSS_HSYNC terminal is high on the rising edge of PWRONRSTn. This allows the CLKOUT1 signal to be output on the XDMA_EVENT_INTR0 terminal without software intervention. In this mode, the output is held low while PWRONRSTn is active and begins to toggle after PWRONRSTn is released. 5.13.2.5.2 CLKOUT2 The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one of seven internal signals through configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must be configured for Mode 3 to connect the CLKOUT2 signal to the XDMA_EVENT_INTR1 terminal. The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the XDMA_EVENT_INTR1 terminal. 5.13.3 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing or decreasing such delays. TI recommends using the available IO buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences. The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control register is configured for fast mode (0b). Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 139 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com For the LPDDR2, DDR3, and DDR3L memory interfaces, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the memory interface timings are met. 5.13.4 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 140 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.5 Controller Area Network (CAN) For more information, see the Controller Area Network (CAN) section of the AM437x Sitara Processors Technical Reference Manual. 5.13.5.1 DCAN Electrical Data and Timing Table 5-19. Timing Requirements for DCANx Receive (see Figure 5-17) OPP100 NO. fbaud(baud) 1 tw(RX) OPP50 MIN MAX (1) (1) Maximum programmable baud rate MAX 1 Mbps (1) (1) ns 1 Pulse duration, receive data bit H-2 H+2 UNIT MIN H+2 H+2 (1) H = period of baud rate, 1/programmed baud rate. Table 5-20. Switching Characteristics for DCANx Transmit (see Figure 5-17) NO. 2 OPP100 PARAMETER fbaud(baud) Maximum programmable baud rate tw(TX) Pulse duration, transmit data bit OPP50 MIN MAX H - 2(1) H + 2(1) MIN MAX H - 2(1) H + 2(1) 1 1 UNIT Mbps ns (1) H = period of baud rate, 1/programmed baud rate. 1 DCANx_RX 2 DCANx_TX Figure 5-17. DCANx Timings Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 141 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.6 DMTimer 5.13.6.1 DMTimer Electrical Data and Timing Table 5-21. Timing Requirements for DMTimer [1-11] (see Figure 5-18) NO. 1 (1) MIN tc(TCLKIN) MAX 4P+1 (1) Cycle time, TCLKIN UNIT ns P = period of PICLKOCP (interface clock). Table 5-22. Switching Characteristics for DMTimer [4-7] (see Figure 5-18) NO. PARAMETER MIN MAX UNIT 2 tw(TIMERxH) Pulse duration, high 4P-3 (1) ns 3 tw(TIMERxL) Pulse duration, low 4P-3 (1) ns (1) P = period of PICLKTIMER (functional clock). 1 TCLKIN 2 3 TIMER[x] Figure 5-18. Timer Timing 142 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.7 Ethernet Media Access Controller (EMAC) and Switch 5.13.7.1 Ethernet MAC and Switch Electrical Data and Timing The Ethernet MAC and Switch implemented in the device supports GMII mode, but the design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package terminals. Therefore, the device does not support GMII mode. MII mode is supported with the remaining GMII signals. The AM437x Sitara Processors Technical Reference Manual and this document may reference internal signal names when discussing peripheral input and output signals because many of the package terminals can be multiplexed to one of several peripheral signals. For example, the terminal names for port 1 of the Ethernet MAC and switch have been changed from GMII to MII to indicate their Mode 0 function, but the internal signal is named GMII. However, documents that describe the Ethernet switch reference these signals by their internal signal name. For a cross-reference of internal signal names to terminal names, see Table 4-10. Operation of the Ethernet MAC and switch in RGMII mode is not supported for OPP50. Table 5-23. Ethernet MAC and Switch Timing Conditions TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time tF Input signal fall time 1(1) 5(1) ns (1) (1) ns 30 pF 1 5 Output Condition CLOAD Output load capacitance 3 (1) Except when specified otherwise. 5.13.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing Table 5-24. Timing Requirements for MDIO_DATA (see Figure 5-19) NO. MIN 1 tsu(MDIO-MDC) Setup time, MDIO valid before MDC high 2 th(MDIO-MDC) Hold time, MDIO valid from MDC high TYP MAX UNIT 90 ns 0 ns 1 2 MDIO_CLK (Output) MDIO_DATA (Input) Figure 5-19. MDIO_DATA Timing - Input Mode Table 5-25. Switching Characteristics for MDIO_CLK (see Figure 5-20) NO. PARAMETER MIN TYP MAX UNIT 1 tc(MDC) Cycle time, MDC 400 ns 2 tw(MDCH) Pulse duration, MDC high 160 ns 3 tw(MDCL) Pulse duration, MDC low 160 4 tt(MDC) Transition time, MDC Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 ns 5 Specifications ns 143 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4 1 3 2 MDIO_CLK 4 Figure 5-20. MDIO_CLK Timing Table 5-26. Switching Characteristics for MDIO_DATA (see Figure 5-21) NO. 1 PARAMETER td(MDC-MDIO) MIN Delay time, MDC high to MDIO valid TYP 10 MAX UNIT 390 ns 1 MDIO_CLK (Output) MDIO_DATA (Output) Figure 5-21. MDIO_DATA Timing - Output Mode 5.13.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing Table 5-27. Timing Requirements for GMII[x]_RXCLK - MII Mode (see Figure 5-22) 10 Mbps NO. MIN TYP 100 Mbps MAX MIN TYP MAX UNIT 1 tc(RX_CLK) Cycle time, RX_CLK 399.96 400.04 39.996 40.004 ns 2 tw(RX_CLKH) Pulse Duration, RX_CLK high 140 260 14 26 ns 3 tw(RX_CLKL) Pulse Duration, RX_CLK low 140 260 14 26 ns 4 tt(RX_CLK) Transition time, RX_CLK 5 ns 5 4 1 3 2 GMII[x]_RXCLK 4 Figure 5-22. GMII[x]_RXCLK Timing - MII Mode 144 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-28. Timing Requirements for GMII[x]_TXCLK - MII Mode (see Figure 5-23) 10 Mbps NO. MIN 100 Mbps TYP MAX MIN TYP MAX UNIT 1 tc(TX_CLK) Cycle time, TX_CLK 399.96 400.04 39.996 40.004 ns 2 tw(TX_CLKH) Pulse Duration, TX_CLK high 140 260 14 26 ns 3 tw(TX_CLKL) Pulse Duration, TX_CLK low 140 260 14 26 ns 4 tt(TX_CLK) Transition time, TX_CLK 5 ns 5 4 1 3 2 GMII[x]_TXCLK 4 Figure 5-23. GMII[x]_TXCLK Timing - MII Mode Table 5-29. Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode (see Figure 5-24) 10 Mbps NO. 1 2 MIN tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK th(RX_CLK-RXD) Hold time RXD[3:0] valid after RX_CLK th(RX_CLK-RX_DV) Hold time RX_DV valid after RX_CLK th(RX_CLK-RX_ER) Hold time RX_ER valid after RX_CLK 100 Mbps TYP MAX MIN TYP MAX UNIT 8 8 ns 8 8 ns 1 2 GMII[x]_MRCLK (Input) GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER (Inputs) Figure 5-24. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 145 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-30. Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode (see Figure 5-25) NO. 1 PARAMETER td(TX_CLK-TXD) Delay time, TX_CLK high to TXD[3:0] valid td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid 10 Mbps MIN 5 TYP 100 Mbps MAX MIN 25 5 TYP MAX 25 UNIT ns 1 GMII[x]_TXCLK (input) GMII[x]_TXD[3:0], GMII[x]_TXEN (outputs) Figure 5-25. GMII[x]_TXD[3:0], GMII[x]_TXEN Timing - MII Mode 146 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing Table 5-31. Timing Requirements for RMII[x]_REFCLK - RMII Mode (see Figure 5-26) NO. MIN TYP MAX UNIT 1 tc(REF_CLK) Cycle time, REF_CLK 19.999 20.001 ns 2 tw(REF_CLKH) Pulse Duration, REF_CLK high 7 13 ns 3 tw(REF_CLKL) Pulse Duration, REF_CLK low 7 13 ns 1 2 RMII[x]_REFCLK (Input) 3 Figure 5-26. RMII[x]_REFCLK Timing - RMII Mode Table 5-32. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode (see Figure 5-27) NO. 1 2 MIN tsu(RXD-REF_CLK) Setup time, RXD[1:0] valid before REF_CLK tsu(CRS_DV-REF_CLK) Setup time, CRS_DV valid before REF_CLK tsu(RX_ER-REF_CLK) Setup time, RX_ER valid before REF_CLK th(REF_CLK-RXD) Hold time RXD[1:0] valid after REF_CLK th(REF_CLK-CRS_DV) Hold time, CRS_DV valid after REF_CLK th(REF_CLK-RX_ER) Hold time, RX_ER valid after REF_CLK TYP MAX UNIT 4 ns 2 ns 1 2 RMII[x]_REFCLK (input) RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER (inputs) Figure 5-27. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 147 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-33. Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode (see Figure 5-28) NO. 1 2 3 PARAMETER td(REF_CLK-TXD) Delay time, REF_CLK high to TXD[1:0] valid td(REF_CLK-TXEN) Delay time, REF_CLK to TXEN valid tr(TXD) Rise time, TXD outputs tr(TX_EN) Rise time, TX_EN output tf(TXD) Fall time, TXD outputs tf(TX_EN) Fall time, TX_EN output MIN TYP MAX UNIT 2 14.2 ns 1 5 ns 1 5 ns 1 RMII[x]_REFCLK (Input) RMII[x]_TXD[1:0], RMII[x]_TXEN (Outputs) 3 2 Figure 5-28. RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode 148 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing Table 5-34. Timing Requirements for RGMII[x]_RCLK - RGMII Mode (see Figure 5-29) 10 Mbps NO. 1 MIN 100 Mbps TYP MAX MIN TYP 1000 Mbps MAX MIN TYP MAX UNIT tc(RXC) Cycle time, RXC 360 440 36 44 7.2 8.8 ns 2 tw(RXCH) Pulse duration, RXC high 160 240 16 24 3.6 4.4 ns 3 tw(RXCL) Pulse duration, RXC low 160 240 16 24 3.6 4.4 ns 4 tt(RXC) Transition time, RXC 0.75 ns 0.75 0.75 1 4 2 4 3 RGMII[x]_RCLK Figure 5-29. RGMII[x]_RCLK Timing - RGMII Mode Table 5-35. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode (see Figure 5-30) 10 Mbps NO. MIN MAX MIN TYP 1000 Mbps MAX MIN TYP MAX tsu(RD-RXC) Setup time, RD[3:0] valid before RXC high or low 1 1 1 tsu(RX_CTL-RXC) Setup time, RX_CTL valid before RXC high or low 1 1 1 th(RXC-RD) Hold time, RD[3:0] valid after RXC high or low 1 1 1 th(RXC-RX_CTL) Hold time, RX_CTL valid after RXC high or low 1 1 1 tt(RD) Transition time, RD 0.75 0.75 0.75 tt(RX_CTL) Transition time, RX_CTL 0.75 0.75 0.75 1 2 3 TYP 100 Mbps UNIT ns ns ns (A) RGMII[x]_RCLK 1 1st Half-byte 2 2nd Half-byte (B) RGMII[x]_RD[3:0] RGRXD[3:0] RGRXD[7:4] RXDV RXERR (B) RGMII[x]_RCTL 3 A. B. RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the respective timing requirements. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL carries RXDV on rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK. Figure 5-30. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 149 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-36. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode (see Figure 5-31) NO. 1 10 Mbps PARAMETER MIN 100 Mbps TYP MAX MIN 1000 Mbps TYP MAX MIN TYP MAX UNIT tc(TXC) Cycle time, TXC 360 440 36 44 7.2 8.8 ns 2 tw(TXCH) Pulse duration, TXC high 160 240 16 24 3.6 4.4 ns 3 tw(TXCL) Pulse duration, TXC low 160 240 16 24 3.6 4.4 ns 4 tt(TXC) Transition time, TXC 0.75 ns 0.75 0.75 1 4 2 4 3 RGMII[x]_TCLK Figure 5-31. RGMII[x]_TCLK Timing - RGMII Mode Table 5-37. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode (see Figure 5-32) NO. 10 Mbps PARAMETER 1 2 MIN TYP 100 Mbps MAX MIN TYP 1000 Mbps MAX MIN TYP MAX tsk(TD-TXC) TD to TXC output skew -0.5 0.5 -0.5 0.5 -0.5 0.5 tsk(TX_CTL-TXC) TX_CTL to TXC output skew -0.5 0.5 -0.5 0.5 -0.5 0.5 tt(TD) Transition time, TD 0.75 0.75 0.75 tt(TX_CTL) Transition time, TX_CTL 0.75 0.75 0.75 UNIT ns ns (A) RGMII[x]_TCLK 1 1 2 (B) 1st Half-byte 2nd Half-byte (B) TXEN TXERR RGMII[x]_TD[3:0] RGMII[x]_TCTL A. B. The Ethernet MAC and switch implemented in the device supports internal TX delay mode. Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK. Figure 5-32. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode 150 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8 External Memory Interfaces The device includes the following external memory interfaces: * General-purpose memory controller (GPMC) * LPDDR2, DDR3, and DDR3L Memory Interface (EMIF) 5.13.8.1 General-Purpose Memory Controller (GPMC) NOTE For more information, see the Memory Subsystem and General-Purpose Memory Controller section of the AM437x Sitara Processors Technical Reference Manual. The GPMC is the unified memory controller used to interface external memory devices such as: * Asynchronous SRAM-like memories and ASIC devices * Asynchronous page mode and synchronous burst NOR flash * NAND flash 5.13.8.1.1 GPMC and NOR Flash--Synchronous Mode Table 5-39 and Table 5-40 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-33 through Figure 5-37). Table 5-38. GPMC and NOR Flash Timing Conditions--Synchronous Mode TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 0.3 1.8 ns tF Input signal fall time 0.3 1.8 ns 3 30 pF Output Condition CLOAD Output load capacitance Table 5-39. GPMC and NOR Flash Timing Requirements--Synchronous Mode OPP100 NO. MIN MAX OPP50 MIN MAX UNIT F12 tsu(dV-clkH) Setup time, input data gpmc_ad[15:0] valid before output clock gpmc_clk high 3.5 13.2 ns F13 th(clkH-dV) Hold time, input data gpmc_ad[15:0] valid after output clock gpmc_clk high 2.5 2.75 ns F21 tsu(waitV-clkH) Setup time, input wait gpmc_wait[x](1) valid before output clock gpmc_clk high 3.5 13.2 ns F22 th(clkH-waitV) Hold time, input wait gpmc_wait[x](1) valid after output clock gpmc_clk high 2.5 2.5 ns (1) In gpmc_wait[x], x is equal to 0 or 1. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 151 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-40. GPMC and NOR Flash Switching Characteristics--Synchronous Mode NO. PARAMETER OPP100 OPP50 MIN MAX MIN MAX UNIT F0 1 / tc(clk) Frequency(1), output clock gpmc_clk F1 tw(clkH) Typical pulse duration, output clock gpmc_clk high 0.5P(2) 0.5P(2) 0.5P(2) 0.5P(2) ns F1 tw(clkL) Typical pulse duration, output clock gpmc_clk low 0.5P(2) 0.5P(2) 0.5P(2) 0.5P(2) ns tdc(clk) Duty cycle error, output clock gpmc_clk -500 500 -500 500 ps 100 (3) 50 MHz tJ(clk) Jitter standard deviation , output clock gpmc_clk 33.33 33.33 ps tR(clk) Rise time, output clock gpmc_clk 2 2 ns tF(clk) Fall time, output clock gpmc_clk 2 2 ns tR(do) Rise time, output data gpmc_ad[15:0] 2 2 ns tF(do) Fall time, output data gpmc_ad[15:0] 2 2 ns F2 td(clkH-csnV) Delay time, output clock gpmc_clk rising edge to output chip select gpmc_csn[x](4) transition F(5) - 2.2 F(5) + 4.5 F(5) - 3.2 F(5) + 9.5 ns F3 td(clkH-csnIV) Delay time, output clock gpmc_clk rising edge to output chip select gpmc_csn[x](4) invalid E(6) - 2.2 E(6) + 4.5 E(6) - 3.2 E(6) + 9.5 ns F4 td(aV-clk) Delay time, output address gpmc_a[27:1] valid to output clock gpmc_clk first edge B(7) - 4.5 B(7) + 3.1 B(7) - 5.5 B(7) + 13.1 ns F5 td(clkH-aIV) Delay time, output clock gpmc_clk rising edge to output address gpmc_a[27:1] invalid -2.3 4.5 -3.3 15.3 ns F6 td(be[x]nV-clk) Delay time, output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n valid to output clock gpmc_clk first edge B(7) - 1.9 B(7) + 2.3 B(7) - 2.9 B(7) + 12.3 ns F7 td(clkH-be[x]nIV) Delay time, output clock gpmc_clk rising edge to output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n invalid(8) D(9) - 2.3 D(9) + 1.9 D(9) - 3.3 D(9) + 6.9 ns F7 td(clkL-be[x]nIV) Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 invalid(10) D(9) - 2.3 D(9) + 1.9 D(9) - 3.3 D(9) + 6.9 ns F7 td(clkL-be[x]nIV) Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 invalid(11) D(9) - 2.3 D(9) + 1.9 D(9) - 3.3 D(9) + 11.9 ns F8 td(clkH-advn) Delay time, output clock gpmc_clk rising edge to output address valid and address latch enable gpmc_advn_ale transition G(12) - 2.3 G(12) + 4.5 G(12) - 3.3 G(12) + 9.5 ns F9 td(clkH-advnIV) Delay time, output clock gpmc_clk rising edge to output address valid and address latch enable gpmc_advn_ale invalid D(9) - 3.3 D(9) + 9.5 ns F10 td(clkH-oen) Delay time, output clock gpmc_clk rising edge to output enable gpmc_oen transition H(13) - 2.3 H(13) + 3.5 H(13) - 3.3 H(13) + 8.5 ns F11 td(clkH-oenIV) Delay time, output clock gpmc_clk rising edge to output enable gpmc_oen invalid H(13) - 2.3 H(13) + 3.5 H(13) - 3.3 H(13) + 8.5 ns F14 td(clkH-wen) Delay time, output clock gpmc_clk rising edge to output write enable gpmc_wen transition I(14) - 2.3 I(14) + 4.5 I(14) - 3.3 I(14) + 9.5 ns F15 td(clkH-do) Delay time, output clock gpmc_clk rising edge to output data gpmc_ad[15:0] transition(8) J(15) - 2.3 J(15) + 2.7 J(15) - 3.3 J(15) + 7.7 ns F15 td(clkL-do) Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition(10) J(15) - 2.3 J(15) + 2.7 J(15) - 3.3 J(15) + 7.7 ns F15 td(clkL-do) Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition(11) J(15) - 2.3 J(15) + 2.7 J(15) - 3.3 J(15) + 12.7 ns F17 td(clkH-be[x]n) Delay time, output clock gpmc_clk rising edge to output lower byte enable and command latch enable gpmc_be0n_cle transition(8) J(15) - 2.3 J(15) + 1.9 J(15) - 3.3 J(15) + 6.9 ns F17 td(clkL-be[x]n) Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 transition(10) J(15) - 2.3 J(15) + 1.9 J(15) - 3.3 J(15) + 6.9 ns F17 td(clkL-be[x]n) Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 transition(11) J(15) - 2.3 J(15) + 1.9 J(15) - 3.3 J(15) + 11.9 ns 152 Specifications D(9) - 2.3 D(9) + 4.5 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-40. GPMC and NOR Flash Switching Characteristics--Synchronous Mode (continued) NO. F18 F19 F20 OPP100 PARAMETER tw(csnV) tw(be[x]nV) tw(advnV) MIN OPP50 MAX MIN MAX UNIT Pulse duration, output chip select gpmc_csn[x](4) low Read A(16) A(16) ns Write A (16) A(16) ns Pulse duration, output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n low Read C(17) C(17) ns Write C (17) (17) ns Pulse duration, output address valid and address latch enable gpmc_advn_ale low Read K(18) K(18) ns Write (18) (18) ns K C K (1) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider. (2) P = gpmc_clk period in ns (3) The jitter probability density can be approximated by a Gaussian function. (4) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. (5) For csn falling edge (CS activated): - - - Case GpmcFCLKDivider = 0: - F = 0.5 x CSExtraDelay x GPMC_FCLK(19) Case GpmcFCLKDivider = 1: - F = 0.5 x CSExtraDelay x GPMC_FCLK(19) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even) - F = (1 + 0.5 x CSExtraDelay) x GPMC_FCLK(19) otherwise Case GpmcFCLKDivider = 2: - F = 0.5 x CSExtraDelay x GPMC_FCLK(19) if ((CSOnTime - ClkActivationTime) is a multiple of 3) - F = (1 + 0.5 x CSExtraDelay) x GPMC_FCLK(19) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3) - F = (2 + 0.5 x CSExtraDelay) x GPMC_FCLK(19) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3) (6) For single read: E = (CSRdOffTime - AccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) For burst read: E = (CSRdOffTime - AccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) For burst write: E = (CSWrOffTime - AccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) (7) B = ClkActivationTime x GPMC_FCLK(19) (8) First transfer only for CLK DIV 1 mode. (9) For single read: D = (RdCycleTime - AccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) For burst read: D = (RdCycleTime - AccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) For burst write: D = (WrCycleTime - AccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) (10) Half cycle; for all data after initial transfer for CLK DIV 1 mode. (11) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK. (12) For ADV falling edge (ADV activated): - Case GpmcFCLKDivider = 0: - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) - Case GpmcFCLKDivider = 1: - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even) - G = (1 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) otherwise - Case GpmcFCLKDivider = 2: - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) if ((ADVOnTime - ClkActivationTime) is a multiple of 3) - G = (1 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3) - G = (2 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Reading mode: - Case GpmcFCLKDivider = 0: - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) - Case GpmcFCLKDivider = 1: - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even) - G = (1 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) otherwise - Case GpmcFCLKDivider = 2: - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3) - G = (1 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3) - G = (2 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Writing mode: - Case GpmcFCLKDivider = 0: Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 153 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 - - www.ti.com - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) Case GpmcFCLKDivider = 1: - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even) - G = (1 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) otherwise Case GpmcFCLKDivider = 2: - G = 0.5 x ADVExtraDelay x GPMC_FCLK(19) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3) - G = (1 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3) - G = (2 + 0.5 x ADVExtraDelay) x GPMC_FCLK(19) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3) (13) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction): - Case GpmcFCLKDivider = 0: - H = 0.5 x OEExtraDelay x GPMC_FCLK(19) - Case GpmcFCLKDivider = 1: - H = 0.5 x OEExtraDelay x GPMC_FCLK(19) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even) - H = (1 + 0.5 x OEExtraDelay) x GPMC_FCLK(19) otherwise - Case GpmcFCLKDivider = 2: - H = 0.5 x OEExtraDelay x GPMC_FCLK(19) if ((OEOnTime - ClkActivationTime) is a multiple of 3) - H = (1 + 0.5 x OEExtraDelay) x GPMC_FCLK(19) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3) - H = (2 + 0.5 x OEExtraDelay) x GPMC_FCLK(19) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3) For OE rising edge (OE deactivated): - Case GpmcFCLKDivider = 0: - H = 0.5 x OEExtraDelay x GPMC_FCLK(19) - Case GpmcFCLKDivider = 1: - H = 0.5 x OEExtraDelay x GPMC_FCLK(19) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even) - H = (1 + 0.5 x OEExtraDelay) x GPMC_FCLK(19) otherwise - Case GpmcFCLKDivider = 2: - H = 0.5 x OEExtraDelay x GPMC_FCLK(19) if ((OEOffTime - ClkActivationTime) is a multiple of 3) - H = (1 + 0.5 x OEExtraDelay) x GPMC_FCLK(19) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3) - H = (2 + 0.5 x OEExtraDelay) x GPMC_FCLK(19) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3) (14) For WE falling edge (WE activated): - Case GpmcFCLKDivider = 0: - I = 0.5 x WEExtraDelay x GPMC_FCLK(19) - Case GpmcFCLKDivider = 1: - I = 0.5 x WEExtraDelay x GPMC_FCLK(19) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even) - I = (1 + 0.5 x WEExtraDelay) x GPMC_FCLK(19) otherwise - Case GpmcFCLKDivider = 2: - I = 0.5 x WEExtraDelay x GPMC_FCLK(19) if ((WEOnTime - ClkActivationTime) is a multiple of 3) - I = (1 + 0.5 x WEExtraDelay) x GPMC_FCLK(19) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3) - I = (2 + 0.5 x WEExtraDelay) x GPMC_FCLK(19) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3) For WE rising edge (WE deactivated): - Case GpmcFCLKDivider = 0: - I = 0.5 x WEExtraDelay x GPMC_FCLK (19) - Case GpmcFCLKDivider = 1: - I = 0.5 x WEExtraDelay x GPMC_FCLK(19) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even) - I = (1 + 0.5 x WEExtraDelay) x GPMC_FCLK(19) otherwise - Case GpmcFCLKDivider = 2: - I = 0.5 x WEExtraDelay x GPMC_FCLK(19) if ((WEOffTime - ClkActivationTime) is a multiple of 3) - I = (1 + 0.5 x WEExtraDelay) x GPMC_FCLK(19) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3) - I = (2 + 0.5 x WEExtraDelay) x GPMC_FCLK(19) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3) (15) J = GPMC_FCLK(19) (16) For single read: A = (CSRdOffTime - CSOnTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) x PageBurstAccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) x PageBurstAccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) With n being the page burst access number. (17) For single read: C = RdCycleTime x (TimeParaGranularity + 1) x GPMC_FCLK(19) For burst read: C = (RdCycleTime + (n - 1) x PageBurstAccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) For burst write: C = (WrCycleTime + (n - 1) x PageBurstAccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) With n being the page burst access number. (18) For read: K = (ADVRdOffTime - ADVOnTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) For write: K = (ADVWrOffTime - ADVOnTime) x (TimeParaGranularity + 1) x GPMC_FCLK(19) (19) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. 154 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 F1 F0 F1 gpmc_clk F2 F3 F18 gpmc_csn[x] (A) F4 gpmc_a[10:1] Valid Address F6 F7 F19 gpmc_be0n_cle F19 gpmc_be1n F6 F8 F8 F20 F9 gpmc_advn_ale F10 F11 gpmc_oen F13 F12 gpmc_ad[15:0] gpmc_wait[x] A. B. D0 (B) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-33. GPMC and NOR Flash--Synchronous Single Read--(GpmcFCLKDivider = 0) Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 155 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com F1 F0 F1 gpmc_clk F2 gpmc_csn[x] F3 (A) F4 gpmc_a[10:1] Valid Address F6 F7 gpmc_be0n_cle F7 gpmc_be1n F6 F8 F8 F9 gpmc_advn_ale F10 F11 gpmc_oen F13 F13 F12 gpmc_ad[15:0] D0 F21 gpmc_wait[x] A. B. F12 D1 D2 D3 F22 (B) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-34. GPMC and NOR Flash--Synchronous Burst Read--4x16-bit (GpmcFCLKDivider = 0) 156 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 F1 F1 F0 gpmc_clk F2 gpmc_csn[x] F3 (A) F4 Valid Address gpmc_a[10:1] F17 F6 F17 F17 gpmc_be0n_cle F17 F17 F17 gpmc_be1n F6 F8 F8 F9 gpmc_advn_ale F14 F14 gpmc_wen F15 gpmc_ad[15:0] gpmc_wait[x] A. B. D0 D1 F15 D2 F15 D3 (B) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-35. GPMC and NOR Flash--Synchronous Burst Write--(GpmcFCLKDivider > 0) Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 157 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com F1 F0 F1 gpmc_clk F2 gpmc_csn[x] F3 (A) F6 F7 gpmc_be0n_cle Valid F6 F7 gpmc_be1n Valid F4 gpmc_a[27:17] Address (MSB) F12 F4 gpmc_ad[15:0] F5 Address (LSB) F13 D0 F8 D1 F12 D2 F8 D3 F9 gpmc_advn_ale F10 F11 gpmc_oen gpmc_wait[x] A. B. (B) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-36. GPMC and Multiplexed NOR Flash--Synchronous Burst Read 158 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 F1 F1 F0 gpmc_clk F2 F3 F18 gpmc_csn[x] (A) F4 gpmc_a[27:17] Address (MSB) F17 F6 F17 F6 F17 F17 gpmc_be1n F17 F17 gpmc_be0n_cle F8 F8 F20 F9 gpmc_advn_ale F14 F14 gpmc_wen F15 gpmc_ad[15:0] Address (LSB) D0 F22 gpmc_wait[x] A. B. D1 F15 F15 D2 D3 F21 (B) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-37. GPMC and Multiplexed NOR Flash--Synchronous Burst Write Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 159 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.1.2 GPMC and NOR Flash--Asynchronous Mode Table 5-42 and Table 5-43 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-38 through Figure 5-43). Table 5-41. GPMC and NOR Flash Timing Conditions--Asynchronous Mode TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 0.3 1.8 ns tF Input signal fall time 0.3 1.8 ns 3 30 pF Output Condition CLOAD Output load capacitance Table 5-42. GPMC and NOR Flash Internal Timing Parameters--Asynchronous Mode(1)(2) OPP100 NO. MIN FI1 Delay time, output data gpmc_ad[15:0] generation from internal functional clock GPMC_FCLK(3) FI2 Delay time, input data gpmc_ad[15:0] capture from internal functional clock GPMC_FCLK(3) FI3 OPP50 MAX MIN MAX UNIT 6.5 6.5 ns 4 4 ns Delay time, output chip select gpmc_csn[x] generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns FI4 Delay time, output address gpmc_a[27:1] generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns FI5 Delay time, output address gpmc_a[27:1] valid from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns FI6 Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle, output upper-byte enable gpmc_be1n generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns FI7 Delay time, output enable gpmc_oen generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns FI8 Delay time, output write enable gpmc_wen generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns FI9 Skew, internal functional clock GPMC_FCLK(3) 100 100 ps (1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field. (2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally. (3) GPMC_FCLK is general-purpose memory controller internal functional clock. 160 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-43. GPMC and NOR Flash Timing Requirements--Asynchronous Mode NO. OPP100 MIN FA5(1) tacc(d) (2) FA20 tacc1-pgmode(d) FA21(3) tacc2-pgmode(d) OPP50 MAX MIN UNIT MAX H(4) H(4) ns Page mode successive data access time P (5) P(5) ns Page mode first data access time H(4) H(4) ns Data access time (1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field. (2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field. (3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field. (4) H = AccessTime x (TimeParaGranularity + 1) x GPMC_FCLK(6) (5) P = PageBurstAccessTime x (TimeParaGranularity + 1) x GPMC_FCLK(6) (6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. Table 5-44. GPMC and NOR Flash Switching Characteristics--Asynchronous Mode NO. OPP100 PARAMETER MIN OPP50 MAX MIN 2 MAX tR(d) Rise time, output data gpmc_ad[15:0] tF(d) Fall time, output data gpmc_ad[15:0] Read FA0 tw(be[x]nV) Pulse duration, output lower-byte enable and command latch enable gpmc_be0n_cle, output upper-byte enable gpmc_be1n valid time Write N(1) N(1) FA1 tw(csnV) Pulse duration, output chip select gpmc_csn[x](2) low Read A(3) A(3) Write (3) A(3) FA3 td(csnV-advnIV) Delay time, output chip select Read gpmc_csn[x](2) valid to output address valid and address latch enable Write gpmc_advn_ale invalid FA4 td(csnV-oenIV) FA9 UNIT 2 ns 2 2 ns N(1) N(1) A ns ns B(4) - 0.2 B(4) + 2.0 B(4) - 0.2 B(4) + 2.0 B(4) - 0.2 B(4) + 2.0 B(4) - 0.2 B(4) + 2.0 Delay time, output chip select gpmc_csn[x](2) valid to output enable gpmc_oen invalid (Single read) C(5) - 0.2 C(5) + 2.0 C(5) - 0.2 C(5) + 2.0 ns td(aV-csnV) Delay time, output address gpmc_a[27:1] valid to output chip select gpmc_csn[x](2) valid J(6) - 0.2 J(6) + 2.0 J(6) - 0.2 J(6) + 2.0 ns FA10 td(be[x]nV-csnV) Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle, output upper-byte enable gpmc_be1n valid to output chip select gpmc_csn[x](2) valid J(6) - 0.2 J(6) + 2.0 J(6) - 0.2 J(6) + 2.0 ns FA12 td(csnV-advnV) Delay time, output chip select gpmc_csn[x](2) valid to output address valid and address latch enable gpmc_advn_ale valid K(7) - 0.2 K(7) + 2.0 K(7) - 0.2 K(7) + 2.0 ns FA13 td(csnV-oenV) Delay time, output chip select gpmc_csn[x](2) valid to output enable gpmc_oen valid L(8) - 0.2 L(8) + 2.0 L L(8) + 2.0 ns FA16 tw(aIV) Pulse durationm output address gpmc_a[26:1] invalid between 2 successive read and write accesses G(9) FA18 td(csnV-oenIV) Delay time, output chip select gpmc_csn[x](2) valid to output enable gpmc_oen invalid (Burst read) I(10) - 0.2 FA20 tw(aV) Pulse duration, output address gpmc_a[27:1] valid -- 2nd, 3rd, and 4th accesses D(11) FA25 td(csnV-wenV) Delay time, output chip select gpmc_csn[x](2) valid to output write enable gpmc_wen valid E(12) - 0.2 (8) - 0.2 G(9) I(10) + 2.0 I(10) - 0.2 ns I(10) + 2.0 D(11) E(12) + 2.0 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 E(12) - 0.2 ns ns ns E(12) + 2.0 Specifications ns 161 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-44. GPMC and NOR Flash Switching Characteristics--Asynchronous Mode (continued) NO. OPP100 PARAMETER FA27 td(csnV-wenIV) Delay time, output chip select gpmc_csn[x](2) valid to output write enable gpmc_wen invalid FA28 td(wenV-dV) Delay time, output write enable gpmc_ wen valid to output data gpmc_ad[15:0] valid FA29 td(dV-csnV) Delay time, output data gpmc_ad[15:0] valid to output chip select gpmc_csn[x](2) valid FA37 td(oenV-aIV) Delay time, output enable gpmc_oen valid to output address gpmc_ad[15:0] phase end OPP50 UNIT MIN MAX MIN MAX F(13) - 0.2 F(13) + 2.0 F(13) - 0.2 F(13) + 2.0 ns 5 ns J(6) + 2.8 ns 2.8 ns 2.8 J(6) - 0.2 J(6) + 2.8 J(6) - 0.2 2.8 GPMC_FCLK(14) (14) (1) For single read: N = RdCycleTime x (TimeParaGranularity + 1) x For single write: N = WrCycleTime x (TimeParaGranularity + 1) x GPMC_FCLK For burst read: N = (RdCycleTime + (n - 1) x PageBurstAccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(14) For burst write: N = (WrCycleTime + (n - 1) x PageBurstAccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(14) (2) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. (3) For single read: A = (CSRdOffTime - CSOnTime) x (TimeParaGranularity + 1) x GPMC_FCLK(14) For single write: A = (CSWrOffTime - CSOnTime) x (TimeParaGranularity + 1) x GPMC_FCLK(14) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) x PageBurstAccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(14) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) x PageBurstAccessTime) x (TimeParaGranularity + 1) x GPMC_FCLK(14) with n being the page burst access number (4) For reading: B = ((ADVRdOffTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (ADVExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) For writing: B = ((ADVWrOffTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (ADVExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (5) C = ((OEOffTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (OEExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (6) J = (CSOnTime x (TimeParaGranularity + 1) + 0.5 x CSExtraDelay) x GPMC_FCLK(14) (7) K = ((ADVOnTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (ADVExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (8) L = ((OEOnTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (OEExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (9) G = Cycle2CycleDelay x GPMC_FCLK(14) (10) I = ((OEOffTime + (n - 1) x PageBurstAccessTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (OEExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (11) D = PageBurstAccessTime x (TimeParaGranularity + 1) x GPMC_FCLK(14) (12) E = ((WEOnTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (WEExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (13) F = ((WEOffTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (WEExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. 162 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 GPMC_FCLK (A) gpmc_clk FA5 (B) FA1 gpmc_csn[x] (C) FA9 gpmc_a[10:1] Valid Address FA0 FA10 Valid gpmc_be0n_cle FA0 Valid gpmc_be1n FA10 FA3 FA12 gpmc_advn_ale FA4 FA13 gpmc_oen gpmc_wait[x] A. B. C. Data IN 0 Data IN 0 gpmc_ad[15:0] (C) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-38. GPMC and NOR Flash--Asynchronous Read--Single Word Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 163 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 GPMC_FCLK www.ti.com (A) gpmc_clk FA5 (B) FA5 (B) FA1 gpmc_csn[x] FA1 (C) FA16 FA9 FA9 gpmc_a[10:1] Address 0 Address 1 FA0 FA10 FA0 FA10 gpmc_be0n_cle Valid Valid FA0 gpmc_be1n FA0 Valid FA10 Valid FA10 FA3 FA3 FA12 FA12 gpmc_advn_ale FA4 FA13 FA4 FA13 gpmc_oen gpmc_ad[15:0] gpmc_wait[x] A. B. C. Data Upper (C) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-39. GPMC and NOR Flash--Asynchronous Read--32-Bit 164 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 GPMC_FCLK (A) gpmc_clk FA21 (B) FA20 (C) FA20 (C) FA20 (C) FA1 gpmc_csn[x] (D) FA9 Add0 gpmc_a[10:1] Add1 Add2 Add3 D0 D1 D2 Add4 FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA12 gpmc_advn_ale FA18 FA13 gpmc_oen gpmc_ad[15:0] gpmc_wait[x] A. B. C. D. D3 D3 (D) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-40. GPMC and NOR Flash--Asynchronous Read--Page Mode 4x16-Bit Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 165 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com gpmc_fclk gpmc_clk FA1 gpmc_csn[x] (A) FA9 gpmc_a[10:1] Valid Address FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA3 FA12 gpmc_advn_ale FA27 FA25 gpmc_wen FA29 gpmc_ad[15:0] gpmc_wait[x] A. Data OUT (A) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-41. GPMC and NOR Flash--Asynchronous Write--Single Word 166 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 GPMC_FCLK (A) gpmc_clk FA1 FA5 gpmc_csn[x] (B) (C) FA9 gpmc_a[27:17] Address (MSB) FA0 FA10 gpmc_be0n_cle Valid FA0 FA10 gpmc_be1n Valid FA3 FA12 gpmc_advn_ale FA4 FA13 gpmc_oen FA29 gpmc_ad[15:0] gpmc_wait[x] A. B. C. FA37 Address (LSB) Data IN Data IN (C) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-42. GPMC and Multiplexed NOR Flash--Asynchronous Read--Single Word Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 167 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com gpmc_fclk gpmc_clk FA1 gpmc_csn[x] (A) FA9 gpmc_a[27:17] Address (MSB) FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA3 FA12 gpmc_advn_ale FA27 FA25 gpmc_wen FA29 gpmc_ad[15:0] gpmc_wait[x] A. FA28 Valid Address (LSB) Data OUT (A) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-43. GPMC and Multiplexed NOR Flash--Asynchronous Write--Single Word 168 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8.1.3 GPMC and NAND Flash--Asynchronous Mode Table 5-46 and Table 5-47 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-44 through Figure 5-47). Table 5-45. GPMC and NAND Flash Timing Conditions--Asynchronous Mode TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time 0.3 1.8 ns tF Input signal fall time 0.3 1.8 ns 3 30 pF Output Condition CLOAD Output load capacitance Table 5-46. GPMC and NAND Flash Internal Timing Parameters--Asynchronous Mode(1)(2) OPP100 NO. MIN OPP50 MAX MIN MAX UNIT GNFI1 Delay time, output data gpmc_ad[15:0] generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns GNFI2 Delay time, input data gpmc_ad[15:0] capture from internal functional clock GPMC_FCLK(3) 4.0 4.0 ns GNFI3 Delay time, output chip select gpmc_csn[x] generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns GNFI4 Delay time, output address valid and address latch enable gpmc_advn_ale generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns GNFI5 Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns GNFI6 Delay time, output enable gpmc_oen generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns GNFI7 Delay time, output write enable gpmc_wen generation from internal functional clock GPMC_FCLK(3) 6.5 6.5 ns GNFI8 Skew, functional clock GPMC_FCLK(3) 100 100 ps (1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field. (2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally. (3) GPMC_FCLK is general-purpose memory controller internal functional clock. Table 5-47. GPMC and NAND Flash Timing Requirements--Asynchronous Mode OPP100 NO. GNF12(1) MIN tacc(d) Access time, input data gpmc_ad[15:0] OPP50 MAX J(2) MIN MAX J(2) UNIT ns (1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. (2) J = AccessTime x (TimeParaGranularity + 1) x GPMC_FCLK(3) (3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 169 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-48. GPMC and NAND Flash Switching Characteristics--Asynchronous Mode NO. OPP100 PARAMETER MIN OPP50 MAX MIN MAX UNIT tR(d) Rise time, output data gpmc_ad[15:0] 2 2 ns tF(d) Fall time, output data gpmc_ad[15:0] 2 2 ns GNF0 tw(wenV) Pulse duration, output write enable gpmc_wen valid GNF1 td(csnV-wenV) Delay time, output chip select gpmc_csn[x](2) valid to output write enable gpmc_wen valid B(3) - 0.2 B(3) + 2.0 B(3) - 0.2 B(3) + 2.0 ns GNF2 tw(cleH-wenV) Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle high to output write enable gpmc_wen valid C(4) - 0.2 C(4) + 2.0 C(4) - 0.2 C(4) + 2.0 ns GNF3 tw(wenV-dV) Delay time, output data gpmc_ad[15:0] valid to output write enable gpmc_wen valid D(5) - 0.2 D(5) + 2.8 D(5) - 0.2 D(5) + 2.0 ns GNF4 tw(wenIV-dIV) Delay time, output write enable gpmc_wen invalid to output data gpmc_ad[15:0] invalid E(6) - 0.2 E(6) + 2.8 E(6) - 0.2 E(6) + 2.0 ns GNF5 tw(wenIV-cleIV) Delay time, output write enable gpmc_wen invalid to output lower-byte enable and command latch enable gpmc_be0n_cle invalid F(7) - 0.2 F(7) + 2.0 F(7) - 0.2 F(7) + 2.0 ns GNF6 tw(wenIV-csnIV) Delay time, output write enable gpmc_wen invalid to output chip select gpmc_csn[x](2) invalid G(8) - 0.2 G(8) + 2.0 G(8) - 0.2 G(8) + 2.0 ns GNF7 tw(aleH-wenV) Delay time, output address valid and address latch enable gpmc_advn_ale high to output write enable gpmc_wen valid C(4) - 0.2 C(4) + 2.0 C(4) - 0.2 C(4) + 2.0 ns GNF8 tw(wenIV-aleIV) Delay time, output write enable gpmc_wen invalid to output address valid and address latch enable gpmc_advn_ale invalid F(7) - 0.2 F(7) + 2.0 F(7) - 0.2 F(7) + 2.0 ns GNF9 tc(wen) Cycle time, write H(9) ns (10) (10) (10) (10) + 2.0 ns K(11) ns A(1) ns H(9) (2) GNF10 td(csnV-oenV) Delay time, output chip select gpmc_csn[x] valid to output enable gpmc_oen valid GNF13 tw(oenV) Pulse duration, output enable gpmc_oen valid GNF14 tc(oen) Cycle time, read GNF15 tw(oenIV-csnIV) A(1) Delay time, output enable gpmc_oen invalid to output chip select gpmc_csn[x](2) invalid I - 0.2 I + 2.0 I - 0.2 I K(11) L(12) (13) M L(12) (13) - 0.2 M + 2.0 (13) M ns (13) - 0.2 M + 2.0 ns (1) A = (WEOffTime - WEOnTime) x (TimeParaGranularity + 1) x GPMC_FCLK(14) (2) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. (3) B = ((WEOnTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (WEExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (4) C = ((WEOnTime - ADVOnTime) x (TimeParaGranularity + 1) + 0.5 x (WEExtraDelay - ADVExtraDelay)) x GPMC_FCLK(14) (5) D = (WEOnTime x (TimeParaGranularity + 1) + 0.5 x WEExtraDelay) x GPMC_FCLK(14) (6) E = ((WrCycleTime - WEOffTime) x (TimeParaGranularity + 1) - 0.5 x WEExtraDelay) x GPMC_FCLK(14) (7) F = ((ADVWrOffTime - WEOffTime) x (TimeParaGranularity + 1) + 0.5 x (ADVExtraDelay - WEExtraDelay)) x GPMC_FCLK(14) (8) G = ((CSWrOffTime - WEOffTime) x (TimeParaGranularity + 1) + 0.5 x (CSExtraDelay - WEExtraDelay)) x GPMC_FCLK(14) (9) H = WrCycleTime x (1 + TimeParaGranularity) x GPMC_FCLK(14) (10) I = ((OEOnTime - CSOnTime) x (TimeParaGranularity + 1) + 0.5 x (OEExtraDelay - CSExtraDelay)) x GPMC_FCLK(14) (11) K = (OEOffTime - OEOnTime) x (1 + TimeParaGranularity) x GPMC_FCLK(14) (12) L = RdCycleTime x (1 + TimeParaGranularity) x GPMC_FCLK(14) (13) M = ((CSRdOffTime - OEOffTime) x (TimeParaGranularity + 1) + 0.5 x (CSExtraDelay - OEExtraDelay)) x GPMC_FCLK(14) (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. 170 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 GPMC_FCLK gpmc_csn[x] GNF1 GNF6 GNF2 GNF5 (A) gpmc_be0n_cle gpmc_advn_ale gpmc_oen GNF0 gpmc_wen GNF3 GNF4 gpmc_ad[15:0] A. Command In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. Figure 5-44. GPMC and NAND Flash--Command Latch Cycle GPMC_FCLK gpmc_csn[x] GNF1 GNF6 GNF7 GNF8 (A) gpmc_be0n_cle gpmc_advn_ale gpmc_oen GNF9 GNF0 gpmc_wen GNF3 gpmc_ad[15:0] A. GNF4 Address In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. Figure 5-45. GPMC and NAND Flash--Address Latch Cycle Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 171 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 GPMC_FCLK www.ti.com (A) GNF12 (B) GNF10 gpmc_csn[x] GNF15 (C) gpmc_be0n_cle gpmc_advn_ale GNF14 GNF13 gpmc_oen gpmc_ad[15:0] gpmc_wait[x] A. B. C. DATA (C) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1. Figure 5-46. GPMC and NAND Flash--Data Read Cycle GPMC_FCLK GNF1 gpmc_csn[x] GNF6 (A) gpmc_be0n_cle gpmc_advn_ale gpmc_oen GNF9 GNF0 gpmc_wen GNF3 gpmc_ad[15:0] A. GNF4 DATA In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. Figure 5-47. GPMC and NAND Flash--Data Write Cycle 172 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8.2 Memory Interface The device has a dedicated interface to LPDDR2, DDR3, and DDR3L SDRAM. It supports JEDEC standard compliant LPDDR2, DDR3, and DDR3L SDRAM devices with a 16- or 32-bit data path to external SDRAM memory. For more details on the LPDDR2, DDR3, and DDR3L memory interface, see the EMIF section of the AM437x Sitara Processors Technical Reference Manual. 5.13.8.2.1 DDR3 and DDR3L Routing Guidelines This section provides the timing specification for the DDR3 and DDR3L interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR3 or DDR3L memory system without the need for a complex timing closure process. For more information regarding the guidelines, see Understanding TI's PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedence over the generic guidelines and must be adhered to for a reliable DDR3 or DDR3L interface operation. NOTE All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise noted. 5.13.8.2.1.1 Board Designs TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 5-49 and Figure 5-48. Table 5-49. Switching Characteristics for DDR3 Memory Interface NO. 1 PARAMETER tc(DDR_CK) tc(DDR_CKn) Cycle time, DDR_CK and DDR_CKn MIN MAX UNIT 2.5 3.3(1) ns (1) The JEDEC JESD79-3F Standard defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 and DDR3L memory devices. Therefore, all standard-speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz. 1 DDR_CK DDR_CKn Figure 5-48. DDR3 Memory Interface Clock Timing Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 173 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.1.2 DDR3 Device Combinations Because there are several possible combinations of device counts and single-side or dual-side mounting, Table 5-50 summarizes the supported device configurations. Table 5-50. Supported DDR3 Device Combinations NUMBER OF DDR3 DEVICES DDR3 DEVICE WIDTH (BITS) MIRRORED? DDR3 EMIF WIDTH (BITS) 1 16 N 16 2 8 Y (1) 16 2 16 Y (1) 32 (1) 32 4 (1) 8 Y DDR3 devices are mirrored when half of the devices are placed on the top of the board and the other half are placed on the bottom of the board. 5.13.8.2.1.3 DDR3 Interface 5.13.8.2.1.3.1 DDR3 Interface Schematic The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 5-49 shows the schematic connections for 16-bit interface using one x16 DDR3 device. Figure 5-50 shows the schematic connections for 16-bit interface without using VTT termination for the ADDR_CTRL net class signals. Figure 5-51 shows the schematic connections for 16-bit interface using two x8 DDR3 devices. Figure 5-52 shows the schematic connections for 32-bit interface using two x16 DDR3 device and Figure 5-53 shows the schematic connections for 32-bit interface using four x8 DDR3 devices. When not using all or part of a DDR3 interface, the proper method of handling the unused pins is to tie off the DDR_DQS[x] pins to the VDDS_DDR supply via a 1-k resistor and pulling the DDR_DQSn[x] pins to ground via a 1k- resistor. This must be done for each byte not used. Although these signals have internal pullup and pulldown, external pullup and pulldown provide additional protection against external electrical noise causing activity on the signals. Also, include the 49.9- pulldown for DDR_VTP. The VDDS_DDR and DDR_VREF power supply terminals need to be connected to their respective power supplies even if the DDR3 interface is not being used. All other DDR3 interface pins can be left unconnected. The supported modes for use of the DDR3 EMIF are 32 bits wide, 16 bits wide, or not used. The device can only source one load connected to the DQS[x] and DQ[x] net class signals and up to four loads connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see Section 5.13.8.2.1.3.9. 174 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 16-Bit DDR3 Interface 16-Bit DDR3 Device DDR_D15 DQU7 8 DDR_D8 DQU0 DDR_DQM1 DDR_DQS1 DDR_DQSn1 DMU DQSU DQSUn DDR_D7 DQL7 8 DDR_D0 DQL0 DDR_DQM0 DDR_DQS0 DDR_DQSn0 DML DQSL DQSLn DDR_CK DDR_CKn CK CKn DDR_ODT0 DDR_CSn0 DDR_BA0 DDR_BA1 DDR_BA2 Zo VDDS_DDR Zo ODT CSn BA0 BA1 BA2 DDR_A0 0.1 F DDR_VTT A0 Zo A15 Zo 16 DDR_A15 DDR_CASn DDR_RASn DDR_WEn DDR_CKE0 DDR_RESETn ZQ DDR_VREF 0.1 F CASn RASn WEn CKE RESETn ZQ VREFDQ VREFCA 0.1 F DDR_VREF 0.1 F DDR_VTP 49.9 (1%, 20 mW) Zo ZQ Termination is required. See terminator comments. Value determined according to the DDR3 memory device data sheet. Copyright (c) 2016, Texas Instruments Incorporated Figure 5-49. 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device With VTT Termination Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 175 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 16-Bit DDR3 Interface 16-Bit DDR3 Device DDR_D15 DQU7 8 DDR_D8 DQU0 DDR_DQM1 DDR_DQS1 DDR_DQSn1 DMU DQSU DQSUn DDR_D7 DQL7 8 DDR_D0 DQL0 DDR_DQM0 DDR_DQS0 DDR_DQSn0 DML DQSL DQSLn DDR_CK DDR_CKn CK CKn DDR_ODT0 DDR_CSn0 DDR_BA0 DDR_BA1 DDR_BA2 ODT CSn BA0 BA1 BA2 DDR_A0 A0 16 DDR_A15 A15 DDR_CASn DDR_RASn DDR_WEn DDR_CKE0 DDR_RESETn ZQ DDR_VREF 0.1 F CASn RASn WEn CKE RESETn ZQ VREFDQ VREFCA 0.1 F VDDS_DDR 0.1 F (A) 1 K 1% DDR_VREF 0.1 F 1 K 1% DDR_VTP 49.9 (1%, 20 mW) ZQ Value determined according to the DDR3 memory device data sheet. Copyright (c) 2016, Texas Instruments Incorporated A. VDDS_DDR is the power supply for the DDR3 memories and the DDR3 interface. Figure 5-50. 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device Without VTT Termination 176 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 16-Bit DDR3 Interface 8-Bit DDR3 Devices DDR_D15 DQ7 8 DDR_D8 DQ0 DDR_DQM1 NC DDR_DQS1 DDR_DQSn1 DDR_D7 DM/TDQS TDQSn DQS DQSn DQ7 8 DDR_D0 DQ0 DDR_DQM0 NC DDR_DQS0 DDR_DQSn0 DDR_CK DDR_CKn DDR_ODT0 DDR_CSn0 DDR_BA0 DDR_BA1 DDR_BA2 DDR_A0 DM/TDQS TDQSn DQS DQSn Zo CK CKn CK CKn ODT CSn BA0 BA1 BA2 ODT CSn BA0 BA1 BA2 A0 A0 Zo A15 A15 Zo CASn RASn WEn CKE RESETn ZQ VREFDQ VREFCA CASn RASn WEn CKE RESETn ZQ VREFDQ VREFCA 0.1 F VDDS_DDR Zo DDR_VTT 16 DDR_A15 DDR_CASn DDR_RASn DDR_WEn DDR_CKE0 DDR_RESETn ZQ DDR_VREF 0.1 F 0.1 F DDR_VREF ZQ 0.1 F 0.1 F DDR_VTP 49.9 (1%, 20 mW) Zo ZQ Termination is required. See terminator comments. Value determined according to the DDR3 memory device data sheet. Copyright (c) 2016, Texas Instruments Incorporated Figure 5-51. 16-Bit DDR3 Interface Using Two 8-Bit DDR3 Devices With VTT Termination Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 177 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 32-bit DDR3 EMIF DDR_CKE1 DDR_ODT1 DDR_CSn1 NC NC NC 16-Bit DDR3 Devices DDR_D31 DQU7 8 DDR_D24 DQU0 DDR_DQM3 DDR_DQS3 DDR_DQSn3 DMU DQSU DQSUn DDR_D23 DQL7 8 DDR_D16 DQL0 DDR_DQM2 DDR_DQS2 DDR_DQSn2 DML DQSL DQSLn DDR_D15 DQU7 8 DDR_D8 DQU0 DDR_DQM1 DDR_DQS1 DDR_DQSn1 DMU DQSU DQSUn DDR_D7 DQL7 8 DDR_D0 DQL0 DDR_DQM0 DDR_DQS0 DDR_DQSn0 DML DQSL DQSLn DDR_CLK DDR_CLKn DDR_ODT0 DDR_CSn0 DDR_BA0 DDR_BA1 DDR_BA2 DDR_A0 Zo CK CKn CK CKn ODT CSn BA0 BA1 BA2 ODT CSn BA0 BA1 BA2 A0 A0 Zo A15 A15 Zo CASn RASn WEn CKE RSTn ZQ VREFDQ VREFCA CASn RASn WEn CKE RSTn 0.1 F VDDS_DDR Zo DDR_VTT 16 DDR_A15 DDR_CASn DDR_RASn DDR_WEn DDR_CKE0 DDR_RESETn ZQ DDR_VREF 0.1 F 0.1 F DDR_VREF ZQ VREFDQ VREFCA ZQ 0.1 F DDR_VTP 49.9 (1% 20mW) Zo ZQ Termination is required. See terminator comments. Value determined according to the DDR memory device data sheet. Copyright (c) 2016, Texas Instruments Incorporated Figure 5-52. 32-Bit DDR3 Interface Using Two 16-Bit DDR3 Devices With VTT Termination 178 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 32-bit DDR3 EMIF DDR_CKE1 DDR_ODT1 DDR_CSn1 NC NC NC 8-Bit DDR3 Devices 8-Bit DDR3 Devices DDR_D31 DQ7 8 DDR_D24 DQ0 DDR_DQM3 NC DDR_DQS3 DDR_DQSn3 DDR_D23 DM/TQS TDQSn DQS DQSn DQ7 8 DDR_D16 DQ0 DDR_DQM2 NC DDR_DQS2 DDR_DQSn2 DDR_D15 DM/TQS TDQSn DQS DQSn DQ7 8 DDR_D8 DQ0 DDR_DQM1 NC DDR_DQS1 DDR_DQSn1 DDR_D7 DM/TQS TDQSn DQS DQSn DQ7 8 DDR_D0 DQ0 DDR_DQM0 NC DDR_DQS0 DDR_DQSn0 DM/TQS TDQSn DQS DQSn Zo DDR_CLK DDR_CLKn CK CKn CK CKn CK CKn CK CKn DDR_ODT0 DDR_CSn0 DDR_BA0 DDR_BA1 DDR_BA2 ODT CSn BA0 BA1 BA2 ODT CSn BA0 BA1 BA2 ODT CSn BA0 BA1 BA2 ODT CSn BA0 BA1 BA2 DDR_A0 A0 A0 A0 A15 A15 CASn RASn WEn CKE RSTn ZQ VREFDQ VREFCA CASn RASn WEn CKE RSTn A15 CASn RASn WEn CKE RSTn ZQ VREFDQ VREFCA 0.1 F VDDS_DDR Zo DDR_VTT A0 Zo A15 Zo 16 DDR_A15 DDR_CASn DDR_RASn DDR_WEn DDR_CKE0 DDR_RESETn ZQ DDR_VREF 0.1 F 0.1 F ZQ VREFDQ VREFCA 0.1 F ZQ ZQ 0.1 F CASn RASn WEn CKE RSTn ZQ VREFDQ VREFCA DDR_VREF ZQ 0.1 F DDR_VTP 49.9 (1% 20mW) Zo ZQ Termination is required. See terminator comments. Value determined according to the DDR memory device data sheet. Copyright (c) 2016, Texas Instruments Incorporated Figure 5-53. 32-Bit DDR3 Interface Using Four 8-Bit DDR3 Devices With VTT Termination Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 179 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.1.3.2 Compatible JEDEC DDR3 Devices Table 5-51 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface. Table 5-51. Compatible JEDEC DDR3 Devices (Per Interface) NO. PARAMETER 1 JEDEC DDR3 device speed grade 2 JEDEC DDR3 device bit width 3 CONDITION MIN tC(DDR_CK) and tC(DDR_CKn) = 2.5ns MAX UNIT DDR3-1600 x8 x32 1 4 (1) JEDEC DDR3 device count Devices (1) For valid DDR3 device configurations and device counts, see Section 5.13.8.2.1.3.1, Figure 5-49, and Figure 5-51. 5.13.8.2.1.3.3 DDR3 PCB Stackup The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 5-52. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint. Table 5-52. Minimum PCB Stackup(1) LAYER TYPE DESCRIPTION 1 Signal Top signal routing 2 Plane Ground 3 Plane Split Power Plane 4 Signal Bottom signal routing (1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in the power plane. Table 5-53. PCB Stackup Specifications(1) NO. PARAMETER MIN 1 PCB routing and plane layers 4 2 Signal routing layers 2 3 Full ground reference layers under DDR3 routing region(2) 1 4 Full VDDS_DDR power reference layers under the DDR3 routing region(2) TYP MAX UNIT 1 (3) 5 Number of reference plane cuts allowed within DDR3 routing region 6 Number of layers between DDR3 routing layer and reference plane(4) 7 PCB routing feature size 8 PCB trace width, w 9 PCB BGA escape via pad size(5) 18 10 PCB BGA escape via hole size 10 13 Single-ended impedance, Zo(6) 50 75 Zo Zo+5 14 0 0 4 mils 4 (7)(8) Impedance control Zo-5 mils 20 mils mils (1) For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation. (2) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers. (3) No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation. (4) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop. (5) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available for power routing. An 18-mil pad is required for minimum layer count escape. (6) Zo is the nominal singled-ended impedance selected for the PCB. (7) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo defined by the single-ended impedance parameter. (8) Tighter impedance control is required to ensure flight time skew is minimal. 180 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8.2.1.3.4 DDR3 Placement Figure 5-54 shows the required placement for the device as well as the DDR3 devices. The dimensions for this figure are defined in Table 5-54. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. X1 X2 X2 X2 DDR3 Controller Y Figure 5-54. Placement Specifications Table 5-54. Placement Specifications(1) NO. PARAMETER 1 X1(2)(3)(4) 2 X2 (2)(3) 3 Y Offset(2)(3)(4) 4 Clearance from non-DDR3 signal to DDR3 keepout region(5)(6) MIN MAX UNIT 1000 mils 600 mils 1500 mils 4 w (1) DDR3 keepout region to encompass entire DDR3 routing area. (2) For dimension definitions, see Figure 5-54. (3) Measurements from center of device to center of DDR3 device. (4) Minimizing X1 and Y improves timing margins. (5) w is defined as the signal trace width. (6) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 181 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.1.3.5 DDR3 Keepout Region The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout region is defined for this purpose and is shown in Figure 5-55. This region should encompass all DDR3 circuitry and the region size varies with component placement and DDR3 routing. Additional clearances required for the keepout region are shown in Table 5-54. Non-DDR3 signals should not be routed on the same signal layer as DDR3 signals within the DDR3 keepout region. Non-DDR3 signals may be routed in the region provided they are routed on layers separated from DDR3 signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the entire keepout region. DDR3 Controller DDR3 Keepout Region Encompasses Entire DDR3 Routing Area Figure 5-55. DDR3 Keepout Region 5.13.8.2.1.3.6 DDR3 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. Table 5-55 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the DDR3 interface and DDR3 devices. Additional bulk bypass capacitance may be needed for other circuitry. Table 5-55. Bulk Bypass Capacitors(1) NO. PARAMETER MIN 2 MAX UNIT 1 VDDS_DDR bulk bypass capacitor count 2 VDDS_DDR bulk bypass total capacitance 3 DDR3#1 bulk bypass capacitor count 4 DDR3#1 bulk bypass total capacitance 20 F 5 DDR3#2 bulk bypass capacitor count(2) 2 Devices 6 DDR3#2 bulk bypass total capacitance(2) 20 F 2 Devices (3) 7 DDR3#3 bulk bypass capacitor count 8 DDR3#3 bulk bypass total capacitance(3) 9 DDR3#4bulk bypass capacitor count(3) 10 DDR3#4 bulk bypass total capacitance(3) Devices 20 F 2 Devices 20 F 2 Devices 20 F (1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the highspeed (HS) bypass capacitors and DDR3 signal routing. (2) Only used when two DDR3 devices are used. (3) Only used when four DDR3 devices are used. 182 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8.2.1.3.7 DDR3 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, device DDR3 power, and device DDR3 ground connections. Table 5-56 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to: 1. Fit as many HS bypass capacitors as possible. 2. Minimize the distance from the bypass cap to the power terminals being bypassed. 3. Use the smallest physical sized capacitors possible with the highest capacitance readily available. 4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible. 5. Minimize via sharing. Note the limites on via sharing shown in Table 5-56. Table 5-56. High-Speed Bypass Capacitors NO. PARAMETER MIN (1) 1 HS bypass capacitor package size 2 Distance, HS bypass capacitor to VDDS_DDR and VSS terminal being bypassed(2)(3)(4) 3 VDDS_DDR HS bypass capacitor count 4 VDDS_DDR HS bypass capacitor total capacitance 5 Trace length from VDDS_DDR and VSS terminal to connection via(2) 6 Distance, HS bypass capacitor to DDR3 device being bypassed(5) TYP MAX UNIT 0201 0402 10 mils 400 mils 20 (6) 7 DDR3 device HS bypass capacitor count 8 DDR3 device HS bypass capacitor total capacitance(6) 9 Number of connection vias for each HS bypass capacitor(7)(8) 10 Trace length from bypass capacitor connect to connection via(2)(8) 11 Number of connection vias for each DDR3 device power and ground terminal(9) 12 Trace length from DDR3 device power and ground terminal to connection via(2)(7) Devices 1 F 35 70 mils 150 mils 12 Devices 0.85 F 2 Vias 35 100 1 mils Vias 35 60 mils (1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor. (2) Closer and shorter is better. (3) Measured from the nearest VDDS_DDR and ground terminal to the center of the capacitor package. (4) Three of these capacitors should be underneath the device, between the cluster of VDDS_DDR and ground terminals, between the DDR3 interfaces on the package. (5) Measured from the DDR3 device power and ground terminal to the center of the capacitor package. (6) Per DDR3 device. (7) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board. (8) An HS bypass capacitor may share a via with a DDR3 device mounted on the same side of the PCB. A wide trace should be used for the connection and the length from the capacitor pad to the DDR3 device pad should be less than 150 mils. (9) Up to two pairs of DDR3 power and ground terminals may share a via. 5.13.8.2.1.3.8 Return Current Bypass Capacitors Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals hopping from one signal layer to another. The bypass capacitor here provides a path for the return current to hop planes along with the signal. As many of these return current bypass capacitors should be used as possible. Because these are returns for signal current, the signal via size may be used for these capacitors. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 183 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.1.3.9 DDR3 Net Classes Table 5-57 lists the clock net classes for the DDR3 interface. Table 5-58 lists the signal net classes, and associated clock net classes, for signals in the DDR3 interface. These net classes are used for the termination and routing rules that follow. Table 5-57. Clock Net Class Definitions CLOCK NET CLASS CK PIN NAMES DDR_CK and DDR_CKn DQS0 DDR_DQS0 and DDR_DQSn0 DQS1 DDR_DQS1 and DDR_DQSn1 DQS2 DDR_DQS2 and DDR_DQSn2 DQS3 DDR_DQS3 and DDR_DQSn3 Table 5-58. Signal Net Class Definitions SIGNAL NET CLASS ASSOCIATED CLOCK NET CLASS ADDR_CTRL CK DQ0 DQS0 DDR_D[7:0], DDR_DQM0 DQ1 DQS1 DDR_D[15:8], DDR_DQM1 DQ2 DQS2 DDR_D[23:16], DDR_DQM2 DQ3 DQS3 DDR_D[31:24], DDR_DQM3 PIN NAMES DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CSn1, DDR_CASn, DDR_RASn, DDR_WEn, DDR_CKE0, DDR_CKE1, DDR_ODT0, DDR_ODT1 5.13.8.2.1.3.10 DDR3 Signal Termination Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are covered in the routing rules in the following sections. Figure 5-50 provides an example DDR3 schematic with one 16-bit DDR3 memory device that does not have VTT termination on the address and control signals. A typical DDR3 point-to-point topology may provide acceptable signal integrity without VTT termination. System performance should be verified by performing signal integrity analysis using specific PCB design details before implementing this topology. 5.13.8.2.1.3.11 DDR3 DDR_VREF Routing DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the device. DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with a voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1 F bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate routing congestion. 5.13.8.2.1.3.12 DDR3 VTT Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike DDR_VREF, VTT is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power subplane. VTT should be bypassed near the terminator resistors. 184 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew between them. CK is a bit more complicated because it runs at a higher transition rate and is differential. The following subsections show the topology and routing for various DDR3 configurations for CK and ADDR_CTRL. The figures in the following subsections define the terms for the routing specification detailed in Table 5-59. 5.13.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16) Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as one 16-bit bank or two x16 DDR3 devices arranged as one 32-bit bank. These two devices may be mounted on one side of the PCB, or may be mirrored in a pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB. 5.13.8.2.1.4.2 CK and ADDR_CTRL Topologies, Two DDR3 Devices Figure 5-56 shows the topology of the CK net classes and Figure 5-57 shows the topology for the corresponding ADDR_CTRL net classes. + - + - AS+ AS- AS+ AS- DDR3 Differential CK Input Buffers Clock Parallel Terminator VDDS_DDR Rcp A1 Device Differential Clock Output Buffer A2 A3 AT Cac + - Rcp A1 A2 A3 0.1 F AT Routed as Differential Pair NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. Figure 5-56. CK Topology for Two DDR3 Devices Device Address and Control Output Buffer A1 A2 AS AS DDR3 Address and Control Input Buffers A3 Address and Control Terminator Rtt Vtt AT NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. Figure 5-57. ADDR_CTRL Topology for Two DDR3 Devices Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 185 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.1.4.3 CK and ADDR_CTRL Routing, Two DDR3 Devices A1 A1 Figure 5-58 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 5-59 shows the corresponding ADDR_CTRL routing. VDDS_DDR A3 A3 = Rcp Cac Rcp 0.1 F AT AT AS+ AS- A2 A2 NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. A1 Figure 5-58. CK Routing for Two Single-Side DDR3 Devices Rtt A3 = Vtt AT AS A2 NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. Figure 5-59. ADDR_CTRL Routing for Two Single-Side DDR3 Devices 186 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 A1 A1 To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 5-60 and Figure 5-61 show the routing for CK and ADDR_CTRL, respectively, for two DDR3 devices mirrored in a single-pair configuration. VDDS_DDR A3 A3 = Rcp Cac Rcp 0.1 F AT AT AS+ AS- A2 A2 NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. A1 Figure 5-60. CK Routing for Two Mirrored DDR3 Devices Rtt = AT Vtt AS A3 A2 NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. Figure 5-61. ADDR_CTRL Routing for Two Mirrored DDR3 Devices Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 187 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.1.4.4 Using Four 8-Bit DDR3 Devices Two DDR3 devices are supported on the DDR3 interface consisting of four x8 DDR3 devices arranged as one 32-bit bank. These four devices may be mounted on one side of the PCB, or may be mirrored in pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB. 5.13.8.2.1.4.5 CK and ADDR_CTRL Topologies, Four DDR3 Devices Figure 5-62 shows the topology of the CK net classes and Figure 5-63 shows the topology for the corresponding ADDR_CTRL net classes. + - + - + - + - AS+ AS- AS+ AS- AS+ AS- AS+ AS- DDR Differential CK Input Buffers Clock Parallel Terminator VDDS_DDR Rcp A1 Device Differential Clock Output Buffer A2 A3 A3 A4 AT Cac + - Rcp A1 A2 A3 A3 A4 0.1 F AT Routed as Differential Pair NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. Figure 5-62. CK Topology for Four DDR3 Devices Device Address and Control Output Buffer A1 A2 A3 A4 AS AS AS AS DDR Address and Control Input Buffers A3 Address and Control Terminator Rtt Vtt AT NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. Figure 5-63. ADDR_CTRL Topology for Four DDR3 Devices 5.13.8.2.1.4.6 CK and ADDR_CTRL Routing, Four DDR3 Devices Figure 5-64 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 5-65 shows the corresponding ADDR_CTRL routing. 188 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 A1 A1 www.ti.com VDDS_DDR A3 A3 = A3 A3 A4 A4 Rcp Cac Rcp 0.1 F AT AT AS+ AS- A2 A2 NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. A1 Figure 5-64. CK Routing for Four Single-Side DDR3 Devices Rtt A3 = A4 A3 AT Vtt AS A2 NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification. Figure 5-65. ADDR_CTRL Routing for Four Single-Side DDR3 Devices Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 189 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com A1 A1 To save PCB space, the four DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 5-66 and Figure 5-67 show the routing for CK and ADDR_CTRL, respectively, for four DDR3 devices mirrored in a single-pair configuration. VDDS_DDR A3 A3 = A3 A3 A4 A4 Rcp Cac Rcp 0.1 F AT AT AS+ AS- A2 A2 A1 Figure 5-66. CK Routing for Four Mirrored DDR3 Devices Rtt = A4 A3 AT Vtt AS A3 A2 Figure 5-67. ADDR_CTRL Routing for Four Mirrored DDR3 Devices 190 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8.2.1.4.7 One 16-Bit DDR3 Device One DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as one 16-bit bank. 5.13.8.2.1.4.8 CK and ADDR_CTRL Topologies, One DDR3 Device Figure 5-68 shows the topology of the CK net classes and Figure 5-69 shows the topology for the corresponding ADDR_CTRL net classes. DDR3 Differential CK Input Buffer AS+ AS- + - Clock Parallel Terminator VDDS_DDR Rcp A1 Device Differential Clock Output Buffer A2 AT Cac + - Rcp A1 A2 0.1 F AT Routed as Differential Pair Figure 5-68. CK Topology for One DDR3 Device AS DDR3 Address and Control Input Buffers Device Address and Control Output Buffer A1 A2 Address and Control Terminator Rtt AT Vtt Figure 5-69. ADDR_CTRL Topology for One DDR3 Device Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 191 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.1.4.9 CK and ADDR_CTRL Routing, One DDR3 Device A1 A1 Figure 5-70 shows the CK routing for one DDR3 device. Figure 5-71 shows the corresponding ADDR_CTRL routing. VDDS_DDR Rcp Cac Rcp 0.1 F AT AT = AS+ AS- A2 A2 A1 Figure 5-70. CK Routing for One DDR3 Device Rtt AT = Vtt AS A2 Figure 5-71. ADDR_CTRL Routing for One DDR3 Device 5.13.8.2.1.5 Data Topologies and Routing Definition No matter the number of DDR3 devices used, the data line topology is always point to point, so its definition is simple. 5.13.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point singled ended. Figure 5-72 and Figure 5-73 show these topologies. 192 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Device DQS[x] IO Buffer DDR3 DQS[x] IO Buffer DQS[x]+ DQS[x]Routed Differentially x = 0, 1, 2, 3 Figure 5-72. DQS[x] Topology Device DQ[x] IO Buffer DDR3 DQ[x] IO Buffer DQ[x] x = 0, 1, 2, 3 Figure 5-73. DQ[x] Topology 5.13.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices Figure 5-74 and Figure 5-75 show the DQS[x] and DQ[x] routing. DQS[x]+ DQS[x]- DQS[x] Routed Differentially x = 0, 1, 2, 3 Figure 5-74. DQS[x] Routing With Any Number of Allowed DDR3 Devices DQ[x] x = 0, 1, 2, 3 Figure 5-75. DQ[x] Routing With Any Number of Allowed DDR3 Devices Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 193 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.1.6 Routing Specification 5.13.8.2.1.6.1 CK and ADDR_CTRL Routing Specification Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address Control Longest Manhattan distance. Given the clock and address pin locations on the device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 5-76 shows this distance for two loads. It is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 5-59. 194 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 (A) A1 A8 CACLMY CACLMX A8 (A) A8 (A) Rtt A3 = Vtt (A) A1 A8 AT AS A2 CACLMY CACLMX A8 (A) A8 (A) A8 (A) A8 (A) Rtt A3 = A. A4 A3 AT Vtt AS A2 It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK and ADDR_CTRL skew matching and length control. The length of shorter CK and ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Nonincluded lengths are grayed out in the figure. Assuming A8 is the longest, CACLM = CACLMY + CACLMX + 300 mils. The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8. Figure 5-76. CACLM for Two or Four Address Loads on One Side of PCB Table 5-59. CK and ADDR_CTRL Routing Specification(1)(2)(3) NO. PARAMETER MIN TYP MAX UNIT 2500 mils 25 mils 660 mils 1 A1+A2 length 2 A1+A2 skew 3 A3 length 4 A3 skew(4) 25 mils 5 (5) 125 mils A3 skew Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 195 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-59. CK and ADDR_CTRL Routing Specification(1)(2)(3) (continued) NO. PARAMETER MAX UNIT 660 mils A4 skew 25 mils AS length 100 mils 9 AS skew 25 mils 10 AS+ and AS- length 70 mils 11 AS+ and AS- skew 5 mils 12 AT length(6) 6 A4 length 7 8 MIN TYP 500 (7) 13 AT skew 14 AT skew(8) 15 CK and ADDR_CTRL nominal trace length(9) 16 Center-to-center CK to other DDR3 trace spacing(10) mils 100 CACLM-50 (10)(11) CACLM mils 5 mils CACLM+50 mils 4 w 4 w 3 w 17 Center-to-center ADDR_CTRL to other DDR3 trace spacing 18 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(10) 19 CK center-to-center spacing(12) 20 CK spacing to other net(10) 21 Rcp(13) Zo-1 Zo Zo+1 22 Rtt(13)(14) Zo-5 Zo Zo+5 4 w (1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class. (2) The use of vias should be minimized. (3) Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump between the VDDS_DDR plane and the ground plane when the net class switches layers at a via. (4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom). (5) Nonmirrored configuration (all DDR3 memories on same side of PCB). (6) While this length can be increased for convenience, its length should be minimized. (7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required. (8) CK net class only. (9) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 5.13.8.2.1.6.1 and Figure 5-76. (10) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length. (11) Signals from one DQ net class should be considered other DDR3 traces to another DQ net class. (12) CK spacing set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 5-53. (13) Source termination (series resistor at driver) is specifically not allowed. (14) Termination values should be uniform across the net class. 5.13.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs, DQLM0 and DQLM1. NOTE It is not required, nor is it recommended, to match the lengths across all bytes. Length matching is only required within each byte. 196 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Given the DQS[x] and DQ[x] pin locations on the device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 5-77 shows this distance for a twoload case. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 5-60. DQLMX0 DQ[0:7], DM0, DQS0 DQ0 DQ1 DQ[8:15], DM1, DQS1 DQLMX1 DQ[16:23], DM2, DQS2 DQ2 DQLMX2 DQ[24:31], DM3, DQS3 DQ3 DQLMY3 DQLMY2 DQLMY0 DQLMY1 DQLMX3 3 2 1 0 DQ0 - DQ3 represent data bytes 0 - 3. There are four DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore: DQLM0 = DQLMX0 + DQLMY0 DQLM1 = DQLMX1 + DQLMY1 DQLM2 = DQLMX2 + DQLMY2 DQLM3 = DQLMX3 + DQLMY3 Figure 5-77. DQLM for Any Number of Allowed DDR3 Devices Table 5-60. DQS[x] and DQ[x] Routing Specification(1)(2) NO. MAX UNIT 1 (3)(4) PARAMETER MIN TYP DQ0 nominal length DQLM0 mils 2 DQ1 nominal length(3)(5) DQLM1 mils 3 DQ2 nominal length DQLM2 mils 4 DQ3 nominal length DQLM3 mils 5 DQ[x] skew(6) 25 mils 6 DQS[x] skew 5 mils 25 mils (6)(7) 7 DQS[x]-to-DQ[x] skew 8 Center-to-center DQ[x] to other DDR3 trace spacing(8)(9) 4 w 9 Center-to-center DQ[x] to other DQ[x] trace spacing(8)(10) 3 w 10 DQS[x] center-to-center spacing(11) 11 DQS[x] center-to-center spacing to other net(8) 4 w (1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes. (2) External termination disallowed. Data termination should use built-in ODT functionality. (3) DQLMn is the longest Manhattan distance of a byte. For definition, see Section 5.13.8.2.1.6.2 and Figure 5-77. (4) DQLM0 is the longest Manhattan length for the DQ0 net class. (5) DQLM1 is the longest Manhattan length for the DQ1 net class. (6) Length matching is only done within a byte. Length matching across bytes is not required. To maintain tighter delay skew, route the DQ[x] and DQS[x] signals within a byte to have same number of VIA and layer transitions. (7) Each DQS clock net class is length matched to its associated DQ signal net class. (8) Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length. (9) Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class. (10) This applies to spacing within same DQ[x] signal net class. (11) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the singleended impedance defined in Table 5-53. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 197 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.2 LPDDR2 Routing Guidelines This section provides the timing specification for the LPDDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR2 memory system without the need for a complex timing closure process. For more information regarding guidelines for using this LPDDR2 specification, see Understanding TI's PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedence over the generic guidelines and must be adhered to for a reliable LPDDR2 interface operation. 5.13.8.2.2.1 LPDDR2 Board Designs TI only supports board designs using LPDDR2 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the LPDDR2 memory interface are shown in Table 5-61 and Figure 5-78. Table 5-61. Switching Characteristics for LPDDR2 Memory Interface NO. 1 PARAMETER tc(DDR_CK) Cycle time, DDR_CK and DDR_CKn MIN MAX 7.52 3.76(1) UNIT ns (1) The JEDEC JESD209-2F standard defines the maximum clock period of 100 ns for all standard-speed bin LPDDR2 memory. The device has only been tested per the limits published in this table. 1 DDR_CK DDR_CKn Figure 5-78. LPDDR2 Memory Interface Clock Timing 5.13.8.2.2.2 LPDDR2 Device Configurations There are several possible combinations of device counts and single-side or dual-side mounting. Table 562 lists all the supported configurations. Table 5-62. Supported LPDDR2 Device Combinations NUMBER OF LPDDR2 DEVICES LPDDR2 DEVICE WIDTH (BITS) MIRRORED?(1) LPDDR2 EMIF WIDTH (BITS) 1 32 N 32 (2) 32 N 32 1 16 N 16 2(2) 16 N 16 2 (1) Two LPDDR2 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of the board. (2) Two devices are supported only with twin-die configuration which embeds two devices in the same package. Details on treating unused pins are listed in Section 5.13.8.2.2.3.1. 198 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8.2.2.3 LPDDR2 Interface 5.13.8.2.2.3.1 LPDDR2 Interface Schematic The LPDDR2 interface schematic varies, depending upon the width of the LPDDR2 devices used. Figure 5-79 shows the schematic connections for 16-bit interface using one x16 LPDDR2 device. Two x16 LPDDR2 devices are supported for twin-die configuration which embeds two devices in the same package. 16-Bit LPDDR2 Interface 16-Bit LPDDR2 Device DDR_D15 DQ15 8 DDR_D8 DQ8 DDR_DQM1 DDR_DQS1 DDR_DQSn1 DM1 DQS1_t DQS1_c DDR_D7 DQ7 8 DDR_D0 DQ0 DDR_DQM1 DDR_DQS1 DDR_DQSn1 DM0 DQS0_t DQS0_c DDR_CK DDR_CKn CK_t CK_c DDR_CKE0 DDR_CKE1 DDR_CSn0 DDR_CSn1 DDR_RASn DDR_CASn DDR_WEn DDR_BA0 DDR_BA1 DDR_BA2 DDR_A1 DDR_A2 DDR_A10 DDR_A13 CKE0 CKE1 CS0_n CS1_n CA0 CA1 CA2 CA7 CA8 CA9 CA5 CA6 CA4 CA3 ZQ DDR_VREF 0.1 F ZQ0/1 Vref(CA) Vref(DQ) 0.1 F VDDS_DDR 0.1 F 1K DDR_VREF 0.1 F 1K DDR_VTP 49.9 (1%, 20 mW) Copyright (c) 2016, Texas Instruments Incorporated Figure 5-79. 16-Bit Interface Using One 16-Bit LPDDR2 Device Figure 5-80 shows the schematic connections for 32-bit interface using one x32 LPDDR2 device. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 199 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 32-Bit LPDDR2 Interface 32-Bit LPDDR2 Device DDR_D31 DQ31 8 DDR_D24 DQ24 DDR_DQM3 DDR_DQS3 DDR_DQSn3 DM31 DQS3_t DQS3_c DDR_D23 DQ23 8 DDR_D16 DQ16 DDR_DQM2 DDR_DQS2 DDR_DQSn2 DM2 DQS2_t DQS2_c DDR_D15 DQ15 8 DDR_D8 DQ8 DDR_DQM1 DDR_DQS1 DDR_DQSn1 DM1 DQS1_t DQS1_c DDR_D7 DQ7 8 DQ0 DDR_D0 DDR_DQM0 DDR_DQS0 DDR_DQSn0 DDR_CK DDR_CKn DM0 DQS0_t DQS0_c CK_t CK_c DDR_CKE0 DDR_CKE1 DDR_CSn0 DDR_CSn1 DDR_RASn DDR_CASn DDR_WEn DDR_BA0 DDR_BA1 DDR_BA2 DDR_A1 DDR_A2 DDR_A10 DDR_A13 CKE0 CKE1 CS0_n CS1_n CA0 CA1 CA2 CA7 CA8 CA9 CA5 CA6 CA4 CA3 ZQ DDR_VREF 0.1 F ZQ0/1 Vref(CA) Vref(DQ) 0.1 F VDDS_DDR 0.1 F 1K DDR_VREF 0.1 F 1K DDR_VTP 49.9 (1% 20mW) Copyright (c) 2016, Texas Instruments Incorporated Figure 5-80. 32-Bit Interface Using One 32-Bit LPDDR2 Device When not using a part of LPDDR2 interface (using x16 or not using the LPDDR2 interface): * Connect the VDDS_DDR supply to 1.8 V * Connect the DDR_VREF supply to 0.9 V * Tie off DDR_DQS[x] (x=0,1,2,3) that are unused to VSS via 1 k * Tie off DDR_DQSn[x] (x=0,1,2,3) that are unused to VDDS_DDR via 1 k * All other unused pins can be left as NC. Note: All the unused DDR ADDR_CTRL lines used for DDR3 operation should be left as NC. 200 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices Table 5-63 shows the supported LPDDR2 device configurations which are compatible with this interface. Table 5-63. Compatible JEDEC LPDDR2 Devices (Per Interface) NO. PARAMETER 1 JEDEC LPDDR2 device speed grade 2 JEDEC LPDDR2 device bit width 3 JEDEC LPDDR2 device count CONDITION MIN tc(DDR_CK) and tc(DDR_CKn) MAX UNIT LPDDR2-533 x16 x32 Bits 1 2(1) Devices (1) Two devices are supported only with twin-die configuration which embeds two devices in the same package. 5.13.8.2.2.3.3 LPDDR2 PCB Stackup Table 5-64 shows the minimum stackup requirements. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint. Table 5-64. Minimum PCB Stackup LAYER TYPE DESCRIPTION 1 Signal Top signal routing 2 Plane Ground 3 Plane Power 4 Signal Bottom signal routing PCB stackup specifications for LPDDR2 interface are listed in Table 5-65. Table 5-65. PCB Stackup Specifications(1) NO. PARAMETER MIN TYP MAX UNIT 1 PCB routing and plane layers 4 2 Signal routing layers 2 3 Full ground reference layers under LPDDR2 routing region(1) 1 4 Full VDDS_DDR power reference layers under the LPDDR2 routing region(1) 1 5 Number of reference plane cuts allowed within LPDDR2 routing region(2) 0 6 Number of layers between LPDDR2 routing layer and reference plane(3) 0 7 PCB routing feature size 4 8 PCB trace width, w 4 9 PCB BGA escape via pad size(4) 18 10 PCB BGA escape via hole size 10 11 Single-ended impedance, Zo(5) 50 75 12 Impedance control(6)(7) Zo Zo+5 Zo-5 mils mils 20 mils mils (1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer return current as the trace routes switch routing layers. (2) No traces should cross reference plane cuts within the LPDDR2 routing region. High-speed signal traces crossing reference plane cuts create large return current paths which can lead to excessive crosstalk and EMI radiation. (3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop. (4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available for power routing. An 18-mil pad is required for minimum layer count escape. (5) Zo is the nominal singled-ended impedance selected for the PCB. (6) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo defined by the single-ended impedance parameter. (7) Tighter impedance control is required to ensure flight time skew is minimal. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 201 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.2.3.4 LPDDR2 Placement Figure 5-81 shows the placement rules for the device as well as the LPDDR2 memory device. Placement restrictions are provided as a guidance to restrict maximum trace lengths and allow for proper routing space. X1 Y LPDDR2 interface Figure 5-81. Placement Specifications Table 5-66. Placement Specifications(1) NO. MAX UNIT 1 X1 Offset(2)(3) 1500 mils 2 Y Offset(2)(3)(4) 1500 mils 3 PARAMETER MIN (4)(5) Clearance from non-LPDDR2 signal to LPDDR2 keepout region 4 w (1) LPDDR2 keepout region to encompass entire LPDDR2 routing area. (2) Measurements from center of device to center of LPDDR2 device. (3) Minimizing X1 and Y improves timing margins. (4) w is defined as the signal trace width. (5) Non-LPDDR2 signals allowed within LPDDR2 keepout region provided they are separated from LPDDR2 routing layers by a ground plane. 5.13.8.2.2.3.5 LPDDR2 Keepout Region The region of the PCB used for LPDDR2 circuitry must be isolated from other signals. The LPDDR2 keepout region is defined for this purpose and is shown in Figure 5-82. This region should encompass all LPDDR2 circuitry and the region size varies with component placement and LPDDR2 routing. NonLPDDR2 signals should not be routed on the same signal layer as LPDDR2 signals within the LPDDR2 keepout region. Non-LPDDR2 signals may be routed in the region provided they are routed on layers separated from LPDDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover the entire keepout region. 202 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 LPDDR2 interface LPDDR2 Keepout Region Encompasses Entire LPDDR2 Routing Area Figure 5-82. LPDDR2 Keepout Region 5.13.8.2.2.3.6 LPDDR2 Net Classes Table 5-67. Clock Net Class Definitions for the LPDDR2 Interface CLOCK NET CLASS CK PIN NAMES DDR_CK and DDR_CKn DQS0 DDR_DQS0 and DDR_DQSn0 DQS1 DDR_DQS1 and DDR_DQSn1 DQS2 DDR_DQS2 and DDR_DQSn2 DQS3 DDR_DQS3 and DDR_DQSn3 Table 5-68. Signal Net Class and Associated Clock Net Class for LPDDR2 Interface SIGNAL NET CLASS ASSOCIATED CLOCK NET CLASS ADDR_CTRL CK DQ0 DQS0 DDR_D[7:0], DDR_DQM0 DQ1 DQS1 DDR_D[15:8], DDR_DQM1 DQ2 DQS2 DDR_D[23:16], DDR_DQM2 DQ3 DQS3 DDR_D[31:24], DDR_DQM3 PIN NAMES DDR_BA[2:0], DDR_CSn0, DDR_CSn1, DDR_CKE0, DDR_CKE1, DDR_RASn, DDR_CASn, DDR_WEn, DDR_A1, DDR_A2, DDR_A10, DDR_A13 5.13.8.2.2.3.7 LPDDR2 Signal Termination On-device termination (ODT) is available for DQ[3:0] signal net classes, but is not specifically required for normal operation. System designers may evaluate the need for additional series termination if required based on signal integrity, EMI and overshoot/undershoot reduction. 5.13.8.2.2.3.8 LPDDR2 DDR_VREF Routing DDR_VREF is the reference voltage for the input buffers on the LPDDR2 memory as well as the device. DDR_VREF is intended to be half the LPDDR2 power supply voltage and is typically generated with a voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1-F bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate routing congestion. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 203 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.8.2.2.4 Routing Specification 5.13.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification DQS[x] lines are point-to-point differential and DQ[x] lines are point-to-point single ended. Figure 5-83 and Figure 5-84 represent the supported topologies. Figure 5-85 and Figure 5-86 show the DQS[x] and DQ[x] routing. Figure 5-87 shows the DQLM for the LPDDR2 interface. Device DQS[x] IO Buffer DDR3 DQS[x] IO Buffer DQS[x]+ DQS[x]Routed Differentially x = 0, 1, 2, 3 Figure 5-83. DQS[x] Topology Device DQ[x] IO Buffer DDR3 DQ[x] IO Buffer DQ[x] x = 0, 1, 2, 3 Figure 5-84. DQ[x] Topology DQS[x]+ DQS[x]- DQS[x] Routed Differentially x = 0, 1, 2, 3 Figure 5-85. DQS[x] Routing 204 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 DQ[x] x = 0, 1, 2, 3 Figure 5-86. DQ[x] Routing DQLMXi DQi LPDDR2 interface i = 0, 1, 2, 3 DQLMYi DQLM0 = DQLMX0 + DQLMY0 DQLM1 = DQLMX1 + DQLMY1 DQLM2 = DQLMX2 + DQLMY2 DQLM3 = DQLMX3 + DQLMY3 DQ0 - DQ3 represent data bytes 0 - 3. There are four DQLMs, one for each data byte, in a 32-bit interface and two DQLMs, one for each data byte, in a 16bit interface. Each DQLM is the longest Manhattan distance of the byte. Figure 5-87. DQLM for LPDDR2 Interface Trace routing specifications for the DQ[x] and the DQS[x] are specified in Table 5-69. Table 5-69. DQS[x] and DQ[x] Routing Specification(1)(2) NO. MAX UNIT 1 DQ0 nominal length(3)(4) PARAMETER MIN TYP DQLM0 mils 2 DQ1 nominal length(3)(5) DQLM1 mils 3 DQ2 nominal length (3)(6) DQLM2 mils 4 DQ3 nominal length (3)(7) DQLM3 mils 5 DQ[x] skew(8) 50 mils 6 DQS[x] skew 10 mils 7 Via count per each trace in DQ[x], DQS[x] 8 Via count difference across a given DQ[x], DQS[x] 9 DQS[x]-to-DQ[x] skew(8)(9) 2 0 50 (10)(11) 10 Center-to-center DQ[x] to other LPDDR2 trace spacing 11 Center-to-center DQ[x] to other DQ[x] trace spacing(10)(12) 12 DQS[x] center-to-center spacing(13) 13 DQS[x] center-to-center spacing to other net(10) mils 4 w 3 w 4 w Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 205 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com (1) DQS[x] represents the DQS0, DQS1, DQS2, DQS3 clock net classes, and DQ[x] represents the DQ0, DQ1, DQ2, DQ3 signal net classes. (2) External termination disallowed. Data termination should use built-in ODT functionality. (3) DQLMn is the longest Manhattan distance of a byte. (4) DQLM0 is the longest Manhattan length for the DQ0 net class. (5) DQLM1 is the longest Manhattan length for the DQ1 net class. (6) DQLM2 is the longest Manhattan length for the DQ2 net class. (7) DQLM3 is the longest Manhattan length for the DQ3 net class. (8) Length matching is only done within a byte. Length matching across bytes is not required. (9) Each DQS clock net class is length matched to its associated DQ signal net class. (10) Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length. (11) Other LPDDR2 trace spacing means signals that are not part of the same DQ[x] signal net class. (12) This applies to spacing within same DQ[x] signal net class. (13) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the singleended impedance. 5.13.8.2.2.4.2 CK and ADDR_CTRL Routing Specification CK signals are routed as point-to-point differential, and ADDR_CTRL signals are routed as point-to-point single ended. The supported topology for CK and ADDR_CTRL are shown in Figure 5-88 through Figure 5-91. ADDR_CTRL are routed very similar to DQ and CK is routed very similar to DQS. CK+ Device CK Output Buffer LPDDR2 Input Buffer CKRouted Differentially Figure 5-88. CK Signals Topology Device ADDR_CTRL Output Buffer LPDDR2 ADDR_CTRL Input Buffer ADDR_CTRL Figure 5-89. ADDR_CTRL Signals Topology CK+ CK- CK- Routed Differentially Figure 5-90. CK Signals Routing 206 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 ADDR_CTRL Figure 5-91. ADDR_CTRL Signals Routing CACLMX LPDDR2 interface CACLM = CACLMX + CACLMY CACLMY CACLM is the longest Manhattan distance of the CK/ADDR_CTRL signal class. Figure 5-92. CACLM for LPDDR2 Interface Trace routing specifications for the CK and the ADD_CTRL are specified in Table 5-70. Table 5-70. CK and ADDR_CTRL Routing Specification NO. PARAMETER MIN TYP (1) MAX UNIT 1 CK and ADDR_CTRL nominal trace length CACLM mils 2 ADDR_CTRL skew 50 mils 3 CK skew 10 mils 4 Via count per each trace ADDR_CTRL, CK 5 Via count difference across ADDR_CTRL, CK 6 ADDR_CTRL-to-CK skew 7 Center-to-center ADDR_CTRL to other LPDDR2 trace spacing(2)(3) 2 0 50 8 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing 9 CK center-to-center spacing(4) 10 CK center-to-center spacing to other net(2) (2) mils 4 w 3 w 4 w (1) CACLM is the longest Manhattan distance of ADDR_CTRL and CK. (2) Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length. (3) Other LPDDR2 trace spacing means signals that are not part of the same CK, ADDR_CTRL signal net class. (4) CK pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single ended impedance. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 207 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.9 Display Subsystem (DSS) NOTE For more information, see the Display Subsystem chapter of the AM437x Sitara Processors Technical Reference Manual. The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or internal (SRAM) memory on an LCD panel or a TV set. The display subsystem integrates the following elements: * Display controller (DISPC) module * Remote frame buffer interface (RFBI) module The DSS can be used in the following configuration: LCD display with parallel interface 5.13.9.1 DSS--Parallel Interface In parallel interface, the paths of the display subsystem modules are the display controller and the RFBI. The display controller has two I/O pad modes and could be in the following configuration: * Bypass mode (RFBI disabled), which implements the MIPI DPI protocol * RFBI mode (RFBI enabled), which implements MIPI DBI 2.0 type B protocol 5.13.9.1.1 DSS--Parallel Interface--Bypass Mode Two types of LCD panel are supported: * Thin film transistor (TFT) or active matrix technology * Supertwisted nematic (STN) or passive matrix technology Both configurations are discussed in the following paragraphs. 5.13.9.1.1.1 DSS--Parallel Interface--Bypass Mode--TFT Mode Table 5-72 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-93). Table 5-71. DSS Timing Conditions--TFT Mode VALUE TIMING CONDITION PARAMETER MIN UNIT MAX Output Condition CLOAD Output load capacitance 10 pF Table 5-72. DSS Switching Characteristics--TFT Mode NO. PARAMETER OPP100 OPP50 MIN MAX MIN MAX UNIT DL0 td(pclkA-hsync) Delay time, output pixel clock dss_pclk active edge to output horizontal synchronization dss_hsync transition -2.4 2.4 -3.5 2.5 ns DL1 td(pclkA-vsync) Delay time, output pixel clock dss_pclk active edge to output vertical synchronization dss_vsync transition -2.4 2.4 -3.5 2.5 ns DL2 td(pclkA-acbiasA) Delay time, output pixel clock dss_pclk active edge to output data enable dss_acbias active level -2.4 2.4 -3.5 2.5 ns DL3 td(pclkA-dV) Delay time, output pixel clock dss_pclk active edge to output data dss_data[23:0] valid -2.4 2.4 -3.5 2.5 ns DL4 1 / tc(pclk) Frequency(1), output pixel clock dss_pclk 75 MHz 208 Specifications 100 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-72. DSS Switching Characteristics--TFT Mode (continued) NO. OPP100 PARAMETER DL5 tw(pclk) Pulse duration, output pixel clock dss_pclk low or high tJ(pclk) Peak-peak jitter, output pixel clock dss_pclk OPP50 UNIT MIN MAX MIN MAX 0.45P(2) 0.55P(2)(3) 0.45P(2) 0.55P(2)(3) ns 200 ps 200 (1) The pixel clock frequency is software programmable via the pixel clock DISPC_DIVISOR register. (2) P = dss_pclk period in ns (3) tw(pclk) = 0.66P when DISPC_DIVISOR[7:0] PCD = 3 DL5 DL4 dss_pclk DL1 dss_vsync DL0 dss_hsync DL2 dss_acbias DL3 dss_data[23:0] A. B. C. D. The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins. The pixel clock frequency is programmable. All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual. Figure 5-93. DSS--TFT Mode 5.13.9.1.1.2 DSS--Parallel Interface--Bypass Mode--STN Mode Table 5-74 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-94). Table 5-73. DSS Timing Conditions--STN Mode VALUE TIMING CONDITION PARAMETER MIN UNIT MAX Output Condition CLOAD Output load capacitance 40 pF Table 5-74. DSS Switching Characteristics--STN Mode (1) NO. (1) (2) (3) (4) PARAMETER DL3 td(pclkA-dV) Delay time, output pixel clock dss_pclk active edge to output data dss_data[7:0] valid DL4 1 / tc(pclk) Frequency (2), output pixel clock dss_pclk DL5 tw(pclk) Pulse duration, output pixel clock dss_pclk low or high OPP100 OPP50 UNIT MIN MAX MIN MAX -6 6 -6 6 ns 45 MHz 0.45P (3) 0.55P (3) (4) 0.45P (3) 0.55P (3) (4) ns 45 The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low. The pixel clock frequency is software programmable via the pixel clock divider DISPC_DIVISOR register. P = dss_pclk period in ns tW(pclk) = 0.66P when DISPC_DIVISOR[7:0] PCD = 3 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 209 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-74. DSS Switching Characteristics--STN Mode(1) (continued) NO. OPP100 PARAMETER tJ(pclk) MIN Peak-peak jitter, output pixel clock dss_pclk OPP50 MAX MIN 200 MAX UNIT 200 ps DL5 DL4 dss_pclk dss_vsync dss_hsync dss_acbias DL3 dss_data[23:0] A. B. C. D. E. The pixel data bus depends on the use of 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins. All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too. dss_vsync width must be programmed to be as small as possible. The pixel clock frequency is programmable. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual. Figure 5-94. DSS--STN Mode 5.13.9.1.2 DSS--Parallel Interface--RFBI Mode--Applications 5.13.9.1.2.1 DSS--Parallel Interface--RFBI Mode--MIPI DBI 2.0--LCD Panel The Remote Frame Buffer Interface (RFBI) module provides the necessary control signals and data (MIPI(R) DBI 2.0 type B protocol) to interface to the LCD driver of the LCD panel. Table 5-76 and Table 5-77 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-95, Figure 5-96, and Figure 5-97). Table 5-75. DSS Timing Conditions--RFBI Mode--MIPI DBI 2.0--LCD Panel (1) TIMING CONDITION PARAMETER VALUE MIN MAX UNIT Input Conditions tR Input signal rise time 7 ns tF Input signal fall time 7 ns 30 pF Output Condition CLOAD (1) 210 Output load capacitance For any information regarding the RFBI registers configuration, see the Display Subsystem / Display Subsystem Environment / LCD Support / Parallel Interface / Parallel Interface in RFBI Mode (MIPI DBI Protocol) / Transaction Timing Diagrams section of the AM437x Sitara Processors Technical Reference Manual. Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-76. DSS Timing Requirements--RFBI Mode--MIPI DBI 2.0--LCD Panel NO. PARAMETER OPP100 MIN OPP50 MAX MIN MAX UNIT DR0 tsu(dV-rdH) Setup time, input data rfbi_da[15:0] valid to output read enable rfbi_rd high 7 7 ns DR1 th(rdH-dIV) Hold time, output read enable rfbi_rd high to input data rfbi_da[15:0] invalid 5 5 ns td(Data Input data rfbi_da[15:0] sampled at the end of the access time sampled) N(1) N(1) ns (1) N = (AccessTime) x (TimeParaGranularity + 1) x L4CLK Table 5-77. DSS Switching Characteristics--RFBI Mode--MIPI DBI 2.0--LCD Panel OPP100 PARAMETER tw(wrH) MIN Pulse duration, output write enable rfbi_wr high OPP50 MAX MIN MAX UNIT A(1) A(1) ns (2) (2) ns tw(wrL) Pulse duration, output write enable rfbi_wr low B td(a0-wrL) Delay time, output command/data control rfbi_a0 transition to output write enable rfbi_wr low C(3) C(3) B ns td(wrH-a0) Delay time, output write enable rfbi_wr high to output command/data control rfbi_a0 transition D(4) D(4) ns td(csx-wrL) Delay time, output chip select rfbi_csx(14) low to output write enable rfbi_wr low E(5) E(5) ns td(wrH-csxH) Delay time, output write enable rfbi_wr high to output chip select rfbi_csx(14) high F(6) F(6) ns td(dV) Output data rfbi_da[15:0] valid G(7) G(7) ns (8) (8) ns td(a0H-rdL) Delay time, output command/data control rfbi_a0 high to output read enable rfbi_rd low H H td(rdlH-a0) Delay time, output read enable rfbi_rd high to output command/data control rfbi_a0 transition I(9) I(9) ns tw(rdH) Pulse duration, output read enable rfbi_rd high J(10) J(10) ns (11) K(11) ns tw(rdL) Pulse duration, output read enable rfbi_rd low K td(rdL-csxL) Delay time, output read enable rfbi_rd low to output chip select rfbi_csx(14) low L(12) L(12) ns td(rdH-csxH) Delay time, output read enable rfbi_rd high to output chip select rfbi_csx(14) high M(13) M(13) ns tR(wr) Rise time, output write enable rfbi_wr 7 7 ns tF(wr) Fall time, output write enable rfbi_wr 7 7 ns tR(a0) Rise time, output command/data control rfbi_a0 7 7 ns tF(a0) Fall time, output command/data control rfbi_a0 7 7 ns (14) tR(csx) Rise time, output chip select rfbi_csx 7 7 ns tF(csx) Fall time, output chip select rfbi_csx(14) 7 7 ns tR(d) Rise time, output data rfbi_da[15:0] 7 7 ns tF(d) Fall time, output data rfbi_da[15:0] 7 7 ns tR(rd) Rise time, output read enable rfbi_rd 7 7 ns tF(rd) Fall time, output read enable rfbi_rd 7 7 ns (1) A = (WECycleTime - WEOffTime) x (TimeParaGranularity + 1) x L4CLK (2) B = (WEOffTime - WEOntime) x (TimeParaGranularity + 1) x L4CLK (3) C = WEOnTime x (TimeParaGranularity + 1) x L4CLK (4) D = (WECycleTime + CSPulseWidth - WEOffTime) x (TimeParaGranularity + 1) x L4CLK if mode Write to Read or Read to Write is enabled (5) E = (WEOnTime - CSOnTime) x (TimeParaGranularity + 1) x L4CLK (6) F = (CSOffTime - WEOffTime) x (TimeParaGranularity + 1) x L4CLK (7) G = WECycleTime x (TimeParaGranularity + 1) x L4CLK Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 211 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com (8) H = REOnTime x (TimeParaGranularity + 1) x L4CLK (9) I = (RECycleTime + CSPulseWidth - REOffTime) x (TimeParaGranularity + 1) x L4CLK if mode Write to Read or Read to Write is enabled (10) J = (RECycleTime - REOffTime) x (TimeParaGranularity + 1) x L4CLK (11) K = (REOffTime - REOntime) x (TimeParaGranularity + 1) x L4CLK (12) L = (REOnTime - CSOnTime) x (TimeParaGranularity + 1) x L4CLK (13) M = (CSOffTime - REOffTime) x (TimeParaGranularity + 1) x L4CLK (14) In rfbi_csx, x is equal to 0 or 1. CsPulseWidth WeCycleTime WeCycleTime rfbi_a0 CsOffTime CsOffTime CsOnTime rfbi_csx CsOnTime (A) WeOffTime WeOffTime WeOnTime WeOnTime rfbi_wr rfbi_da[n:0] (B) DATA0 DATA1 rfbi_rd rfbi_te_vsync[1:0] rfbi_hsync[1:0] A. B. C. In rfbi_csx, x is equal to 0 or 1. rfbi_da[n:0], n up to 15 For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual. Figure 5-95. DSS--RFBI Mode--MIPI DBI 2.0--LCD Panel--Command / Data Write AccessTime AccessTime ReCycleTime ReCycleTime CsPulseWidth rfbi_a0 CsOffTime rfbi_csx CsOffTime CsOnTime CsOnTime ReOffTime ReOffTime (A) ReOnTime ReOnTime rfbi_rd DR0 rfbi_da[n:0] (B) DATA0 DR1 DATA1 rfbi_wr rfbi_te_vsync[1:0] rfbi_hsync[1:0] A. B. C. In rfbi_csx, x is equal to 0 or 1. rfbi_da[n:0], n up to 15 For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual. Figure 5-96. DSS--RFBI Mode--MIPI DBI 2.0--LCD Panel--Command / Data Read 212 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 WECycleTime ReCycleTime AccessTime WECycleTime rfbi_a0 CsOffTime CsOffTime CsOnTime rfbi_csx CsOffTime CsOnTime CsOnTime (A) WEOffTime WEOffTime WEOnTime WEOnTime rfbi_wr ReOffTime ReOnTime rfbi_rd CsPulseWidth rfbi_da[n:0] (B) WRITE CsPulseWidth WRITE READ rfbi_te_vsync[1:0] rfbi_hsync[1:0] A. B. C. In rfbi_csx, x is equal to 0 or 1. rfbi_da[n:0], n up to 15 For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual. Figure 5-97. DSS--RFBI Mode--MIPI DBI 2.0--LCD Panel--Command / Data Write to Read and Read to Write Modes 5.13.9.1.2.2 DSS--Parallel Interface--RFBI Mode--Pico DLP The Remote Frame Buffer Interface (RFBI) module can provide also the necessary control signals and data to interface to the Pico DLP driver of the Pico DLP panel. Table 5-78 assumes testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-98). Table 5-78. DSS Timing Conditions--RFBI Mode--Pico DLP VALUE TIMING CONDITION PARAMETER MIN UNIT MAX Output Condition CLOAD Output load capacitance 5 pF To use Pico DLP application, RFBI register must be configured as shown in Table 5-79: Table 5-79. DSS Register Configuration--RFBI Mode--Pico DLP REGISTER AND BIT FIELD(1) DESCRIPTION BIT VALUES Selection parallel mode RFBI_CONFIGi and ParallelMode [1:0] 0b11: 16-bit parallel output interface selected Time Granularity (multiplies signal timing latencies by 2). RFBI_CONFIGi andTimeGranularity [4] CS signal assertion time from Start Access Time RFBI_ONOFF_TIMEi and CSOnTime [3:0] 0b0000 CS signal deassertion time from Start Access Time RFBI_ONOFF_TIMEi and CSOffTime [9:4] 0b000100: 4 cycles WE signal assertion time from Start Access Time RFBI_ONOFF_TIMEi and WEOnTime [13:10] 0b0000 WE signal deassertion time from Start Access Time RFBI_ONOFF_TIMEi and WEOffTime [19:14] 0b000010: 2 cycles RE signal assertion time from Start Access Time RFBI_ONOFF_TIMEi and REOnTime [23:20] 0b0000 0b0: x2 latency disable Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 213 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-79. DSS Register Configuration--RFBI Mode--Pico DLP (continued) REGISTER AND BIT FIELD(1) DESCRIPTION BIT VALUES RE signal deassertion time from Start Access Time RFBI_ONOFF_TIMEi and REOffTime [29:24] 0b0000 Write cycle time RFBI_CYCLE_TIMEi and WECycleTime [5:0] 0b000100: 4 cycles Read cycle time RFBI_CYCLE_TIMEi and ReCycleTime [11:6] 0b000000 CS pulse width RFBI_CYCLE_TIMEi and CSPulseWidth [17:12] 0b000000 Read to Write CS pulse width enable RFBI_CYCLE_TIMEi and RWEnable [18] 0b0 Read to Read CS pulse width enable RFBI_CYCLE_TIMEi and RREnable [19] 0b0 Write to Write CS pulse width enable RFBI_CYCLE_TIMEi and WWEnable [20] 0b0 Write to Read CS pulse width enable RFBI_CYCLE_TIMEi and WREnable [21] 0b0 From Start Access Time to CLK rising edge used for the first data capture RFBI_CYCLE_TIMEi and AccessTime [27:22] 0b000000 (1) i is equal to 0 or 1. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual. 214 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-80. DSS Switching Characteristics--RFBI Mode--Pico DLP(1)(2)(3) OPP100 PARAMETER MIN OPP50 MAX MIN MAX UNIT tw(wrH) Pulse duration, output write enable rfbi_wr high A(4) A(4) ns tw(wrL) Pulse duration, output write enable rfbi_wr low B(5) B(5) ns (6) (6) ns td(a0-wrL) Delay time, output command/data control rfbi_a0 transition to output write enable rfbi_wr low C C td(wrH-a0) Delay time, output write enable rfbi_wr high to output command/data control rfbi_a0 transition D(7) D(7) ns td(csx-wrL) Delay time, output chip select rfbi_csx(8) low to output write enable rfbi_wr low E(9) E(9) ns td(wrH-csxH) Delay time, output write enable rfbi_wr high to output chip select rfbi_csx(8) high F(10) F(10) ns td(dataV) Output data rfbi_da[15:0](11) valid G(12) G(12) ns td(Skew) Skew between output write enable falling rfbi_wr and output data rfbi_da[15:0](11) high or low 15.5 15.5 ns td(a0H-rdL) Delay time, output command/data control rfbi_a0 high to output read enable rfbi_rd low H(13) H(13) ns td(rdlH-a0) Delay time, output read enable rfbi_rd high to output command/data control rfbi_a0 transition I(14) I(14) ns tw(rdH) Pulse duration, output read enable rfbi_rd high J(15) J(15) ns (16) K(16) ns tw(rdL) Pulse duration, output read enable rfbi_rd low K td(rdL-csxL) Delay time, output read enable rfbi_rd low to output chip select rfbi_csx(8) low L(17) L(17) ns td(rdL-csxH) Delay time, output read enable rfbi_rd low to output chip select rfbi_csx(8) high M(18) M(18) ns tR(wr) Rise time, output write enable rfbi_wr 7 7 ns tF(wr) Fall time, output write enable rfbi_wr 7 7 ns tR(a0) Rise time, output command/data control rfbi_a0 7 7 ns tF(a0) Fall time, output command/data control rfbi_a0 7 7 ns (8) tR(csx) Rise time, output chip select rfbi_csx 7 7 ns tF(csx) Fall time, output chip select rfbi_csx(8) 7 7 ns tR(d) Rise time, output data rfbi_da[15:0](11) 7 7 ns (11) tF(d) Fall time, output data rfbi_da[15:0] 7 7 ns tR(rd) Rise time, output read enable rfbi_rd 7 7 ns tF(rd) Fall time, output read enable rfbi_rd 7 7 ns (19) CsOnTime CS signal assertion time from Start Access Time - RFBI_ONOFF_TIMEi Register 0 CsOffTime CS signal deassertion time from Start Access Time - RFBI_ONOFF_TIMEi Register 40(19) ns WeOnTime WE signal assertion time from Start Access Time - RFBI_ONOFF_TIMEi Register 0(19) ns WeOffTime WE signal deassertion time from Start Access Time - RFBI_ONOFF_TIMEi Register 20(19) ns ReOnTime RE signal assertion time from Start Access Time - RFBI_ONOFF_TIMEi Register - ns ReOffTime RE signal deassertion time from Start Access Time - RFBI_ONOFF_TIMEi Register - ns WeCycleTime Write cycle time - RFBI_CYCLE_TIMEi Register 40(19) ns ReCycleTime Read cycle time - RFBI_CYCLE_TIMEi Register - ns CsPulseWidth CS pulse width - RFBI_CYCLE_TIMEi Register 0(19) ns Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 ns Specifications 215 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com (1) See DM Operating Condition Addendum for OPP voltages. (2) At OPP100, L4 clock is 100 MHz and at OPP50, L4 clock is 50 MHz. (3) rfbi_wr must be at 25 MHz. (4) A = (WECycleTime - WEOffTime) x (TimeParaGranularity + 1) x L4CLK (5) B = (WEOffTime - WEOntime) x (TimeParaGranularity + 1) x L4CLK (6) C = WEOnTime x (TimeParaGranularity + 1) x L4CLK (7) D = (WECycleTime + CSPulseWidth - WEOffTime) x (TimeParaGranularity + 1) x L4CLK if mode Write to Read or Read to Write is enabled. (8) In rfbi_csx, x is equal to 0 or 1. (9) E = (WEOnTime - CSOnTime) x (TimeParaGranularity + 1) x L4CLK (10) F = (CSOffTime - WEOffTime) x (TimeParaGranularity + 1) x L4CLK (11) 16-bit parallel output interface is selected in DSS register. (12) G = WECycleTime x (TimeParaGranularity + 1) x L4CLK (13) H = REOnTime x (TimeParaGranularity + 1) x L4CLK (14) I = (RECycleTime + CSPulseWidth - REOffTime) x (TimeParaGranularity + 1) x L4CLK if mode Write to Read or Read to Write is enabled. (15) J = (RECycleTime - REOffTime) x (TimeParaGranularity + 1) x L4CLK (16) K = (REOffTime - REOntime) x (TimeParaGranularity + 1) x L4CLK (17) L = (REOnTime - CSOnTime) x (TimeParaGranularity + 1) x L4CLK (18) M = (CSOffTime - REOffTime) x (TimeParaGranularity + 1) x L4CLK (19) These values are calculated by the following formula: RFBI Register (Value) x L4 Clock (ns). CsPulseWidth WeCycleTime WeCycleTime rfbi_a0 CsOffTime CsOnTime rfbi_csx CsOffTime CsOnTime (A) WeOffTime WeOffTime WeOnTime WeOnTime rfbi_wr DATA0 (B) rfbi_da[n:0] rfbi_rd DATA1 rfbi_te_vsync[1:0] rfbi_hsync[1:0] A. B. In rfbi_csx, x is equal to 0 or 1. rfbi_da[n:0], n up to 15 Figure 5-98. DSS--RFBI Mode--Pico DLP--Command / Data Write 216 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.10 Camera (VPFE) The camera (VPFE) controller receives input video/image data from external capture devices and stores it to external memory which is transferred into the external memory via a built-in DMA engine. An internal buffer block provides a high bandwidth path between the module and the external memory. The Cortex-A9 will process the image data based on application requirements. 5.13.10.1 Camera (VPFE) Timing The following tables assume testing over recommended operating conditions. Table 5-81. VPFE Timing Requirements 1.8 V, 3.3 V NO. OPP50 MIN OPP100 MAX MIN UNIT MAX VF1 tc(CAMx_CLK) Cycle time, pixel clock input, CAMx_CLK 20 13.3 ns VF2 tsu(CAMx_D- Setup time, CAMx_D to CAMx_CLK rising edge 7.5 3.5 ns Setup time, CAMx_HD to CAMx_CLK rising edge 7.5 3.5 ns Setup time, CAMx_VD to CAMx_CLK rising edge 7.5 3.5 ns Setup time, CAMx_WEN to CAMx_CLK rising edge 7.5 3.5 ns CAMx_CLK) VF3 tsu(CAMx_HDCAMx_CLK) VF4 tsu(CAMx_VDCAMx_CLK) VF5 tsu(CAMx_WENCAMx_CLK) VF6 tsu(C_FLD-CAMx_CLK) Setup time, CAMx_FIELD to CAMx_CLK rising edge 7.5 3.5 ns VF7 th(CAMx_CLK- Hold time, CAMx_D valid after CAMx_CLK rising edge 6.5 2.5 ns Hold time, CAMx_HD to CAMx_CLK rising edge 6.5 2.5 ns Hold time, CAMx_VD to CAMx_CLK rising edge 6.5 2.5 ns Hold time, CAMx_WEN to CAMx_CLK rising edge 6.5 2.5 ns Hold time, CAMx_FIELD to CAMx_CLK rising edge 6.5 2.5 ns CAMx_D) VF8 th(VDIN-HDCAMx_CLK) VF9 th(CAMx_VDCAMx_CLK) VF10 th(CAMx_WENCAMx_CLK) VF11 th(C_FLD-CAMx_CLK) Table 5-82. VPFE Output Switching Characteristics 1.8 V, 3.3 V NO. PARAMETER OPP50 MIN VF12 td(CAMx_HD- OPP100 MAX MIN UNIT MAX Output delay time, CAMx_HD to CLK rising edge 9 15 2 9 ns Output delay time, CAMx_VD to CLK rising edge 9 15 2 9 ns Output delay time, CAMx_WEN to CLK rising edge 9 15 2 9 ns CAMx_CLK) VF13 td(CAMx_VDCAMx_CLK) VF14 td(CAMx_WENCAMx_CLK) Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 217 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com VF1 CAMx_CLK (Falling Edge) CAMx_CLK (Rising Edge) VF7 VF2 VF7 CAMx_D[xx] CAMx_HD, CAMx_VD, CAMx_FIELD VF8, VF9, VF11 VF3, VF4, VF6 VF10 VF5 CAMx_WEN Figure 5-99. Camera Input Timings CAMx_CLK (Falling Edge) CAMx_CLK (Rising Edge) VF15, VF16, VF17 VF12, VF13, VF14 CAMx_HD, CAMx_VD, CAMx_FIELD VF15, VF16, VF17 VF12, VF13, VF14 Figure 5-100. Camera Output Timings VF18 CAMx_HD (Falling Edge) CAMx_HD (Rising Edge) VF19 VF20 CAMx_D[xx] Figure 5-101. Camera Input Timings With VDIN0_HD as Pixel Clock 218 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.11 Inter-Integrated Circuit (I2C) For more information, see the Inter-Integrated Circuit (I2C) section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual. 5.13.11.1 I2C Electrical Data and Timing Table 5-83. I2C Timing Conditions - Slave Mode TIMING CONDITION PARAMETER STANDARD MODE MIN MAX FAST MODE MIN MAX UNIT Output Condition Cb Capacitive load for each bus line 400 400 pF Table 5-84. Timing Requirements for I2C Input Timings (see Figure 5-102) STANDARD MODE NO. MIN MAX FAST MODE MIN MAX UNIT 1 tc(SCL) Cycle time, SCL 10 2.5 us 2 tsu(SCLH-SDAL) Setup Time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 us 3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 us 4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 us 5 tw(SCLH) Pulse duration, SCL high 4 0.6 us 6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100(1) 7 (2) 3.45 (3) 0 (2) ns (3) th(SCLL-SDAV) Hold time, SDA valid after SCL low 0 8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 0.9 4.7 9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb(4) 300 ns 10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb(4) 300 ns 11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb(4) 300 ns 12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb(4) 300 ns 13 tsu(SCLH-SDAH) Setup time, high before SDA high (for STOP condition) 4 14 tw(SP) Pulse duration, spike (must be suppressed) 0 1.3 us 0.6 50 0 us us 50 ns (1) A fast-mode I2C-busTM device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-Bus Specification) before the SCL line is released. (2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (4) Cb is line load in pF. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 219 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 9 11 I2C[x]_SDA 6 8 14 4 13 5 10 I2C[x]_SCL 1 12 3 7 2 3 Stop Start Repeated Start Stop Figure 5-102. I2C Receive Timing Table 5-85. Switching Characteristics for I2C Output Timings (see Figure 5-120) NO. 15 STANDARD MODE PARAMETER MIN MAX FAST MODE MIN MAX UNIT tc(SCL) Cycle time, SCL 10 2.5 us 16 tsu(SCLH-SDAL) Setup Time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 us 17 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 us 18 tw(SCLL) Pulse duration, SCL low 4.7 1.3 us 19 tw(SCLH) Pulse duration, SCL high 4 0.6 us 20 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 21 th(SCLL-SDAV) Hold time, SDA valid after SCL low 22 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 23 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb(1) 300 ns 24 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb(1) 300 ns 25 tf(SDA) Fall time, SDA 300 20 + 0.1Cb(1) 300 ns 300 (1) 300 ns 250 100 0 3.45 4.7 26 tf(SCL) Fall time, SCL 27 tsu(SCLH-SDAH) Setup time, high before SDA high (for STOP condition) ns 0 0.9 1.3 4 20 + 0.1Cb us us 0.6 us (1) Cb is line load in pF. 24 26 I2C[x]_SDA 21 23 19 28 20 25 I2C[x]_SCL 27 16 18 22 17 18 Stop Start Repeated Start Stop Figure 5-103. I2C Transmit Timing 220 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.12 Multichannel Audio Serial Port (McASP) The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission (DIT). 5.13.12.1 McASP Device-Specific Information The device includes two multichannel audio serial port (McASP) interface peripherals (McASP0 and McASP1). The McASP module consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or, alternatively, the transmit and receive sections may be synchronized. The McASP module also includes shift registers that may be configured to operate as either transmit data or receive data. The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a DIT format where the bit stream is encoded for SPDIF, AES-3, IEC60958, CP-430 transmission. The receive section of the McASP peripheral supports the TDM synchronous serial format. The McASP module can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format; however, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode, which is useful for nonaudio data (for example, passing control information between two devices). The McASP peripheral has additional capability for flexible clock generation and error detection/handling, as well as error management. The device McASP0 and McASP1 modules have up to four serial data pins each. The McASP FIFO size is 256 bytes and two DMA and two interrupt requests are supported. Buffers are used transparently to better manage DMA, which can be leveraged to manage data flow more efficiently. For more detailed information on and the functionality of the McASP peripheral, see the Multichannel Audio Serial Port (McASP) section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 221 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.12.2 McASP Electrical Data and Timing Table 5-86. McASP Timing Conditions TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tR Input signal rise time tF Input signal fall time 1(1) 4(1) ns (1) 4(1) ns 15 30 pF 1 Output Condition CLOAD Output load capacitance (1) Except when specified otherwise. Table 5-87. Timing Requirements for McASP(1) (see Figure 5-104) OPP100 NO. MIN 1 tc(AHCLKRX) Cycle time, McASP[x]_AHCLKR and McASP[x]_AHCLKX 2 tw(AHCLKRX) Pulse duration, McASP[x]_AHCLKR and McASP[x]_AHCLKX high or low 3 tc(ACLKRX) Cycle time, McASP[x]_ACLKR and McASP[x]_ACLKX 4 tw(ACLKRX) Pulse duration, McASP[x]_ACLKR and McASP[x]_ACLKX high or low 5 tsu(AFSRXACLKRX) 6 th(ACLKRXAFSRX) Setup time, McASP[x]_AFSR and McASP[x]_AFSX input valid before McASP[x]_ACLKR and McASP[x]_ACLKX Hold time, McASP[x]_AFSR and McASP[x]_AFSX input valid after McASP[x]_ACLKR and McASP[x]_ACLKX 7 tsu(AXR-ACLKRX) th(ACLKRX-AXR) Hold time, McASP[x]_AXR input valid after McASP[x]_ACLKR and McASP[x]_ACLKX MIN MAX UNIT 38.46 ns 0.5P - 2.5(2) 0.5P - 2.5(2) ns 20 38.46 ns 0.5R - 2.5(3) 0.5R - 2.5(3) ns 12.3 15.5 ACLKR and ACLKX ext in 4 6 ACLKR and ACLKX ext out 4 6 -1 -1 ACLKR and ACLKX ext in 1.6 2.3 ACLKR and ACLKX ext out 1.6 2.3 12.3 15.5 ACLKR and ACLKX ext in 4 6 ACLKR and ACLKX ext out 4 6 -1 -1 ACLKR and ACLKX ext in 1.6 2.3 ACLKR and ACLKX ext out 1.6 2.3 ACLKR and ACLKX int ACLKR and ACLKX int ACLKR and ACLKX int 8 MAX 20 ACLKR and ACLKX int Setup time, McASP[x]_AXR input valid before McASP[x]_ACLKR and McASP[x]_ACLKX OPP50 ns ns ns ns (1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 (2) P = McASP[x]_AHCLKR and McASP[x]_AHCLKX period in nano seconds (ns). (3) R = McASP[x]_ACLKR and McASP[x]_ACLKX period in ns. 222 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 2 1 2 McASP[x]_ACLKR/X (Falling Edge Polarity) McASP[x]_AHCLKR/X (Rising Edge Polarity) 4 4 3 McASP[x]_ACLKR/X (CLKRP = CLKXP = 0) McASP[x]_ACLKR/X (CLKRP = CLKXP = 1) (A) (B) 6 5 McASP[x]_AFSR/X (Bit Width, 0 Bit Delay) McASP[x]_AFSR/X (Bit Width, 1 Bit Delay) McASP[x]_AFSR/X (Bit Width, 2 Bit Delay) McASP[x]_AFSR/X (Slot Width, 0 Bit Delay) McASP[x]_AFSR/X (Slot Width, 1 Bit Delay) McASP[x]_AFSR/X (Slot Width, 2 Bit Delay) 8 7 McASP[x]_AXR[x] (Data In/Receive) A. B. For CLKRP = CLKXP = receiver is configured for For CLKRP = CLKXP = receiver is configured for A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP falling edge (to shift data in). 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP rising edge (to shift data in). C31 Figure 5-104. McASP Input Timing Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 223 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-88. Switching Characteristics for McASP(1) (see Figure 5-105) OPP100 NO. MIN 9 tc(AHCLKRX) Cycle time, McASP[x]_AHCLKR and McASP[x]_AHCLKX 10 tw(AHCLKRX) Pulse duration, McASP[x]_AHCLKR and McASP[x]_AHCLKX high or low 11 tc(ACLKRX) Cycle time, McASP[x]_ACLKR and McASP[x]_ACLKX 12 tw(ACLKRX) Pulse duration, McASP[x]_ACLKR and McASP[x]_ACLKX high or low Delay time, McASP[x]_ACLKR and McASP[x]_ACLKX transmit edge to McASP[x]_AFSR and McASP[x]_AFSX output valid 13 14 td(ACLKRX-AFSRX) td(ACLKX-AXR) Delay time, McASP[x]_ACLKR and McASP[x]_ACLKX transmit edge to McASP[x]_AFSR and McASP[x]_AFSX output valid with Pad Loopback Delay time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output valid Delay time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output valid with Pad Loopback Disable time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output high impedance 15 tdis(ACLKX-AXR) Disable time, McASP[x]_ACLKX transmit edge to McASP[x]_AXR output high impedance with Pad Loopback OPP50 MAX MIN MAX UNIT 20(2) 38.46 ns 0.5P - 2.5(3) 0.5P - 2.5(3) ns 20 38.46 ns 0.5P - 2.5(3) 0.5P - 2.5(3) ns ACLKR and ACLKX int 0 7.25 0 8.5 ACLKR and ACLKX ext in 2 14 2.7 18 ns ACLKR and ACLKX ext out 2 14 2.7 18 ACLKX int 0 7.25 0 8.5 ACLKX ext in 2 14 2.7 18 ns ACLKX ext out 2 14 2.7 18 ACLKX int 0 7.25 0 8.5 ACLKX ext in 2 14 2.7 18 ns ACLKX ext out 2 14 2.7 18 (1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1 ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 (2) 50 MHz (3) P = AHCLKR and AHCLKX period. 224 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 10 10 9 McASP[x]_ACLKR/X (Falling Edge Polarity) McASP[x]_AHCLKR/X (Rising Edge Polarity) 12 11 McASP[x]_ACLKR/X (CLKRP = CLKXP = 1) McASP[x]_ACLKR/X (CLKRP = CLKXP = 0) 12 (A) (B) 13 13 13 13 McASP[x]_AFSR/X (Bit Width, 0 Bit Delay) McASP[x]_AFSR/X (Bit Width, 1 Bit Delay) McASP[x]_AFSR/X (Bit Width, 2 Bit Delay) McASP[x]_AFSR/X (Slot Width, 0 Bit Delay) 13 13 13 McASP[x]_AFSR/X (Slot Width, 1 Bit Delay) McASP[x]_AFSR/X (Slot Width, 2 Bit Delay) McASP[x]_AXR[x] (Data Out/Transmit) 14 15 A0 A. B. For CLKRP = CLKXP = receiver is configured for For CLKRP = CLKXP = receiver is configured for A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP rising edge (to shift data in). 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP falling edge (to shift data in). Figure 5-105. McASP Output Timing Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 225 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.13 Multichannel Serial Port Interface (McSPI) For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual. 5.13.13.1 McSPI Electrical Data and Timing The following timings are applicable to the different configurations of McSPI in master or slave mode for any McSPI and any channel (n). 5.13.13.1.1 McSPI--Slave Mode Table 5-89. McSPI Timing Conditions--Slave Mode TIMING CONDITION PARAMETER MIN MAX UNIT Input Conditions tr Input signal rise time 5 ns tf Input signal fall time 5 ns 20 pF Output Condition Cload Output load capacitance Table 5-90. Timing Requirements for McSPI Input Timings--Slave Mode (see Figure 5-106) OPP100 NO. MIN 1 tc(SPICLK) Cycle time, SPI_CLK 2 tw(SPICLKL) Typical Pulse duration, SPI_CLK low 3 OPP50 MIN 0.45P(1) 0.45P(1) 0.45P(1) 0.45P(1) ns (1) (1) (1) (1) ns 62.5 0.45P MAX UNIT MAX 83.2 0.45P 0.45P ns tw(SPICLKH) Typical Pulse duration, SPI_CLK high 4 tsu(SIMO-SPICLK) Setup time, SPI_D[x] (SIMO) valid before SPI_CLK active edge(2)(3) 0.45P 12 13 ns 5 th(SPICLK-SIMO) Hold time, SPI_D[x] (SIMO) valid after SPI_CLK active edge(2)(3) 12 13 ns 8 tsu(CS-SPICLK) Setup time, SPI_CS valid before SPI_CLK first edge(2) 12 13 ns 9 th(SPICLK-CS) Hold time, SPI_CS valid after SPI_CLK last edge(2) 12 13 ns (1) P = SPI_CLK period. (2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and capture input data. (3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. Table 5-91. Switching Characteristics for McSPI Output Timings--Slave Mode (see Figure 5-107) NO. PARAMETER OPP100 MIN OPP50 UNIT MAX MIN MAX 0 19 ns 29 ns 6 td(SPICLK-SOMI) Delay time, SPI_CLK active edge to SPI_D[x] (SOMI) transition(1)(2) 17 7 td(CS-SOMI) Delay time, SPI_CS active edge to SPI_D[x] (SOMI) transition(2) 26 (1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and capture input data. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. 226 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 PHA=0 EPOL=1 SPI_CS[x] (In) 1 3 8 SPI_SCLK (In) 2 9 POL=0 1 3 2 POL=1 SPI_SCLK (In) 4 4 5 SPI_D[x] (SIMO, In) 5 Bit n-1 Bit n-3 Bit n-2 Bit 0 Bit n-4 PHA=1 EPOL=1 SPI_CS[x] (In) 1 3 8 SPI_SCLK (In) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (In) 4 5 SPI_D[x] (SIMO, In) Bit n-1 4 5 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure 5-106. SPI Slave Mode Receive Timing Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 227 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com PHA=0 EPOL=1 SPI_CS[x] (In) 1 3 8 SPI_SCLK (In) 2 9 POL=0 1 3 2 POL=1 SPI_SCLK (In) SPI_D[x] (SOMI, Out) 6 7 6 Bit n-1 Bit n-2 Bit n-3 Bit 0 Bit n-4 PHA=1 EPOL=1 SPI_CS[x] (In) 1 3 8 SPI_SCLK (In) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (In) 6 SPI_D[x] (SOMI, Out) Bit n-1 6 6 Bit n-2 Bit n-3 6 Bit 1 Bit 0 Figure 5-107. SPI Slave Mode Transmit Timing 228 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.13.1.2 McSPI--Master Mode Table 5-92. McSPI Timing Conditions--Master Mode LOW LOAD TIMING CONDITION PARAMETER MIN HIGH LOAD MAX MIN UNIT MAX Input Conditions tr Input signal rise time 4 8 ns tf Input signal fall time 4 8 ns 5 25 pF Output Condition Cload Output load capacitance Table 5-93. Timing Requirements for McSPI Input Timings--Master Mode (see Figure 5-108) OPP100 NO. LOW LOAD MIN OPP50 HIGH LOAD MAX MIN MAX LOW LOAD MIN MAX HIGH LOAD MIN UNIT MAX 4 tsu(SOMI-SPICLK)(1) Setup time, SPI_D[x] (SOMI) valid before SPI_CLK active edge(2) 3 4.5 4.5 4.5 ns 5 th(SPICLK-SOMI)(1) Hold time, SPI_D[x] (SOMI) valid after SPI_CLK active edge(2) 6 6 6 6 ns (1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to capture input data. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. Table 5-94. Switching Characteristics for McSPI Output Timings--Master Mode (see Figure 5-109) OPP100 NO. PARAMETER LOW LOAD MIN 1 2 3 6 8 9 MAX MAX Cycle time, SPI_CLK tw(SPICLKL) Typical Pulse duration, SPI_CLK low 0.45P tw(SPICLKH) Typical Pulse duration, SPI_CLK high 0.45P(1) tr(SPICLK) Rising time, SPI_CLK 3.5 3.5 tf(SPICLK) Falling time, SPI_CLK 3.5 3.5 td(SPICLK- 20.8 MIN LOW LOAD tc(SPICLK) SIMO) 7 OPP50 HIGH LOAD Delay time, SPI_CLK active edge to SPI_D[x] (SIMO) transition(2) td(CS-SIMO) Delay time, SPI_CS active edge to SPI_D[x] (SIMO) transition(2) td(CS-SPICLK) Delay time, SPI_CS active to SPI_CLK first edge td(SPICLK-CS) Delay time, SPI_CLK last edge to SPI_CS inactive (1) 41.6 0.45P (1) 0.45P(1) -1 4.5 0.45P (1) 0.45P(1) -1 4.5 MIN HIGH LOAD MAX 41.6 0.55P (1) 0.55P(1) 6.5 0.45P (1) 0.45P(1) MIN UNIT MAX 41.6 ns 0.45P(1) ns 3.5 3.82 ns 3.5 3.44 ns 6.5 ns 6.5 ns 0.45P(1) 0 6.5 6.5 0.45P (1) ns (1) 0.45P (1) 0.45P(1) 0 6.5 0.45P Mode 1 and 3(3) A - 4.2(4) A - 4.2(4) A - 5.2(4) A - 5.2(4) ns Mode 0 and 2(3) B - 4.2(5) B - 4.2(5) B - 5.2(5) B - 5.2(5) ns Mode 1 and 3(3) B - 4.2(5) B - 4.2(5) B - 5.2(5) B - 5.2(5) ns Mode 0 and 2(3) A - 4.2(4) A - 4.2(4) A - 5.2(4) A - 5.2(4) ns (1) P = SPI_CLK period. (2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI. (3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable: - SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3). - SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2). Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 229 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com (4) Case P = 20.8 ns, A = (TCS+1)*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register). Case P > 20.8 ns, A = (TCS+0.5)*Fratio*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register). Note: P = SPI_CLK clock period. (5) B = (TCS+0.5)*TSPICLKREF*Fratio (TCS is a bit field of MCSPI_CH(i)CONF register, Fratio: Even2). PHA=0 EPOL=1 SPI_CS[x] (Out) 1 3 8 SPI_SCLK (Out) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (Out) 4 4 5 SPI_D[x] (SOMI, In) 5 Bit n-1 Bit n-3 Bit n-2 Bit 0 Bit n-4 PHA=1 EPOL=1 SPI_CS[x] (Out) 1 3 8 SPI_SCLK (Out) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (Out) 4 5 SPI_D[x] (SOMI, In) Bit n-1 4 5 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure 5-108. SPI Master Mode Receive Timing 230 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 PHA=0 EPOL=1 SPI_CS[x] (Out) 1 3 8 SPI_SCLK (Out) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (Out) 6 7 SPI_D[x] (SIMO, Out) Bit n-1 6 Bit n-3 Bit n-2 Bit 0 Bit n-4 PHA=1 EPOL=1 SPI_CS[x] (Out) 1 3 8 SPI_SCLK (Out) 9 2 POL=0 1 2 3 POL=1 SPI_SCLK (Out) 6 SPI_D[x] (SIMO, Out) Bit n-1 6 Bit n-2 6 Bit n-3 6 Bit 1 Bit 0 Figure 5-109. SPI Master Mode Transmit Timing Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 231 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.14 Quad Serial Port Interface (QSPI) The Quad SPI (QSPI) module allows single, dual or quad read access to external SPI devices. This module provides a memory mapped register interface, which provides a direct interface to access data from external SPI devices and to simplify software requirements. It functions as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories. General SPI features: * Programmable clock divider * Six pin interface (QSPI_CLK, QSPI_D0, QSPI_D1,QSPI_D2,QSPI_D3, QSPI_CS0) * One external chip select signal * Support for 3-, 4- or 6-pin SPI interface * Programmable CS0 to DATA_OUT delay from 0 to 3 QSPI_CLKs * Only supports SPI MODE 3 NOTE For more information, see the Quad Serial Port Interface section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual. Table 5-95 displays the switching characteristics for the Quad SPI module. Table 5-95. QSPI Switching Characteristics (see Figure 5-110 and Figure 5-111) NO. OPP100 PARAMETER MIN OPP50 MAX MIN (1) UNIT ns 1 tc(QSPI_CLK) Cycle time, QSPI_CLK 20.8 2 tw(QSPI_CLKL) Pulse duration, QSPI_CLK low 9.77 (1) 9.77 (1) ns 3 tw(QSPI_CLKH) Pulse duration, QSPI_CLK high 9.77 (1) 9.77 (1) ns 4 td(CS-QSPI_CLK) Delay time, QSPI_CSn active edge to QSPI_CLK transition M*P+5 (2) (3) M*P+5 (2) (3) ns 5 td(QSPI_CLK- M*P+5 (2) (3) M*P+5 (2) (3) ns QSPI_CSn) Delay time, QSPI_CLK transition to QSPI_CSn inactive edge 6 td(QSPI_CLK-D1) Delay time, QSPI_CLK active edge to QSPI_D[0] transition 7 tsu(D-QSPI_CLK) Setup time, QSPI_D[3:0] valid before active QSPI_CLK edge 8 th(QSPI_CLK-D) (1) (2) (3) 20.8 MAX (1) 0 Hold time, QSPI_D[3:0] valid after active QSPI_CLK edge 5.5 0 5.5 ns 8.5 8.5 ns 0 0 ns Maximum supported frequency is 48 MHz. P = QSPI_CLK period. M = Programmable via Data Delay Zero (DD0) register. QSPI_CSn 5 1 4 3 2 QSPI_CLK 6 min QSPI_D[3:0] 6 Command n-1 7 max Command n-2 8 Read Data 1 7 8 Read Data 0 Figure 5-110. QSPI Read Active High Polarity 232 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 QSPI_CS 5 1 4 3 2 QSPI_CLK 6 QSPI_D[0] min 6 Command n-1 max 6 Command n-2 min 6 max Write Data 1 Write Data 0 QSPI_D[3:1] Figure 5-111. QSPI Write Active High Polarity Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 233 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.15 HDQ/1-Wire Interface (HDQ/1-Wire) NOTE For more information, see HDQ/1-Wire Interface chapter of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual. The module is intended to work with both HDQ and 1-Wire protocols. The protocols use one wire to communicate between the master and the slave. The protocols employ an asynchronous return to one mechanism where, after any command, the line is pulled high. 5.13.15.1 HDQ Protocol Table 5-96 and Table 5-97 assume testing over the recommended operating conditions (see Figure 5-112, Figure 5-113, Figure 5-114, and Figure 5-115). Table 5-96. HDQ Timing Requirements PARAMETER MIN MAX UNIT tCYCD Bit window 190 tHW1 Reads 1 32 66 s tHW0 Reads 0 70 145 s tRSPS Command to host respond time(1) 190 320 s MAX UNIT s (1) Defined by software Table 5-97. HDQ Switching Characteristics PARAMETER DESCRIPTION MIN tB Break timing 190 tBR Break recovery 40 tCYCH Bit window 190 tDW1 Sends 1 (write) tDW0 Sends 0 (write) s s 250 s 0.5 50 s 86 145 s tB tBR HDQ Figure 5-112. HDQ Break (Reset) Timing tCYCH tHW0 tHW1 HDQ Figure 5-113. HDQ Read Bit Timing (Data) tCYCD tDW0 tDW1 HDQ Figure 5-114. HDQ Write Bit Timing (Command/Address or Data) 234 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Command_byte_written Data_byte_received 0_(LSB) Break tRSPS 1 7_(MSB) 6 1 0_(LSB) 6 HDQ Figure 5-115. HDQ Communication Timing 5.13.15.2 1-Wire Protocol Table 5-98 and Table 5-99 assume testing over the recommended operating conditions (see Figure 5-116, Figure 5-117, and Figure 5-118). Table 5-98. HDQ/1-Wire Timing Requirements--1-Wire Mode PARAMETER MIN MAX UNIT tPDH Presence pulse delay high 15 60 s tPDL Presence pulse delay low 60 240 s tRDV + tREL Read bit-zero time 60 s Table 5-99. HDQ/1-Wire Switching Characteristics--1-Wire Mode PARAMETER MIN MAX UNIT tRSTL Reset time low DESCRIPTION 480 960 s tRSTH Reset time high 480 tSLOT Bit cycle time 60 120 s tLOW1 Write bit-one time 1 15 s tLOW0 Write bit-zero time 60 120 s tREC Recovery time 1 tLOWR Read bit strobe time 1 s s 15 s tRSTH 1-WIRE tRTSL tPDH tPDL Figure 5-116. 1-Wire Break (Reset) Timing tSLOT_and_tREC tRDV_and_tREL 1-WIRE tLOWR Figure 5-117. 1-Wire Read Bit Timing (Data) tSLOT_and_tREC tLOW0 1-WIRE tLOW1 Figure 5-118. 1-Wire Write Bit Timing (Command/Address or Data) Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 235 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.16 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) For more information, see the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem Interface (PRU-ICSS) section of the AM437x Sitara Processors Technical Reference Manual. 5.13.16.1 Programmable Real-Time Unit (PRU-ICSS PRU) Table 5-100. PRU-ICSS PRU Timing Conditions TIMING CONDITION PARAMETER MIN MAX UNIT 3 30 pF MAX UNIT Output Condition Cload Capacitive load for each bus line 5.13.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing Table 5-101. PRU-ICSS PRU Timing Requirements - Direct Input Mode (see Figure 5-119) NO. 1 2 3 (1) (2) MIN 2*P (1) tw(GPI) Pulse width, GPI tr(GPI) Rise time, GPI 1.00 3.00 ns tf(GPI) Fall time, GPI 1.00 3.00 tsk(GPI) Internal skew between GPI[n:0] signals (2) ns 5.00 ns MAX UNIT P = L3_CLK (PRU-ICSS ocp clock) period. n = 16, 11 for PRU-ICSS1 and 19 for PRU-ICSS0 1 2 GPI[m:0] 3 Figure 5-119. PRU-ICSS PRU Direct Input Timing Table 5-102. PRU-ICSS PRU Switching Requirements - Direct Output Mode (see Figure 5-120) NO. 1 2 3 (1) (2) MIN 2*P (1) tw(GPO) Pulse width, GPO tr(GPO) Rise time, GPO 1.00 3.00 ns tf(GPO) Fall time, GPO 1.00 3.00 tsk(GPO) Internal skew between GPO[n:0] signals (2) 5.00 ns ns P = L3_CLK (PRU-ICSS ocp clock) period. n = 11 for PRU-ICSS1 and 19 for PRU-ICSS0 1 2 GPO[n:0] 3 Figure 5-120. PRU-ICSS PRU Direct Output Timing 236 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing Table 5-103. PRU-ICSS PRU Timing Requirements - Parallel Capture Mode (see Figure 5-121 and Figure 5-122) NO. MIN MAX UNIT 1 tc(CLOCKIN) Cycle time, CLOCKIN 20.00 ns 2 tw(CLOCKIN_L) Pulse duration, CLOCKIN low 10.00 ns 3 tw(CLOCKIN_H) Pulse duration, CLOCKIN high 10.00 ns 4 tr(CLOCKIN) Rising time, CLOCKIN 1.00 3.00 ns 5 tf(CLOCKIN) Falling time, CLOCKIN 1.00 3.00 ns 6 tsu(DATAIN-CLOCKIN) Setup time, DATAIN valid before CLOCKIN 4.00 ns 7 th(CLOCKIN-DATAIN) Hold time, DATAIN valid after CLOCKIN 0 ns tr(DATAIN) Rising time, DATAIN 1.00 3.00 tf(DATAIN) Falling time, DATAIN 1.00 3.00 8 ns 1 3 5 4 2 CLOCKIN DATAIN 7 6 8 Figure 5-121. PRU-ICSS PRU Parallel Capture Timing - Rising Edge Mode 1 3 4 5 2 CLOCKIN DATAIN 6 7 8 Figure 5-122. PRU-ICSS PRU Parallel Capture Timing - Falling Edge Mode 5.13.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing Table 5-104. PRU-ICSS PRU Timing Requirements - Shift In Mode (see Figure 5-123) NO. (1) MIN MAX UNIT 1 tc(DATAIN) Cycle time, DATAIN 10.00 2 tw(DATAIN) Pulse width, DATAIN 0.45*P (1) 0.55*P (1) ns ns 3 tr(DATAIN) Rising time, DATAIN 1.00 3.00 ns 4 tf(DATAIN) Falling time, DATAIN 1.00 3.00 ns P = L3_CLK (PRU-ICSS ocp clock) period. Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 237 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 1 2 3 4 DATAIN Figure 5-123. PRU-ICSS PRU Shift In Timing Table 5-105. PRU-ICSS PRU Switching Requirements - Shift Out Mode (see Figure 5-124) NO. MIN MAX 10.00 UNIT 1 tc(CLOCKOUT) Cycle time, CLOCKOUT 2 tw(CLOCKOUT) Pulse width, CLOCKOUT 0.45*P (1) 0.55*P (1) ns ns 3 tr(CLOCKOUT) Rising time, CLOCKOUT 1.00 3.00 ns 4 tf(CLOCKOUT) Falling time, CLOCKOUT 5 td(CLOCKOUT- Delay time, CLOCKOUT to DATAOUT Valid 1.00 3.00 ns -1.50 3.00 ns DATAOUT) 6 (1) tr(DATAOUT) Rising time, DATAOUT 1.00 3.00 tf(DATAOUT) Falling time, DATAOUT 1.00 3.00 ns P = L3_CLK (PRU-ICSS ocp clock) period. 1 2 3 4 CLOCKOUT DATAOUT 5 6 Figure 5-124. PRU-ICSS PRU Shift Out Timing 5.13.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing Table 5-106. PRU-ICSS Timing Requirements - Sigma Delta Mode (see Figure 5-125 and Figure 5-126) NO. MIN MAX UNIT 1 tw(SDx_CLK) Pulse width, SDx_CLK 20.00 2 tr(SDx_CLK) Rising time, SDx_CLK 1.00 3.00 ns 3 tf(SDx_CLK) Falling time, SDx_CLK 1.00 3.00 ns 4 tsu(SDx_D-SDx_CLK) Setup time, SDx_D valid before SDx_CLK active edge 10.00 ns 5 th(SDx_CLK-SDx_D) Hold time, SDx_D valid before SDx_CLK active edge 5.00 ns tr(SDx_D) Rising time, SDx_D 1.00 3.00 tf(SDx_D) Falling time, SDx_D 1.00 3.00 6 238 Specifications ns ns Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 1 2 3 SDx_CLK SDx_D 4 5 6 Figure 5-125. PRU-ICSS Sigma Delta Timing - SD_CLK Rising Active Edge 1 3 2 SDx_CLK SDx_D 4 5 6 Figure 5-126. PRU-ICSS Sigma Delta Timing - SD_CLK Falling Active Edge 5.13.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing Table 5-107. PRU-ICSS Timing Requirements - ENDAT Mode (see Figure 5-127) NO. MIN MAX UNIT 1 tw(ENDATx_IN) Pulse width, ENDATx_IN 40.00 ns 2 tr(ENDATx_IN) Rising time, ENDATx_IN 1.00 10.00 ns 3 tf(ENDATx_IN) Falling time, ENDATx_IN 1.00 10.00 ns MAX UNIT Table 5-108. PRU-ICSS Switching Requirements - ENDAT Mode (see Figure 5-127) NO. MIN 4 tw(ENDATx_CLK) Pulse width, ENDATx_CLK 20.00 5 tr(ENDATx_CLK) Rising time, ENDATx_CLK 1.00 3.00 ns ns 6 tf(ENDATx_CLK) Falling time, ENDATx_CLK 1.00 3.00 ns 7 td(ENDATx_OUT- Delay time, ENDATx_CLK fall to ENDATx_OUT -10.00 10.00 ns ENDATx_CLK) 8 9 tr(ENDATx_OUT) Rising time, ENDATx_OUT 1.00 3.00 tf(ENDATx_OUT) Falling time, ENDATx_OUT 1.00 3.00 td(ENDATx_OUT_EN- Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN -10.00 10.00 ns ns ENDATx_CLK) Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 239 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 3 2 ENDATx_IN 1 4 5 6 ENDATx_CLK ENDATx_OUT 8 ENDATx_OUT_EN 9 Figure 5-127. PRU-ICSS ENDAT Timing 5.13.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT) Table 5-109. PRU-ICSS ECAT Timing Conditions TIMING CONDITION PARAMETER MIN MAX UNIT Output Condition Cload Capacitive load for each bus line 30 pF 5.13.16.2.1 PRU-ICSS ECAT Electrical Data and Timing Table 5-110. PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN (see Figure 5-128) NO. MIN MAX UNIT 1 tw(EDIO_LATCH_IN) Pulse width, EDIO_LATCH_IN 100.00 2 tr(EDIO_LATCH_IN) Rising time, EDIO_LATCH_IN 1.00 3.00 ns 3 tf(EDIO_LATCH_IN) Falling time, EDIO_LATCH_IN 1.00 3.00 ns 4 tsu(EDIO_DATA_IN- Setup time, EDIO_DATA_IN valid before EDIO_LATCH_IN active edge 20.00 ns Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN active edge 20.00 ns EDIO_DATA_IN) tr(EDIO_DATA_IN) Rising time, EDIO_DATA_IN 1.00 3.00 tf(EDIO_DATA_IN) Falling time, EDIO_DATA_IN 1.00 3.00 EDIO_LATCH_IN) 5 6 240 th(EDIO_LATCH_IN- Specifications ns ns Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 2 3 EDIO_LATCH_IN 1 4 5 EDIO_DATA_IN[7:0] 6 Figure 5-128. PRU-ICSS ECAT Input Validated With LATCH_IN Timing Table 5-111. PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx (see Figure 5-129) NO. MIN MAX UNIT 1 tw(EDC_SYNCx_OUT) Pulse width, EDC_SYNCx_OUT 100.00 2 tr(EDC_SYNCx_OUT) Rising time, EDC_SYNCx_OUT 1.00 3.00 ns 3 tf(EDC_SYNCx_OUT) Falling time, EDC_SYNCx_OUT 1.00 3.00 ns 4 tsu(EDIO_DATA_IN- Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT active edge 24.50 ns Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT active edge 22.00 ns EDIO_DATA_IN) tr(EDIO_DATA_IN) Rising time, EDIO_DATA_IN 1.00 3.00 tf(EDIO_DATA_IN) Falling time, EDIO_DATA_IN 1.00 3.00 EDC_SYNCx_OUT) 5 6 th(EDC_SYNCx_OUT- 2 ns ns 3 EDC_SYNCx_OUT 1 4 5 EDIO_DATA_IN[7:0] 6 Figure 5-129. PRU-ICSS ECAT Input Validated With SYNCx Timing Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 241 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-112. PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF) (see Figure 5-130) NO. MIN MAX UNIT 4*P (1) 5*P (1) ns Rising time, EDIO_SOF 1.00 3.00 ns Falling time, EDIO_SOF 1.00 3.00 ns 1 tw(EDIO_SOF) Pulse duration, EDIO_SOF 2 tr(EDIO_SOF) 3 tf(EDIO_SOF) 4 tsu(EDIO_DATA_IN- Setup time, EDIO_DATA_IN valid before EDIO_SOF active edge EDIO_SOF) 5 th(EDIO_SOF-EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDIO_SOF active edge 6 (1) 20.00 ns 20.00 ns tr(EDIO_DATA_IN) Rising time, EDIO_DATA_IN 1.00 3.00 tf(EDIO_DATA_IN) Falling time, EDIO_DATA_IN 1.00 3.00 ns P = PRU-ICSS IEP clock source period. 2 3 EDIO_SOF 1 4 5 EDIO_DATA_IN[7:0] 6 Figure 5-130. PRU-ICSS ECAT Input Validated With SOF Table 5-113. PRU-ICSS ECAT Timing Requirements - LATCHx_IN (see Figure 5-131) NO. MIN UNIT 1 tw(EDC_LATCHx_IN) Pulse duration, EDC_LATCHx_IN 2 tr(EDC_LATCHx_IN) Rising time, EDC_LATCHx_IN 1.00 3.00 ns 3 tf(EDC_LATCHx_IN) Falling time, EDC_LATCHx_IN 1.00 3.00 ns (1) 3*P MAX (1) ns P = PRU-ICSS IEP clock source period. 2 3 EDC_LATCHx_IN 1 Figure 5-131. PRU-ICSS ECAT LATCHx_IN Timing 242 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-114. PRU-ICSS ECAT Switching Requirements - Digital IOs NO. MIN MAX 14*P (1) 32*P (1) ns Rising time, EDIO_OUTVALID 1.00 3.00 ns Falling time, EDIO_OUTVALID 1.00 3.00 ns Delay time, EDIO_OUTVALID to EDIO_DATA_OUT 0.00 18*P (1) ns 1 tw(EDIO_OUTVALID) Pulse duration, EDIO_OUTVALID 2 tr(EDIO_OUTVALID) 3 tf(EDIO_OUTVALID) 4 td(EDIO_OUTVALID- UNIT EDIO_DATA_OUT) 5 tr(EDIO_DATA_OUT) Rising time, EDIO_DATA_OUT 1.00 3.00 ns 6 tf(EDIO_DATA_OUT) Falling time, EDIO_DATA_OUT 1.00 3.00 ns 7 tsk(EDIO_DATA_OUT) EDIO_DATA_OUT skew 8.00 ns (1) P = PRU-ICSS IEP clock source period. 5.13.16.3 PRU-ICSS MII_RT and Switch Table 5-115. PRU-ICSS MII_RT Switch Timing Conditions TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tr Input signal rise time tf Input signal fall time 1 (1) 5 (1) ns (1) (1) ns 20 pF 1 5 Output Condition CLOAD (1) Output load capacitance Except when specified otherwise. 5.13.16.3.1 PRU-ICSS MDIO Electrical Data and Timing Table 5-116. PRU-ICSS MDIO Timing Requirements - MDIO_DATA (see Figure 5-132) NO. MIN 1 tsu(MDIO-MDC) Setup time, MDIO valid before MDC high 2 th(MDIO-MDC) Hold time, MDIO valid from MDC high TYP MAX UNIT 90 ns 0 ns 1 2 MDIO_CLK (Output) MDIO_DATA (Input) Figure 5-132. PRU-ICSS MDIO_DATA Timing - Input Mode Table 5-117. PRU-ICSS MDIO Switching Characteristics - MDIO_CLK (see Figure 5-133) NO. MIN TYP MAX UNIT 1 tc(MDC) Cycle time, MDC 400 ns 2 tw(MDCH) Pulse duration, MDC high 160 ns 3 tw(MDCL) Pulse duration, MDC low 160 4 tt(MDC) Transition time, MDC Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 ns 5 Specifications ns 243 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 4 1 3 2 MDIO_CLK 4 Figure 5-133. PRU-ICSS MDIO_CLK Timing Table 5-118. PRU-ICSS MDIO Switching Characteristics - MDIO_DATA (see Figure 5-134) NO. 1 MIN td(MDC-MDIO) Delay time, MDC high to MDIO valid TYP 10 MAX UNIT 390 ns 1 MDIO_CLK (Output) MDIO_DATA (Output) Figure 5-134. PRU-ICSS MDIO_DATA Timing - Output Mode 5.13.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing Table 5-119. PRU-ICSS MII_RT Timing Requirements - MII_RXCLK (see Figure 5-135) 10 Mbps NO. MIN TYP 100 Mbps MAX MIN TYP MAX UNIT 1 tc(RX_CLK) Cycle time, RX_CLK 399.96 400.04 39.996 40.004 ns 2 tw(RX_CLKH) Pulse Duration, RX_CLK high 140 260 14 26 ns 3 tw(RX_CLKL) Pulse Duration, RX_CLK low 140 260 14 26 ns 4 tt(RX_CLK) Transition time, RX_CLK 3 ns 3 4 1 3 2 MII_RXCLK 4 Figure 5-135. PRU-ICSS MII_RXCLK Timing 244 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-120. PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK (see Figure 5-136) 10 Mbps NO. MIN 100 Mbps TYP MAX MIN TYP MAX UNIT 1 tc(TX_CLK) Cycle time, TX_CLK 399.96 400.04 39.996 40.004 ns 2 tw(TX_CLKH) Pulse Duration, TX_CLK high 140 260 14 26 ns 3 tw(TX_CLKL) Pulse Duration, TX_CLK low 140 260 14 26 ns 4 tt(TX_CLK) Transition time, TX_CLK 3 ns 3 4 1 3 2 MII_TXCLK 4 Figure 5-136. PRU-ICSS MII_TXCLK Timing Table 5-121. PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER (see Figure 5-137) 10 Mbps NO. 1 2 MIN tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK th(RX_CLK-RXD) Hold time RXD[3:0] valid after RX_CLK th(RX_CLK-RX_DV) Hold time RX_DV valid after RX_CLK th(RX_CLK-RX_ER) Hold time RX_ER valid after RX_CLK TYP 100 Mbps MAX MIN TYP MAX UNIT 8 8 ns 8 8 ns 1 2 MII_MRCLK (Input) MII_RXD[3:0], MII_RXDV, MII_RXER (Inputs) Figure 5-137. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 245 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-122. PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN (see Figure 5-138) 10 Mbps NO. 1 MIN td(TX_CLK-TXD) Delay time, TX_CLK high to TXD[3:0] valid td(TX_CLK-TX_EN) Delay time, TX_CLK to TX_EN valid TYP 5 100 Mbps MAX MIN 25 5 TYP MAX UNIT 25 ns 1 MII_TXCLK (input) MII_TXD[3:0], MII_TXEN (outputs) Figure 5-138. PRU-ICSS MII_TXD[3:0], MII_TXEN Timing 5.13.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART) Table 5-123. Timing Requirements for PRU-ICSS UART Receive (see Figure 5-139) NO. 3 (1) tw(RX) Pulse width, receive start, stop, data bit MIN MAX 0.96U (1) 1.05U (1) UNIT ns U = UART baud time = 1/programmed baud rate. Table 5-124. Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit (see Figure 5-139) NO. 1 fbaud(baud) Maximum programmable baud rate 2 tw(TX) Pulse width, transmit start, stop, data bit (1) MIN MAX UNIT 0 12 MHz U - 2 (1) U + 2 (1) ns U = UART baud time = 1/programmed baud rate. 3 2 UART_TXD Start Bit Data Bits 5 4 UART_RXD Start Bit Data Bits Figure 5-139. PRU-ICSS UART Timing 246 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.17 Multimedia Card (MMC) Interface For more information, see the Multimedia Card (MMC) section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual. 5.13.17.1 MMC Electrical Data and Timing Table 5-125. MMC Timing Conditions TIMING CONDITION PARAMETER MIN TYP MAX UNIT Input Conditions tr Input signal rise time 1 5 ns tf Input signal fall time 1 5 ns 3 30 pF Output Condition Cload Output load capacitance Table 5-126. Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0] (see Figure 5-140) OPP50/OPP100 NO. 1.8 V MIN TYP 3.3 V MAX MIN UNIT TYP MAX 1 tsu(CMDV-CLKH) Setup time, MMC_CMD valid before MMC_CLK rising clock edge 4.1 4.1 ns 2 th(CLKH-CMDV) Hold time, MMC_CMD valid after MMC_CLK rising clock edge 1.5 1.5 ns 3 tsu(DATV-CLKH) Setup time, MMC_DATx valid before MMC_CLK rising clock edge 4.1 4.1 ns 4 th(CLKH-DATV) Hold time, MMC_DATx valid after MMC_CLK rising clock edge 1.5 1.5 ns Table 5-127. Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0] (see Figure 5-140) OPP50/OPP100 NO. 1.8 V MIN 1 tsu(CMDV-CLKH) Setup time, MMC_CMD valid before MMC_CLK rising clock edge 2 th(CLKH-CMDV) Hold time, MMC_CMD valid after MMC_CLK rising clock edge 3 tsu(DATV-CLKH) Setup time, MMC_DATx valid before MMC_CLK rising clock edge 4 th(CLKH-DATV) Hold time, MMC_DATx valid after MMC_CLK rising clock edge TYP 3.3 V MAX MIN TYP UNIT MAX 4.1 4.1 ns 2.55 3.76 ns 4.1 4.1 ns 2.55 3.76 ns Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 247 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 1 2 MMC[x]_CLK (Output) MMC[x]_CMD (Input) MMC[x]_DAT[7:0] (Inputs) 3 4 Figure 5-140. MMC[x]_CMD and MMC[x]_DAT[7:0] Input Timing 248 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-128. Switching Characteristics for MMC[x]_CLK (see Figure 5-141) NO. 5 STANDARD MODE PARAMETER MIN TYP fop(CLK) Operating frequency, MMC_CLK tcop(CLK) Operating period: MMC_CLK fid(CLK) Identification mode frequency, MMC_CLK tcid(CLK) Identification mode period: MMC_CLK HIGH-SPEED MODE MAX MIN TYP MAX 24 UNIT 48 MHz 41.7 20.8 ns 400 400 kHz 2500 2500 ns tf(CLK)(1) tr(CLK)(1) tf(CLK)(1) tr(CLK)(1) ns 6 tw(CLKL) Pulse duration, MMC_CLK low (0.5*P) - 7 tw(CLKH) Pulse duration, MMC_CLK high (0.5*P) - (0.5*P) - 8 tr(CLK) Rise time, All Signals (10% to 90%) 2.2 2.2 ns 9 tf(CLK) Fall time, All Signals (10% to 90%) 2.2 2.2 ns (0.5*P) - ns (1) P = MMC_CLK period. 5 6 7 8 9 MMC[x]_CLK (Output) Figure 5-141. MMC[x]_CLK Timing Table 5-129. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]--HSPE=0 (see Figure 5-142) OPP50/OPP100 NO. PARAMETER 1.8 V MIN 3.3 V TYP MAX MIN UNIT TYP MAX 10 td(CLKL-CMD) Delay time, MMC_CLK falling clock edge to MMC_CMD transition -4 14 -4 17.5 ns 11 td(CLKL-DAT) Delay time, MMC_CLK falling clock edge to MMC_DATx transition -4 14 -4 17.5 ns 10 MMC[x]_CLK (Output) MMC[x]_CMD (Output) MMC[x]_DAT[7:0] (Outputs) 11 Figure 5-142. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing--HSPE=0 Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 249 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Table 5-130. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]--HSPE=1 (see Figure 5-143) OPP50/OPP100 NO. PARAMETER 1.8 V MIN 3.3 V TYP MAX MIN TYP MAX UNIT 12 td(CLKL-CMD) Delay time, MMC_CLK rising clock edge to MMC_CMD transition 0.8 7.4 0.8 7.4 ns 13 td(CLKL-DAT) Delay time, MMC_CLK rising clock edge to MMC_DATx transition 0.8 7.4 0.8 7.4 ns 12 MMC[x]_CLK (Output) MMC[x]_CMD (Output) MMC[x]_DAT[7:0] (Outputs) 13 Figure 5-143. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing--HSPE=1 250 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 5.13.18 Universal Asynchronous Receiver/Transmitter (UART) For more information, see the Universal Asynchronous Receiver/Transmitter (UART) section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual. 5.13.18.1 UART Electrical Data and Timing Table 5-131. Timing Requirements for UARTx Receive (see Figure 5-144) NO. 3 tw(RX) Pulse width, receive start, stop, data bit MIN MAX 0.96U(1) 1.05U(1) UNIT ns (1) U = UART baud time = 1/programmed baud rate. Table 5-132. Switching Characteristics for UARTx Transmit (see Figure 5-144) NO. PARAMETER MIN 1 fbaud(baud) Maximum programmable baud rate 2 tw(TX) Pulse width, transmit start, stop, data bit U - 2(1) MAX UNIT 3.6864 MHz U + 2(1) ns (1) U = UART baud time = 1/programmed baud rate. 2 2 2 UARTx_TXD Start Bit Stop Bit Data Bits 3 3 UARTx_RXD Start Bit 3 Stop Bit Data Bits Figure 5-144. UART Timings Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 251 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.13.18.2 UART IrDA Interface The IrDA module operates in three different modes: * Slow infrared (SIR) ( 115.2 kbps) * Medium infrared (MIR) (0.576 Mbps and 1.152 Mbps) * Fast infrared (FIR) (4 Mbps). Figure 5-145 shows the UART IrDA pulse parameters. Table 5-133 and Table 5-134 list the signaling rates and pulse durations for UART IrDA receive and transmit modes. Pulse Duration 50% Pulse Duration 50% 50% Figure 5-145. UART IrDA Pulse Parameters Table 5-133. UART IrDA--Signaling Rate and Pulse Duration--Receive Mode SIGNALING RATE ELECTRICAL PULSE DURATION UNIT MIN MAX 2.4 kbps 1.41 88.55 s 9.6 kbps 1.41 22.13 s 19.2 kbps 1.41 11.07 s 38.4 kbps 1.41 5.96 s 57.6 kbps 1.41 4.34 s 115.2 kbps 1.41 2.23 s 0.576 Mbps 297.2 518.8 ns 1.152 Mbps 149.6 258.4 ns 4 Mbps (Single pulse) 67 164 ns 4 Mbps (Double pulse) 190 289 ns SIR MIR FIR 252 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Table 5-134. UART IrDA--Signaling Rate and Pulse Duration--Transmit Mode ELECTRICAL PULSE DURATION SIGNALING RATE UNIT MIN MAX 2.4 kbps 78.1 78.1 s 9.6 kbps 19.5 19.5 s 19.2 kbps 9.75 9.75 s 38.4 kbps 4.87 4.87 s 57.6 kbps 3.25 3.25 s 115.2 kbps 1.62 1.62 s 0.576 Mbps 414 419 ns 1.152 Mbps 206 211 ns 4 Mbps (Single pulse) 123 128 ns 4 Mbps (Double pulse) 248 253 ns SIR MIR FIR Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Specifications 253 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com 5.14 Emulation and Debug 5.14.1 IEEE 1149.1 JTAG 5.14.1.1 JTAG Electrical Data and Timing Table 5-135. Timing Requirements for JTAG (see Figure 5-146) OPP100 NO. MIN OPP50 MAX MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 60 60 ns 1a tw(TCKH) Pulse duration, TCK high (40% of tc) 24 24 ns 1b tw(TCKL) Pulse duration, TCK low (40% of tc) 24 24 ns tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 3 3 ns tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 3 3 ns th(TCKH-TDI) Input hold time, TDI valid from TCK high 8 8 ns th(TCKH-TMS) Input hold time, TMS valid from TCK high 8 8 ns 3 4 Table 5-136. Switching Characteristics for JTAG (see Figure 5-146) NO. 2 OPP100 PARAMETER td(TCKL-TDO) Delay time, TCK low to TDO valid OPP50 MIN MAX MIN MAX 0 23 0 23 UNIT ns 1 1a 1b TCK 2 TDO 3 4 TDI/TMS Figure 5-146. JTAG Timing 254 Specifications Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 6 Device and Documentation Support 6.1 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all processors and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, XAM4379xZDN). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully-qualified development-support product. X and P devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZDN), the temperature range (for example, blank is the default commercial temperature range), and the device speed range, in megahertz (for example, 80 is 800 MHz). Figure 6-1 provides a legend for reading the complete device name for any device. For orderable part numbers of AM437x devices in the ZDN package type, see the Package Option Addendum of this document, the TI website, or contact your TI sales representative. For additional description of the device nomenclature markings on the die, see the AM437x Sitara Processors Silicon Errata. Device and Documentation Support Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 255 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 X AM4379 A www.ti.com ZDN ( ) ( ) S PREFIX X = Experimental device Blank = Qualified device SUFFIX Blank = Only Public Boot Supported S = High-Security (AM437xHS) device, Secure Boot Supported (A) DEVICE SPEED RANGE 30 = 300-MHZ Cortex-A9 60 = 600-MHz Cortex-A9 80 = 800-MHz Cortex-A9 100 = 1000-MHz Cortex-A9 DEVICE ARM Cortex-A9 MPU: AM4372 AM4376 AM4377 AM4378 AM4379 TEMPERATURE RANGE Blank = 0C to 90C (commercial junction temperature) A = -40C to 105C (extended junction temperature) D = -40C to 90C (industrial junction temperature) DEVICE REVISION CODE A = silicon revision 1.1 B = silicon revision 1.2 (B) PACKAGE TYPE ZDN = 491-pin plastic BGA, with Pb-free solder balls A. B. The device shown in this device nomenclature example is one of several valid part numbers for this family of devices. For orderable device part numbers, see the Package Option Addendum of this document. BGA = Ball Grid Array. Figure 6-1. Device Nomenclature 6.2 Tools and Software TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Models AM437x BSDL Model ZDN package BSDL model. AM437x IBIS Model ZDN package IBIS model. Design Kits and Evaluation Modules AM437x Evaluation Module Enables developers to immediately start evaluating the AM437x processor family (AM4372, AM4376, AM4377, AM4378 and AM4379 ) and begin building applications such as portable navigation, patient monitoring, home/building automation, barcode scanners, portable data terminals and others. AM437x Industrial Development Kit (IDK) An application development platform for evaluating the industrial communication and control capabilities of Sitara AM4379 and AM4377 processors for industrial applications. AM437x Starter Kit Provides a stable and affordable platform to quickly start evaluation of Sitara ARM Cortex-A9 AM437x Processors (AM4372, AM4376, AM4378) and accelerate development for HMI, industrial and networking applications. It is a low-cost development platform based on the ARM Cortex-A9 processor that is integrated with options such as Dual Gigabit Ethernet, DDR3L, Camera and Capacitive Touch Screen LCD. TI Designs ARM MPU with Integrated BiSS C Master Interface Reference Design Impelementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU). Sercos III Slave For AM437x Communication Development Platform Reference Design Combines the AM437x Sitara processor family from Texas Instruments (TI) and the Sercos III media access control (MAC) layer into a single system-on-chip (SoC) solution. Targeted for Sercos III slave communications, the TIDEP0039 allows designers to implement the real-time Sercos III communication standard for a broad range of industrial automation equipment. EnDat 2.2 System Reference Design Implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and the line termination implemented on the Sitara AM437x Industrial Development Kit. 256 Device and Documentation Support Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 Acontis EtherCAT Master Stack Reference Design A highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performane TI Sitara MPUs, it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT communication interface boards, EtherCAT based PLC or motion control applications. SPI Master with Signal Path Delay Compensation Reference Design Describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7MHz. Isolated Current Shunt and Voltage Measurement Reference Design for Motor Drives Using AM437x Uses the AMC130x reinforced isolated delta-sigma modulators along with AM437x Sitara ARM Cortex-A9 Processor, which implements Sinc filters on PRU-ICSS. The design provides an ability to evaluate the performance of these measurements: three motor currents, three inverter voltages, and the DC Link voltage. Single Chip Drive for Industrial Communications and Motor Control Implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. AM437x Low Power Suspend Mode with LPDDR2 Realizes processor power consumption less than 0.1 mW while keeping LPDDR2 memory in self refresh consuming ~ 1.6 mW. The system solution is comprised of AM437x Sitara processor, LPDDR2 memory and TPS65218 power management IC and optimized for new low power mode along with support for legacy low power modes. AM437x Discrete Power Reference Design Provides flexibility to power designers. This reference design implementation is a BOM-optimized discrete power solution for the AM437x processor with a minimal number of discrete ICs and basic feature set. T Embedded USB 2.0 Reference Design The USB 2.0 reference design guidelines are extremely important for designers considering USB2.0 electrical compliance testing. The guidelines are applicable to AM335x and AM437x but also generic to other processors. The approach taken for these guidelines is highly practical, without complex formulas or theory. ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design Implementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable. Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design. Software Processor SDK for AM437X Sitara Processors - Linux and TI-RTOS Support A unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI's broad portfolio, allowing developers to seamlessly reuse and migrate software across devices. Programmable Real-time Unit (PRU) Software Support Package An add-on package that provides a framework and examples for developing software for the Programmable Real-time Unit subsystem and Industrial Communication Sub-System (PRU-ICSS) in the supported TI processors. SYS/BIOS Industrial Software Development Kit (SDK) for Sitara Processors Gives customers the ability to easily add real-time industrial communications to their design so they can focus on differentiating their application code. TI Dual-Mode Bluetooth(R) Stack Comprised of Single-Mode and Dual-Mode offerings implementing the Bluetooth 4.0 specification. The Bluetooth stack is fully Bluetooth Special Interest Group (SIG) qualified, certified and royalty-free, provides simple command line sample applications to speed development, and upon request has MFI capability. Device and Documentation Support Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 257 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 www.ti.com Development Tools Clock Tree Tool for Sitara ARM Processors Interactive clock tree configuration software that provides information about the clocks and modules in Sitara devices. Pin Mux Tool Provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDK) or used to configure customer's custom software. Version 3 of the Pin Mux utility adds the capability of automatically selecting a mux configuration that satisfies the entered requirements. Power Estimation Tool (PET) Provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be applied to further reduce overall power consumption. XDS200 USB Debug Probe Connects to the target board via a TI 20-pin connector (with multiple adapters for TI 14-pin, ARM 10-pin and ARM 20-pin) and to the host PC via USB2.0 High Speed (480Mbps). It also requires a license of Code Composer Studio IDE running on the host PC. XDS560v2 System Trace USB and Ethernet Debug Probe Adds system pin trace in its large external memory buffer. Available for selected TI devices, this external memory buffer captures device-level information that allows obtaining accurate bus performance activity and throughput, as well as power management of core and peripherals. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB). XDS560v2 System Trace USB Debug Probe Adds system pin trace in its large external memory buffer. Available for selected TI devices, this external memory buffer captures device-level information that allows obtaining accurate bus performance activity and throughput, as well as power management of core and peripherals. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB). 6.3 Documentation Support To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The current documentation that describes the processor, related peripherals, and other technical collateral is listed below. Errata AM437x Sitara Processors Silicon Errata Describes specifications for this microprocessor. the known exceptions to the functional Application Reports High-Speed Interface Layout Guidelines As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution. User's Guides AM437x Sitara Processors Technical Reference Manual Collection of documents providing detailed information on the device including power, reset, and clock control, interrupts, memory map, and switch fabric interconnect. Detailed information on the microprocessor unit (MPU) subsystem as well as a functional description of the peripherals supported is also included. Discrete Power Solution for AM437x Details the implementation of a BOM-optimized discrete power solution for the AM437x processor with a minimal number of discrete ICs and basic feature set. The solution represents a baseline for a discrete power solution that can be extended for additional features of the AM437x processor. Powering the AM335x/AM437x with TPS65218 A reference for connectivity between the TPS65218 power management IC and the AM335x or AM437x processor. 258 Device and Documentation Support Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 AM437x GP EVM Hardware User's Guide Describes the hardware architecture of the AM437x Evaluation Module (EVM) (part number TMDXEVM437X), which is based on the Texas Instruments (TI) AM437x processor. This EVM is also commonly known as the AM437x General Purpose (GP) EVM. White Papers Highly Integrated industrial Drive to Connect, Control and Communicate Discusses the overall drive architecture with emphasis on the highly integrated industrial drive solution by Texas Instruments. Ensuring Real-Time Predictability High-performance processors like ARM Cortex-A cores have an entirely different set of resources and pro- cessing capabilities than those of real-time processing cores, like the Programmable Real-Time Unit (PRU) coprocessor in TI's Sitara processors. Mainline Linux Ensures Stability and Innovation Enabling and empowering the rapid development of new functionality starts at the foundational level of the system's software environment - that is, at the level of the Linux kernel - and builds upward from there. Scalable Solutions for HMI A well designed HMI system decreases that gap between the production process and operator through an intuitive visualization system, layers of detail to allow for a bird's eye view down to the minute details, as well as training material and documentation at the operators' fingertips. Linaro Speeds Development in TI Linux SDKs Linaro's software is not a Linux distribution; in fact, it is distribution neutral. The focus of the organization's 120 engineers is on optimizing base-level open-source software in areas that interact directly with the silicon such as multimedia, graphics, power management, the Linux kernel and booting processes. Getting Started on TI ARM Embedded Processor Development Beginning with an overview of ARM technology and available processor platforms, this paper will then explore the fundamentals of embedded design that influence a system's architecture and, consequently, impact processor selection. The Yocto Project: Changing the Way Embedded Linux Software Solutions are Developed Enabling complex silicon devices such as SoC with operating firmware and application software can be a challenge for equipment manufacturers who often are more comfortable with hardware than software issues. Other Documents Sitara AM437x Processor With ARM Cortex-A9 Core TI continues to optimize and expand its portfolio of Sitara processor solutions for the embedded market. With the Sitara AM437x processors support for the ARM Cortex-A9 core, extending performance by up to 40 percent over the current Sitara AM335x processor line. Sitara Processors Using the ARM Cortex-A series of cores, are optimized system solutions that go beyond the core, delivering products that support rich graphics capabilities, LCD displays and multiple industrial protocols. AM437x Evaluation Module Quick Start Guide Designed to help you through the initial setup of the EVM. This EVM allows you to experience Linux and other operating systems (OSs) that showcase the AM437x Cortex-A9 processor, 3D graphics and more. The following documents are related to the processor. Copies of these documents can be obtained directly from the internet or from your Texas Instruments representative. To determine the revision of the Cortex-A9 core used on your device, see the device-specific errata. Cortex-A9 Technical Reference Manual Technical reference manual for the Cortex-A9 processor. ARM Core Cortex-A9 (AT400/AT401) Errata Notice Provides a list of advisories for the different revisions of the Cortex-A9 processor. For a copy of this document, contact your TI representative. Device and Documentation Support Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 259 AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 6.4 www.ti.com Related Links Table 6-1 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 6-1. Related Links 6.5 PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY AM4372 Click here Click here Click here Click here Click here AM4376 Click here Click here Click here Click here Click here AM4377 Click here Click here Click here Click here Click here AM4378 Click here Click here Click here Click here Click here AM4379 Click here Click here Click here Click here Click here Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community The TI engineer-ro-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 6.6 Trademarks Sitara, E2E are trademarks of Texas Instruments. NEON is a trademark of ARM Ltd or its subsidiaries. ARM, Cortex are registered trademarks of ARM Ltd or its subsidiaries. Bluetooth is a registered trademark of Bluetooth SIG. EtherCAT is a registered trademark of EtherCAT Technology Group. PowerVR SGX is a trademark of Imagination Technologies Limited. Linux is a registered trademark of Linus Torvalds. 1-Wire is a registered trademark of Maxim Integrated Products, Inc. EtherNet/IP is a trademark of ODVA, Inc. PROFIBUS, PROFINET are registered trademarks of PROFIBUS & PROFINET International (PI). All other trademarks are the property of their respective owners. 6.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 6.8 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 260 Device and Documentation Support Copyright (c) 2014-2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851D - JUNE 2014 - REVISED SEPTEMBER 2016 7 Mechanical, Packaging, and Orderable Information 7.1 Via Channel The ZDN package has been specially engineered with Via Channel technology. This technology allows larger than normal PCB via and trace sizes and reduced PCB signal layers to be used in a PCB design with the 0.65-mm pitch package, and substantially reduces PCB costs. It allows PCB routing in only two signal layers (four layers total) due to the increased layer efficiency of the Via Channel BGA technology. NOTE Via Channel technology implemented on the this package makes it possible to build a product with a 4-layer PCB, but a 4-layer PCB may not meet system performance goals. Therefore, system performance using a 4-layer PCB design must be evaluated during product design. 7.2 Packaging Information The following packaging information and addendum reflect the most current data available for the designated device. This data is subject to change without notice and without revision of this document. The following figure is a preliminary package drawing for the ZDN package option. Note: The ZDN package is shown with a 17-mm x 17-mm array of 491 solder balls with 0.65-mm pitch, with via channel array (VCA) technology. Mechanical, Packaging, and Orderable Information Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 Copyright (c) 2014-2016, Texas Instruments Incorporated 261 PACKAGE OPTION ADDENDUM www.ti.com 29-Dec-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) AM4372BZDN60 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 AM4372BZDN60 AM4372BZDN80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 AM4372BZDN80 AM4372BZDNA60 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4372BZDNA60 AM4372BZDNA80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4372BZDNA80 AM4376BZDN100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 AM4376BZDN100 AM4376BZDN80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 AM4376BZDN80 AM4376BZDNA100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4376BZDNA100 AM4376BZDNA80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4376BZDNA80 AM4376BZDND100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 AM4376BZDND100 AM4376BZDND30 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 AM4376BZDND30 AM4376BZDND80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 AM4376BZDND80 AM4377BZDNA100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4377BZDNA100 AM4377BZDNA80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4377BZDNA80 AM4377BZDND100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 AM4377BZDND100 AM4377BZDND80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 AM4377BZDND80 AM4378BZDN100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 AM4378BZDN100 AM4378BZDN80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 AM4378BZDN80 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 29-Dec-2016 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) AM4378BZDNA100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4378BZDNA100 AM4378BZDNA80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4378BZDNA80 AM4378BZDND100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 AM4378BZDND100 AM4378BZDND80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 AM4378BZDND80 AM4379BZDNA100 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4379BZDNA100 AM4379BZDNA80 ACTIVE NFBGA ZDN 491 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 AM4379BZDNA80 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-Dec-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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