1
FEATURES
DESCRIPTION/ORDERING INFORMATION
PCA9546A4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008www.ti.com
•1-of-4 Bidirectional Translating Switches •Low Standby Current•I
2
C Bus and SMBus Compatible •Operating Power-Supply Voltage Range of2.3 V to 5.5 V•Active-Low Reset Input
•5.5-V Tolerant Inputs•Three Address Pins, Allowing up to EightDevices on the I
2
C Bus •0 to 400-kHz Clock Frequency•Channel Selection Via I
2
C Bus •Latch-Up Performance Exceeds 100 mA PerJESD 78•Power Up With All Switch ChannelsDeselected •ESD Protection Exceeds JESD 22•Low R
ON
Switches – 2000-V Human-Body Model (A114-A)•Allows Voltage-Level Translation Between – 200-V Machine Model (A115-A)1.8-V, 2.5-V, 3.3-V, and 5-V Buses
– 1000-V Charged-Device Model (C101)•No Glitch on Power Up•Supports Hot Insertion
The PCA9546A is a quad bidirectional translating switch controlled via the I
2
C bus. The SCL/SDA upstream pairfans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels canbe selected, determined by the contents of the programmable control register.
An active-low reset ( RESET) input allows the PCA9546A to recover from a situation in which one of thedownstream I
2
C buses is stuck in a low state. Pulling RESET low resets the I
2
C state machine and causes all thechannels to be deselected, as does the internal power-on reset function.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGV Reel of 2500 PCA9546ARGVR PD546AQFN – RGY Reel of 1000 PCA9546ARGYR PD546APCA9546ADTube of 40
PCA9546ADG4
PCA9546ADRSOIC – D Reel of 2500 PCA9546APCA9546ADRG4
PCA9546ADTReel of 250
PCA9546ADTG4Tube of 40 PCA9546ADW
PCA9546A– 40 °C to 85 °C SOIC – DW Reel of 2000 PCA9546ADWRReel of 250 PCA9546ADWT PREVIEWPCA9546APWTube of 90
PCA9546APWE4
PCA9546APWRTSSOP – PW Reel of 2000 PD546APCA9546APWRE4
PCA9546APWTReel of 250
PCA9546APWTE4Reel of 2000 PCA9546ADGVR PD546ATVSOP – DGV
Reel of 250 PCA9546ADGVT PREVIEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
D, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
RESET
SD0
SC0
SD1
SC1
GND
VCC
SDA
SCL
A2
SC3
SD3
SC2
SD2
RGY PACKAGE
(TOP VIEW)
215 SDAA1
314 SCL
RESET
413 A2SD0
512 SC3SC0
611 SD3SD1
710 SC2SC1
1
8
A0
GND
16
9
SD2 VCC
RGV PACKAGE
(TOP VIEW)
8
SC2
13
SDA
16
5
A1
SC1
6
15
A0
GND
VCC
7
14
SD2
1 12 SCL
RESET
2 11 A2SD0
10 SC3
3
SC0
49SD3SD1
PCA9546A
4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
The pass gates of the switches are constructed such that the V
CC
pin can be used to limit the maximum highvoltage, which will be passed by the PCA9546A. This allows the use of different bus voltages on each pair, sothat 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. Externalpullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant.
TERMINAL FUNCTIONS
NO.
NAME DESCRIPTIOND, DGV, DW, PW,
RGVAND RGY
1 15 A0 Address input 0. Connect directly to V
CC
or ground.2 16 A1 Address input 1. Connect directly to V
CC
or ground.3 1 RESET Active low reset input. Connect to V
CC
through a pullup resistor, if not used.4 2 SD0 Serial data 0. Connect to V
CC
through a pullup resistor.5 3 SC0 Serial clock 0. Connect to V
CC
through a pullup resistor.6 4 SD1 Serial data 1. Connect to V
CC
through a pullup resistor.7 5 SC1 Serial clock 1. Connect to V
CC
through a pullup resistor.8 6 GND Ground9 7 SD2 Serial data 2. Connect to V
CC
through a pullup resistor.10 8 SC2 Serial clock 2. Connect to V
CC
through a pullup resistor.11 9 SD3 Serial data 3. Connect to V
CC
through a pullup resistor.12 10 SC3 Serial clock 3. Connect to V
CC
through a pullup resistor.13 11 A2 Address input 2. Connect directly to V
CC
or ground.14 12 SCL Serial clock line. Connect to V
CC
through a pullup resistor.15 13 SDA Serial data line. Connect to V
CC
through a pullup resistor.16 14 V
CC
Supply power
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Switch Control Logic
I2C Bus Control
Input Filter
Power-On Reset
PCA9546A
SC0
SDA
SCL
RESET
GND
SD3
SD2
SD1
SD0
SC3
SC2
SC1
VCC
A1
A0
A2
5
14
3
16
8
11
9
6
4
12
10
7
15
1
2
13
PCA9546A4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
BLOCK DIAGRAM
A. Pin numbers shown are for the D, DGV, DW, PW and RGY packages.
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Device Address
1 1 1 0A1A2 A0
Slave Address
R/W
Fixed Hardware
Selectable
Control Register
Channel Selection Bits
(Read/Write)
Channel 0
Channel 1
Channel 2
Channel 3
B3 B2 B1 B0
3 2 1 0
XXXX
4567
Control Register Definition
PCA9546A
4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
Following a start condition, the bus master must output the address of the slave it is accessing. The address ofthe PCA9546A is shown in Figure 1 . To conserve power, no internal pullup resistors are incorporated on thehardware-selectable address pins, and they must be pulled high or low.
Figure 1. PCA9546A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,while a logic 0 selects a write operation.
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9546A,which is stored in the control register (see Figure 2 ). If multiple bytes are received by the PCA9546A, it will savethe last byte received. This register can be written and read via the I
2
C bus.
Figure 2. Control Register
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (seeTable 1 ). This register is written after the PCA9546A has been addressed. The four LSBs of the control byte areused to determine which channel or channels are to be selected. When a channel is selected, the channelbecomes active after a stop condition has been placed on the I
2
C bus. This ensures that all SCn/SDn lines are ina high state when the channel is made active, so that no false conditions are generated at the time ofconnection. A stop condition always must occur right after the acknowledge cycle.
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RESET Input
Power-On Reset
Voltage Translation
2
Maximum
Typical
Minimum
VCC (V)
4.543.532.5 5 5.5
1
5
4.5
4
3.5
3
2.5
2
1.5
Vpass (V)
PCA9546A4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)
(1)
B7 B6 B5 B4 B3 B2 B1 B0 COMMAND
0 Channel 0 disabledX X X X X X X
1 Channel 0 enabled0 Channel 1 disabledX X X X X X X1 Channel 1 enabled0 Channel 2 disabledX X X X X X X1 Channel 2 enabled0 Channel 3 disabledX X X X X X X1 Channel 3 enabledNo channel selected,0 0 0 0 0 0 0 0
power-up/reset default state
(1) Several channels can be enabled at the same time. For example, B3 =0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 aredisabled, and channels 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signalis asserted low for a minimum of t
WL
, the PCA9446A resets its registers and I
2
C state machine and deselects allchannels. The RESET input must be connected to V
CC
through a pullup resistor.
When power is applied to V
CC
, an internal power-on reset holds the PCA9546A in a reset condition until V
CC
hasreached V
POR
. At this point, the reset condition is released, and the PCA9546A registers and I
2
C state machineare initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, V
CC
mustbe lowered below 0.2 V to reset the device.
The pass-gate transistors of the PCA9546A are constructed such that the V
CC
voltage can be used to limit themaximum voltage that will be passed from one I
2
C bus to another.
Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated usingthe data specified in the electrical characteristics section of this data sheet). In order for the PCA9546A to act asa voltage translator, the V
pass
voltage must be equal to or lower than the lowest bus voltage. For example, if themain bus is running at 5 V, and the downstream buses are 3.3 V and 2.7 V, then V
pass
must be equal to or below2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 3 , V
pass
(max) is at 2.7 V when thePCA9546A supply voltage is 3.5 V or lower, so the PCA9546A supply voltage could be set to 3.3 V. Pullupresistors then can be used to bring the bus voltages to their appropriate levels (see Figure 12 ).
Figure 3. V
pass
Voltage vs V
CC
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I
2
C Interface
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
SDA
SCL
Start Condition
S
Stop Condition
P
PCA9546A
4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
The I
2
C bus is for two-way two-line communication between different ICs or modules. The two lines are a serialdata line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullupresistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is notbusy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the highperiod of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 4 ).
Figure 4. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while theclock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high isdefined as the stop condition (P) (see Figure 5 ).
Figure 5. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls themessage is the master, and the devices that are controlled by the master are the slaves (see Figure 6 ).
Figure 6. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is notlimited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDAline before the receiver can send an ACK bit.
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Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for ACK
NACK
ACK
A AS 1 1 1 0 A2 A1 A0 0
Start Condition
SDA
R/W ACK From Slave ACK From Slave
P
B0B1B2B3XXXX
Stop Condition
Slave Address Control Register
ANA
S 1 1 1 0 A2 A1 A0 1
SDA P
B3 B2 B1 B0
Start Condition R/W ACK From Slave NACK From Master Stop Condition
Slave Address Control Register
0 0 0 0
PCA9546A4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a mastermust generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. Thedevice that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stablelow during the high pulse of the ACK-related clock period (see Figure 7 ). Setup and hold times must be takeninto account.
Figure 7. Acknowledgment on the I
2
C Bus
Data is transmitted to the PCA9546A control register using the write mode shown in Figure 8 .
Figure 8. Write Control Register
Data is read from the PCA9546A control register using the read mode shown in Figure 9 .
Figure 9. Read Control Register
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
PCA9546A
4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range – 0.5 7 VV
I
Input voltage range
(2)
– 0.5 7 VI
I
Input current ± 20 mAI
O
Output current ± 25 mAContinuous current through V
CC
± 100 mAContinuous current through GND ± 100 mAD package 73DGV package 120DW package 57θ
JA
Package thermal impedance
(3)
°C/WPW package 108RGV package 51.38RGY package 50P
tot
Total power dissipation 400 mWT
stg
Storage temperature range – 65 150 °CT
A
Operating free-air temperature range – 40 85 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.3 5.5 VSCL, SDA 0.7 ×V
CC
6V
IH
High-level input voltage VA2 – A0, RESET 0.7 ×V
CC
V
CC
+ 0.5SCL, SDA – 0.5 0.3 ×V
CCV
IL
Low-level input voltage VA2 – A0, RESET – 0.5 0.3 ×V
CC
T
A
Operating free-air temperature – 40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics
PCA9546A4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
POR
Power-on reset voltage
(2)
No load, V
I
= V
CC
or GND V
POR
1.6 2.1 V5 V 3.64.5 V to 5.5 V 2.6 4.53.3 V 1.9V
pass
Switch output voltage V
SWin
= V
CC
, I
SWout
= – 100 µA V3 V to 3.6 V 1.6 2.82.5 V 1.52.3 V to 2.7 V 1.1 2V
OL
= 0.4 V 3 7I
OL
SCL, SDA 2.3 V to 5.5 V mAV
OL
= 0.6 V 6 10SCL, SDA ± 1SC3 – SC0, SD3 – SD0 ± 1I
I
V
I
= V
CC
or GND 2.3 V to 5.5 V µAA2 – A0 ± 1RESET ± 15.5 V 3 12Operating mode f
SCL
= 100 kHz V
I
= V
CC
or GND, I
O
= 0 3.6 V 3 112.7 V 3 105.5 V 0.3 1I
CC
Low inputs V
I
= GND, I
O
= 0 3.6 V 0.1 1 µA2.7 V 0.1 1Standby mode
5.5 V 0.3 1High inputs V
I
= V
CC
, I
O
= 0 3.6 V 0.1 12.7 V 0.1 1SCL or SDA input at 0.6 V,
8 15Other inputs at V
CC
or GNDSupply-current
ΔI
CC
SCL, SDA µAchange
SCL or SDA input at V
CC
– 0.6 V,
2.3 V to 5.5 V 8 15Other inputs at V
CC
or GNDA2 – A0 4.5 6C
i
V
I
= V
CC
or GND 2.3 V to 5.5 V pFRESET 4.5 5.5SCL, SDA 15 19C
io(OFF)
(3)
V
I
= V
CC
or GND, Switch OFF 2.3 V to 5.5 V pFSC3 – SC0, SD3 – SD0 6 84.5 V to 5.5 V 4 9 16V
O
= 0.4 V, I
O
= 15 mAR
ON
Switch on-state resistance 3 V to 3.6 V 5 11 20 Ω
V
O
= 0.4 V, I
O
= 10 mA 2.3 V to 2.7 V 7 16 45
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V
CC
), T
A
= 25 °C.(2) The power-on reset circuit resets the I
2
C bus logic with V
CC
< V
POR
. V
CC
must be lowered to 0.2 V to reset the device.(3) C
io(ON)
depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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I
2
C Interface Timing Requirements
Switching Characteristics
Interrupt and Reset Timing Requirements
PCA9546A
4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10 )
STANDARD MODE FAST MODEI
2
C BUS I
2
C BUS
UNITMIN MAX MIN MAX
f
scl
I
2
C clock frequency 0 100 0 400 kHzt
sch
I
2
C clock high time 4 0.6 µst
scl
I
2
C clock low time 4.7 1.3 µst
sp
I
2
C spike time 50 50 nst
sds
I
2
C serial-data setup time 250 100 nst
sdh
I
2
C serial-data hold time 0
(1)
0
(1)
µst
icr
I
2
C input rise time 1000 20 + 0.1C
b
(2)
300 nst
icf
I
2
C input fall time 300 20 + 0.1C
b
(2)
300 nst
ocf
I
2
C output fall time 10-pF to 400-pF bus 300 20 + 0.1C
b
(2)
300 nst
buf
I
2
C bus free time between stop and start 4.7 1.3 µst
sts
I
2
C start or repeated start condition setup 4.7 0.6 µst
sth
I
2
C start or repeated start condition hold 4 0.6 µst
sps
I
2
C stop condition setup 4 0.6 µst
vdL(Data)
Valid-data time (high to low)
(3)
SCL low to SDA output low valid 1 1 µst
vdH(Data)
Valid-data time (low to high)
(3)
SCL low to SDA output high valid 0.6 0.6 µsACK signal from SCL lowt
vd(ack)
Valid-data time of ACK condition 1 1 µsto SDA output lowC
b
I
2
C bus capacitive load 400 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal), in order tobridge the undefined region of the falling edge of SCL.(2) C
b
= total bus capacitance of one bus line in pF(3) Data taken using a 1-k Ωpullup resistor and 50-pF load (see Figure 10 )
over recommended operating free-air temperature range, C
L
≤100 pF (unless otherwise noted) (see Figure 10 )
FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT)
R
ON
= 20 Ω, C
L
= 15 pF 0.3t
pd
(1)
Propagation delay time SDA or SCL SDn or SCn nsR
ON
= 20 Ω, C
L
= 50 pF 1
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
WL
Pulse duration, RESET low 6 nst
rst
(1)
RESET time (SDA clear) 500 nst
REC(STA)
Recovery time from RESET to start 0 ns
(1) t
rst
is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,signaling a stop condition. It must be a minimum of t
WL
.
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PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
VCC
CL = 50 pF
(See Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tvd(ACK)
or tvdL
tvdH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or Repeat
Start Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
Two Bytes for Complete
Device Programming
I2C PORT LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDn, SCn
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Address
Bit 1
Address
Bit 6 ACK
(A)
BYTE DESCRIPTION
I2C address + R/W
Control register data
1
2
PCA9546A4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
A. C
L
includes probe and jig capacitance.B. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω,t
r
/t
f
≤30 ns.C. The outputs are measured one at a time, with one transition per measurement.
Figure 10. I
2
C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
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SCL
SDA
LEDx
RESET
30%
50%
50%
LED OFF
ACK or Read CycleStart
tREC tWL
trst
trst
PCA9546A
4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Reset Timing
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APPLICATION INFORMATION
PCA9546A
SD1
SDA Channel 0
Channel 1
Channel 2
Channel 3
See Note A
I2C/SMBus
Master SCL
RESET
SC1
SD2
SC2
SD3
SC3
SD0
SC0
VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
See Note A
See Note A
See Note A
SDA
SCL
A2
A1
A0
GND
15
14
3
8
1
2
13
16
12
11
10
9
7
6
5
4
PCA9546A4-CHANNEL I
2
C AND SMBus SWITCHWITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
Figure 12 shows an application in which the PCA9546A can be used.
A. Pin numbers shown are for the D, DGV, DW, PW, and RGY packages.
Figure 12. Typical Application
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
PCA9546AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADW ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADWR ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546ADWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCA9546A
PCA9546APW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546APWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PACKAGE OPTION ADDENDUM
www.ti.com 15-Aug-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
PCA9546APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546APWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PD546A
PCA9546ARGVR ACTIVE VQFN RGV 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD546A
PCA9546ARGVRG4 ACTIVE VQFN RGV 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD546A
PCA9546ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD546A
PCA9546ARGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PD546A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Aug-2013
Addendum-Page 3
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9546ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
PCA9546ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PCA9546ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PCA9546APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCA9546APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCA9546ARGVR VQFN RGV 16 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PCA9546ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9546ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
PCA9546ADR SOIC D 16 2500 333.2 345.9 28.6
PCA9546ADWR SOIC DW 16 2000 367.0 367.0 38.0
PCA9546APWR TSSOP PW 16 2000 367.0 367.0 35.0
PCA9546APWT TSSOP PW 16 250 367.0 367.0 35.0
PCA9546ARGVR VQFN RGV 16 2500 367.0 367.0 35.0
PCA9546ARGYR VQFN RGY 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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