ES29DL800E-90RWCI - Exel Microelectronics, Inc.

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

ES29LV400E

4Mbit(512Kx 8/256K x 16)

CMOS 3.0 Volt-only, Boot Sector Flash Memory

GENERAL FEATURES

• Single powe r su pp ly operation

- 2.7V -3.6V for read, program and erase operations

•Sector Structure

- 16Kbyte x 1, 8Kbyte x 2, 32Kbyte x 1 boot sectors

- 64Kbyte x 7sectors

• Top or Bottom boot block

- ES29LV400ET for Top boot block device

- ES29LV400EB for Bottom boot block device

• Package Options

- 48-pin TSOP

- 48-ball FBGA ( 6 x 8 mm )

- Pb-free packages

- All Pb-free products are RoHS-Compliant

• Low Vcc write inhibit

• Manufactured on 0.18um process technology

• Compatible with JEDEC standards

- Pinout and software compatible with single-power

supply flash standard

DEVICE PERFORMANCE

• Read access time

- 70ns / 90ns

• Program and era se time

- Program time : 6us/byte, 8us/word ( typical )

- Sector erase time : 0.7sec/sector ( typical )

• Power consumption (typical values)

- 200nA in standby or automatic sleep mode

- 7mA active read current at 5 MHz

- 15mA active write current during program or erase

• Minimum 100,000 prog ram/erase cycles per sector

• 20 Year data reten tion at 125

SOFTWARE FEATURES

• Erase Suspend / Erase Resume

• Data# poll and toggle for Pro gr a m/erase status

• Unlock Bypass program

• Autoselec t mode

• Auto-sleep mode after t

ACC

+ 30ns

HARDWARE FEATURES

• Hardware reset input pin ( RESET#)

- Provides a hardware reset to device

- Any internal device operation is terminated and the

device returns to read mode by the reset

• Ready/Busy# output pin ( R Y/BY#)

- Provides a program or erase operational status

about whether it is finished for read or still being

progressed

• Sector protection / unprotection ( RESET# , A9 )

- Hardware method of locking a sector to prevent

any program or erase operation within that sector

- Two methods are provided :

- In-system method by RESET# pin

- A9 high-voltage method for PROM programmers

• Temporary Sector Unprotection ( RESET# )

- Allows temporary unprotection of previously

protected sectors to change data in-system

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

The ES29LV400 is a 4 megabit, 3.0 volt-only flash

memory device, organized as 512K x 8 bits (Byte

mode) or 256K x 16 b its (Word mode) which is con-

figurable by BYTE#. Four boot sectors and seven

main sectors are provided : 16Kbytes x 1, 8Kbytes

x 2, 32Kbytes x 1 and 64Kbytes x 7. The device is

manufactured with ESI’s proprietary, high perfor-

mance and highly reliable 0.18um CMOS flash

technology. The device can be programmed or

erased in-system with standard 3.0 Volt Vcc supply

( 2.7V-3.6V) and can also be programmed in stan-

dard EPROM progra mmers. The d evice of fers min-

imum endurance of 100,000 program/erase cycles

and more than 10 ye ar s of da ta retent ion .

The ES29LV400 offers access time as fast as

70ns, allowing operation of high-speed micropro-

cessors without wait states. Three separate control

pins are provided to eliminate bus contention : chip

enable (CE#), write enable (WE#) and output

enable (OE#).

All program and erase operation are automatically

and internally performed and controlled by embed-

ded program/erase algorithms built in the device.

The device automatically generates and times the

necessary high-voltage pulses to be applied to the

cells, performs the verification, a nd count s the num-

ber of sequences. Some status bit s (DQ7 , DQ6 and

DQ5) read by data# polling or toggling between

consecutive read cycles provide to the users the

internal status of program/erase operation: whether

it is successfully done or still being progressed.

The ES29LV400 is completely compatible with the

JEDEC standard command set of single power sup-

ply Flash. Commands are written to the internal

command register using standard write timings of

microprocessor and data can be read out from the

cell array in the device with th e sam e way as u sed in

other EPROM or flash devices.

GENERAL PRODUCT DESCRIPTION

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Command

Analog Bias

Generator

Address Latch

BYTE#

CE#

OE#

A<0:17>

RESET#

Vcc

Vss

Chip Enable

Output Enable

Logic

Vcc Detector Timer/

Counter

Y-Decoder

X-Decoder

Y-Decoder

Cell Array

Data Latch/

Sense Amps

Input/Output

Buffers

Sector Switches

RY/BY#

Write

State

Machine

FUNCTION BLOCK DIAGRAM

PRODUCT SELECTOR GUIDE

Family Part Number ES29LV400

Voltage Range 2.7 ~ 3.6V

Speed Option 70 90

Max Access Time (ns) 70 90

CE# Access (ns) 70 90

OE# Access (ns) 35 40

DQ0-DQ15(A-1)

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

PIN DESCRIPTION

Pin Description

A0-A17 18 Addresses

DQ0-DQ14 15 Data Inputs/Outputs

DQ15/A-1 DQ15 (Data Input/Output, Word Mode)

A-1 (LSB Address Input, Byte Mode)

CE# Chip Enable

OE# Output Enable

WE# Write Enable

RESET# Hardware Reset Pin, Active Low

BYTE# Selects 8-bit or 16-bit mode

RY/BY# Ready/Busy Output

Vcc 3.0 volt-only single power supply

(see Product Selector Guide for speed options and voltage supply tolerances)

Vss Device Ground

NC Pin Not Connected Internally

LOGIC SYMBOL

DQ0 ~ DQ15

(A-1)

RY/BY#

BYTE#

RESET#

OE#

CE#

A0 ~ A17

WE#

18 16 or 8

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

CONNECTION DIAGRAM

48-Ball FBGA (6 x 8 mm)

(Top View, Balls Facing Down)

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

BYTE#

Vss

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

Vcc

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

Vss

CE#

48-Pin Standard TSOP

ES29LV400

A13 A12 A14 A15 A16

DQ15/

Vss

WE#

OE#CE#

A0A1

A11 DQ7 DQ14 DQ13 DQ6

NC NC

DQ5

DQ2

DQ0 DQ8 DQ9 DQ1

DQ10 DQ11 DQ3

DQ12 Vcc DQ4

A10

A B C D E F G H

BYTE# A-1

RESET#

RY/

A7 A17 A6

Vss

BY#

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Several device operational modes are provided in

the ES29LV400 device. Commands are used to ini-

tiate the device operations. They are latched and

stored into internal registers with the address and

data information needed to execute the device

operation.

The available device operational modes are listed

in Table 1 with the required input s, controls, and the

resulting outputs. Each operational mode is

described in further detail in the following subsec-

tions.

Read

The internal state of the device is set for the read

mode and the de vice is read y for r eading ar ray dat a

upon device power-up, or after a har dware reset. To

read the stored data from the cell array of the

device, CE# and OE# pins should be driven to V

while WE# pin remains at V

. CE# is the power

control and selects the device. OE# is the output

control and gates array data to the output pins.

Word or byte mode of output data is determined by

the BYTE# pin. No additional command is needed

in this mode to obtain array data. Standard micro-

processor read cycles that assert valid addresses

on the device address inputs produce valid data on

the device dat a output s. The device st ays at the read

mode until another operation is activated by writing

commands into the internal command re gister. Refer

to the AC read cycle timing diagrams for further

details ( Fig. 16 ).

Word/Byte Mode Configuration ( BYTE# )

The device data output can be configured by BYTE#

into one of two modes : word and byte modes. If the

BYTE# pin is set at log ic ‘1’, th e de vice is con figur ed

in word mode, DQ0 - DQ15 are active and controlled

by CE# and OE#. If the BYTE# pin is set at logic ‘0’,

the device is configured in byte mode, and only data

I/O pins DQ0 - DQ7 are active and controlled by CE#

and OE#. The data I/O pins DQ8 - DQ14 are tri-

stated, and the DQ15 pin is used as an input for the

LSB (A-1) address.

Standby Mode

When the device is not selected or activated in a

system, it needs to stay at the standby mode, in

which current consumption is greatly reduced with

outputs in the high impedance state.

DEVICE BUS OPERATIONS

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

The device enters the CMOS standby mode when

CE# and RESET# pins are both held at Vcc

0.3V.

(Note that this is a more restricted voltage range

than V

IH.

) If CE# and RESET# are held at V

, but

not within Vcc

0.3V, the device will be still in the

standby mode, but the standby current will be

greater than the CMOS standby current (0.2uA typi-

cally). When the device is in the standby mode, only

standard access time (t

) is required for read

access, before it is ready for read data. And even if

the device is deselected by CE# pin during erase or

programming oper ation, the device draws active cur-

rent until the operation is completely done. While the

device stays in the standby mode, the output is

placed in the high impedance state, independent of

the OE# input.

The device can enter the deep power-down mode

where current consumption is greatly reduced down

to less than 0.2uA typically by the following three

ways:

- CMOS standby ( CE#, RESET# = Vcc + 0.3V )

- During the device reset ( RESET# = Vss

+ 0.3V )

- In Autosleep Mode ( after t

ACC

+ 30ns )

Refer to the CMOS DC characteristics Table 7 for

further curr en t s pe cif ic ation.

Autosleep Mode

The device automatically enters a deep power-down

mode called the autosleep mode when addresses

remain stable for t

ACC

+30ns. In this mode, current

consumption is greatly reduced ( less than 0.2uA

typical ), regardless of CE#, WE# and OE# control

signals.

Writing Commands

To write a command or command sequences to ini-

tiate some operations such as program or erase, the

system must drive WE# and CE# to V

, and OE# to

. For program operations, the BYTE# pin deter-

mines whether the device accepts program data in

bytes or words. Refer to “BYTE# timings for Write

Operations” in the Fig. 19 for more information.

Unlock Bypass Mode

To reduce more the programming time, an unlock-

bypass mode is provided. Once the device enters

this mode, only two write cycles are required to ini-

tiate the programming operation instead of four

cycles in the normal program command sequences

which are composed of two unlock cycles, program

set-up cycle and the last cycle with the program data

and addresses. In this mode, two unlock cycles are

saved ( or bypassed ).

Sector Addresses

The entire memory space of cell array is divided into

a many of small sectors: 16Kbytes x 1, 8Kbytes x 2,

32Kbytes x 1 and 64Kbytes x 7 main sectors. In

erase operation, a single sector, multiple sectors, or

the entire device (chip erase) can be selected for

erase. The address space that each sector occupies

is shown in detail in the Table 3-4.

Autoselect Mode

Flash memories are intended for use in applications

where the local CPU alters memory contents. In

such applications, manufacturer and device identifi-

cation (ID) codes must be accessible while the

device resides in the target system ( the so called

“in-system program”). On the other hand, signature

codes have been typically accessed by raising A9

pin to a high voltage in PROM programmers. How-

ever, multiplexing high voltage onto address lines is

not the generally desired system design practice.

Therefore, in the ES29LV400 device an autoselect

command is provided to allow the system to access

the signature codes without any high voltage. The

conventional A9 high-voltage method used in the

PROM programers for signature codes are still sup-

ported in this device.

If the system writes the autoselect command

sequence, the device enters the Autoselect mode.

The system can then read some useful codes such

as manufact ur er an d de vic e ID fr om the int er na l re g-

isters on DQ7 - DQ0. Standard read cycle timings

apply in this mode. In the Autoselect mode, the fol-

lowing three informations can be accessed through

either autoselect command method or A9 high-volt-

age autoselect method. Refer to the Table 2.

Manufacturer ID

Device ID

Sector protection verify

Hardware Device Reset ( RESET# )

The RESET# pin provides a hardware method of

resetting the device to read array data. When the

RESET# pin is driven low for at least a period of t

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the

RESET# pulse The device also resets the internal

state machine to reading array data. The operation

that was interrupted should be reinitiated once after

the device is ready to accept another command

sequence, to ensure data integrity.

CMOS Standby during Device Reset

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at Vss

0.3V, the

device draws the greatly reduced CMOS standby

current ( I

CC4

). If RESET# is held at V

but not

within Vss

0.3V, the standby current will be greater.

RY/BY# and Terminating Operations

If RESET# is asserted during a program or erase

operation, the RY/BY# pin remains a “0” (busy) until

the internal reset operation is completed, which

requires a time of t

READY

(during Embedded Algo-

rithms). The system can thus monitor RY/BY# to

determine whether the reset operation is completed.

If RESET# is asserted when a program or erase

operation is not executing (RY/BY# pin is “1”), the

reset operation is completed within a time of t

READY

(not during Embedded Algorithms). The system can

read data after the RESET# pin returns to V

, which

requires a time of t

RH.

RESET# tied to the System Reset

The RESET# pin may be tied to the system reset cir -

cuitry. A system reset would thus also reset the

Flash memory, enab ling the system to read the boot-

up firmware from the Flash memory.Refer to the AC

Characteristics tables for RESET# parameters and

to Fig. 17 for the timing diagram.

SECTOR PROTECTION

The ES29LV400 features hardware sector protec-

tion. In the device, sector protection is performed on

the sector previously defined in the Table 3-4. Once

after a sector is protected, any program or erase

operation is not allowed in the protected sector. The

previously protected sectors must be unprotected by

one of the unprotect methods provided here before

changing data in those sectors.

Sector protection can be implemented via two

methods.

In-system protection

A9 High-voltage protection

To check whether the sector protection was suc-

cessfully executed or not, another operation called

“protect verification” needs to be performed after

the protection operation on a sector. All protection

and protect verifications provided in the device are

summarized in detail at the Table 1.

In-System Protection

“In-system protection”, the primary method,

requires V

(11.5V~12.5V) on the RESET# with

A6=0, A1=1, and A0=0. This method can be imple-

mented either in-system or via programming equip-

ment. This method uses standard microprocessor

bus cycle timing. Refer to Fig. 26 for timing diagram

and Fig. 2 for the protection algorithm.

A9 High-Voltage Protection

“High-voltage protection”, the alternate method

intended only for programming equipment, must

force V

(11.5~12.5V) on address pin A9 and con-

trol pin OE# with A6=0, A1=1 and A0=0. Refer to

Fig. 28 for timing diagram and Fig. 4 for the protec-

tion algorithm.

SECTOR UNPROTECTION

The previously protected sectors must be unpro-

tected before modifying any data in the sectors.

The sector unprotection algorithm unprotects all

sectors in parallel. All unpr otected sectors mu st first

be protected prior to the first sector unprotection

write cycle to avoid any over-erase due to the intrin-

sic erase characteristics of the protection cell. After

the unprotection operation, all previously protected

sectors will need to be individually re-protected.

Standard microprocessor bus cycle timings are

used in the unprotection and unprotect verification

operations. Three unprotect methods are provided

in the ES29LV400 device. All unprotection and

unprotect verification cycles are summarized in

detail at the Table 1.

In-system unprotection

A9 High-voltage unprotection

Temporary sector unprotection

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

In-System Unprotection

“In-system unprotection”, the primary method,

requires V

(11.5V~12.5V) on the RESET# with

A6=1, A1=1, and A0=0. This method can be imple-

mented either in-system or via programming equip-

ment. This method uses standard microprocessor

bus cycle timing. Refer to Fig. 26 for timing diagram

and Fig. 3 for the unprotection algorithm.

A9 High-Voltage Unprotection

“High-voltage unprotection”, the alternate method

intended only for programming equipment, must

force V

(11.5~12.5V) on address pin A9 and con-

trol pin OE# with A6=1, A1=1 and A0=0. Refer to

Fig. 29 for timing diagram and Fig. 5 for the unpro-

tection algorithm.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system.

The Sector Unprotect mode is activated by setting

the RESET# pin to V

(11.5V-12.5V). During this

mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector

addresses. Once V

is removed from the RESET#

pin, all the previously protected sectors are pro-

tected again. Fig. 1 shows the algorithm, and Fig. 25

shows the timing diagrams for this feature.

HARDWARE DATA PROTECTION

The ES29LV400 device provides some protection

measures against accidental erasure or program-

ming caused by spurious system level signals that

may exist during power transition. During power-up,

all internal registers and latches in the device are

cleared and the device automatically resets to the

read mode. In addition, with its internal state

machine built-in the device, any alteration of the

memory contents or any initiation of new operation-

can only occur after successful completion of spe-

cific command sequences. And several featu res are

incorporated to prevent inadvertent write cycles

resulting from Vc c po we r- up an d power-down transi-

tion or system noise.

Low Vcc Write inhibit

When Vcc is less than V

LKO

, the device does not

accept any write cycles. This protects data during

Vcc power-up and power-down.

The command register and all internal program/

erase circuits are disabled, and the devi ce resets to

the read mode. Subsequent writes are ignored until

Vcc is greater t han V

LKO

. The system must provide

proper signals to the control pins to prevent unin-

tentional writes when Vcc is greater than V

LKO

Wr ite Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical inhibit

Write cycles are inhibited by holding any one of

OE#=V

, CE#=V

or WE#=V

. To initiate a write

cycle, CE# and WE# must be a logical zero while

OE# is a logical one.

Power-up Write Inhibit

If WE#=CE#=V

and OE#=V

during power up,

the device does not accept any commands on the

rising edge of WE#. The internal state machine is

automatically reset to the read mode on power-up.

Notes:

1. All protected sectors are unprotected .

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect

Operation

START

RESET# = V

(Note 1)

Perform Erase or

Program Operations

RESET# = V

Temporary Sector

Unprotect Completed

(Note 2)

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Operation CE# OE# WE# RESET# Addresses

(Note 1)

DQ0

DQ7

DQ8~DQ15

BYTE#

= V

BYTE#

= V

Read LLHHA

OUT

DQ8~DQ14 = High-Z,

DQ15 = A-1

Write LHLHA

(Note 3) (Note 3)

Standby Vcc+

0.3V XX Vcc+

0.3V X High-Z High-Z

High-Z

Output Disable

Reset L H H H X High-Z High-Z

X X X L X High-Z High-Z

In-system

Sector Prote c t

(Note 2) LHL V

SA,A6=L,

A1=H,A0=L (Note 3) X X

Sector Unprotect

(Note 2) L H L V

SA,A6=H,

A1=H,A0=L (Note 3) X X

Temporary Sector

Unprotect X X X

(Note 3) (Note 3) High-Z

A9 High-Volt-

age Method

Sector pro te ct LV

LHSA,A9=V

A6=L,

A1=H,A0=L (Note 3) (Note 3) High-Z

Sector unp r ot e c t LV

SA,A9=V

A6=H,

A1=H,A0=L

Table 1. ES29LV400 Device Bus Operations

Legend:

L=Logic Low=VIL, H=Logic High =VIH, VID=11.5-12.5V, X=Don’t Care, SA=Secto r Address, AIN=Address In, DIN=Data In,

DOUT=Data Out

Notes:

1. Addresses are A17:A0 in word mode (BYTE#= VIH) , A17:A-1 in byte mode (BYTE#=VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment . See the “Sector Pro-

tection and Unprotection” section.

3. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.

Description CE# OE# WE# A17

A12

A11

A10 A9 A8

A7 A6 A5

A2 A1 A0 DQ8~DQ15 DQ7~DQ0

BYTE#

= V

BYTE#

= V

ManufactureID:ESI LLHXX

XLXLL X X4Ah

Device ID:

ES29LV400 LLHX X

X L X L H 22h X B9h(T),BAh(B)

Sector Protection

Verification LLHSAX

XLXHL X X 01h(protected)

00h(unprotected)

Legend:

T= Top Boot Block, B = Bottom Boot Block, L=Logic Low=VIL, H=Logic High=VIH, SA=Sector Address, X = Don’t care

Table 2. Autoselect Codes (A9 High-Voltage Method)

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Table 3. Top Boot Sector Addresses (ES29LV400ET)

Sector Sector address

A17~A12 Sector Size

(Kbytes/Kwords) (X8)

Address Range (X16)

Address Range Remark

SA0 000XXX 64/32 00000h~0FFFFh 00000h~07FFFh

Main Sector

SA1 001XXX 64/32 10000h~1FFFFh 08000h~0FFFFh

SA2 010XXX 64/32 20000h~2FFFFh 10000h~17FFFh

SA3 011XXX 64/32 30000h~3FFFFh 18000h~1FFFFh

SA4 100XXX 64/32 40000h~4FFFFh 20000h~27FFFh

SA5 101XXX 64/32 50000h~5FFFFh 28000h~2FFFFh

SA6 110XXX 64/32 60000h~6FFFFh 30000h~37FFFh

SA7 1110XX 32/16 70000h~77FFFh 38000h~3BFFFh

Boot Sector

SA8 111100 8/4 78000h~79FFFh 3C000h~3CFFFh

SA9 111101 8/4 7A000h~7BFFFh 3D000h~3DFFFh

SA10 11111X 16/8 7C000h~7FFFFh 3E000h~3FFFFh

Note:

The addresses range is A17:A-1 in byte mode (BYTE#=VIL) or A17:A0 in word mode (BYTE#=VIH).

Table 4. Bottom Boot Sector Addresses (ES29LV400EB)

Sector Sector address

A17~A12 Sector Size

(Kbytes/Kwords) (X8)

Address Range (X16)

Address Range Remark

SA0 00000X 16/8 00000h~03FFFh 00000h~01FFFh

Boot Sector

SA1 000010 8/4 04000h~05FFFh 02000h~02FFFh

SA2 000011 8/4 06000h~07FFFh 03000h~03FFFh

SA3 0001XX 32/16 08000h~0FFFFh 04000h~07FFFh

SA4 001XXX 64/32 10000h~1FFFFh 08000h~0FFFFh

Main Sector

SA5 010XXX 64/32 20000h~2FFFFh 10000h~17FFFh

SA6 011XXX 64/32 30000h~3FFFFh 18000h~1FFFFh

SA7 100XXX 64/32 40000h~4FFFFh 20000h~27FFFh

SA8 101XXX 64/32 50000h~5FFFFh 28000h~2FFFFh

SA9 110XXX 64/32 60000h~6FFFFh 30000h~37FFFh

SA10 111XXX 64/32 70000h~7FFFFh 38000h~3FFFFh

Note:

The addresses range is A17:A-1 in byte mode (BYTE#=VIL) or A17:A0 in word mode (BYTE#=VIH).

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

START

RESET# = V

Set up sector

address

COUNT = 1

Wait 1us

First Write

Cycle = 60h?

Sector Protect:

Write 60h to sec-

tor address with

A6 = 0, A1 = 1,

A0 = 0

Wait 150us

Verify Sector

Protect:

Write 40h to sec-

tor address with

A6 = 0, A1 = 1,

A0 = 0

Data = 01h?

Protect another

sector?

Remove V

from RESET#

Write r ese t

command

Sector Protect

complete

Temporary Sector

Unprotect Mode

COUNT=25?

Increment

COUNT

Read from sec-

tor address with

A6 = 0, A1 = 1,

A0 = 0

Device failed

Yes Yes

Reset

COUNT = 1

Yes

Figure 2. In-System Sector

Protect Algorithm

Yes

START

RESET# = V

Set up first sector

address

COUNT = 1

Wait 1us

First Write

Cycle = 60h?

Sector Unpro-

tect:

Write 60h to sec-

tor address with

A6 = 1, A1 = 1,

Wait 15ms

Verify Sector

Unprotect:

Write 40h to sec-

tor address with

A6 = 1, A1 = 1,

A0 = 0

Data = 00h?

Last sector

verified?

Remove V

from

RESET#

Write r ese t

command

Sector Unprotect

complete

Temporary Sector

Unprotect Mode

COUNT

=1000?

Increment

COUNT

Read from sec-

tor address with

A6 = 1, A1 = 1,

A0 = 0

Device failed

Yes Yes

Set up next

sector addr ess

Yes

All sectors

protected ?

Protect all sectors:

The indicated por-

tion of the sector

protect algorithm

must be performed

for all unprotected

sectors pri or to

issuing the first

sector unprotect

address

Yes

Figure 3. In-System Sector

Unprotect Algorithm

In-System Protection / Unprotection Method

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Excel Semiconductor inc.

Yes

SET A9=OE#= V

Remove V

from

A9 and Write

Reset Command

Sector Protection

Complete

Set Sector Addres s

A<17 :12>

CE#, A6, A0=V

RESET#, A1=V

Protect Another

Sector ?

Read Data

Data = 01h?

CE#,OE#,A6,A0=V

RESET#, A1 = V

SET WE# = V

Start

COUNT = 1

Wait 150 us

SET WE# = V

Increase COUNT

COUNT= 25?

Device failed

Yes

SET A9=OE#=V

Remove V

from A9 and

Write Reset Command

Sector Unprotection

Complete

Set Sector AddressA<17 :12>

Read Data

SET WE# = V

COUNT = 1

SET WE# = V

Start

Note: All sectors must be

previously protected.

Wait 15ms

CE#,OE#, A0=V

RESET#, A6, A1=V

Data = 00h?

The Last Sector

Address ?

Yes

Increase Sector

Address

Increase COUNT

Device failed

COUNT=1000?

CE#, A0=V

RESET#,

A6, A1=V

Figure 5. Sector Un-Protection Algorithm

(A9 High-Voltage Method)

Figure 4. Sector Protection Algorithm

(A9 High-Voltage Method)

A9 High-Voltage Method

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Writing specific address and data commands or

sequences into the command register initiates

device operations. Table 5 defines the valid register

command sequences. Note that writing incorrect

address and data values or writing them in the

improper sequence may place the device in an

unknown state. A reset command is required to

return the device to normal operation.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched

on the rising edge of WE# or CE#, whichever hap-

pens first. Refer to the AC Characteristics section for

timing diagrams.

READING ARRAY DATA

The device is automatically set to reading array data

after device power-up. No commands are required

to retrieve data. The device is ready to read array

data after completing an Embedded Program or

Embedded Erase algorithm.

After the device accepts an Erase Suspend com-

mand, the device enters the erase-suspend-read

mode, after which the system can read data from

any non-erase-suspended sector. After completing a

programming opera tio n in the Era se Suspen d mo de ,

the system may once again read array data with the

same exception. See the Erase Suspend/Erase

Resume Commands section for more information.

The system must issue the reset command to return

the device to the read (or erase-suspend-read)

mode if DQ5 goes high during an active program or

erase operation, or if the device is in the autoselect

mode. See the next section, Reset Command, for

more information.

See also Requirements for Reading Array Data in

the Device Bus Operations section for more info rma-

tion.The Read-Only Operations table provides the

read parameters, and Fig. 16 shows the timing dia-

gram

RESET COMMAND

Writing the reset command resets the device to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to

which the system was writing to the read mode.

Once erasure begins, however, the device ignores

reset commands until the operation is complete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device

to which the system was writing to the read mode. If

the program command sequence is written to a sec-

tor that is in the Erase Suspend mode, writing the

reset command returns the device to the erase-sus-

pend-read mode. Once programming begins, how-

ever, the device ignores reset commands until the

operation is complete.

The reset command may be written between the

sequence cycles in an autoselect command

sequence. Once in the autoselect mode, the reset

command must be written to return to the read

mode. If the device entered the autoselect mode

while in the Erase Suspend mode, writing the reset

command returns the device to the erase-suspend-

read mode.

If DQ5 goes high during a program or erase opera-

tion, writing the reset command return s the device to

the read mode (or erase-suspend-read mode if the

device was in Erase-Suspend).

COMMAND DEFINITIONS

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Table 5. ES29LV400 Command Definitions

Command Definitions

Command

Sequence

(Note 1)

Cycles

Bus Cycles (Notes 2~5)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Not e 6) 1 RA RD

Reset (Note 7) 1 XXX F0

Autoselect (N ot e 8)

Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 4A

Byte AAA 555 AAA

Device ID (Top) Word 4555 AA 2AA 55 555 90 X01 B9

Byte AAA 555 AAA X02

Device ID (Bottom) Word 4555 AA 2AA 55 555 90 X01 BA

Byte AAA 555 AAA X02

Sector Protect Verify

(Note 9) Word 4555 AA 2AA 55 555 90 (SA)X02 00/01

Byte AAA 555 AAA (SA)X04

Program Word 4555 AA 2AA 55 555 A0 PA PD

Byte AAA 555 AAA

Unlock Bypass Word 3555 AA 2AA 55 555 20

Byte AAA 555 AAA

Unlock Bypass Program (Note 10) 2 XXX A0 PA PD

Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00

Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Byte AAA 555 AAA AAA 555 AAA

Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Byte AAA 555 AAA AAA 555

Erase Suspend (Note 12) 1 XXX B0

Erase Resume (N ote 13) 1 XXX 30

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A17-A12 uniquely select any sector.

9. The data is 00h for an unprotected sector and 01h for a

protected sector.

10. The Unlock Bypass command is required prior to the Unlock-

Bypass Program command.

11. The Unlock Bypass Reset command is required to return

to the read mode when the device is in the unlock bypass

mode.

12. The system may read and program in non-erasing sectors,

or enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during

a sector erase operation.

13. The Erase Resume command is valid only during the Erase

Suspend mode.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

4. Data bits DQ15-DQ8 are don’t care in command sequences,

except for RD and PD

5. Unless otherwise noted, address bits A17-A11 are don’t cares.

6. No unlock or command cycles required when device is in

read mode.

7. The Reset command is required to return to the read mode

(or to the erase-suspend-read mode if previously in Erase

Suspend) when a device is in the autoselect mode, or if DQ5

goes high (while the device is providing status information).

8. The fourth cycle of the autoselect command sequence

is a read cycle. Data bits DQ15-DQ8 are don’t care. See the

Autoselect Command Sequence section for more information.

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AUTOSELECT COMMAND

The autoselect command sequen ce allows th e ho st

system to access the manufacturer and device

codes, and determine whether or not a sector is

protected, including information about factory-

locked or customer lockable version.

Table 5 shows the address and data requirements.

This method is an alternative to “A9 high-voltage

method” shown in Table 2, which is intended for

PROM programmers and requires V

on address

pin A9. The autoselect command sequen ce may be

written to an address within sector that is either in

the read mode or erase-suspend-read mode. The

auto-select command may not be written while the

device is actively programming or erasing. The

autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the autoselect command.

The device then enters the autoselect mode. The

system may read at any address any number of

times without initiating another autoselect com-

mand sequence .

Once after the device enters the auto-select mode,

the manufacture ID code ( 4Ah ) can be accessed

by one of two ways. Just one read cycle ( with A6,

A1 and A0 = 0 ) can be us ed. Or four consecutive

read cycles ( with A6 = 1 and A1, A0 = 0 ) for con-

tinuation codes (7Fh) and then another last cycle

for the code (4Ah) (with A6, A1 and A0 = 0) can be

used for reading the manufacturer code.

- 4Ah (One-cycle read)

- 7Fh 7Fh 7Fh 7Fh 4Ah (Five-cycle read)

The system must write the reset command to return

to the read mode (or erase-suspend-read mode if

the device was previously in Erase Suspend) .

Identifier Code Address Data

Manufacturer ID 00h 4Ah

Device ID 01h B9h(T),

BAh(B)

Sector Protect Verify (SA)02h 00 / 01

BYTE / WORD PROGRAM

The system may program the device by word or

byte, depending on the state of the BYTE# pin.

Programming is a four-bus-cycle operation. The

program command sequence is initiated by writing

two unlock write cycles, followed by the program

set-up command. The program address and data

are written next, which in turn initiate the Embedd ed

Program algorithm. The system is not required to

provide further contro ls or timing s. The d evice au to-

matically provides internally generated program

pulses and verifies the programmed cell margin.

Table 5 shows the address and data requirements

for the byte prog ram comman d sequence. Note tha t

the autoselect is unavailable while a programming

operation is in progress.

START

Verify Data

Increment Address

Write Program Com-

mand Sequence

Data Poll

from System

Last Address?

Yes

Programming

Completed

Embedded

Program

algorithm in

progress

Yes

Note: See Table 5 for program command sequence

Figure 6. Program Operation

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Program Status Bits : DQ7, DQ6 or RY/BY#

When the Embedded Program algorithm is com-

plete, the device then returns to the read mode and

addresses are no longer latched. The system can

determine the status of the program operation by

using DQ7, DQ6, or RY/BY#. Refer to the Write

Operation Status section Table 6 for information on

these status bits.

Any Commands Ignored during Program-

ming Operation

Any commands written to the device during the

Embedded Progr am alg orith m are ig nored . No te that

a hardware reset can immediately terminates the

program operation. The program command

sequence should be reinitiated once the device has

returned to the read mode, to ensure data integrity.

Programming from “0” back to “1”

Programming is allowed in any sequence and

across sector boundaries. But a bit cannot be pro-

grammed from “0” back to a ”1”. Attempting to do so

may cause the device to set DQ5 = 1, or cause the

DQ7 and DQ6 status bits to indicate the operation

was successful. However, a succeeding read will

show that the data is still “0”. Only erase operations

can convert a “0” to a “1”

Unlock Bypass

In the ES29LV400 device, an unlock bypass pro-

gram mode is provided for faster programming oper-

ation. In this mode, two cycles of program command

sequences can be saved. To enter this mode, an

unlock bypass ente r command should be first written

to the system. The unlock bypass enter command

sequence is initiated by first writing two unlock

cycles. This is followed by a third write cycle contain-

ing the unlock bypass command, 20h. The device

then enters the unlock-bypass program mode. A

two-cycle unlock bypass program command

sequence is all that is required to program in this

mode. The first cycle in this sequence contains the

unlock bypass program set-up command, A0h; the

second cycle contains the program address and

data. Additional data is programmed in the same

manner. This mode dispenses with the initial two

unlock cycles required in the standard program com-

mand sequence, resulting in faster total program-

ming time. Table 5 shows the requirements for the

command sequence.

During the unlock-bypass mode, only the unlock-

bypass program and unlock-bypass reset com-

mands are valid. To exit the unlock-bypass mode,

the system must issue the two-cycle unlock-bypass

reset command sequence. The first cycle must con-

tain the data 90h. The second cycle need to only

contain th e dat a 00h. The device th en returns to the

read mode.

- Unlock Bypass Enter Command

- Unlock Bypass Reset Command

- Unlock Bypass Program Co mmand

CHIP ERASE COMMAND

To erase the entire memory, a chip erase command

is used. This command is a six bus cycle operation.

The chip erase command sequence is initiated by

writing two unlock cycles, followed by a se t-up com-

mand. Two additional unlock write cycles are then

followed by the chip erase comm and, which in tu rn

invokes the Embedded Erase algorithm. The chip

erase command erases the entire memory includ-

ing all other sectors except the protected sectors,

but the internal erase operation is performed on a

single sector base.

Embedded Erase Algorithm

The device does not require the system to prepro-

gram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the

entire memory for an all zero data pattern prior to

electrical erase. The system is not required to pro-

vide any controls or timings during these opera-

tions. Table 5 shows the address and data

requirements for the chip erase command

sequence. Note that the autoselect is unavailable

while an erase operation is in progress

Erase Status Bits : DQ7, DQ6, DQ2, or RY/

BY#

When the Embedded Erase algorithm is complete,

the device returns to the read mode and addresses

are no longer latched. The system can determine

the status of the erase operation by using DQ7,

DQ6, DQ2, or RY/BY#. Refer to the Write Opera-

tion Status section Table 6 for information on these

status bits.

Commands Ignored during Erase Operation

Any command written during the chip erase opera-

tion are ignored. However, note that a hardware

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Rev.0B January 5, 2006

ES29LV400E

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reset immediately terminates the erase operation.If

that occurs, the chip erase command sequence

should be reinitiated once the device has returned to

reading array data. to ensure data integrity. Fig. 7

illustrates the algorithm for the erase operation.

Refer to the Erase and Program Operations tables in

the AC Characteristics section for parameters, and

Fig. 21 section for timing diagrams.

SECTOR ERASE COMMAND

By using a sector erase co mman d, a single sect or or

multiple sectors can be erased. The sector erase

command is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by th e ad dre ss of the se ctor to b e er ased , an d

the sector erase command. Table 5 shows the

address and data requirements for the sector erase

command sequence. Note that the autoselect is

unavailable while an erase operation is in progress.

Embedded Sector Erase Algorithm

The device does not require the system to prepro-

gram prior to erase. The Embedded Erase algorithm

automatically programs and verifies the entire mem-

ory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings these operations.

Sector Erase Time-out Window and DQ3

After the command sequence is written, a sector

erase time-out of 50us occurs. During the time-out

period, additional sector addresses and sector erase

commands may be written. Loading the sector erase

buffer may be done in any sequence, and the num-

ber of sectors may be from one sector to all sectors.

The time between these additional cycles must be

less than 50 us, otherwise the last address and com-

mand ma y not be acce pted, and er asure may be gin.

It is recommended that processor interrupts be dis-

abled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the

last Sector Erase command is written. The system

can monitor DQ3 to determine if the sector erase

timer has timed out (See the section on DQ3:Sector

Erase Timer.). The time-out begins from the rising

edge of the final WE# pulse in the command

sequence.

Any command other than Sector Erase or Erase Sus-

pend during the time-out period resets the device

to the read mode. The system must rewrite the

command sequence and any additional addresses

and command s.

Status Bits : DQ7,DQ6,DQ2, or RY/BY#

When the Sector Erase Embedded Erase algorithm

is complete, the device returns to reading array

data and addresses are no longer latched. Note

that while the Embedded Erase operation is in

progress, the system can read data from the non-

erasing sector. The system can determine the sta-

tus of the erase operation by reading

DQ7,DQ6,DQ2, or RY/BY# in the erasing sector.

Refer to the Write Operation Status section Table 6

for information on these status bits.

Valid Command during Sector Erase

Once the sector erase operation has begun, only

the Erase Suspend command is valid. All other

commands ar e ign o red. Howe ve r, note that a hard-

ware reset immediately terminates the erase oper-

ation. If that occurs, the sector era se command

START

No No

Yes

Write Erase

Command Sequence

(Notes 1,2)

Data Poll to

Erasing Bank

from System

Data = FFh?

Erasure Completed

Embedded

Erase

algorithm in

progress

Notes:

1. See Table 5 for erase command sequence

2. See the section on DQ3 for information on the sector erase timer

Figure 7. Erase Operation

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

sequence should be reinitiated once the device has

returned to reading array data, to ensure data integ-

rity.

Fig. 7 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations

tables in the AC Characteristics section for parame-

ters, and Fig. 21 s ec tion for timin g dia gr a ms .

ERASE SUSPEND/ERASE RESUME

An erase operation is a long-time operation so that

two useful commands are provided in the

ES29LV400 device Erase Suspend and Erase

Resume Commands. Through the two commands,

erase operation can be suspended for a while and

the suspended operation can be resumed later when

it is required. While the erase is suspended, read or

program operations can be performed by the system.

Erase Suspend Command, (B0h)

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then

read data from, or program data to, any sector not

selected for erasure. This command is valid only du r-

ing the sector erase operation, including the 50us

time-out period during the sector erase command

sequence. The Erase Suspend command is ignored

if written during the chip erase operation or Embed-

ded Program algorithm. When the Erase Suspend

command is written during the sector erase opera-

tion, the device requires a maximum of 20us to sus-

pend the erase operation. However, when the Erase

Suspend command is written during the sector erase

time-out, the device immediately terminates the time-

out period and suspends the erase operation.

Read and Program during Erase-Suspend-

Read Mode

After the erase operation has been suspended, the

device enters the erase-suspend-read mode. The

system can read data from or program data to any

sector not selected for erasure. (The device “erase

suspends” all sectors selected for er as ur e. )

Reading at any address within erase-suspended sec-

tors produces status information on DQ7-DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to

determine if a sector is actively erasing or is erase-

suspended. Refer to the Write Operation Status sec-

tion for information on these status bits (Table 6).

After an erase-suspended program operation is

complete, the device returns to the erase-suspend-

read mode. The system ca n determine the st atus for

the program operation using the DQ7 or DQ6 status

bits, just as in the standard Byte Program operation.

Refer to the Write Operation Status section for m ore

information.

Autoselect during Erase-Suspend- Read

Mode

In the erase-suspend-read mode, the system can

also issue the autoselected command sequence.

Refer to the Autoselect Mode and Autoselect Com-

mand Sequence section for details (Table 5).

Erase Resume Command

To resume the sector erase operation, the system

must write the Erase Resume command. Further

writes of the Resume command are ignored.

Another Erase Suspend command can be written

after the chip has resumed erasing.

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Rev.0B January 5, 2006

ES29LV400E

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Program

Unlock

Bypass

Auto-

select

Read

Chip

Erase

Sector

Erase

Erase-

suspend

Read

PA/PD

Resume

30 B0

Suspend

50us

SA/30

Done

COMMAND DIAGRAM

Figure 8. Command Diagram

Done

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

In the ES29LV400 device, several bits are provided

to determine the status of a program or erase oper-

ation: DQ2, DQ3, DQ5, DQ6, DQ7 and RY/BY#.

Table 6 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a

method for determining whethe r a program or erase

operation is complete or in progress. The device

also provides a hardware-based output signal, RY/

BY#, to determine whether an Embedded Program

or Erase operation is in progress or has been com-

pleted.

DQ7 (DATA# POLLING)

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Program or Erase

algorithm is in progress or co mpleted, or wh ether a

device is in Erase Suspend. Data# Polling is valid

after the rising edge of the final WE# pulse in the

command sequence.

During Programming

During the Embedded Program algorithm, the

device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status also

applies to programming during Erase Suspend.

When the Embedded Program algorithm is com-

plete, the device outputs the datum programmed to

DQ7. The system must provide the program

address to read valid status information on DQ7. If

a program address falls within a protected sector,

Data# Polling on DQ7 is active for approximately

250ns, then the device returns to the read mode.

During Erase

During the Embedded Erase algorithm, Data# Poll-

ing produces a “0” on DQ7. When the Embedded

Erase algorithm is complete, or if the device enters

the Erase Suspend mode, Data# polling produces a

“1” on DQ7. The system must provide an address

within any of the sectors selected for erasure to rea d

valid sta tus information on DQ7.

Erase on the Protected Sectors

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 1.8us,

then the device returns to the read mode. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and

ignores the selected se cto rs that are pr otected.

How-

ever, if the system reads DQ7 at an address within a

protected sector, the status may not be valid.

Data# Polling Algorithm

Just prior to the completion of an Embedded

Program or Ease operation, DQ7 may change

asynchronously with DQ0-DQ6 while Output

Enable(OE#) is asserted low. That is, this device

may change from providing status information to

valid data on DQ7. Depending on when the system

samples the DQ7 output, it may read the status or

valid data. Even if the device has completed the

program or erase operation and DQ7 has valid data,

the data outputs on DQ0-DQ7 will appear on

successive read cycles.

Table 6 shows the outputs for Data# Polling on DQ7.

Fig. 9 shows the Data# Polling algorithm. Fig. 22 in

the AC Characteristics section shows the Data#

Polling timing diagram.

WRITE OPERATION STATUS

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Rev.0B January 5, 2006

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RY/BY# ( READY/BUSY# )

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is

in progress or complete. The RY/BY# status is valid

after the rising edge of the final WE# pulse in the

command sequence. Since RY/BY# is an open-

drain output, several RY/BY# pins can be tied

together in parallel with a pull-up resistor to Vcc. If

the output is low (Busy), the device is actively eras-

ing or programmin g. (This includes prog ramming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the

standby mode, o r in t he er ase-suspend-read m od e .

Table 6 shows the outputs for RY/BY#.

DQ6 ( TOGGLE BIT I )

Toggle Bit I on DQ6 indicates whether an Embed-

ded Program or Erase algorithm is in progress or

complete, or whether the device has entered the

Erase Suspend mode. Toggle Bit I may be read at

any address, and is valid after the rising edge of the

final WE# pulse in the command sequence ( prior to

the program or erase op era t ion) , and durin g th e se c-

tor erase tim e-o ut. Durin g an Embe dde d Progr am or

Erase algorithm operatio n, successive read cycles to

any address cause DQ6 to toggle. The system may

use either OE# or CE# to control the read cycles.

When the operation is complete, DQ6 stops tog-

gling.

The system can use DQ6 and DQ2 together to

determine whether a sector is actively erasing or is

erase-suspended. When the device is actively eras-

ing (that is, the Embedded Erase algorithm is in

progress), DQ6 toggles. When the device enters the

Erase Suspend mode, DQ6 stops toggling. How-

ever, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended.

Alternatively, the system can use DQ7(see the sub-

section on DQ7:Data# Polling). DQ6 also toggles

during the erase-suspend-program mode, and stops

toggling once the Embedded Program algorithm is

complete.

Table 6 shows the outputs for Toggle Bit I on DQ6.

Fig. 10 shows the toggle bit algorithm. Fig. 23 in the

“AC Characteristics” section shows the toggle bit

timing diagrams. Fig. 24 shows the differences

between DQ2 and DQ6 in graphical form. See also

the subsection on DQ2 : (Toggle Bit II).

Toggling on the Protected Sectors

After an erase command sequence is written, if all

sectors selec ted for erasing are protected , DQ6 tog-

gles for approximately 1.8us, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected. If a program address falls within a

protected sector, DQ6 toggles for approximately

250ns after th e progr am command se qu ence is wr it-

ten, then returns to reading array data.

DQ2 ( TOGGLE BIT II )

The “Toggle Bit II” on DQ2, when used with DQ6,

indicates whether a particular sector is actively eras-

ing (that is, the Embedded Erase algorithm is in

progress), or whether that sector is erase-sus-

pended. Toggle Bit II is valid after the rising edge of

the final WE# pulse in the command sequence DQ2

START

Read DQ7-DQ0

Addr = VA

DQ7 = Data ?

Yes

FAIL

DQ5 = 1 ?

Read DQ7-DQ0

Addr = VA

DQ7 = Data ? Yes

PASS

Yes

Notes:

1. VA = Valid address for programming. During a sector erase

operation, a valid address is any sector address within the

sector being erased. During chip erase, a valid address in

any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5

Figure 9. Data# Polling Algorithm

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Rev.0B January 5, 2006

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Excel Semiconductor inc.

START

Read DQ7-DQ0

Toggle Bit

= Toggle ?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

DQ5 = 1 ?

Read DQ7-DQ0

Twice

Yes

Read DQ7-DQ0

Toggle Bit

= Toggle ?

Program/Erase

Operation

Complete

Note:

The system should recheck the toggle bit even if DQ5 = “1”

because the toggle bit may stop toggling as DQ5 changes to “1”.

See the subsections on DQ6 and DQ2 for more information.

toggles when the system reads at addresses within

those sectors that have been se lected for eras ure.

(The system may use either OE# or CE# to control

the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-

suspended. DQ6, by comparison, indicates

whether the device is actively erasing , or is in Erase

Suspend, but cannot distinguish which sectors are

selected for erasure. Thus, both status bits are

required for sector and mode information. Refer to

Table 6 to compare outputs for DQ2 and DQ6. Fig.

10 shows the toggle bit algorithm in flowchart form,

and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsec-

tion. Fig. 23 shows the toggle bit timing diagram.

Fig. 24 shows how differently DQ2 operates com-

pared with DQ6.

Reading Toggle Bits DQ6/DQ2

Refer to Fig. 10 for th e following discussio n. When-

ever the system initially begins reading toggle bit

stat us, it must read DQ7- DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typi-

cally, the system would note and store the value of

the toggle bit after the first read. After the second

read, the system would compare the new value of

the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or

erase operation. The system can read array data

on DQ7-DQ0 on the following read cycle. However,

if after the initial two read cycles , the system deter-

mines that the toggle bit is still toggling, the system

also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no

longer toggling, the device has successfully com-

pleted the program or erase operation. If it is still

toggling, the device did not completed the operatio n

successfully, and the system must write the reset

command to return to reading array data. The

remaining scenario is that the system initially deter-

mines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read

cycles, determining the status as described in the

previous paragraph. Alternatively, it may choose to

perform other system tasks. In this case, this sys-

tem must start at the beginning of the algorithm

when it returns to determine the st a tus of th e opera-

tion (top of Fig. 10).

Figure 10. Toggle Bit Algorithm

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

time-out also applies after each additional sector

erase command. When the time-out period is com-

plete, DQ3 switches from a “0” to a”1”. If the time

between additional sector era s e command s fro m the

system can be assumed to be less than 50us, the

system need not monitor DQ3. See also the Sector

Erase Command Sequence section. After the sector

erase command is written, the system should read

the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit

I) to ensure that the device has accepted the com-

mand sequence, and then read DQ3. If DQ3 is “1”,

the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) ar e ign ored

until the erasure operation is complete. If DQ3 is “0”,

the device will accept additional sector erase com-

mands. To ensure the command has been acce pted,

the system software should check the status of DQ3

prior to and following each subsequent sector erase

command. If DQ3 is high on the second status

check, the last command might not have been

accepted. In Table 6, DQ3 status operation is well

defined and summ arized with other status bits, DQ7,

DQ6, DQ5, and DQ2.

DQ5 ( EXCEEDED TIMING LIMITS )

DQ5 indicates whether the program or erase time

has exceed ed a spec ified internal pulse count limit.

Under these conditions DQ5 produces a “1”, indi-

cating that the program or erase cycle was not suc-

cessfully completed. The device may output a “1”

on DQ5 if the system tries to program a “1” to a

location that was previously programmed to “0”

Only an erase operation ca n chan ge a “0 ” ba ck to a

“1”. Under this condition , the device halts th e opera-

tion, and when the timing limit has been exceeded,

DQ5 produces a ”1”. Under both these conditions,

the system m ust write the reset command t o return

to the read mode.

DQ3 ( SECTOR ERASE TIMER )

After writing a sector erase command sequence,

the system may read DQ3 to determine whether or

not erasure has begun. (The sector erase time

does not apply to the chip erase command.) If addi-

tional sectors are selecte d for erasure, the entire

Table 6. Write Operation Status

Notes :

1. DQ5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limit s. Refer to the

section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status informa tion. Refer to the appropriate subsection for further details.

Status DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/

BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Sus-

pend Mode

Erase-Suspend-

Read

Erase Suspended

Sector 1 No toggle 0 N/A Toggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

20ns 20ns

+0.8V

Vss-0.5V

Vss-2.0V

20ns

20ns 20ns

20ns

2.0V

Vcc+0.5V

Vcc+2.0V

Negative Overshoot

Positive Overshoot

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages ..............................................-65oC to +150oC

Ambient Temperature

with Power Appli e d ... .. ..................... ... .. ... ... ......-65oC to +125oC

Voltage with Respect to Ground

Vcc (Note 1) ..........................................................-0.5V to +4.0V

A9, OE# and RESET# (Note 2) ........................-0.5V to +12.5V

All other pins (Note 1) ...................................-0.5V to Vcc + 0.5V

Output Short Circuit Current (Note 3) ................. 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage

transitions, input or I/O pins may overshoot Vss to -2.0V fo r per-

iods of up to 20ns. Maximum DC voltage on input or I/O pins is

Vcc+0.5V. See Fig. 11. During voltage transition, input or I/O pins

may overshoot to Vcc+2.0V for periods up to 20ns. See Fig. 11.

2. Minimum DC input voltage on pins A9, OE# and RESET# is -0.5V

. During voltage transitions, A9, OE# and RESET# may overshoot

Vss to -2.0V for periods of up to 20ns. See Fig. 11. Maximum DC

input voltage on pin A9 is +12.5V which may overshoot to +14.0V

for periods up to 20ns.

3. No more than one output may be shorted to ground at a time. Du-

ration of the short circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditi ons ab-

ove those indicated in the operational sections of this datasheet is

not implied. Exposure of the device to absolute maximum ra ting con-

ditions for extended periods may affect device reliability.

OPERAT ING RANGES

Industrial (I) Devices

Ambient Temperature (T

).................................-40

C to +85

Commercial Devices

Ambient Temperature (T

)....................................0

C to +70

Vcc Supply Voltages

Vcc for all devices ............................................2.7V to 3.6V

Operating ranges define those limits between which the functio-

nality of the device is guaranteed.

Figure 11. Maximum Overshoot Waveform

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

DC CHARACTERISTICS

Table 7. CMOS Compatible

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Load Current VIN=Vss to Vcc

Vcc=Vcc max + 1.0 uA

ILIT A9 Input Load Current Vcc=Vcc max; A9=12.5V 35 uA

ILR RESET# Input Load Current Vcc=Vcc max; RESET#=12.5V 35 uA

ILO Output Leakage Current Vout=Vss to Vcc,

Vcc=Vcc max + 1.0 uA

ICCI Vcc Active Read Current

(Notes 1,2)

CE#=VIL OE#=VIH, Byte

mode

5MHz 7 12

1MHz 2 4

CE#=VIL, OE#=VIH, Word

mode 5MHz 7 12

1MHz 2 4

ICC2 Vcc Active Write Current (Note 2,3) CE#=VIL, OE#=VIH, WE#=VIL 15 30 mA

ICC3 Vcc Standby Current (Note 2) CE#, RESET#= Vcc+0.3V 0.2 10 uA

ICC4 Vcc Reset Current (Note 2) RESET#=Vss + 0.3V 0.2 10 uA

ICC5 Automatic Sleep Mode

(Notes2,4) VIH = Vcc + 0.3V

VIL = Vss + 0.3V 0.2 10 uA

VIL Input Low Voltage -0.5 0.5 V

VIH Input High Voltage 0.7xVcc Vcc+0.3 V

VID Voltage for Autoselect and

Temporary Sector U nprotect Vcc = 3.0V + 10% 11.5 12.5 V

VOL Output Low Voltage IOL = 4.0 mA, Vcc = Vcc min 0.45 V

VOH1 Output High Voltage IOH = -2.0mA, Vcc = Vcc min 0.85 Vcc V

VOH2 IOH = -100 uA, Vcc = Vcc min Vcc - 0.4

VLKO Low Vcc Lock-Out Voltage (Note 5) 2.3 2.5 V

Notes:

1. The Icc current listed is typically less than 2 mA/MHz, w ith OE# at V

, Typical condition : 25

C, Vcc = 3V

2. Maximum I

specifications are tested with Vcc = Vcc max.

3. Icc active while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

ACC

+ 30ns. Typical sleep mode current is

200 nA.

5. Not 100% tested.

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

DC CHARACTERISTICS

Zero-Power Flash

Figure 12. Icc1 Current vs. Time (Showing Active and Automatic Sleep Currents)

0 500 1000 1500 2000 2500 3000 3500 4000

Time in ns

Supply Current in mA

Icc1 (Active Read current)

Icc5 (Automatic Sleep Mode)

012345

Frequency in MHz

Supply Current in mA

2.7V

3.6V

Figure 13. Typical Icc1 vs. Frequency

Note:

Addresses are switching at 1 MHz

Note:

T = 25

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Test Condition 70 90

Output Load 1TTL gate

Output Load Capacitance, CL (including jig

capacitance) 30 pF 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0 - 3.0 V

Input timing measurement reference levels 1.5 V

Output timing measurement reference levels 1.5 V

Table 8. Test Specifications

Key To Switching Waveforms

Device

Under

Test

3.3V

2.7k

Ω

6.2k

Ω

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Figure 14. Test Setup

Note

: Diodes are IN3064 or equivalent

Measurement Level Output

Input

3.0V

0.0V

1.5V 1.5V

Figure 15. Input Waveforms and Measurement Levels

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

AC CHARACTERISTICS

Table 9. Read -Only Operations

Parameter Description Test Setup Speed Options Unit

JEDEC Std. 70 90

tAVAV tRC Read Cycle Time(Note 1) Min 70 90 ns

tAVQV tACC Address to Output Delay CE#,OE#=VIL Max 70 90 ns

tELQV tCE Chip Enable to Output Dela y OE#=VIL Max 70 90 ns

tGLQV tOE Output Enable to Output Delay Max 30 35 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns

tAXQX tOH Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First Min 0 ns

tOEH Output Enable Hold

Time (Note 1) Read Min 0 ns

Toggle and Data# Polling Min 10 ns

Note :

1. Not 100% tested

Address

OE#

WE#

OUTPUTS

Address St able

High-Z Output Valid

CE#

OEH

RESET#

RY/BY# 0V

ACC

Figure 16. Read Operation Timings

High-Z

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

CE#,OE#

RESET#

RY/BY# 0V

READY

CE#,OE#

RESET#

RY/BY#

READY

Figure 17. Reset Timings

(B) During Embedded Algorithm

(A) Not During Embedded Algorithm

AC CHARACTERISTICS

Table 10. Hardware Reset ( RESET #)

Parameter Description All Speed Options Unit

JEDEC Std.

tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode

(See Note) Max 20 us

tReady RESET# Pin Low (Not During Embedded Algorithms) to Read

Mode (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 us

tRB RY/BY# Recovery Time Min 0 ns

Note :

Not 100% tested

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Address Input

CE#

BYTE#

FHQV

DQ15

Output

Data Output

(DQ0-DQ7)

Data Output

(DQ0-DQ7) Data Output

(DQ0-DQ14)

Address Input DQ15

Output

Data Output

(DQ0-DQ14)

FLQZ

ELFL

ELFH

OE#

DQ15/A-1

BYTE#

DQ0-DQ14

DQ15/A-1

BYTE# Switching

Switching from

word to byte mode

The falling edge of the last WE# signal

CE#

BYTE#

WE#

SET

HOLD

)

Figure 19. BYTE# Timing for Write Operations

Figure 18. BYTE# Timing for Read Operations

AC CHARACTERISTICS

Table 11. Word/Byte Configuration (BYTE#)

Note :

Refer to the Erase/Program Operations table for t

and t

specifications.

Parameter Description 70 90 Unit

JEDEC Std.

ELFL

ELFH

CE# to BYTE# Switching Low or High Max 5 ns

FLQZ

BYTE# Switching Low to Output HIGH Z Max 16 ns

FHQV

BYTE# Switching High to Output Active Min 70 90 ns

BYTE# Switching

Switching from

byte to word mode

DQ0-DQ14

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

AC CHARACTERISTICS

Table 12. Erase and Program Operations

Parameter Description 70 90 Unit

JEDEC Std.

tAVAV tWC Write Cycle Time (Note 1) Min 70 90 ns

tAVWL tAS Address Setup Time Min 0 ns

tASO Address Setup Time to OE# lo w during toggle bit polling Min 15 ns

tWLAX tAH Address Hold Time Min 45 ns

tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns

tDVWH tDS Data Setup Time Min 35 45 ns

tWHDX tDH Data Hold Time Min 0 ns

tOEPH Output Enable High during toggle bit polling Min 20 ns

tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 35 ns

tWHDL tWPH Write Pulse Width High Min 30 ns

tSR/W Latency Between Read and Write Operations Min 0 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 6 us

Word Typ 8

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

tVCS Vcc Setup Time (Note 1) Min 50 us

tRB Write Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

NOTES :

1. PA = program address, PD = program data, Dout is the true data at the program address.

2. Illustration shows device in word mode.

Address

OE#

WE#

DATA

555h

CE#

Vcc

RY/BY#

Program Command Sequence (last two cycles)

PA PA

VCS

BUSY

WHWH1

Status Dout

A0h PD

WPH

Read Status Data(last two cycles)

Figure 20. Program Operation Timings

AC CHARACTERISTICS

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Address

OE#

WE#

DATA

2AAh

CE#

Vcc

RY/BY#

Erase Command Sequence (last two cycles)

SA VA

VCS

BUSY

WHWH2

Progress Complete

55h 30h

WPH

Read Status Data

555h for chip erase

10h for chip erase

NOTES :

1. SA = sector address(for Sector Erase), VA = valid address for reading status data(see “Write Operation Status”).

2. These waveforms are for the word mode.

Figure 21. Chip/Sector Erase Operation Timings

AC CHARACTERISTICS

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Address

OE#

WE#

DQ0-DQ6

CE#

RY/BY#

Figure 22. Data# Polling Timings (During Embedded Algorithms)

VA VA

BUSY

HIGH-Z

Valid Data

ACC

OEH

True

Complement

Status Data

Complement

Status Data

True Valid Data

HIGH-Z

DQ7

NOTE : VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle

AC CHARACTERISTICS

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Address

OE#

WE#

DQ6/DQ2

CE#

RY/BY#

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

OEPH

AHT

ASO

OEH

Valid Status Valid Status Valid Status Valid DataValid Data

CEPH

AHT

(first read) (second read) (stops toggling)

NOTE : VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

DQ6

WE#

Enter

Embedded

Erasing

DQ2

Enter

Suspend

Erase Erase

Suspend

Read

Enter Erase

Suspend

Program

Erase

Suspend

Program

Erase

Suspend

Read

Erase

Resume

Erase Erase

Complete

Figure 24. DQ2 vs. DQ6

NOTE : DQ2 toggles only when read at an address within an erase- suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

AC CHARACTERISTICS

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Rev.0B January 5, 2006

ES29LV400E

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CE#

RESET#

RY/BY#

RSP

Figure 25. Temporary Sector Unprotect Timing Diagram

VIDR

Program or Erase Command Sequence t

VIDR

RRB

Vss,V

or V

WE#

Parameter Description All Speed Options Unit

JEDEC Std.

VIDR

Rise and Fall Time (See Note) Min 500 ns

RSP

RESET# Setup Time for Temporary Sector Unprotect Min 4 us

RRB

RESET# Hold T ime from RY/BY# High for Temporary Sector Unprotect Min 4 us

AC CHARACTERISTICS

Table 13. Temporary Sector Unprotect

Note:

Not 100% tested.

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

OE#

WE#

CE#

Valid*

60h 40h

Sector Protect : 150us,

Sector Unprotect: 15ms

Figure 26. Sector Protect & Unprotect Timing Diagram

60h

Valid* Valid*

Status

Sector Protect or Unprotect

RESET#

1us

SA,A6,

A1,A0

* For sector protect, A6=0,A1=1,A0=0 For sector unprotect, A6=1,A1=1,A0=0

AC CHARACTERISTICS

Verify

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

AC CHARACTERISTICS

Table 14. Alternate CE# Controlled Erase and Program Operations

Parameter Description 70 90 Unit

JEDEC Std.

tAVAV tWC Write Cycle Time( Note 1) Min 70 90 ns

tAVWL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 ns

tDVEH tDS Data Setup Time Min 35 45 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 35 ns

tELEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 6 us

Word Typ 8

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

Notes :

1. Not 100% tested

2. See the “Erase And Programming Performance” section for more information.

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Address

OE#

WE#

RESET#

CE#

RY/BY#

Figure 27. Alternate CE# Controlled

Write(Erase/Program) Operation Timings

BUSY

DQ7#

WHWH1 or 2

GHEL

A0 for program

55 for erase

DATA

OUT

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

PD for program

SA for sector erase

555 for chip erase

CPH

NOTES :

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data

3. DQ7# is the complement of the data written to the device. Dout is the data written to the device.

4. Waveforms are for the word mode.

AC CHARACTERISTICS

Data Polling

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

A<17:12>

OE#

WE#

RESET#

CE#

Vcc

Figure 28. Sector Protection timings (A9 High-Voltage Method)

WPP1

0x01

SAx

SAy

OESP

CSP

VIDR

A<0>

A<1>

A<6>

A<9> V

Table 15. AC CHARACTERISTICS

Parameter Description Value Unit

tOE Output Enable to Output Delay Max 30/35 ns

tVIDR Voltage Transition Time Min 500 ns

tWPP1 Write Pulse Width for Protection Operation Min 150 us

tWPP2 Write Pulse Width for Unprotection Operation Min 15 ms

tOESP OE# Setup Time to WE# Active Min 4 us

tCSP CE# Setup Time to WE# Active Min 4 us

tST Voltage Setup Time Min 4 us

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ES29LV400E

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A<17:12>

OE#

WE#

RESET#

CE#

Vcc

Figure 29. Sector Unprotection timings (A9 High-Voltage Method)

WPP2

0x00

SA0

SA1

OESP

CSP

VIDR

A<0>

A<1>

A<6>

A<9> V

NOTE :

It is recommended to verify for all sectors.

AC CHARACTERISTICS

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Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 10 sec Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time 8 sec

Byte Program Time 6 150 u s

Exclude system level overhead (Note 5)

Word Program Time 8 210 us

Chip Program Time (Note 3) Byte Mode 3.1 9.3 sec

Word Mode 2.1 6.3

Notes:

1. Typical program and erase times assume the following conditions: 25oC, 3.0V Vcc, 10,000 cycles. Additionally, programming

typicals assume checkerboard pattern.

2. Under worst case conditions of 90oC, Vcc = 2.7V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times

listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two-or-four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles

Description Min Max

Input voltage with respect to Vss on all pi ns except I/O pins (i ncluding A9, OE#, and RESET#) - 1.0V 12.5 V

Input voltage with respect to Vss on all I/O pins - 1.0V Vcc + 1.0 V

Vcc Current - 100 mA +100 mA

Note: Includes all pins except Vcc. Test conditions: Vcc = 3.0 V, one pin at a time

Parameter Symbol Parameter Desc ription Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 TSOP 6 7.5 pF

FBGA 4.2 5.0 pF

COUT Output Capacitance VOUT = 0 TSOP 8.5 12 pF

FBGA 5.4 6.5 pF

CIN2 Control Pin Capacitance VIN = 0 TSOP 7.5 9 pF

FBGA 3.9 4.7 pF

Table 17. LATCHUP CHARACTERISTICS

Table 18. TSOP, SO, AND BGA PACKAGE CAPACITANCE

Notes:

1. Sampled, not 100% tested. 2. Test conditions TA = 25oC, f=1.0MHz.

Parameter Description Test conditions Min Unit

Minimum Pattern Data Retention Time 150oC10 Years

125oC20 Years

Table 19. DATA RETENTION

Table 16. ERASE AND PROGRAMMING PERFORMANCE

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

PARALLEL TO

SEATING PLANE

θ°

0.25MM

(0.0098”) BSC

SEE DETAIL A

DETAIL A

-A- -B-

SEE DETAIL B

----

---- 1+

0.10 C

-C-

SEATING

PLANE

GAUGE

PLANE

-X-

e/2

X = A OR B

(c)

WITH

PLATING

BASE

METAL

DETAIL B

SECTION B-B

0.08MM (0.0031”)

CA-B S

Package TS 48

JEDEC MO-142 (B) DD

Symbol MIN NOM MAX

A - - 1.20

A1 0.05 - 0.15

A2 0.95 1.00 1.05

b1 0.17 0.20 0.23

b 0.17 0.22 0.27

c1 0.10 - 0.16

c 0.10 - 0.21

D 19.80 20.00 20.20

D1 18.30 18.40 18.50

E 11.90 12.00 12.10

e 0.50 BASIC

L 0.50 0.60 0.70

R 0.08 - 0.20

N48

θ0°5°3°

NOTES:

1. Controlling dimensions are in millimeters(mm). (Dimensioning

and tolerancing conforms to ANSI Y14.5M-1982)

2. Pin 1 identifier for standard pin out (Die up).

3. Pin 1 identifier for reverse pin out (Die down): Ink or Laser mark

4. To be determined at the seating plane. The seating plane is def-

ined as the plane of contact that is made when the package lea-

ds are allowed to rest freely on a flat horizontal surface.

5. Dimension D1 and E do not include mold protrusion. Allowable

mold protrusion is 0.15mm (0.0059”) per side.

6. Dimension b does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.0031”) total in excess

of b dimension at max. material condition. Minimum space

between protrusion and an adjacent lead to be 0.07mm

(0.0028”).

7. These dimensions apply to the flat section of the lead between

0.10mm (0.0039”) and 0.25mm (0.0098”) from the lead tip.

8. Lead coplanarity shall be within 0.10mm (0.004”) as measured

from the seating plane.

9. Dimension “e” is measured at the centerline of the leads.

PHYSICAL DIMENSIONS

48-Pin Standard TSOP (measured in millimeters)

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

PACKAGE xFBD 048

JEDEC N/A

6.00 mm x 8.00 mm PACKAGE

SYMBOL MIN NOM MAX NOTE

A 1.10 OVERALL THICK

NESS

A1 0.21 0.25 0.29 BALL HEIGHT

A2 0.7 0.76 0.82 BODY THICKNESS

D8.00 BSC BODY SIZE

E6.00 BSC BODY SIZE

D1 5.60 BSC BALL FOOTPRINT

E1 4.00 BSC B AL L FOO T PRINT

MD 8 ROW MATRIX SIZED

DIRECTION

ME 6 ROW MATRIX SIZED

DIRECTION

N 48 TOTAL BALL COUNT

b 0.30 0.35 0.40 BALL DIAMETER

e 0.80 BSC BAL L PITCH

SD / SE 0.4 0 BS C SOLDER BALL

PLACEMENT

NOTES:

1. Dimensioning and tolerancing per ASME Y14.5M-1994

2. All dimensions are in millimeters.

3. Ball position designation per JESD 95-1, SPP-010.

4. e represents the solder ball grid pitch.

5. Symbol “MD” is the ball row matrix size in the “D” direction.

Symbol “ME” is the ball column matrix size in the “E” direct-

ion. N is the maximum number of solder balls for matrix si-

ze MD X ME.

6. Dimension “b” is measured at the maximum ball diameter

in a plane parallel to datum Z.

7. SD and SE are measured with respect to datums A and B

and define the position of the center solder ba ll in the out-

er row. When there is an odd number of solder balls in the

outer row parallel to the D or E dimension, respectively, SD

or SE = 0.000 when there is an even number of solder balls

in the outer row, SD or SE = e/2

8. “X” in the package variations denotes part is outer qualifi-

cation.

9. “+” in the package drawing indicate the theoretical center

of depopulated balls.

10. For package thickness A is the controlling dimension.

11. A1 corner to be indentified by chamfer, ink mark, metalli-

zed markings indention or other means.

HFEG DCB A

A1 CORNER INDEX MARK 11 B

SE 7

PIN 1 ID.

SD 7

0.20

0.08 Z

0.25 Z

(4x)

0.15 M Z A B

0.08 M Z

PHYSICAL DIMENSIONS

48-Ball FBGA (6 x 8 mm)

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

ORDERNG INFORMATION

Standard Products

ESI standar d product s are availabl e in several p ackage and oper ating ranges. Th e order nu mber (Valid Combi-

nation) is formed by a combination of the following:

TEMPERATURE RANGE

Blank : Commercial (0

C to + 70

I : Industrial (- 40

C to + 85

PACKAGE TYPE

T : Standard TSOP (48-pin), W : FBGA(48-ball)

SPEED OPTION

70 : 70ns 90 : 90ns

SECTOR ARCHITECTURE

Blank : Uniform sector

T : Top sector

B : Bottom sector

EXCEL SEMICONDUCTOR

COMPONENT GROUP

29 : Flash Memory

TECHNOLOGY

D : 0.18um E : 0.18um (2nd Gen.) F : 0.13um

DENSITY & ORGANIZATION

400 : 4M ( x8 / x16) 800 : 8M ( x8 / x16)

160 : 16M ( x8 / x16) 320 : 32M ( x8 / x16)

640 : 64M ( x8 / x16)

POWER SUPPLY AND INTERFACE

F : 5.0V LV : 3.0V

DL : 3.0V, Dual Bank DS : 1.8V, Dual Bank

BDS : 1.8V, Burst mode, Dual Bank

ES 29 LV 400 X X - XX X X X X

Pb-free

C : Pb product

G : Pb-free product

VOLTAGE RANGE

Blank : 2.7 ~ 3.6V

R : 3.0 ~ 3.6V

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Part No.

ES29LV400ET-70TGI

ES29LV400ET-70TCI

ES29LV400EB-70TGI

ES29LV400EB-70TCI

ES29LV400ET-90TGI

ES29LV400ET-90TCI

ES29LV400EB-90TGI

ES29LV400EB-90TCI

Speed

70ns

90ns

Vcc

2.7 - 3.6V

Boot Sector

Top

Bottom

Top

Bottom

Package

48-pin TSOP

Pb-free

Ball Pitch/Size Body Size

Product Selection Guide

Industrial Device

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Part No.

ES29LV400ET-70WGI

ES29LV400ET-70WCI

ES29LV400EB-70WGI

ES29LV400EB-70WCI

ES29LV400ET-90WGI

ES29LV400ET-90WCI

ES29LV400EB-90WGI

ES29LV400EB-90WCI

Speed

70ns

90ns

Vcc

2.7 - 3.6V

Boot Sector

Top

Bottom

Top

Bottom

Package

48-Ball FBGA

Pb-free

Ball Pitch/Size

0.8mm/0.3mm

Body Size

6mm x 8mm

Product Selection Guide

Industrial Device

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Part No.

ES29LV400ET-70TG

ES29LV400ET-70TC

ES29LV400EB-70TG

ES29LV400EB-70TC

ES29LV400ET-90TG

ES29LV400ET-90TC

ES29LV400EB-90TG

ES29LV400EB-90TC

Speed

70ns

90ns

Vcc

2.7 - 3.6V

Boot Sector

Top

Bottom

Top

Bottom

Package

48-pin TSOP

Pb-free

Ball Pitch/Size Body Size

Product Selection Guide

Commercial Device

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Part No.

ES29LV400ET-70WG

ES29LV400ET-70WC

ES29LV400EB-70WG

ES29LV400EB-70WC

ES29LV400ET-90WG

ES29LV400ET-90WC

ES29LV400EB-90WG

ES29LV400EB-90WC

Speed

70ns

90ns

Vcc

2.7 - 3.6V

Boot Sector

Top

Bottom

Top

Bottom

Package

48-Ball FBGA

Pb-free

Ball Pitch/Size

0.8mm/0.3mm

Body Size

6mm x 8mm

Product Selection Guide

Commercial Device

ESI

Rev.0B January 5, 2006

ES29LV400E

Excel Semiconductor inc.

Excel Semiconductor Inc.

1010 Keumkang Hightech Valley, Sangdaewon1-Dong 133-1, Jung won-Gu , Seongna m-Si, Kyongki- Do, Rep.

of Korea.

Zip Code : 462-807 Tel : +82-31-777-5060 Fax : +82-31-740-3798 / Homepage : www.excelsemi.com

The

attached

datasheets

are

provided by Excel Semicond uctor .inc (ESI). ESI

reserves

the

right

to change the spec-

ifications and products. ESI will answer to your questions about device. If you have any questions, please

contact the

ESI office.

Document Title

4M Flash Memory

Revision History

Revision Numb er Data I tem s

Rev. 0A Sep. 1, 2005 Initial release version.

Rev. 0B Jan. 5, 2006 Add RoHS-Compliant Package Option.