LM49352
LM49352 Mono Class D Audio Codec Subsystem with Ground Referenced
Headphone Amplifiers, Earpiece Driver, and Audio DSP
Literature Number: SNAS467D
LM49352 June 30, 2010
Mono Class D Audio Codec Subsystem with Ground
Referenced Headphone Amplifiers, Earpiece Driver, and
Audio DSP
1.0 General Description
The LM49352 is a high performance mixed signal audio sub-
system. The LM49352 includes a high quality stereo DAC, a
high quality stereo ADC, a stereo headphone amplifier, which
supports True Ground operation, a low EMI Class D loud-
speaker amplifier, and an earpiece speaker amplifier. It com-
bines advanced audio processing, conversion, mixing, and
amplification in the smallest possible footprint while extending
the battery life of feature rich portable devices.
The LM49352 features dual bi-directional I2S or PCM audio
interfaces and an I2C compatible interface for control. The
stereo DAC path features an SNR of 103dB with 24-bit 48 kHz
input. The headphone amplifier delivers 65mWRMS (typ) to a
32Ω single-ended stereo load with less than 1% distortion
(THD+N) when HP_VDD = 2.8V. The loudspeaker amplifier
delivers up to 970mW into an 8Ω load with less than 1% dis-
tortion when LS_VDD = 4.2V.
The LM49352 employs advanced techniques to extend bat-
tery life, to reduce controller overhead, to speed development
time, and to eliminate click and pop artifacts. Boomer audio
power amplifiers are designed specifically for mobile devices
and require minimal PCB area and external components.
2.0 Applications
■Smart Phones
■Mobile Phones and VOIP Phones
■Portable GPS Navigator and Portable Gaming Devices
■Portable DVD/CD/AAC/MP3/MP4 Players
■Digital Cameras/Camcorders
3.0 Key Specifications
■Class D Amplifier Efficiency 93% (typ)
■PEP at A_VDD = 3.3V, 32Ω, 1% THD 58mW (typ)
■PHP at HP_VDD = 2.8V, Stereo 32Ω,
1% THD
65mW/ch (typ)
■PLS at LS_VDD = 5V, 8Ω, 1% THD 1.4W (typ)
■PLS at LS_VDD = 4.2V, 8Ω, 1% THD 970mW (typ)
■PLS at LS_VDD = 3.3V, 8Ω, 1% THD 590mW (typ)
■SNR (Stereo DAC at 48kHz) 103dB (typ)
■PSRR at 217 Hz, A_VDD = 3.3V, (HP from
AUX)
100dB (typ)
4.0 Features
■Ultra efficient, spread spectrum Class D loudspeaker
amplifier that operates at 93% efficiency
■Low voltage, true ground headphone amplifier operation
■High performance 103dB SNR stereo DAC
■High performance 97dB SNR stereo ADC
■Up to 96kHz stereo audio playback
■Up to 48kHz stereo recording
■Dual bidirectional I2S or PCM compatible audio interfaces
■Read/write I2C compatible control interface
■Flexible digital mixer with sample rate conversion
■Sigma-delta PLL clock network that supports system
clocks up to 50MHz including 13MHz, 19.2MHz, and
26MHz
■Dual stereo 5 band parametric equalizers
■Cascadable DSP effects that allow stereo 10 band
parametric equalization
■ALC/Limiter/Compressor on both DAC and ADC paths
■Dedicated Earpiece Speaker Amplifier
■Stereo auxiliary inputs and mono differential input
■Differential microphone input with single-ended option
■Automatic level control for digital audio inputs, mono
differential input, microphone input, and stereo auxiliary
inputs
■Flexible audio routing from input to output
■16 Step volume control for microphone with 2dB steps
■32 Step volume control for auxiliary inputs in 1.5dB steps
■4 Step volume control for class D loudspeaker amplifier
■8 Step volume control for headphone amplifier
■Micro-power shutdown mode
■Available in the 3.3 x 3.3 mm 36 bump micro SMD package
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation 300727 www.national.com
LM49352 Mono Class D Audio Codec Subsystem with Ground Referenced Headphone
Amplifiers, Earpiece Driver, and Audio DSP
5.0 LM49352 Overview
30072777
FIGURE 1. LM49352 Block Diagram
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LM49352
6.0 Typical Application
30072785
FIGURE 2. Example Application in Multimedia Phone with Dedicated Earpiece Speaker and Mono Loudspeaker
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LM49352
30072786
FIGURE 3. Example Application in Multimedia Phone Using Multiple Media Sources
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LM49352
30072787
FIGURE 4. Example Application in a Multimedia Phone with Stereo Loudspeaker
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LM49352
30072788
FIGURE 5. Example Application in a Portable Media Player with Stereo Loudspeakers
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LM49352
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Features ........................................................................................................................................ 1
5.0 LM49352 Overview .......................................................................................................................... 2
6.0 Typical Application ........................................................................................................................... 3
7.0 Connection Diagrams ..................................................................................................................... 10
7.1 PIN TYPE DEFINITIONS ........................................................................................................ 12
8.0 Absolute Maximum Ratings ............................................................................................................ 13
9.0 Operating Ratings ......................................................................................................................... 13
10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; HP_VDD = D_VDD = I/O_VDD = 1.8V ...................... 13
11.0 Typical Performance Characteristics .............................................................................................. 19
12.0 System Control ............................................................................................................................ 29
12.1 I2C SIGNALS ....................................................................................................................... 29
12.2 I2C DATA VALIDITY ............................................................................................................. 29
12.3 I2C START AND STOP CONDITIONS ..................................................................................... 29
12.4 TRANSFERRING DATA ........................................................................................................ 29
12.5 I2C TIMING PARAMETERS .................................................................................................. 31
13.0 Device Register Map .................................................................................................................... 32
14.0 Basic PMC Setup Register ............................................................................................................ 36
15.0 PMC Clocks Register ................................................................................................................... 37
16.0 PMC Clock Divide Register ........................................................................................................... 37
17.0 LM49352 Clock Network .............................................................................................................. 38
18.0 PLL Setup Registers .................................................................................................................... 40
19.0 Analog Mixer Control Registers ..................................................................................................... 44
20.0 ADC Control Registers ................................................................................................................. 53
21.0 DAC Control Registers ................................................................................................................. 55
22.0 Digital Mixer Control Registers ...................................................................................................... 56
23.0 Audio Port Control Registers ......................................................................................................... 60
24.0 Digital Effects Engine ................................................................................................................... 66
25.0 DAC Effects Registers .................................................................................................................. 87
26.0 GPIO Registers ......................................................................................................................... 102
27.0 Schematic Diagram .................................................................................................................... 104
28.0 Demonstration Board Layout ....................................................................................................... 105
29.0 Revision History ........................................................................................................................ 108
30.0 Physical Dimensions .................................................................................................................. 109
List of Figures
FIGURE 1. LM49352 Block Diagram ............................................................................................................. 2
FIGURE 2. Example Application in Multimedia Phone with Dedicated Earpiece Speaker and Mono Loudspeaker ................ 3
FIGURE 3. Example Application in Multimedia Phone Using Multiple Media Sources .................................................. 4
FIGURE 4. Example Application in a Multimedia Phone with Stereo Loudspeaker ...................................................... 5
FIGURE 5. Example Application in a Portable Media Player with Stereo Loudspeakers ................................................ 6
FIGURE 6. I2C Signals: Data Validity ............................................................................................................ 29
FIGURE 7. I2C Start and Stop Conditions ...................................................................................................... 29
FIGURE 8. I2C Chip Address ..................................................................................................................... 29
FIGURE 9. Example I2C Write Cycle ............................................................................................................ 30
FIGURE 10. Example I2C Read Cycle .......................................................................................................... 30
FIGURE 11. I2C Timing Diagram ................................................................................................................. 30
FIGURE 12. Internal Clock Network ............................................................................................................. 39
FIGURE 13. PLL Loop ............................................................................................................................ 40
FIGURE 14. EMI/RFI Filter for the Class D Amplifier ......................................................................................... 45
FIGURE 15. Application Circuit for Headphone Detection ................................................................................... 51
FIGURE 16. Digital Mixer .......................................................................................................................... 56
FIGURE 17. I2S Serial Data Format (24 bit example) ........................................................................................ 60
FIGURE 18. Left Justified Data Format (24 bit example) .................................................................................... 60
FIGURE 19. Right Justified Data Format (24 bit example) .................................................................................. 60
FIGURE 20. PCM Serial Data Format (16 bit example) ...................................................................................... 60
FIGURE 21. ADC DSP Effects Chain ........................................................................................................... 66
FIGURE 22. DAC DSP Effects Chain ........................................................................................................... 66
FIGURE 23. ALC Example ........................................................................................................................ 68
FIGURE 24. ALC Limiter ........................................................................................................................... 69
FIGURE 25. Audio Compressor Effect .......................................................................................................... 82
FIGURE 26. Soft Knee Example with Compression Ratio Setting of 1:3.4 ............................................................... 83
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LM49352
FIGURE 27. Demo Board Schematic .......................................................................................................... 104
FIGURE 28. Top Silkscreen ..................................................................................................................... 105
FIGURE 29. Top Layer ........................................................................................................................... 105
FIGURE 30. Inner Layer 2 ....................................................................................................................... 106
FIGURE 31. Inner Layer 3 ....................................................................................................................... 106
FIGURE 32. Bottom Layer ...................................................................................................................... 107
FIGURE 33. Bottom Silkscreen ................................................................................................................. 107
List of Tables
TABLE 1. Device Register Map .................................................................................................................. 32
TABLE 2. Nonzero I2C Default Registers ....................................................................................................... 35
TABLE 3. PMC_SETUP (0x00h) ................................................................................................................. 36
TABLE 4. PMC_SETUP (0x01h) ................................................................................................................. 37
TABLE 5. PMC_SETUP (0x02h) ................................................................................................................ 37
TABLE 6. DAC Clock Requirements ............................................................................................................. 38
TABLE 7. ADC Clock Requirements ............................................................................................................. 38
TABLE 8. PLL Settings for Common System Clock Frequencies .......................................................................... 40
TABLE 9. PLL_CLOCK_SOURCE (0x03h) .................................................................................................... 41
TABLE 10. PLL_M (0x04h) ........................................................................................................................ 42
TABLE 11. PLL_N (0x05h) ........................................................................................................................ 42
TABLE 12. PLL_N_MOD (0x06h) ................................................................................................................ 42
TABLE 13. PLL_P1 (0x07h) ....................................................................................................................... 43
TABLE 14. PLL_P2 (0x08h) ....................................................................................................................... 43
TABLE 15. CLASS_D_OUTPUT (0x10h) ....................................................................................................... 44
TABLE 16. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... 45
TABLE 17. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ 45
TABLE 18. AUX_OUTPUT (0x13h) .............................................................................................................. 46
TABLE 19. OUTPUT_OPTIONS (0x14h) ....................................................................................................... 47
TABLE 20. ADC_INPUT (0x15h) ................................................................................................................. 48
TABLE 21. MIC_INPUT (0x16h) ................................................................................................................. 48
TABLE 22. AUX_LEVEL (0x18h) ................................................................................................................. 49
TABLE 23. MONO_LEVEL (0x19h) .............................................................................................................. 50
TABLE 24. HP_SENSE (0x1Bh) ................................................................................................................. 52
TABLE 25. ADC Basic (0x20h) ................................................................................................................... 53
TABLE 26. ADC_CLK_DIV (0x21h) ............................................................................................................. 53
TABLE 27. ADC_MIXER (0x23h) ................................................................................................................ 54
TABLE 28. DAC Basic (0x30h) .................................................................................................................. 55
TABLE 29. DAC_CLK_DIV (0x31h) ............................................................................................................. 55
TABLE 30. Input Levels 1 (0x40h) ............................................................................................................... 57
TABLE 31. Input Levels 2 (0x41h) ............................................................................................................... 57
TABLE 32. Audio Port 1 Input (0x42h) .......................................................................................................... 58
TABLE 33. Audio Port 2 Input (0x43h) .......................................................................................................... 58
TABLE 34. DAC Input Select (0x44h) ........................................................................................................... 59
TABLE 35. Decimator Input Select (0x45h) .................................................................................................... 59
TABLE 36. BASIC_SETUP (0x50h/0x60h) ..................................................................................................... 61
TABLE 37. CLK_GEN_1 (0x51h/0x61h) ........................................................................................................ 61
TABLE 38. CLK_GEN_1 (0x52h/62h) ........................................................................................................... 62
TABLE 39. CLK_GEN_1 (0x53h/63h) ........................................................................................................... 62
TABLE 40. DATA_WIDTHS (0x54h/64h) ....................................................................................................... 63
TABLE 41. RX_MODE (0x55h/x65h) ............................................................................................................ 64
TABLE 42. TX_MODE (0x56h/x66h) ............................................................................................................ 65
TABLE 43. ADC EFFECTS (0x70h) ............................................................................................................. 66
TABLE 44. DAC EFFECTS (0x71h) ............................................................................................................. 67
TABLE 45. HPF MODE (0x80h) .................................................................................................................. 67
TABLE 46. ADC_ALC_1 (0x81h) ................................................................................................................. 70
TABLE 47. ADC_ALC_2 (0x82h) ................................................................................................................. 70
TABLE 48. ADC_ALC_3 (0x83h) ................................................................................................................. 71
TABLE 49. ADC_ALC_4 (0x84h) ................................................................................................................. 72
TABLE 50. ADC_ALC_5 (0x85h) ................................................................................................................. 73
TABLE 51. ADC_ALC_6 (0x86h) ................................................................................................................ 74
TABLE 52. ADC_ALC_7 (0x87h) ................................................................................................................ 74
TABLE 53. ADC_ALC_8 (0x88h) ................................................................................................................. 74
TABLE 54. ADC_L_LEVEL (0x89h) ............................................................................................................ 75
TABLE 55. ADC_R_LEVEL (0x8Ah) ............................................................................................................. 76
TABLE 56. EQ_BAND_1 (0x8Bh) ................................................................................................................ 77
TABLE 57. EQ_BAND_2 (0x8Ch) ................................................................................................................ 78
TABLE 58. EQ_BAND_3 (0x8Dh) ................................................................................................................ 79
TABLE 59. EQ_BAND_4 (0x8Eh) ................................................................................................................ 80
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LM49352
TABLE 60. EQ_BAND_5 (0x8Fh) ................................................................................................................ 81
TABLE 61. SOFTCLIP1 (0x90h) ................................................................................................................. 84
TABLE 62. SOFTCLIP2 (0x91h) ................................................................................................................. 85
TABLE 63. SOFTCLIP3 (0x92h) ................................................................................................................. 86
TABLE 64. DAC_ALC_1 (0xA0h) ................................................................................................................ 87
TABLE 65. DAC_ALC_2 (0xA1h) ................................................................................................................ 87
TABLE 66. DAC_ALC_3 (0xA2h) ................................................................................................................ 88
TABLE 67. DAC_ALC_4 (0xA3h) ............................................................................................................... 89
TABLE 68. DAC_ALC_5 (0xA4h) ............................................................................................................... 90
TABLE 69. DAC_ALC_6 (0xA5h) ............................................................................................................... 91
TABLE 70. DAC_ALC_7 (0xA6h) ............................................................................................................... 91
TABLE 71. DAC_ALC_8 (0xA7h) ................................................................................................................ 91
TABLE 72. DAC_L_LEVEL (0xA8h) ............................................................................................................ 92
TABLE 73. DAC_R_LEVEL (0xA9h) ............................................................................................................ 93
TABLE 74. EQ_BAND_1 (0xABh) ............................................................................................................... 94
TABLE 75. EQ_BAND_2 (0xACh) ............................................................................................................... 95
TABLE 76. EQ_BAND_3 (0xADh) ............................................................................................................... 96
TABLE 77. EQ_BAND_4 (0xAEh) ............................................................................................................... 97
TABLE 78. EQ_BAND_5 (0xAFh) ................................................................................................................ 98
TABLE 79. SOFTCLIP1 (0xB0h) ................................................................................................................. 99
TABLE 80. SOFTCLIP2 (0xB1h) ............................................................................................................... 100
TABLE 81. SOFTCLIP3 (0xB2h) ............................................................................................................... 101
TABLE 82. GPIO1 (0xE0h) ...................................................................................................................... 102
TABLE 83. GPIO2 (0xE1h) ...................................................................................................................... 103
TABLE 84. RESET (0xF0h) ..................................................................................................................... 103
TABLE 85. Spread Spectrum (0xF1h) ......................................................................................................... 103
TABLE 86. FORCE (0xFE) ...................................................................................................................... 103
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LM49352
7.0 Connection Diagrams
36 Bump micro SMD
30072711
Order Number LM49352RL
See NS Package Number RLA36MMA
36 Bump micro SMD Marking
300727q7
Top View
XY — Date Code
TT — Die Traceability
G — Boomer
L5 — LM49352RL
LM49352RL Pinout Diagram
30072710
Top View (Bump Side Down)
Ordering Information
Order Number Package Package DWG # Transport Media MSL Level Green Status
LM49352RL 36 Bump micro
SMDxt RLA36MMA 250 units on tape and reel 1 RoHS and
no Sb/Br
LM49352RLX 36 Bump micro
SMDxt RLA36MMA 1000 units on tape and reel 1 RoHS and
no Sb/Br
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LM49352
Pin Descriptions
Pin Pin Name Type Direction Description
A1 HPR Analog Output Headphone right output
A2 A_VDD Supply Input DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog
mixer (AUX and class D), and Earpiece amplifier power supply input
A3 AGND Supply Input DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog
mixer (AUX and class D), and Earpiece amplifier ground
A4 DAC REF Analog Input/Output Filter point for the DAC reference
A5 ADC REF Analog Input Filter point for the ADC reference. Connect this pin to A_VDD.
A6 SDA Digital Input/Output I2C interface data line
B1 HPL Analog Output Headphone left output
B2 AUX_R/AUX+ Analog Input Right analog input or positive differential auxiliary input
B3 AUX_L/AUX- Analog Input Left analog input or negative differential auxiliary input
B4 PORT2_SYNC Digital Input/Output Audio Port 2 sync signal (can be master or slave)
B5 PORT2_SDI Digital Input Audio Port 2 serial data input
B6 SCL Digital Input I2C interface clock line
C1 HP_VSS Analog Output Negative power supply pin for the headphone amplifier
C2 HP_VDD Supply Input Headphone amplifier power supply pin
C3 EP-/AUXOUT- Analog Output Earpiece negative output or Auxiliary negative output
C4 PORT2_SDO /
GPIO Digital Input / Output Audio port 2 serial data output or General Purpose Input Output
C5 PORT2_CLK Digital Input/Output Audio port 2 clock signal (can be master or slave)
C6 MCLK Digital Input Input clock from 0.5MHz to 50 MHz
D1 CP- Analog Input/Output Fly capacitor negative input
D2 CP+ Analog Input/Output Fly capacitor positive input
D3 EP+/AUXOUT+ Analog Output Earpiece positive output or Auxiliary positive output
D4 PORT1_SYNC Digital Input/Output Audio Port 1 sync signal (can be master or slave)
D5 PORT1_SDO Digital Output Audio Port 1 serial data output
D6 DGND Supply Input Digital ground
E1 LSGND Supply Input Loudspeaker ground
E2 LS_VDD Supply Input Loudspeaker amplifier and analog mixer (headphone) supply input
E3 MONO- Analog Input Mono differential negative input
E4 MIC- Analog Input Microphone negative input
E5 PORT1_SDI Digital Input Audio Port 1 serial data input
E6 D_VDD Supply Input DAC (Digital), ADC (Digital), PLL (Digital), digital mixer, DSP core,
and I2C register power supply input
F1 LS + Analog Output Loudspeaker positive output
F2 LS - Analog Output Loudspeaker negative output
F3 MONO+ Analog Input Mono differential positive input
F4 MIC + Analog Input Microphone positive input
F5 PORT1_CLK Digital Input/Output Audio Port 1 clock signal (can be master or slave)
F6 I/O_VDD Supply Input Digital I/O (MCLK, I2S/PCM, I2C) interface power supply input
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LM49352
7.1 PIN TYPE DEFINITIONS
Analog Input — A pin that is used by the analog and
is never driven by the device. Sup-
plies are part of this classification.
Analog Output — A pin that is driven by the device and
should not be driven by external
sources.
Analog Input/Output — A pin that is typically used for filtering
a DC signal within the device. Pas-
sive components can be connected
to these pins.
Digital Input — A pin that is used by the digital but is
never driven by the device.
Digital Output — A pin that is driven by the device and
should not be driven by another de-
vice to avoid contention.
Digital Input/Output — A pin that is either open drain (SDA)
or a bidirectional CMOS in/out. In
the latter case the direction is se-
lected by a control register within the
LM49352.
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LM49352
8.0 Absolute Maximum Ratings (Note
1, Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage
(A_VDD and LS_VDD)6.0V
Digital Supply Voltage
D_VDD 2.2V
I/O Supply Voltage
I/O_VDD 5.5V
Headphone Supply Voltage
HP_VDD 3.0V
Storage Temperature −65°C to +150°C
Power Dissipation (Note 3) Internally Limited
ESD Ratings
Human Body Model (Note 4)
HPR and HPL pins
All other pins
8kV
2.5kV
Machine Model (Note 5) 200V
Junction Temperature 150°C
Thermal Resistance
θJA – RLA36 (soldered down
to PCB with 2in2 1oz. copper plane) 60°C/W
Soldering Information
See Applications Note AN-1112.
9.0 Operating Ratings
Temperature Range −40°C to +85°C
Supply Voltage
A_VDD, LS_VDD, and AVDD_REF
D_VDD
I/O_VDD
HP_VDD
2.7V to 5.5V
1.6V to 2.0V
1.6V to 4.5V
1.7V to 2.8V
10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; HP_VDD = D_VDD = I/
O_VDD = 1.8V (Note 1, Note 2) The following specifications apply for RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless
otherwise specified. Limits apply for TA = 25°C.
Symbol Parameter Conditions
LM49352 Units
(Limit)
Typical
(Note 6)
Limit
(Note 7)
DC CHARACTERISTICS (Digital current combines D_VDD and I/O_VDD. Analog current combines A_VDD, HP_VDD, and
LS_VDD)
DISD Digital Shutdown Current Shutdown Mode,
fMCLK = 13MHz, PLL Off 2 µA
DIDD
Digital Active Current (MP3 Mode)
fMCLK = 11.2896MHz, fS = 44.1kHz,
Stereo DAC On, OSRDAC = 64,
PLL Off, HP On
1.2 1.4 mA (max)
Digital Active Current (FM Mode) fMCLK = 13MHz
Analog Audio modes 0.2 0.5 mA (max)
Digital Active Current
(FM Record Mode)
fMCLK = 12.288MHz, fS = 48kHz,
Stereo ADC On, OSRADC = 128,
PLL Off, Stereo Analog Inputs On
1.3 1.5 mA (max)
Digital Active Current
(CODEC Mode)
fMCLK = 12.288MHz, fS = 8kHz,
Mono ADC On, Mono DAC On,
OSRDAC = 64
OSRADC = 128, PLL Off, MIC On
0.5 0.8 mA (max)
AISD Analog Shutdown Current Shutdown Mode 0.1 5 μA (max)
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LM49352
Symbol Parameter Conditions
LM49352 Units
(Limit)
Typical
(Note 6)
Limit
(Note 7)
AIDD
Analog Supply Current (MP3 Mode)
fMCLK = 11.2896MHz, fS = 44.1kHz
Stereo DAC On, OSRDAC = 64
PLL Off, Stereo HP On
From A_VDD 4.3 6 mA (max)
From HP_VDD 1.5 2.7 mA (max)
Analog Supply Current (FM Mode)
fMCLK = 13MHz, PLL Off
Stereo Auxiliary Inputs On,
PLL Off, Stereo HP On
From A_VDD 1.7 2.6 mA (max)
From HP_VDD 1.5 2.7 mA (max)
Analog Supply Current
(FM Record Mode)
fMCLK = 12.288MHz, fS = 48kHz,
Stereo ADC On, OSRADC = 128,
PLL Off, Stereo Analog Inputs On
7.2 9.3 mA (max)
Analog Supply Current
(CODEC Mode)
fMCLK = 12.288MHz, fS = 8kHz,
Mono ADC On, Mono DAC On,
OSRDAC = 64
OSRADC = 128, PLL Off, MIC On,
EP On
6.6 8.7 mA (max)
PLLIDD PLL Total Active Current
fMCLK = 13MHz,
fPLLOUT = 12MHz, PLL On only
From A_VDD 1.9 2.7 mA (max)
From D_VDD 1.4 2 mA (max)
HPIDD Headphone Quiescent Current Stereo HP On only 1.5 mA
LSIDD Loudspeaker Quiescent Current LS On only 2.2 mA
MICIDD Microphone Quiescent Current Mono MIC 0.4 mA
ADCIDD ADC Total Active Current
fS = 48kHz, Stereo
From A_VDD 5.8 mA
From D_VDD 1.3 mA
DACIDD DAC Total Active Current
fS = 48kHz, Stereo
From A_VDD 3.1 mA
From D_VDD 1 mA
AUXINIDD
Mono/Auxiliary Input Amplifier
Quiescent Current
Mono and AUX Input Amplifiers
enabled 0.6 mA
AUXOUTIDD
Auxiliary Output Amplifier Quiescent
Current
AUXOUT enabled 0.4 mA
Earpiece Mode 1.1 mA
LOUDSPEAKER AMPLIFIER
LSEFF Loudspeaker Efficiency PO = 970mW, RL = 8Ω,
LS_VDD = 4.2V 93 %
THD+N Total Harmonic Distortion + Noise PO = 300mW, f = 1kHz,
RL = 8Ω, Mono Input Signal 0.03 %
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LM49352
Symbol Parameter Conditions
LM49352 Units
(Limit)
Typical
(Note 6)
Limit
(Note 7)
POOutput Power
RL = 8Ω, f = 1kHz, THD+N = 1%, Mono Input Signal
LS_VDD = 5V 1.4 W
LS_VDD = 4.2V 970 mW
LS_VDD = 3.3V 590 510 mW (min)
RL = 4Ω, f = 1kHz, THD+N = 1%,
Mono Input Signal
LS_VDD = 5V 2.4 W
LS_VDD = 4.2V 1.65 W
LS_VDD = 3.3V 980 mW
PSRR Power Supply Rejection Ratio
VRIPPLE = 200mVP-P
fRIPPLE = 217Hz
Mono Input Terminated
VREF = 1.0μF, Input Referred
LS Gain = 12dB
75 60 dB (min)
VRIPPLE = 200mVP-P
fRIPPLE = 217Hz
From DAC, DAC gain = 0dB
74 dB
SNR Signal-to-Noise Ratio
Reference = VOUT (1% THD+N )
Mono gain = 0dB, A-weighted
Mono Input Terminated, LS Gain = 8dB
LS_VDD = 4.2V 95 dB
LS_VDD = 3.3V 93 88 dB (min)
Reference = VOUT (1% THD+N )
DAC Gain = 0dB, A-weighted
fS = 48kHz, OSR = 128
LS Gain = 8dB
LS_VDD = 4.2V 91 dB
LS_VDD = 3.3V 89 dB
eOS Output Noise Mono gain = 0dB, A-weighted,
Mono Input Terminated, Input Referred 43 µV
VOS Offset Voltage Mono gain = 0dB, from Mono Input 10 50 mV (max)
HEADPHONE AMPLIFIERS
THD+N Total Harmonic Distortion + Noise
PO = 15mW, f = 1kHz,
RL = 32Ω
Stereo Analog Input Signal
0.025 0.1 % (max)
POHeadphone Output Power
RL = 32Ω, f = 1kHz, THD+N = 1%,
Stereo Analog Input Signal, In phase
HP_VDD = 2.8V 65 mW
HP_VDD = 1.8V 24 20 mW (min)
RL = 16Ω, f = 1kHz, THD+N = 1%,
Stereo Analog Input Signal, In phase
HP_VDD = 2.8V 73 mW
HP_VDD = 1.8V 24 mW
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LM49352
Symbol Parameter Conditions
LM49352 Units
(Limit)
Typical
(Note 6)
Limit
(Note 7)
PSRR Power Supply Rejection Ratio
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input Terminated, Mono gain = 0dB
VREF = 1.0μF, Mono Differential Input Mode,
Ripple applied to AVDD only 100 85 dB (min)
Ripple applied to AVDD and HPVDD 88 dB
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
From DAC, DAC gain = 0dB
Ripple applied to AVDD
HPVDD, and DVDD
81 dB
SNR Signal to Noise Ratio
Reference = VOUT (1% THD+N )
Gain = 0dB, A-weighted
Stereo Inputs Terminated
98 93 dB (min)
Reference = VOUT (1% THD+N)
Gain = 0dB,
A-weighted, I2S Input = Digital Zero
97 93 dB (min)
eOS Output Noise
Gain = 0dB, A-weighted,
Stereo Inputs Terminated 11 µV
Gain = 0dB, A-weighted,
I2S Input = Digital Zero 12 µV
XTALK Crosstalk
PO = 7.5mW, f = 1kHz,
RL = 32Ω
Stereo Analog Input Signal
85 dB
ΔACH-CH Channel-to-Channel Gain Matching 0.03 dB
VOS Output Offset Voltage
AUX Gain = 0dB
From mono Input 1.4 6 mV (max)
DAC Gain = 0dB
From DAC Input, fMCLK = 12.288MHz 1.6 6 mV (max)
AUXILIARY OUTPUT/EARPIECE AMPLIFIER
THD+N Total Harmonic Distortion
AUX_LINE_OUT, f = 1kHz
From Mono In
RL = 5kΩ, VOUT = 1VRMS
0.002 %
Earpiece mode, f = 1kHz
From Mono In
RL = 32Ω BTL, POUT = 20mW
0.02 %
POUT Output Power Earpiece mode, f = 1kHz
RL = 32Ω BTL, THD+N = 1% 58 50 mW (min)
PSRR Power Supply Rejection Ratio
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input terminated, CREF = 1.0μF
AUX_LINE_OUT
100 dB
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input terminated, CREF = 1.0μF
Earpiece mode,
–6dB cut enabled
100 90 dB
SNR Signal to Noise Ratio Gain = 0dB, VREF = VOUT (1% THD+N)
A-weighted, Mono Input Terminated 105 dB
∈OUT Output Noise Gain = 0dB, VREF = VOUT (1% THD+N)
A-weighted, Mono Input Terminated 7 μV
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LM49352
Symbol Parameter Conditions
LM49352 Units
(Limit)
Typical
(Note 6)
Limit
(Note 7)
VOS Output Offset Voltage
MONO gain = 0dB, From Mono Input
AUX_LINE_OUT 4 mV
Gain = 0dB, From Mono Input
Earpiece mode 4 12 mV (max)
TWU Turn-On time PMC Clock = 300kHz 28 ms
STEREO ADC
THD+NADC
ADC Total Harmonic Distortion +
Noise
Mono Differential Input
VIN = 1VRMS, f = 1kHz
Gain = 0dB, fS = 48kHz
0.007 %
PBADC ADC Passband
HPF On, fS = 48kHz
Lower -3dB Point 220 Hz
HPF On, Upper -3dB Point 0.41*fS kHz
RADC ADC Ripple OSRDAC = 128 0.1 dB
SNRADC ADC Signal to Noise Ratio
Reference = VOUT (0dBFS )
Gain = 6dB,
A-weighted From MIC, fS = 8kHz
98 dB
Reference = VOUT (0dBFS )
Gain = 0dB,
A-weighted From Stereo Input,
fS = 48kHz
97 dB
ADCLEVEL ADC Full Scale Input Level 1.6 VRMS
STEREO DAC
THD+NDAC
DAC Total Harmonic Distortion +
Noise
I2S Input, AUXOUT, OSRDAC = 64
VIN = 500mFFSRMS, f = 1kHz
Gain = 0dB
0.01 %
DACLEVEL DAC Full Scale Output Level 1.08 VRMS
RDAC DAC Ripple 0.1 dB
PBDAC DAC Passband Upper –3dB Point 0.45*fS kHz
SNRDAC DAC Signal to Noise Ratio fS = 48kHz, A-weighted, AUXOUT 103 dB
VOLUME CONTROL
VCRAUX Stereo Input Volume Control Range Minimum Gain –46.5 dB
Maximum Gain 18 dB
VCRMONO MONO Input Volume Control Range Minimum Gain –46.5 dB
Maximum Gain 18 dB
VCRDAC DAC Volume Control Range Minimum Gain –76.5 dB
Maximum Gain 18 dB
VCRADC ADC Volume Control Range Minimum Gain –76.5 dB
Maximum Gain 18 dB
VCRMIC MIC Volume Control Range Minimum Gain 6 dB
Maximum Gain 36 dB
VCRLS
Loudspeaker Amplifier Volume
Control Range
Minimum Gain 0 dB
Maximum Gain 12 dB
VCRHP
Headphone Amplifier Volume
Control Range
Minimum Gain –18 dB
Maximum Gain 0 dB
SSLS
Loudspeaker Amplifier Volume
Control Stepsize
4 dB
SSHP
Headphone Amplifier Volume
Control Stepsize
Refer to
Table 19
dB
SSAUX AUX Input Volume Control Stepsize 1.5 dB
17 www.national.com
LM49352
Symbol Parameter Conditions
LM49352 Units
(Limit)
Typical
(Note 6)
Limit
(Note 7)
SSMONO
MONO Input Volume Control
Stepsize
1.5 dB
SSDAC DAC Volume Control Stepsize 1.5 dB
SSADC ADC Volume Control Stepsize 1.5 dB
SSMIC MIC Volume Control Stepsize 2 dB
SVAUX AUX Volume Setting Variation ±1 dB (max)
SVMONO MONO Volume Setting Variation ±1 dB (min)
SVMIC MIC Volume Setting Variation ±1 dB (max)
ANALOG INPUTS
AUX_RIN Auxiliary Input Impedance
AUX Gain = 18dB 10 kΩ
AUX Gain = 0dB 38 kΩ
AUX Gain = –46.5dB 64 kΩ
MONO_RIN Mono Input Impedance
MONO Gain = 18dB 10 kΩ
MONO Gain = 0dB 38 kΩ
MONO Gain = –46.5dB 64 kΩ
MIC_RIN Microphone Input Impedance All MIC gain settings 50 kΩ
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.
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LM49352
11.0 Typical Performance Characteristics
Class D Loudspeaker Amplifier Efficiency
vs Output Power
THD+N < 10%, RL = 8Ω
Green >> LSVDD = 3.3V
Gray >> LSVDD = 4.2V
Blue >> LSVDD = 5V
0 400 800 1200 1600 2000
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
OUTPUT POWER (mW)
300727b2
DAC Frequency Response
fS = 48kHz
Blue >> OSR = 64
Light Blue >> OSR = 128
300727b3
DAC Frequency Response
fS = 8kHz
Blue >> OSR = 64
Light Blue >> OSR = 128
300727b4
DAC THD+N vs Frequency
fS = 8kHz, OSR = 128
I2S Input = 500mFFS
300727b5
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LM49352
DAC THD+N vs Frequency
fS = 8kHz, OSR = 64
I2S Input = 500mFFS
300727b6
DAC THD+N vs Input Level
fS = 48kHz, OSR = 64
I2S Input = 1kHz
300727b8
Stereo Audio ADC Frequency Response
fS = 48kHz, OSR = 64
From MIC, MIC Gain = 6dB, CIN = 1µF
300727b9
Stereo Audio ADC Frequency Response
fS = 8kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
300727c0
Mono Voice ADC Frequency Response
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
300727c1
Mono Voice ADC Frequency Response
fS = 8kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
300727c2
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LM49352
Stereo Audio HPF ADC Frequency Response
fS = 48kHz, OSR = 128
From MONO/AUX, MONO>AUX Gain = 0dB, CIN = 1µF
Blue >> No HPF
Light Blue >> HPF Mode = '101'
Green >> HPF Mode = '110'
Light Green >> HPF Mode = '111'
300727c3
Mono Voice HPF ADC Frequency Response
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
Gray >> No HPF
Blue >> HPF Mode = '000'
Light Blue >> HPF Mode = '001'
Green >> HPF Mode = '010'
Light Green >> HPF Mode = '011'
Yellow >> HPF Mode = '100'
300727c4
Mono Voice HPF ADC Frequency Response
fS = 8kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
Gray >> No HPF
Blue >> HPF Mode = '000'
Light Blue >> HPF Mode = '001'
Green >> HPF Mode = '010'
Light Green >> HPF Mode = '011'
Yellow >> HPF Mode = '100'
300727e9
ADC THD+N vs Frequency
fS = 48kHz, OSR = 128
From MONO/AUX, MONO/AUX Gain = 6dB, VIN = 1VRMS
300727c5
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LM49352
ADC THD+N vs Frequency
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, VIN = 500mVRMS
300727c6
ADC THD+N vs Input Voltage
fS = 48kHz, OSR = 128
From MONO/AUX, MONO/AUX Gain = 0dB, fIN = 1kHz
300727c7
ADC THD+N vs Input Voltage
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, VIN = 1kHz
300727c8
Loudspeaker THD+N vs Input Voltage
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, LSVDD = 3.3V, POUT = 300VRMS, RL = 8Ω
300727c9
Loudspeaker THD+N vs Input Voltage
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, LSVDD = 4.2V, POUT = 300VRMS, RL = 8Ω
300727d0
Loudspeaker THD+N vs Input Voltage
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, LSVDD = 5V, POUT = 300VRMS, RL = 8Ω
300727d1
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LM49352
Loudspeaker THD+N vs Input Voltage
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, LSVDD = 3.3V, POUT = 300VRMS, RL = 4Ω
300727d2
Loudspeaker THD+N vs Output Power
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, fIN = 1kHz, RL = 8Ω
Blue >> LSVDD = 3.3V
Light Blue >> LSVDD = 4.2V
Green >> LSVDD = 5V
300727f0
Loudspeaker THD+N vs Output Power
fS = 48kHz, OSR = 128
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, fIN = 1kHz, RL = 4Ω
Blue >> LSVDD = 3.3V
Light Blue >> LSVDD = 4.2V
Green >> LSVDD = 5V
300727f1
Loudspeaker PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 3.3V, VRIPPLE = 200mVPP, Input Referred
300727d3
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LM49352
Loudspeaker PSRR vs Frequency
fS = 48kHz, OSR = 128
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 4.2V, VRIPPLE = 200mVPP, Input Referred
300727d4
Loudspeaker PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 5V, VRIPPLE = 200mVPP, Input Referred
300727d5
Headphone PSRR vs Frequency
DAC Input, DAC Gain = 0dB, LS Gain = 12dB
LSVDD = 3,3V, AVDD = 3.3V, DVDD = 1.8V, VRIPPLE =
200mVPP
Ripple on LSVDD, AVDD, DVDD, Input Referred
300727d6
HeadphoneTHD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 3.3V, POUT = 15mW, RL = 32Ω
Stereo In Phase
300727d7
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LM49352
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 2.8V, POUT = 15mW, RL = 32Ω
Stereo In Phase
300727d8
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, POUT = 15mW, RL = 16Ω
Stereo In Phase
300727d9
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 2.8V, POUT = 15mW, RL = 16Ω
Stereo in Phase
300727e0
Headphone THD+N vs Output Power
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
Stereo In Phase, fIN = 1kHz, RL = 32Ω
Blue >> HPVDD = 1.8V
Light Blue >> HPVDD = 2.8V
300727r0
25 www.national.com
LM49352
Headphone THD+N vs Output Power
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
Stereo In Phase, fIN = 1kHz, RL = 16Ω
Blue >> HPVDD = 1.8V
Light Blue >> HPVDD = 2.8V
300727q9
Headphone PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.3V, VRIPPLE = 200mVPP
Ripple on HPVDD, AVDD
300727e1
Headphone PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.3V, VRIPPLE = 200mVPP
Ripple on AVDD only
300727e2
Headphone PSRR vs Frequency
DAC Input, DAC Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.3V, DVDD = 1.8V, VRIPPLE =
200mVPP
Ripple on HPVDD, AVDD, DVDD
300727e3
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LM49352
Headphone Crosstalk vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.3V, POUT = 15mW, RL = 32Ω
300727e4
Earpiece THD+N vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.3V, POUT = 20mW, RL = 32Ω
Earpiece Mode
300727e5
Earpiece THD+N vs Output Power
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.3V, fIN = 1kHz, RL = 32Ω
Earpiece Mode
300727q8
Earpiece PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = –6dB
AVDD = 3.3V, VRIPPLE = 200mVPP, Earpiece Mode
300727e6
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LM49352
Auxiliary Output THD+N vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.3V, VOUT = 1VRMS, RL = 5kΩ
AUXOUT Mode
300727e7
Auxiliary Output THD+N vs Output Voltage
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.3V, fIN = 1kHz, RL = 5kΩ
AUXOUT Mode
300727f2
Auxiliary Output PSRR vs FRequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.3V, VRIPPLE = 200mVPP, AUXOUT Mode
300727e8
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LM49352
12.0 System Control
Method 1. I2C Compatible Interface
12.1 I2C SIGNALS
In I2C mode the LM49352 pin SCL is used for the I2C clock
SCL and the pin SDA is used for the I2C data signal SDA. Both
these signals need a pull-up resistor according to I2C speci-
fication. The I2C slave address for LM49352 is 00110102.
12.2 I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.
30072723
FIGURE 6. I2C Signals: Data Validity
12.3 I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates
START and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
30072724
FIGURE 7. I2C Start and Stop Conditions
12.4 TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
After the START condition, the I2C master sends a chip ad-
dress. This address is seven bits long followed by an eight bit
which is a data direction bit (R/W). The LM49352 address is
00110102. For the eighth bit, a “0” indicates a WRITE and a
“1” indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
30072725
FIGURE 8. I2C Chip Address
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LM49352
Register changes take effect at the SCL rising edge during
the last ACK from slave.
30072726
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
FIGURE 9. Example I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle
waveform.
30072727
FIGURE 10. Example I2C Read Cycle
30072728
FIGURE 11. I2C Timing Diagram
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LM49352
12.5 I2C TIMING PARAMETERS
Symbol Parameter Limit Units
Min Typ Max
1 Hold Time (repeated) START Condition 0.6 µs
2 Clock Low Time 1.3 µs
3 Clock High Time 600 ns
4 Setup Time for a Repeated START Condition 600 ns
5Data Hold Time (Output direction, delay generated by LM49352) 50 (Note 8) ns
Data Hold Time (Input direction, delay generated by the Master) 50 ns
6 Data Setup Time 100 ns
7 Rise Time of SDA 300 ns
8 Fall Time of SDA 300 ns
9 Set-up Time for STOP condition 600 ns
10 Bus Free Time between a STOP and a START Condition 1.3 µs
Note 8: Data guaranteed by fall time.
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LM49352
13.0 Device Register Map
TABLE 1. Device Register Map
Address Register 7 6 5 4 3 2 1 0
BASIC SETUP
0x00h PMC CHIP PORT2 PORT1 MCLK OSC PLL_P2
ENB
PLL CHIP
SETUP ACTIVE CLK OVR CLK OVR OVR ENB ENB ENABLE
0x01h PMC
CLOCKS PMC_CLK_SEL
0x02h PMC
CLK_DIV PMC_CLK_DIV(R)
PLL
0x03h PLL_CLK_SEL
0x04h PLL M PLL M
0x05h PLL N PLL N
0x06h PLL
N_MOD PLL P2[8] PLL P1[8] PLL N_MOD
0x07h PLL P PLL P1 [7:0]
0x08h PLL P2 PLL P2[7:0]
ANALOG MIXER
0x10h CLASSD AUX_LS MONO_LS DACL_LS DACR_LS
0x11h HEAD AUX_HPL MONO
_HPL DACL_HPL DACR_HPL
PHONESL
0x12h HEAD AUX_HPR MONO
_HPR DACL
_HPR
DACR
_HPR
PHONESR
0x13h AUX_OUT AUX_AUX MONO
_AUX MIC_AUX DACL_AUX DACR
_AUX
0x14h OUTPUT
OPTIONS LS_LEVEL AUX_LINE
_OUT
AUX_NEG
_6dB LR_HP_LEVEL RSVD
0x15h ADC MONO
_ADCL
AUX
_ADCR MIC_ADCL MIC_ADCR DACL
_ADCL
DACR
_ADCR
0x16h MIC_LVL MUTE SE/DIFF MIC_LEVEL
0x18h AUXL_LVL SE/DIFF AUX_LEVEL
0x19h MONO_LV AUXL_MO
NO_IN SE/DIFF MONO_LEVEL
0x1Bh HP
_SENSE HP SENSE
_AUX_D
HP SENSE
_AUX
HP
SENSE_D HP SENSE
ADC
0x20h ADC BASIC DSPONLY ADC_CLK_SEL MUTE_R MUTE_L ADC_OSR MONO
0x21h ADC
CLOCK ADC_CLK_DIV (T)
0x23h ADC
_MIXER STEREO
_LINK ADC_MIX_LEVEL_R ADC_MIX_LEVEL_L
DAC
0x30h DAC
_BASIC DSPONLY DAC_CLK_SEL MUTE_R MUTE_L DAC_OSR
0x31h DAC
_CLOCK DAC_CLK_DIV (S)
DIGITAL MIXER
0x40h IPLVL1 PORT2_RX_R_LVL PORT2_RX_L_LVL PORT1_RX_R_LVL PORT1_RX_L_LVL
0x41h IPLVL2 INTERP_L_LVL INTERP_R_LVL ADC_R_LVL ADC_L_LVL
0x42h OPPORT1 MONO SWAP R_SEL L_SEL
0x43h OPPORT2 MONO SWAP R_SEL L_SEL
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LM49352
Address Register 7 6 5 4 3 2 1 0
0x44h OPDAC SWAP ADCR PORT2R PORT1R ADCL PORT2L PORT1L
0x45h OPDECI MXRCLK_SEL R_SEL L_SEL
AUDIO PORT 1
0x50h BASIC
STEREO
_SYNC
_MODE
STEREO
_SYNC
_PHASE
CLK_PH SYNC_MS CLK_MS TX_ENB RX_ENB STEREO
0x51h CLK_GEN1 CLK_SEL HALF_CYCLE_DIVDER
0x52h CLK_GEN2 SYNTH
_DENOM SYNTH_NUM
0x53h SYNC
_GEN SYNC_WIDTH(MONO MODE) SYNC_RATE
0x54h DATA
_WIDTH TX_EXTRA_BITS TX_WIDTH RX_WIDTH
0x55h RX_MODE A/ULAW COMPAND MSB_POSITION RX_MODE
0x56h TX_MODE A/ULAW COMPAND MSB_POSITION TX_MODE
AUDIO PORT 2
0x60h BASIC
STEREO
_SYNC
_MODE
STEREO
_SYNC
_PHASE
CLK_PH SYNC_MS CLK_MS TX_ENB RX_ENB STEREO
0x61h CLK_GEN1 CLK_SEL HALF_CYCLE_DIVDER
0x62h CLK_GEN2 SYNTH_D
ENOM SYNTH_NUM
0x63h SYNC
_GEN SYNC_WIDTH (MONO MODE) SYNC_RATE
0x64h DATA
_WIDTH TX_EXTRA_BITS TX_WIDTH RX_WIDTH
0x65h RX_MODE A/ULAW COMPAND MSB_POSITION RX_MODE
0x66h TX_MODE A/ULAW COMPAND MSB_POSITION TX_MODE
EFFECTS ENGINE
0x70h ADC FX ADC ADC ADC ADC ADC
SCLP ENB EQ ENB PK ENB ALC ENB HPF_ENB
0x71h DAC FX DAC RSVD DAC DAC DAC
SCLP ENB EQ ENB PK ENB ALC ENB
ADC EFFECTS
0x80h HPF HPF MODE
0x81h ADC SOURCE SOURCE SOURCE STEREO LIMITER ADC_SAMPLE
ALC 1 OVR RSEL LSEL LINK
0x82h ADC NG_ENB NOISE_FLOOR
ALC 2
0x83h ADC ALC_TARGET_LEVEL
ALC 3
0x84h ADC ATTACK_RATE
ALC 4
0x85h ADC PK_DECAY_RATE DECAY_RATE/RELEASE_RATE
ALC 5
0x86h ADC HOLDTIME
ALC 6
0x87h ADC MAX_LEVEL
ALC 7
0x88h ADC MIN_LEVEL
ALC 8
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LM49352
Address Register 7 6 5 4 3 2 1 0
0x89h ADC L STEREO
LINK ADC_L_LEVEL
LEVEL
0x8Ah ADC R ADC_R_LEVEL
LEVEL
0x8Bh EQ BAND 1 LEVEL FREQ
0x8Ch EQ BAND 2 Q LEVEL FREQ
0x8Dh EQ BAND 3 Q LEVEL FREQ
0x8Eh EQ BAND 4 Q LEVEL FREQ
0x8Fh EQ BAND 5 LEVEL FREQ
0x90h SOFTCLIP
1 SOFT
KNEE THRESHOLD
0x91h SOFTCLIP
2 RATIO
0x92h SOFTCLIP
3 LEVEL
ADC EFFECT MONITORS
0x98h LVLMONL ADC LEFT LEVEL MONITOR
0x99h LVLMONR ADC RIGHT LEVEL MONITOR
0x9Ah FXCLIP SCLP
_R CLIP
SCLP
_L CLIP
EQ
_R CLIP
EQ
_L CLIP
GAIN
_R CLIP
GAIN
_L CLIP
ADC
_R CLIP
ADC
_L CLIP
0x9Bh ALCMONL SCLP_R SCLP_L ADC LEFT ALC MONITOR
DISTORT DISTORT
0x9Ch ALCMONR SCLP_L SCLP_R ADC RIGHT ALC MONITOR
DISTORT DISTORT
DAC EFFECTS
0xA0h DAC STEREO LIMITER DAC_SAMPLE
ALC 1 LINK
0xA1h DAC NG_ENB NOISE_FLOOR
ALC 2
0xA2h DAC AGC_TARGET_LEVEL
ALC 3
0xA3h DAC ATTACK_RATE
ALC 4
0xA4h DAC PK_DECAY_RATE DECAY_RATE/RELEASE_RATE
ALC 5
0xA5h DAC HOLDTIME
ALC 6
0xA6h DAC MAX_LEVEL
ALC 7
0xA7h DAC MIN_LEVEL
ALC 8
0xA8h DAC L STEREO
LINK DAC_L_LEVEL
LEVEL
0xA9h DAC R DAC_R_LEVEL
LEVEL
0xABh EQ BAND 1 LEVEL FREQ
0xACh EQ BAND 2 Q LEVEL FREQ
0xADh EQ BAND 3 Q LEVEL FREQ
0xAEh EQ BAND 4 Q LEVEL FREQ
0xAFh EQ BAND 5 LEVEL FREQ
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LM49352
Address Register 7 6 5 4 3 2 1 0
0xB0h SOFTCLIP
1 SOFT
KNEE THRESHOLD
0xB1h SOFTCLIP
2 RATIO
0xB2h SOFTCLIP
3 LEVEL
DAC EFFECT MONITORS
0xB8h LVLMONL DAC LEFT LEVEL MONITOR
0xB9h LVLMONR DAC RIGHT LEVEL MONITOR
0xBAh FXCLIP SCLP
_R CLIP
SCLP
_L CLIP
EQ
_R CLIP
EQ
_L CLIP RSVD RSVD GAIN
_R CLIP
GAIN
_L CLIP
0xBBh ALCMONL SCLP_R SCLP_L DAC LEFT ALC MONITOR
DISTORT DISTORT
0xBCh ALCMONR SCLP_L SCLP_R DAC RIGHT ALC MONITOR
DISTORT DISTORT
GPIO
0xE0h GPIO1 GPIO_RX GPIO_TX GPIO_MODE
0xE1h GPIO2 TEMP SHORT
SPREAD SPECTRUM
0xF0h RESET SOFT
_RESET RSVD RSVD RSVD RSVD RSVD
0xF1h SS SS
_DISABLE RSVD RSVD
0xFEh FORCE CPFORCE DACREF RSVD
Unless otherwise specified, the default values of the I2C reg-
isters is 0x00h.
TABLE 2. Nonzero I2C Default Registers
Address Register Default Data Value
0x02h PMC_CLK_DIV 0x50h
0x30h DAC_BASIC 0x02h
0x31h DAC_CLOCK 0x03h
0x84h ADC_ALC_4 0x0Ah
0x85h ADC_ALC_5 0x0Ah
0x86h ADC_ALC_6 0x0Ah
0x87h ADC_ALC_7 0x1Fh
0x89h ADC_L_LEVEL 0x33h
0x8Ah ADC_R_LEVEL 0x33h
0xA3h DAC_ALC_4 0x0Ah
0xA4h DAC_ALC_5 0x0Ah
0xA5h DAC_ALC_6 0x0Ah
0xA6h DAC_ALC_7 0x33h
0xA8h DAC_L_LEVEL 0x33h
0xA9h DAC_R_LEVEL 0x33h
0xF0h RESET 0x02h
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LM49352
14.0 Basic PMC Setup Register
This register is used to control the LM49352's Basic Power Management Setup:
TABLE 3. PMC_SETUP (0x00h)
Bits Field Description
0 CHIP_ENABLE
When this bit is set the power management will enable the MCLK I/O or internal
oscillator1. It will then use this clock to sequence the enabling of the analog references and
bias points. When this bit is cleared the PMC will bring the analog down gently and disable
the MCLK or oscillator.
CHIP _ENABLE Chip Status
0 Turn Chip Off
1 Turn Chip On
1 PLL_ENB
This enables the PLL.
PLL_ENABLE PLL Status
0 PLL Off
1 PLL On
2 PLL_P2ENB
This enables the P2 output of the PLL.
PLL_P2ENB PLL P2 Status
0 PLL P2 Off
1 PLL P2 On
3 OSC_ENB
This enables the internal 300kHz Oscillator. For analog only chip modes, the oscillator can
be used instead of an external system clock to drive the chip's power management (PMC).
OSC_ENABLE Oscillator Status
0 Oscillator Off
1 Oscillator On
4 MCLK_OVR
This forces the MCLK input to enable, regardless of requirement. If set, the audio ports and
digital mixer can be activated even if the chip is in shutdown mode. This assumes that MCLK
is selected as the PMC clock source (reg 0x01h) and that there is an active clock signal
driving the MCLK pin. Setting this bit reduces power consumption, by allowing audio ports
and digital mixer to operate while the analog sections of the chip are powered down.
MCLK_OVR Comment
0 I/O control is automatic
1 MCLK input forced on.
5 PORT1_CLK_OVR
This forces the clock input of Audio Port 1 input to enable, regardless of other port settings.
PORT1_CLK_OVR Comment
0 I/O control is automatic
1 PORT_CLK input forced on
6 PORT2_CLK_OVR
This forces the clock input of Audio Port 2 input to enable, regardless of other port settings.
PORT2_CLK_OVR Comment
0 I/O control is automatic
1 PORT_CLK input forced on
7 CHIP_ACTIVE This bit is used to readback the enable status of the chip.
1. If the PMC is set to operate from one of the audio ports then it will wait for the port to be enabled or the relevant override bit to
be set, forcing the port clock input to enable.
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LM49352
15.0 PMC Clocks Register
This register is used to control the LM49352's Basic Power Management Clock:
TABLE 4. PMC_SETUP (0x01h)
Bits Field Description
1:0 PMC_CLK_SEL This selects the source of the PMC input clock.
PMC_CLK_SEL PMC Input Clock Source
00 MCLK (Default divide is 40.5)
01 Internal 300kHz Oscillator
10 DAC SOURCE CLOCK
11 ADC SOURCE CLOCK
16.0 PMC Clock Divide Register
This register is used to control the LM49352's Power Management Circuit Clock Divider:
TABLE 5. PMC_SETUP (0x02h)
Bits Field Description
7:0 PMC_CLK_DIV This programs the half cycle divider that precedes the PMC. The PMC should run from a
300kHz clock. The default of this divider is 0x50h (divide by 40.5) to get a ≈300kHz PMC
clock from a 12MHz or 12.288MHz MCLK.
Program this divider with the required division, multiplied by 2, and subtract 1.
PMC_CLK_DIV Divide by
00000000 1
00000001 1
00000010 1.5
00000011 2
00000100 2.5
00000101 3
— —
11111101 126
11111110 127.5
11111111 128
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LM49352
17.0 LM49352 Clock Network
(Refer to Figure 12)
The audio DAC and ADC operate at a clock frequency of 2*OSR*fS where OSR is the oversampling ratio and fS is the sampling
frequency of the DAC or ADC. The DAC can operate at three different OSR settings (128, 125, 64). The ADC can operate at two
different OSR settings (128, 125). For example, if the stereo DAC or ADC is set at OSR = 128, a 12.288MHz clock is required for
48kHz data. If a 12.288MHz clock is not available, then the internal PLL can be used to generate the desired clock frequency.
Otherwise, if a 12.288MHz is available, the PLL can be bypassed to reduce power consumption. The DAC clock divider or ADC
clock divider can also be used to generate the correct clock. If an 18.432 MHz clock is available, the DAC or ADC clock divider
could be set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without using a PLL.
The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by the MCLK input,
the PORT1_CLK input, the PORT2_CLK input, or PLL output.
For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to the PLL can come
from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input.
The LM49352's Power Management Circuit (PMC) requires a clock that is independent from the DAC or ADC. It is recommended
to provide a ≈300kHz clock at Point C. The PMC clock divider is available to generate the correct clock to the PMC block. The
PMC clock path can be driven directly by the MCLK input, the internal 300kHz oscillator, the DAC_SOURCE_CLK, or the
ADC_SOURCE_CLK.
TABLE 6. DAC Clock Requirements
DAC Sample Rate
(kHz)
Clock Required at A
(OSR = 128)
Clock Required at A
(OSR = 125)
Clock Required at A
(OSR = 64)
Clock Required at A
(OSR = 32)
8 2.048 MHz 2 MHz 1.024 MHz 0.512 MHz
11.025 2.8224 MHz 2.75625 MHz 1.4112 MHz 0.7056 MHz
12 3.072 MHz 3 MHz 1.536 MHz 0.768 MHz
16 4.096 MHz 4 MHz 2.048 MHz 1.024 MHz
22.05 5.6448 MHz 5.5125 MHz 2.8224 MHz 1.4112 MHz
24 6.144 MHz 6 MHz 3.072 MHz 1.536 MHz
32 8.192 MHz 8 MHz 4.096 MHz 2.048MHz
44.1 11.2896 MHz 11.025 MHz 5.6448 MHz 2.8224 MHz
48 12.288 MHz 12 MHz 6.144 MHz 3.072 MHz
96 24.576 MHz 24 MHz 12.288 MHz 6.144 MHz
TABLE 7. ADC Clock Requirements
ADC Sample Rate
(kHz)
Clock Required at B
(OSR = 128)
Clock Required at B
(OSR = 125)
8 2.048 MHz 2 MHz
11.025 2.8224 MHz 2.75625 MHz
12 3.072 MHz 3 MHz
16 4.096 MHz 4 MHz
22.05 5.6448 MHz 5.5125 MHz
24 6.144 MHz 6 MHz
32 8.192 MHz 8 MHz
44.1 11.2896 MHz 11.025 MHz
48 12.288 MHz 12 MHz
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LM49352
30072713
FIGURE 12. Internal Clock Network
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LM49352
18.0 PLL Setup Registers
30072730
FIGURE 13. PLL Loop
The LM49352 contains a PLL for flexible operation of its dual audio ports. The PLL has a P1 and P2 output divider thereby allowing
the PLL to generate two distinct clock outputs. The equations for the PLL's generated output clocks are as follows:
fOUT1 = (fIN . N / M . P1)
fOUT2 = (fIN . N / M . P2)
where:
N = PLL_N + PLL_N_MOD
M = (PLL_M + 1) / 2
P1 = (PLL_P1 + 1) / 2
P2 = (PLL_P2 + 1) / 2
The VCO frequency and comparison frequencies are as follows:
fVCO = fOUT.P
fCOMP = fIN/M
Keep fVCO between 140MHz to 240MHz and keep fCOMP between 700KHz to 5MHz.
TABLE 8. PLL Settings for Common System Clock Frequencies
fIN (MHz) M N N_MOD P fOUT (Hz) Error (Hz)
12 2.5 32 0 12.5 12288000 0
13 15.5 175 26 12 12287970 –30
14.4 12.5 128 0 12 12288000 0
16.2 13.5 128 0 12.5 12288000 0
16.8 3.5 32 0 12.5 12288000 0
19.2 12.5 96 0 12 12288000 0
19.68 20.5 160 0 12.5 12288000 0
19.8 16.5 128 0 12.5 12288000 0
26 32.5 192 0 12.5 12288000 0
27 22.5 128 0 12.5 12288000 0
12 12.5 147 0 12.5 11289600 0
12.288 10 147 0 16 11289600 0
13 9 144 19 18.5 11289603 +3
14.4 12.5 147 0 15 11289600 0
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LM49352
fIN (MHz) M N N_MOD P fOUT (Hz) Error (Hz)
16.2 22.5 196 0 12.5 11289600 0
16.8 12.5 126 0 15 11289600 0
19.2 20 147 0 12.5 11289600 0
19.68 20.5 147 0 12.5 11289600 0
19.8 27.5 196 0 12.5 11289600 0
26 18.5 144 19 18 11289602.1 2.1
27 37.5 196 0 12.5 12289600 0
11.2896 10.5 195 0 17.5 12000000 0
12.288 8 125 0 16 12000000 0
13 6.5 102 0 17 12000000 0
13.5 4.5 68 0 17 12000000 0
14.4 6 85 0 17 12000000 0
16.2 13.5 170 0 17 12000000 0
16.8 7 85 0 17 12000000 0
19.2 8 85 0 17 12000000 0
19.68 20.5 200 0 16 12000000 0
19.8 16.5 170 0 17 12000000 0
26 6.5 36 0 12 12000000 0
11.2896 8 125 0 16 11025000 0
12 10 147 0 16 11025000 0
12.288 8 114 27 16 11025000 0
13 6.5 96 15 17.5 11025000 0
13.5 10 147 0 18 11025000 0
14.4 4 49 0 16 11025000 0
16.2 4 49 0 18 11025000 0
16.8 16 189 0 18 11025000 0
19.2 16 147 0 16 11025000 0
19.68 16 189 0 18 11025000 0
19.8 16 147 0 16.5 11025000 0
26 5 27 18 13 1102500 0
TABLE 9. PLL_CLOCK_SOURCE (0x03h)
Bits Field Description
1:0 PLL_CLK_SEL This selects the source of the input clock to the PLL.
PLL_CLK_SEL PLL Input Clock Source
00 MCLK
01 PORT1_CLK
10 PORT2_CLK
11 RESERVED
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LM49352
TABLE 10. PLL_M (0x04h)
Bits Field Description
6:0 PLL_M This programs the PLL's M divider to divide from 1 to 64.
PLL_M PLL Input Divider Value
000000 1
000001 1
000010 1.5
000011 2
000100 2.5
000101 3
— —
1111101 63
1111110 63.5
1111111 64
TABLE 11. PLL_N (0x05h)
Bits Field Description
7:0 PLL_N This programs the PLL N divider to divide from 1 to 250.
PLL_N Feedback Divider Value
00000000 to 00001010 10
00001011 11
00001100 12
00001101 13
00001110 14
00001111 15
— —
11111000 248
11111001 249
11111010 to 11111111 250
TABLE 12. PLL_N_MOD (0x06h)
Bits Field Description
4:0 PLL_N_MOD This programs the sigma-delta modulator in the PLL.
PLL_N_MOD Fractional Part of N
00000 0
00001 1/32
00010 2/32
00011 3/32
00100 4/32
00101 5/32
— —
11101 20/32
11110 30/32
11111 31/32
5 PLL_P1[8] This sets the MSB of the 1st P Divider on the PLL which is part of a standard half-cycle divider
control.
6 PLL_P2[8] This sets the MSB of the 2nd P Divider on PLL which is part of a standard half-cycle divider
control.
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LM49352
TABLE 13. PLL_P1 (0x07h)
Bits Field Description
7:0 PLL_P1[7:0] This programs the 8 LSBs of the PLL's P1 Divider. These LSBs combine with PL1_P1[8] which
allows the P1 divider to divide by up to 256.
PLL_P1 [8:0] P1 Divider Value
000000000 1
000000001 1
000000010 1.5
000000011 2
000000100 2.5
000000101 3
— —
111111101 255
111111110 255.5
111111111 256
TABLE 14. PLL_P2 (0x08h)
Bits Field Description
7:0 PLL_P2[7:0] This programs 8 LSBs of the PLL's P2 Divider. These LSBs combine with PLL_P2[8] which
allows the P2 divider to divide by up to 256.
PLL_P2 [8:0] P2 Divider Value
000000000 1
000000001 1
000000010 1.5
000000011 2
000000100 2.5
000000101 3
— —
111111101 255
111111110 255.5
111111111 256
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LM49352
19.0 Analog Mixer Control Registers
This register is used to control the LM49352's Analog Mixer:
TABLE 15. CLASS_D_OUTPUT (0x10h)
Bits Field Description
0 DACR_LS The right DAC output is added to the loudspeaker output.
1 DACL_LS The left DAC output is added to the loudspeaker output.
2 RSVD Reserved
3 RSVD Reserved
4 MONO_LS The MONO input is added to the loudspeaker output.
5 AUX_LS The AUX input is added to the loudspeaker output.
Class D Loudspeaker Amplifier
The LM49352 features a filterless modulation scheme. The differential outputs of the device switch at 300kHz from VDD to GND.
When there is no input signal applied, the two outputs (LS+ and LS-) switch with a 50% duty cycle, with both outputs in phase.
Because the outputs of the LM49352 are differential, the two signals cancel each other. This results in no net voltage across the
speaker, thus there is no load current during an idle state, conserving power.
With an input signal applied, the duty cycle (pulse width) of the LM49352 outputs changes. For increasing output voltages, the duty
cycle of LS+ increases, while the duty cycle of LS- decreases. For decreasing output voltages, the converse occurs, the duty cycle
of LS- increases while the duty cycle of LS+ decreases. The difference between the two pulse widths yields the differential output
voltage.
Spread Spectrum Modulation
The LM49352 features a fitlerless spread spectrum modulation scheme that eliminates the need for output filters, ferrite beads or
chokes. The switching frequency varies by ±30% about a 300kHz center frequency, reducing the wideband spectral content,
improving EMI emissions radiated by the speaker and associated cables and traces. Where a fixed frequency class D exhibits
large amounts of spectral energy at multiples of the switching frequency, the spread spectrum architecture of the LM49352 spreads
that energy over a larger bandwidth. The cycle-to-cycle variation of the switching period does not affect the audio reproduction or
efficiency.
Class D Power Dissipation and Efficiency
In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required to produce it
with the difference being the power dissipated, typically, in the IC. The key here is “useful” work. For audio systems, the energy
delivered in the audible bands is considered useful including the distortion products of the input signal. Sub-sonic (DC) and super-
sonic components (>22kHz) are not useful. The difference between the power flowing from the power supply and the audio band
power being transduced is dissipated in the LM49352 and in the transducer load. The amount of power dissipation in the LM49352's
class D amplifier is very low. This is because the ON resistance of the switches used to form the output waveforms is typically less
than 0.25Ω. This leaves only the transducer load as a potential "sink" for the small excess of input power over audio band output
power. The LM49352 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to act as a
heat sink.
EMI/RFI Filtering
If system level PCB layout constraints require the LM49352’s Class D output bumps to be placed far away from the speaker or the
Class D output traces to be routed near EMI/RFI sensitive components, an external EMI/RFI filter should be used. A series ferrite
bead placed close to the Class D output bumps along with a shunt capacitor to ground placed close to the ferrite bead will reduce
the EMI/RFI emissions of the Class D amplifier’s switching outputs. The ferrite bead must be rated with a current rating high enough
to properly drive the loudspeaker. The ferrite bead that is rated for 1A or greater is recommended. The DC resistance of the ferrite
bead is another important specification that must be taken into consideration. A low DC resistance will minimize any power losses
dissipated by the EMI/RFI filter thereby preserving the power efficiency advantages of the Class D amplifier. Selecting a ferrite
bead with high DC resistance will decrease output power delivered to speaker and reduce the Class D amplifier’s efficiency. The
shunt capacitor needs to have low ESR. A 10pF ceramic capacitor with a X7R dielectric is recommended as a starting point. Care
needs to be taken to ensure that the value of the shunt capacitor does not exceed 47pF when using a low resistance ferrite bead
in order to prevent permanent damage to the low side FETs of the Class D output stage.
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LM49352
30072732
FIGURE 14. EMI/RFI Filter for the Class D Amplifier
TABLE 16. LEFT HEADPHONE_OUTPUT (0x11h)
Bits Field Description
0 DACR_HPL The right DAC output is added to the left headphone output.
1 DACL_HPL The left DAC output is added to the left headphone output.
2 RSVD Reserved
3 RSVD Reserved
4 MONO_HPL The MONO input is added to the left headphone output.
5 AUX_HPL The AUX input is added to the left headphone output.
TABLE 17. RIGHT HEADPHONE_OUTPUT (0x12h)
Bits Field Description
0 DACR_HPR The right DAC output is added to the right headphone output.
1 DACL_HPR The left DAC output is added to the right headphone output.
2 RSVD Reserved
3 RSVD Reserved
4 MONO_HPR The MONO input is added to the right headphone output.
5 AUX _HPR The AUX input is added to the right headphone output.
Headphone Amplifier Function
The LM49352 headphone amplifier features National’s ground referenced architecture that eliminates the large DC-blocking ca-
pacitors required at the outputs of traditional headphone amplifiers. A low-noise inverting charge pump creates a negative supply
(HP_VSS) from the positive supply voltage (LS_VDD). The headphone amplifiers operate from these bipolar supplies, with the
amplifier outputs biased about GND, instead of a nominal DC voltage (typically VDD/2), like traditional amplifiers. Because there is
no DC component to the headphone output signals, the large DC-blocking capacitors (typically 220μF) are not necessary, con-
serving board space and system cost, while improving frequency response.
Charge Pump Capacitor Selection
Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.
Charge Pump Flying Capacitor (C6)
The flying capacitor (C6) affects the load regulation and output impedance of the charge pump. A C6 value that is too low results
in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C6 improves load regulation and lowers charge
pump output impedance to an extent. Above 2.2μF, the RDS(ON) of the charge pump switches and the ESR of C6 and C5 dominate
the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Please refer
to the demonstration board schematic shown in Figure 27.
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LM49352
Charge Pump Flying Capacitor (C5)
The value and ESR of the hold capacitor (C5) directly affects the ripple on CPVSS. Increasing the value of C5 reduces output ripple.
Decreasing the ESR of C5 reduces both output ripple and charge pump output impedance. A lower value capacitor can be used
in systems with low maximum output power requirements. Please refer to the demonstration board schematic shown in Figure 27.
TABLE 18. AUX_OUTPUT (0x13h)
Bits Field Description
0 DACR_AUX The right DAC output is added to the AUX output.
1 DACL_AUX The left DAC output is added to the AUX output.
2 MIC_AUX The MIC input is added to the AUX output.
3 RSVD Reserved
4 MONO_AUX The MONO input is added to the AUX output.
5 AUX_AUX The AUX input is added to the AUX output.
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LM49352
Auxiliary Output Amplifier
The LM49352’s auxiliary output (AUXOUT) amplifier provides differential drive capability to loads that are connected across its
outputs. This results in output signals at the AUX_OUT+ and AUX_OUT- pins that are 180 degrees out of phase with respect to
each other. This effectively doubles the maximum possible output swing for a specific supply voltage when compared to single-
ended output configurations. The differential output configuration also allows the load to be isolated from ground since both the
AUX_OUT+ and AUX_OUT- pins are biased at the same DC potential. This eliminates the need for any large and expensive DC
blocking capacitors at the AUXOUT amplifier outputs. The load can then be directly connected to the positive and negative outputs
of the AUXOUT amplifier which then isolates it from any ground noise, thereby improving signal to noise ratio (SNR) and power
supply rejection ratio (PSRR).
The AUXOUT amplifier has two modes of operation. The primary mode of operation is high current drive mode (Earpiece Mode)
where the AUXOUT amplifier can be used to differentially drive a mono earpiece speaker. The secondary mode of operation is
low current drive mode where the AUXOUT amplifier operates in a power saving mode (AUX_LINE_OUT Mode) to provide a
differential output that is used as a mono differential line level input to a standalone mono differential input class D amplifier
(LM4675) for stereo loudspeaker applications.
TABLE 19. OUTPUT_OPTIONS (0x14h)
Bits Field Description
0 RSVD Reserved
3:1 LR_HP_LEVEL
This sets the gain of the left and right headphone amplifiers. The gain of the left and right headphone
amplifiers are always set to the same level.
LR_HP_LEVEL Gain (dB)
000 0
001 –1.5
010 –3
011 –6
100 –9
101 –12
110 –15
111 –18
4 AUX_NEG_6dB
This sets the gain of the Auxiliary output amplifier.
AUX_NEG_6dB Gain (dB)
0 0
1 –6
5 AUX_LINE_OUT
This sets the Auxiliary output amplifier mode of operation.
AUX_LINE_OUT Auxiliary Output Mode
0 Earpiece Amplifier
1 AUX_LINE_OUT
7:6 LS_LEVEL
This sets the gain of the Class D loudspeaker amplifier.
LS_LEVEL Gain (dB)
00 0
01 4
10 8
11 12
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LM49352
TABLE 20. ADC_INPUT (0x15h)
Bits Field Description
0 DACR_ADCR The right DAC output is added to the ADC right input.
1 DACL_ADCL The left DAC output is added to the ADC left input.
2 MIC_ADCR The MIC input is added to the ADC right input.
3 MIC_ADCL The MIC input is added to the ADC left input.
4 AUX_ADCR The AUX input is added to the ADC right input.
5 MONO_ADCL The MONO input is added to the ADC left input.
TABLE 21. MIC_INPUT (0x16h)
Bits Field Description
3:0 MIC_LEVEL This sets the gain of the microphone preamp.
MIC_LEVEL Gain
0000 6dB
0001 8dB
0010 10dB
0011 12dB
0100 14dB
0101 16dB
0110 18dB
0111 20dB
1000 22dB
1001 24dB
1010 26dB
1011 28dB
1100 30dB
1101 32dB
1110 34dB
1111 36dB
4 SE_DIFF If set, the MIC negative input is ignored. In single-ended mode, the MIC negative input pin should
left floating.
5 MUTE If set, the microphone preamp is muted.
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LM49352
TABLE 22. AUX_LEVEL (0x18h)
Bits Field Description
5:0 AUX_LEVEL This programs the AUX input level. All gain changes are performed at zero crossings.
AUX_LEVEL Level AUX_LEVEL Level
000000 –46.5dB 100000 1.5dB
000001 –45dB 100001 3dB
000010 –43.5dB 100010 4.5dB
000011 –42dB 100011 6dB
000100 –40.5dB 100100 7.5dB
000101 –39dB 100101 9dB
000110 –37.5dB 100110 10.5dB
000111 –36dB 100111 12dB
001000 –34.5dB 101000 13.5dB
001001 –33dB 101001 15dB
001010 –31.5dB 101010 16.5dB
001011 –30dB 101011 18dB
001100 –28.5dB
001101 –27dB
001110 –25.5dB
001111 –24dB
010000 –22.5dB
010001 –21dB
010010 –19.5dB
010011 –18dB
010100 –16.5dB
010101 –15dB
010110 –13.5dB
010111 –12dB
011000 –10.5dB
011000 –9dB
011001 –7.5dB
011010 –6dB
011100 –4.5dB
011101 –3dB
011110 –1.5dB
011111 0dB
6 SE/DIFF If set, the AUXL input is ignored. In single-ended mode, the AUXL input pin should be left
floating.
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LM49352
TABLE 23. MONO_LEVEL (0x19h)
Bits Field Description
5:0 MONO_LEVEL This programs the MONO input level. All gain changes are performed at zero crossings.
MONO_LEVEL Level MONO_LEVEL Level
000000 –46.5dB 100000 1.5dB
000001 –45dB 100001 3dB
000010 –43.5dB 100010 4.5dB
000011 –42dB 100011 6dB
000100 –40.5dB 100100 7.5dB
000101 –39dB 100101 9dB
000110 –37.5dB 100110 10.5dB
000111 –36dB 100111 12dB
001000 –34.5dB 101000 13.5dB
001001 –33dB 101001 15dB
001010 –31.5dB 101010 16.5dB
001011 –30dB 101011 18dB
001100 –28.5dB
001101 –27dB
001110 –25.5dB
001111 –24dB
010000 –22.5dB
010001 –21dB
010010 –19.5dB
010011 –18dB
010100 –16.5dB
010101 –15dB
010110 –13.5dB
010111 –12dB
011000 –10.5dB
011000 –9dB
011001 –7.5dB
011010 –6dB
011100 –4.5dB
011101 –3dB
011110 –1.5dB
011111 0dB
6 SE/DIFF If set, the MONO– input is ignored. In single-ended mode, the MONO- input pin should
be left floating.
7 AUXL_MONO If set, AUXL is routed to the MONO Input Amplifier.
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LM49352
Headphone Detection Circuit
The LM49352 features a headphone detection circuit (HDC) that automatically enables the headphone amplifier whenever the
insertion of a headphone plug is detected and disables the headphone amplifier during the removal of a headphone plug. The HDC
optimizes power management by automatically disabling any output amplifier that is not in use. The HDC eliminates the necessity
of polling the I2C bus for status changes. However, since the HDC requires the use of the GPIO pin, the PORT2_SDO functionality
sensing is required.
The HDC requires a headphone jack with a normally closed mechanical switch and a pullup resistor, RPU, tied between the me-
chanical switch and I/O_VDD (Refer to Figure 14). Choosing a RPU value of at least 500kΩ ensures minimal current draw through
the pullup resistor. When the headphone amplifier is disabled, an internal 50kΩ pulldown, RPD, is connected to each headphone
amplifier output. Without the presence of a headphone plug, the headphone jack’s mechanical switch is closed thereby connecting
the right headphone amplifier output to RPU. The GPIO pin detects a logic low level due to the voltage division between RPU and
RPD. When the GPIO pin is set to HPSENSE mode, a logic low voltage reading causes the HDC to disable the headphone amplifier.
When a headphone plug is inserted, the mechanical connection between RPU and RPD is broken, resulting in a logic high level
detected by the GPIO pin. A logic high voltage reading causes the HDC to enable the headphone amplifier.
The HDC has four modes of operation that automatically enable/disable different combinations of the audio output amplifiers
contained within the LM49352. Having the choice of four different HDC settings maximizes power management flexibility to suit a
particular application. Please refer to the HP_SENSE (reg 0x1Bh) register table for a detailed discussion on the different HDC
modes of operation.
30072793
FIGURE 15. Application Circuit for Headphone Detection
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LM49352
TABLE 24. HP_SENSE (0x1Bh)
Bits Field Description
0 HP SENSE This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on. If a headphone removal is detected the headphone amplifier will automatically
turn off.
HPSENSE Headphone Sense Status
0 Off
1 On
1 HPSENSE_D This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Class D loudspeaker amplifier will turn off. If a headphone removal is
detected the headphone amplifier will automatically turn off and the Class D loudspeaker amplifier
will turn on. This bit overrides bit 0 of this register.
HPSENSE_D Headphone Sense Status
0 Off
1 On
2 HPSENSE_AUX This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Earpiece / Auxout amplifier will turn off. If a headphone removal is
detected the headphone amplifier will automatically turn off and the Earpiece / Auxout amplifier will
turn on. This bit overrides bit 0 and bit 1 of this register.
HPSENSE_AUX Headphone Sense Status
0 Off
1 On
3 HPSENSE_AUX_D This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Class D loudspeaker amplifier along with the Earpiece / Auxout
amplifier will turn off. If a headphone removal is detected the headphone amplifier will automatically
turn off and the Class D loudspeaker amplifier along with the Earpiece / Auxout amplifier will turn
on. This bit overrides bit 0, bit 1, and bit 2 of this register.
HPSENSE_AUX_D Headphone Sense Status
0 Off
1 On
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LM49352
20.0 ADC Control Registers
This register is used to control the LM49352's ADC:
TABLE 25. ADC Basic (0x20h)
Bits Field Description
0 MONO This sets mono or stereo operation of the ADC.
MONO ADC Operation
0 Stereo Audio
1 Mono Voice (Right ADC channel disabled, Left ADC channel active)
1 OSR This sets the oversampling ratio of the ADC.
OSR Stereo Audio ADC
Oversampling Ratio
Mono Voice ADC Oversampling Ratio
0 128 125
1 128 128
2 MUTE_L If set, a digital mute is applied to the Left (or mono) ADC output.
3 MUTE_R If set, a digital mute is applied to the Right ADC output.
6:4 ADC_CLK_SEL This selects the source of the ADC clock domain, ADC_SOURCE_CLK.
ADC_CLK_SEL Source
000 MCLK
001 PORT1_RX_CLK
010 PORT2_RX_CLK
011 PLL_OUTPUT1
100 PLL_OUTPUT2
7 ADC_DSP_ONLY If set, the ADC's analog circuitry is disabled to reduce power consumption, however, ADC DSP
functionality is maintained. This can be used to perform asynchronous resampling between audio
rates of a common family. Setting this bit is also useful whenever applying Automatic Level Control
(ALC) to an analog only audio path.
TABLE 26. ADC_CLK_DIV (0x21h)
Bits Field Description
7:0 ADC_CLK_DIV This programs the half cycle divider that preceeds the ADC. The input of this divider should be
around 12MHz. The default of this divider is 0x00.
Program this divider with the division you want, multiplied by 2, and subtract 1.
ADC_CLK_DIV Divides by
00000000 1
00000001 1
00000010 1.5
00000011 2
— —
11111101 127
11111110 127.5
11111111 128
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LM49352
TABLE 27. ADC_MIXER (0x23h)
Bits Field Description
1:0 ADC_MIX_LEVEL_L This sets the input level to the left ADC channel.
ADC_MIX_LEVEL_L Level
00 0dB
01 1.35dB
10 3.5dB
11 6dB
3.2 ADC_MIX_LEVEL_R This sets the input level to the right ADC channel.
ADC_MIX_LEVEL_R Level
00 0dB
01 1.35dB
10 3.5dB
11 6dB
4 STEREO_LINK If set, this links ADC_MIX_LEVEL_R with ADC_MIX_LEVEL_L.
STEREO_LINK Status
0 Off
1 On
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LM49352
21.0 DAC Control Registers
This register is used to control the LM49352's DAC:
TABLE 28. DAC Basic (0x30h)
Bits Field Description
1:0 MODE This programs the over sampling ratio of the stereo DAC.
MODE DAC Oversampling Ratio
00 125
01 128
10 64 (Default)
11 RSVD
2 MUTE_L This digitally mutes the Left DAC output.
3 MUTE_R This digitally mutes the Right DAC output.
6:4 DAC_CLK_SEL This selects the source of the DAC clock domain, DAC_SOURCE_CLK.
DAC_CLK_SEL Source
000 MCLK
001 PORT1_RX_CLK
010 PORT2_RX_CLK
011 PLL_OUTPUT1
100 PLL_OUTPUT2
7 DSP_ONLY If set, the DAC's analog circuitry is disabled to reduce power consumption, however DAC DSP
functionality is maintained. This can be used to perform asyncronous resampling between audio rates
of a common family.
TABLE 29. DAC_CLK_DIV (0x31h)
Bits Field Description
7:0 DAC_CLK_DIV This programs the half cycle divider that precedes the DAC. The input of this divider should be
around 12MHz. The default of this divider is 0x03 which gives a division by 2.
Program this divider with the division you want, multiplied by 2, and subtract 1.
DAC_CLK_DIV Divides by
00000000 1
00000001 1
00000010 1.5
00000011 2 (Default)
— —
11111101 127
11111110 127.5
11111111 128
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LM49352
22.0 Digital Mixer Control Registers
Digital Mixer
The LM49352’s digital mixer allows for flexible routing of digital audio signals between both audio ports, DAC, and ADC. This mixer
handles which digital data path (Port1 RX data, Port2 RX data, or ADC output) is routed to the DAC input. The digital mixer also
selects the appropriate digital data path (Port1 RX data, Port2 RX data, ADC output, or DAC DSP (Interpolator) output) that is used
for data transmission on Audio Port 1 and 2. Audio inputs to the digital mixer can be attenuated down to -18dB to avoid clipping
conditions. The digital mixer also allows direct routing from the DAC interpolator output to the ADC decimator input which allows
the DAC and ADC DSP blocks to be cascaded witjhout having to enable the analog of the DAC and ADC in order to save power.
Another key feature of the digital mixer is sample rate conversion (SRC) between audio ports. This allows simultaneous operation
of the dual audio ports even if each port is operating at a different sample rate. The LM49352 can be used as an audio port bridge
with SRC capability. The digital mixer allows either straight pass through between audio ports or, if desired, DSP effects can be
added to the digital audio signal during audio port bridge operation. The digital mixer automatically handles stereo I2S to mono
PCM conversion between audio ports and vice versa.
30072701
FIGURE 16. Digital Mixer
The LM49352 includes two separate and independent DSP blocks, one for the DAC and the other for the ADC. The digital mixer
also allows both DSP blocks to be cascaded together in either order so that the DSP effects from both blocks can be combined
into the same signal path. For example, the 5 band parametric EQ of each DSP block can be combined together to form a 10 band
parametric EQ for added flexibility.
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LM49352
This register is used to control the LM49352's digital mixer:
TABLE 30. Input Levels 1 (0x40h)
Bits Field Description
1:0 PORT1_RX_L
_LVL
This programs the input level of the data arriving from the left receive channel of Audio Port 1.
PORT1_RX_L_LVL Level
00 0dB
01 –6dB
10 –12dB
11 –18dB
3:2 PORT1_RX_R
_LVL
This programs the input level of the data arriving from the right receive channel of Audio Port 1.
PORT1_RX_R_LVL Level
00 0dB
01 –6dB
10 –12dB
11 –18dB
5:4 PORT2_RX_L
_LVL
This programs the input level of the data arriving from the left receive channel of Audio Port 2.
PORT2_RX_L_LVL Level
00 0dB
01 –6dB
10 –12dB
11 –18dB
7:6 PORT2_RX_R
_LVL
This programs the input level of the data arriving from the right receive channel of Audio Port 2.
PORT2_RX_R_LVL Level
00 0dB
01 –6dB
10 –12dB
11 –18dB
TABLE 31. Input Levels 2 (0x41h)
Bits Field Description
1:0 ADC_L_LVL This programs the input level of the data arriving from the left ADC channel.
ADC_L_LVL Level
00 0dB
01 –6dB
10 –12dB
11 –18dB
3:2 ADC_R_LVL This programs the input level of the data arriving from the right ADC channel.
ADC_R_LVL Level
00 0dB
01 –6dB
10 –12dB
11 –18dB
5:4 INTERP_L_LVL This programs the input level of the data arriving from the left DAC's interpolator output.
INTERP_L_LVL Level
00 0dB
01 –6dB
10 –12dB
11 –18dB
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LM49352
Bits Field Description
7:6 INTERP_R_LVL This programs the input level of the data arriving from the right DAC's interpolator output.
INTERP_R_LVL Level
00 0dB
01 –6dB
10 –12dB
11 –18dB
TABLE 32. Audio Port 1 Input (0x42h)
Bits Field Description
1:0 L_SEL This selects which input is fed to the Left TX Channel of Audio Port 1.
L_SEL Selected Input
00 None
01 ADC_L
10 PORT2_RX_L
11 DAC_INTERP_L
3:2 R_SEL This selects which input is fed to the Right TX Channel of Audio Port 1.
R_SEL Selected Input
00 None
01 ADC_R
10 PORT2_RX_R
11 DAC_INTERP_R
4 SWAP If set, this swaps the Left and Right outputs to Audio Port 1.
5 MONO If set, the right channel is ignored and the left channel becomes (left+right)/2.
TABLE 33. Audio Port 2 Input (0x43h)
Bits Field Description
1:0 L_SEL This selects which input is fed to Audio Port 2's Left TX Channel.
L_SEL Selected Input
00 None
01 ADC_L
10 PORT1_RX_L
11 DAC_INTERP_L
3:2 R_SEL This selects which input is fed to Audio Port 2's Right TX Channel.
R_SEL Selected Input
00 None
01 ADC_R
10 PORT1_RX_R
11 DAC_INTERP_R
4 SWAP If set, this swaps the Left and Right outputs to Audio Port 2.
5 MONO If set, the right channel is ignored and the left channel becomes (left+right)/2.
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LM49352
TABLE 34. DAC Input Select (0x44h)
Bits Field Description
0 PORT1_L This adds Audio Port 1's left RX channel to the DAC's left input.
1 PORT2_L This adds Audio Port 2's left RX channel to the DAC's left input.
2 ADC_L This adds the ADC's left output to the DAC's left input.
3 PORT1_R This adds Audio Port 1's right RX channel to the DAC's right input.
4 PORT2_R This adds Audio Port 2's right RX channel to the DAC's right input.
5 ADC_R This adds the ADC's right output to the DAC's right input.
6 SWAP If set, this swaps the Left and Right inputs to the DAC.
TABLE 35. Decimator Input Select (0x45h)
Bits Field Description
1:0 L_SEL This selects which input is fed to the left ADC's decimator input.
L_SEL Selected Input
00 None
01 PORT1_RX_L
10 PORT2_RX_L
11 DAC_INTERP_L
3:2 R_SEL This selects which input is fed to the right ADC's decimator input.
R_SEL Selected Input
00 None
01 PORT1_RX_R
10 PORT2_RX_R
11 DAC_INTERP_R
5:4 MXR_CLK_SEL This selects sets the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source
with the highest clock frequency. If the DAC interpolator output (DAC_OSR_L or DAC_OSR_R) is
selected, then MXR_CLK_SEL should be set to '10'.
MXR_CLK_SEL Selected Input
00 Auto
01 MCLK
10 DAC
11 ADC
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LM49352
23.0 Audio Port Control Registers
30072771
FIGURE 17. I2S Serial Data Format (24 bit example)
30072772
FIGURE 18. Left Justified Data Format (24 bit example)
30072770
FIGURE 19. Right Justified Data Format (24 bit example)
30072734
FIGURE 20. PCM Serial Data Format (16 bit example)
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LM49352
The following registers are used to control the LM49352's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is
programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh) registers.
TABLE 36. BASIC_SETUP (0x50h/0x60h)
Bits Field Description
0 STEREO If set, the audio port will receive and transmit stereo data.
1 RX_ENABLE If set, the input is enabled (enables the SDI port and input shift register and any clock
generation required).
2 TX_ENABLE If set, the output is enabled (enables the SDO port and output shift register and any clock
generation required).
3 CLOCK_MS If set, the audio port will transmit the clock when either the RX or TX is enabled.
4 SYNC_MS If set, the audio port will transmit the sync signal when either the RX or TX is enabled.
5 CLOCK_PHASE This sets how data is clocked by the Audio Port.
CLOCK_PHASE Audio Data Mode
0I2S (TX on falling edge, RX on rising edge)
1 PCM (TX on rising edge, RX on falling edge)
6 STEREO_SYNC_PHASE If set, this reverses the left and right channel data of the Audio Port.
STEREO_SYNC_PHASE Audio Port Data Orientation
0Left channel data goes to left channel output.
Right channel data goes to right channel output.
1Right channel data goes to left channel output.
Left channel data goes to right channel output.
7 SYNC_INVERT If this bit is set the SYNC is inverted before the receiver and transmitter.
SYNC_INVERT SYNC ORIENTATION
0 SYNC Low = Left, SYNC High = Right
1 SYNC Low = Right, SYNC High = Left
TABLE 37. CLK_GEN_1 (0x51h/0x61h)
Bits Field Description
5:0 HALF_CYCLE_CLK_
DIV
This programs the half-cycle divider that generates the master clocks in the audio port. The default
of this divider is 0x00, i.e. bypassed.
Program this divider with the required division multiplied by 2, and subtract 1.
HALF_CYCLE_CLK_DIV Divides By
000000 BYPASS
000001 1
000010 1.5
000011 2
— —
111101 31
111110 31.5
11111 32
6 CLOCK_SEL This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider.
0 = DAC_SOURCE_CLK
1 = ADC_SOURCE_CLK
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LM49352
TABLE 38. CLK_GEN_1 (0x52h/62h)
Bits Field Description
2:0 SYNTH_NUM Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in
master mode.
SYNTH_NUM Numerator
000 SYNTH_DENOM (1/1)
001 100/SYNTH_DENOM
010 96/SYNTH_DENOM
011 80/SYNTH_DENOM
100 72/SYNTH_DENOM
101 64/SYNTH_DENOM
110 48/SYNTH_DENOM
111 0/SYNTH_DENOM
3 SYNTH_DENOM Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master
mode.
SYNTH_DENOM Denominator
0 128
1 125
TABLE 39. CLK_GEN_1 (0x53h/63h)
Bits Field Description
2:0 SYNC_RATE This sets the number of clock cycles before the sync pattern repeats. This depends if the audio port
data is mono or stereo.
In MONO mode:
SYNC_RATE Number of Clock Cycles
000 8
001 12
010 16
011 18
100 20
101 24
110 25
111 32
In STEREO mode:
SYNC_RATE Number of Clock Cycles
000 16
001 24
010 32
011 36
100 40
101 48
110 50
111 64
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LM49352
Bits Field Description
5:3 SYNC_WIDTH In MONO mode, this programs the width (in number of bits) of the SYNC signal.
SYNC_WIDTH Width of SYNC (in bits)
000 1
001 2
010 4
011 7
100 8
101 11
110 15
111 16
TABLE 40. DATA_WIDTHS (0x54h/64h)
Bits Field Description
2:0 RX_WIDTH This programs the expected bits per word of the serial data input SDI.
RX_WIDTH Bits
000 24
001 20
010 18
011 16
100 14
101 13
110 12
111 8
5:3 TX_WIDTH This programs the bits per word of the serial data output SDO.
TX_WIDTH Description
000 24
001 20
010 18
011 16
100 14
101 13
110 12
111 8
7:6 TX_EXTRA_BITS This programs the TX data output padding.
TX_EXTRA_BITS Description
00 0
01 1
10 High-Z
11 High-Z
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LM49352
TABLE 41. RX_MODE (0x55h/x65h)
Bits Field Description
0 RX_MODE This sets the RX data input justification with respect to the SYNC signal.
RX_MODE Description
0 MSB Justified
1 LSB Justified
5:1 MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of
the frame (LSB Justified).
MSB_POSITION Description
00000 0(Left Justified/PCM Long)
00001 1(I2S/PCM Short)
00010 2
00011 3
00100 4
00101 5
00110 6
00111 7
01000 8
01001 9
01010 10
01011 11
01100 12
01101 13
01110 14
01111 15
10000 16
10001 17
10010 18
10011 19
10100 20
10101 21
10110 22
10111 23
11000 24
11001 25
11010 26
11011 27
11100 28
11101 29
11110 30
11111 31
6 COMPAND If set, audio data will be companded.
7μLaw/A-Law This sets the audio companding mode.
μLaw/A-Law Compand Mode
0μLaw
1 A-Law
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LM49352
TABLE 42. TX_MODE (0x56h/x66h)
Bits Field Description
0 TX_MODE This sets the TX data output justification with respect to the SYNC signal.
TX_MODE Description
0 MSB Justified
1 LSB Justified
5:1 MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of
the frame (LSB Justified).
MSB_POSITION Description
00000 0(Left Justified/PCM Long)
00001 1(I2S/PCM Short)
00010 2
00011 3
00100 4
00101 5
00110 6
00111 7
01000 8
01001 9
01010 10
01011 11
01100 12
01101 13
01110 14
01111 15
10000 16
10001 17
10010 18
10011 19
10100 20
10101 21
10110 22
10111 23
11000 24
11001 25
11010 26
11011 27
11100 28
11101 29
11110 30
11111 31
6 COMPAND If set, audio data will be companded.
7μLaw/A-Law This sets the audio companding mode.
μLaw/A-Law Compand Mode
0μLaw
1 A-Law
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LM49352
24.0 Digital Effects Engine
Digital Signal Processor (DSP)
The LM49352 is designed to handle the entire audio signal conditioning and processing within the audio system, thereby freeing
up the workload of any other applications processor contained within the system. The LM49352 features two independent DSPs,
one for the DAC and the other for the ADC. Each DSP is fully featured and performs as a professional quality digital audio effects
engine. Both DSP engines feature digital volume control, automatic level control (ALC), digital soft clip compression, and a 5-band
parametric EQ. The effects chain of each DSP engine is shown by the diagrams below.
30072735
FIGURE 21. ADC DSP Effects Chain
30072736
FIGURE 22. DAC DSP Effects Chain
The ADC and DAC DSP engines can be cascaded together in any order via the digital mixer to combine different audio effects to
the same signal path. For example, a signal can be processed with high-pass filtering from the ADC effects engine with ALC from
the DAC effects engine. The 5-band parametric EQs from each DSP engine can be combined to form a single 10-band parametric
EQ or a single 5-band parametric EQ with ±30dB (instead of ±15dB) gain control for each band.
TABLE 43. ADC EFFECTS (0x70h)
Bits Field Description
0 ADC_HPF_ENB This enables the ADC's High Pass Filter.
1 ADC_ALC_ENB This enables the ADC's Automatic Level Control.
2 ADC_PK_ENB This enables the ADC's Peak Detector.
3 ADC_EQ_ENB This enables the ADC's 5-band Parametric EQ.
4 ADC_SCLP_ENB This enables the ADC's Soft Clip Feature.
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LM49352
TABLE 44. DAC EFFECTS (0x71h)
Bits Field Description
0 DAC_ALC_ENB This enables the DAC's Automatic Level Control.
1 DAC_PK_ENB This enables the DAC's Peak Detector.
2 DAC_EQ_ENB This enables the DAC's 5-band Parametric EQ.
3 RSVD Reserved
4 ADC_SCLP_ENB This enables the DAC's Soft Clip Feature.
TABLE 45. HPF MODE (0x80h)
Bits Field Description
2:0 HPF_MODE This configures the ADC's High Pass Filter (HPF). To calculate the –3dB cutoff frequency, multiply
the coefficient by the sample rate (Hz): fC = Xn.fS(Hz)
HPF_MODE Coefficient Filter Characteristics
fC = 220Hz for:
000 X0 = 0.0275 8kHz Voice
001 X1 = 0.01833 12kHz Voice
010 X2 = 0.01375 16kHz Voice
011 X3 = 0.009166 24kHz Voice
100 X4 = 0.006875 32kHz Voice
fC = 100Hz for:
101 X5 = 0.003125 32kHz Audio
110 X6 = 0.0020833 48kHz Audio
fC = 150Hz for:
111 X7 = 0.0015625 96kHz Audio
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LM49352
ALC Overview
The Automatic Level Control (ALC) system can be used to regulate the audio output level to a user defined target level. The ALC
feature is especially useful whenever the level of the audio input is unknown, unpredictable, or has a large dynamic range. The
main purpose of the ALC is to optimize the dynamic range of the audio input to audio output path.
There are two separate and independent ALC circuits in the LM49352. One of the ALC circuits is located within the DAC DSP
effects block. The other ALC circuit is integrated into the ADC DSP effects block. The DAC ALC controls the DAC digital gain. The
ADC ALC controls the mono/auxiliary input amplifier gain or microphone preamplifier gain. The dual ALCs can be used to regulate
the level of the analog (AUX, MONO, MIC) and digital (Port1 Data In, Port2 Data In) audio inputs. The ALC regulated output can
be routed to any of the LM49352’s amplifier outputs for playback. The ALC regulated output can also be routed to Audio Port1 or
Audio Port2 for digital data transmission via I2S or PCM.
Only audio inputs that are considered signals (rather than noise) are sent to the ALC’s peak detector block. The peak detector
compares the level of the audio input versus the ALC target level (TARGET_LEVEL). Signals lower than the target level will be
amplified and signals higher than the target level will be attenuated. Any audio input that is lower than the level specified by the
noise floor level (NOISE_FLOOR) will be considered as noise and will be gated from the ALC’s peak detector in order to avoid
noise pumping. So it is important to set NOISE_FLOOR to correlate with the signal to noise ratio of the corresponding audio path.
In some instances (ie. Conference calls), it may be desirable to mute audio input signals that consist solely of background noise
from the audio output. This is accomplished by enabling the ALC’s noise gate (NG_ENB). When the noise gate is enabled, signals
lower than the noise floor level will be muted from the audio output.
If the audio input signal is below the target level, the ALC will increase the gain of the corresponding volume control until the signal
reaches the target level. The rate at which the ALC performs gain increases is known as decay rate (DECAY RATE). But before
each ALC gain increase the ALC must wait a predetermined amount of time (HOLD TIME). If the audio input signal is above the
target level, the ALC will decrease the gain of the corresponding volume control until the signal reaches the target level. The rate
at which the ALC performs attenuation is known as attack rate (ATTACK RATE). The ALC’s peak detector tracks increases in
audio input signal amplitude instantaneously, but tracks decreases in audio input signal amplitude at programmable rate (PEAK
DECAY TIME). ATTACK RATE, DECAY RATE, HOLD TIME, and PEAK DECAY TIME are fully adjustable which allows flexible
operation of the ALC circuit. The ALC’s timers are based on the sample rate of the DAC or ADC, so the closest corresponding
sample rate must be programmed into the DAC SAMPLE setting (for DAC ALC) or the ADC SAMPLE (for ADC ALC).
30072791
FIGURE 23. ALC Example
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LM49352
Limiter
The LM49352’s ALC features a limiter function. The purpose of the limiter is to limit the maximum level of the audio signal to the
specified ALC target level. When the limiter is enabled, the ALC will decrease the gain of the volume control whenever the audio
signal is higher than the specified target level. The programmed I2C gain setting when the limiter is first enabled is the maximum
gain setting that the ALC limiter will apply to the audio signal. Gain increases beyond the original I2C gain setting are disabled.
This is in contrast to ALC operation with the limiter disabled, where the ALC may increase gain of audio signals below target level
using gain settings beyond the original I2C gain setting. Therefore, it is important to set the gain of the audio path to the desired
setting before enabling the ALC limiter function.
The limiter’s target level can be set just below the clipping level of the output amplifier or ADC in order to prevent harsh distortions
delivered to the loudspeaker or headphone on the receiving end. This method of ALC limiter operation is also known as “no clip”
mode. Operating the ALC limiter in “no clip” mode maximizes the dynamic range of the audio amplifier or ADC while ensuring that
the audio signal will never clip. Utilizing the ALC limiter in “no clip” mode also protects the loudspeaker from damage due to harmful
overdriven conditions.
The ALC limiter’s target level can also be set for a predetermined maximum output power or voltage level. This method of ALC
limiter operation is known as “power limit” mode. Operating the ALC limiter in “power limit” mode prevents the speaker or headphone
from playing at unsafe hearing levels that can permanently damage the end user’s ears. “Power limit” operation is especially useful
for applications such as listening to music through a set of headphones. Another benefit of using the ALC limit in “power limit” mode
is to extend battery life by reducing power consumption of the output amplifiers during audio playback.
30072792
FIGURE 24. ALC Limiter
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LM49352
TABLE 46. ADC_ALC_1 (0x81h)
Bits Field Description
2:0 ADC_SAMPLE This programs the timers on the ALC with the closest sample rate of the ADC.
ADC_SAMPLE Expected ADC fS
000 8kHz
001 12kHz
010 16kHz
011 24kHz
100 32kHz
101 48kHz
110 96kHz
111 192kHz
3 LIMITER If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the
signal as soon as it reaches target and release it at the decay rate, once signal level reduces below
target. The I2C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC
will apply. Care should be taken when choosing the optimum I2C gain setting whenever enabling
the Limiter.
4 STEREO LINK If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo
output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual
mono.
5 SOURCE_RSEL If both SOURCE_OVR and this bit is set, the right ADC ALC channel will be active.
6 SOURCE_LSEL If both SOURCE_OVR and this bit is set, the left ADC ALC channel will be active.
7 SOURCE_OVR If set, the active channel of the ADC ALC is determined by SOURCE_RSEL and SOURCE_LSEL.
If cleared, the active channel of the ADC ALC is determined by the selected input to the ADC.
MONO enables left ALC, AUX enables right ALC, MIC enables left and / or right ALC depending
on which ADC channel MIC is selected to.
TABLE 47. ADC_ALC_2 (0x82h)
Bits Field Description
3:0 NOISE_FLOOR This sets the anticipated noise floor. Signals lower than the noise floor specified will be gated from
the ALC to avoid noise pumping.
NOISE_FLOOR Noise Floor (dB)
0000 –39
0001 –42
0010 –45
0011 –48
0100 –51
0101 –54
0110 –57
0111 –60
1000 –63
1001 –66
1010 –69
1011 –72
1100 –75
1101 –78
1110 –81
1111 –84
4 NG_ENB This enables the Noise Gate.
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TABLE 48. ADC_ALC_3 (0x83h)
Bits Field Description
4:0 TARGET_LEVEL This sets the desired target output level. Signals lower than this will be amplified and signals larger
than this will be attenuated.
TARGET_LEVEL Target Level (dB)
00000 –1.5
00001 –3
00010 –4.5
00011 –6
00100 –7.5
00101 –9
00110 –10.5
00111 –12
01000 –13.5
01001 –15
01010 –16.5
01011 –18
01100 –19.5
01101 –21
01110 –22.5
01111 –24
10000 –25.5
10001 –27
10010 –28.5
10011 –30
10100 –31.5
10101 –33
10110 –34.5
10111 –36
11000 –37.5
11001 –39
11010 –40.5
11011 –42
11100 –43.5
11101 –45
11110 –46.5
11111 –48
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TABLE 49. ADC_ALC_4 (0x84h)
Bits Field Description
4:0 ATTACK_RATE This sets the rate at which the ALC will reduce gain if it detects the input signal is large.
ATTACK_RATE Time between gain steps (μs)
00000 21
00001 42
00010 83
00011 167
00100 250
00101 333
00110 417
00111 542
01000 729
01001 958
01010 1250 (Default)
01011 1604
01100 1896
01101 2208
01110 2792
01111 3708
10000 4792
10001 5688
10010 6563
10011 8396
10100 11000
10101 14167
10110 17083
10111 20000
11000 25000
11001 32000
11010 45000
11011 60000
11100 75000
11101 87500
11110 100000
11111 114583
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LM49352
TABLE 50. ADC_ALC_5 (0x85h)
Bits Field Description
4:0 DECAY_RATE This sets the rate at which the ALC will increase gain if it detects the input signal is too
small.
DECAY_RATE Time between gain steps (μs)
00000 104
00001 125
00010 167
00011 250
00100 292
00101 396
00110 500
00111 708
01000 896
01001 1250
01010 1396 (Default)
01011 2000
01100 2708
01101 3500
01110 4750
01111 6250
10000 8000
10001 11000
10010 14000
10011 18500
10100 25000
10101 32000
10110 42000
10111 55000
11000 72500
11001 100000
11010 125000
11011 160000
11100 225000
11101 300000
11110 375000
11111 500000 (0.5s)
7:5 PK_DECAY_RATE PK_DECAY_RATE Max Time to track decay
000 1.3ms (Default)
001 2.6ms
010 5.3ms
011 10.6ms
100 21.3ms
101 42.6.3ms
110 85.5ms
111 2.73 secs
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LM49352
TABLE 51. ADC_ALC_6 (0x86h)
Bits Field Description
4:0 HOLD_TIME This sets how long the ALC circuit waits before increasing the gain.
HOLD_TIME Time (ms)
00000 1
00001 1.25
00010 1.6
00011 2
00100 2.5
00101 3.2
00110 4
00111 5
01000 6.25
01001 8
01010 10 (Default)
01011 12.5
01100 16
01101 20
01110 25
01111 32
10000 40
10001 50
10010 64
10011 80
10100 100
10101 125
10110 160
10111 200
11000 250
11001 320
11010 400
11011 500
11100 640
11101 800
11110 1000
11111 1250
TABLE 52. ADC_ALC_7 (0x87h)
Bits Field Description
5:0 MAX_LEVEL This sets the maximum allowed gain of the volume control to the output
amplifier whenever the ALC is use. If the volume control is less than 6 bits
the relevant LSBs are used as the limit and the MSBs are ignored.
TABLE 53. ADC_ALC_8 (0x88h)
Bits Field Description
5:0 MIN_LEVEL This sets the minimum allowed gain of the volume control to the output
amplifier whenever the ALC is use. If the volume control is less than 6 bits the
relevant LSBs are used as the limit and the MSBs are ignored.
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LM49352
TABLE 54. ADC_L_LEVEL (0x89h)
Bits Field Description
5:0 ADC_L_LEVEL This sets the post ADC digital gain of the left channel.
ADC_L_LEVEL Level ADC_L_LEVEL Level
000000 -76.5dB 100000 -28.5dB
000001 -75dB 100001 -27dB
000010 -73.5dB 100010 -25.5dB
000011 -72dB 100011 -24dB
000100 -70.5dB 100100 -22.5dB
000101 -69dB 100101 -21dB
000110 -67.5dB 100110 -20.5dB
000111 -66dB 100111 -18dB
001000 -64.5dB 101000 -16.5dB
001001 -63dB 101001 -15dB
001010 -61.5dB 101010 -13.5dB
001011 -60dB 101011 -12dB
001100 -58.5dB 101100 -10.5dB
001101 -57dB 101101 -9dB
001110 -55.5dB 101110 -7.5dB
001111 -54dB 101111 -6dB
010000 -52.5dB 110000 -4.5dB
010001 -51dB 110001 -3dB
010010 -49.5dB 110010 -1.5dB
010011 -48dB 110011 0dB
010100 -46.5dB 110100 1.5dB
010101 -45dB 110101 3dB
010110 -43.5dB 110110 4.5dB
010111 -42dB 110111 6dB
011000 -40.5dB 111000 7.5dB
011001 -39dB 111001 9dB
011010 -37.5dB 111010 10.5dB
011011 -36dB 111011 12dB
011100 -34.5dB 111100 13.5dB
011101 -33dB 111101 15dB
011110 -31.5dB 111110 16.5dB
011111 -30dB 111111 18dB
6 STEREO_LINK If set, this links the ADC_R_LEVEL with ADC_L_LEVEL.
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LM49352
TABLE 55. ADC_R_LEVEL (0x8Ah)
Bits Field Description
5:0 ADC_R_LEVEL This sets the post ADC digital gain of the right channel.
ADC_R_LEVEL Level ADC_R_LEVEL Level
000000 -76.5dB 100000 -28.5dB
000001 -75dB 100001 -27dB
000010 -73.5dB 100010 -25.5dB
000011 -72dB 100011 -24dB
000100 -70.5dB 100100 -22.5dB
000101 -69dB 100101 -21dB
000110 -67.5dB 100110 -20.5dB
000111 -66dB 100111 -18dB
001000 -64.5dB 101000 -16.5dB
001001 -63dB 101001 -15dB
001010 -61.5dB 101010 -13.5dB
001011 -60dB 101011 -12dB
001100 -58.5dB 101100 -10.5dB
001101 -57dB 101101 -9dB
001110 -55.5dB 101110 -7.5dB
001111 -54dB 101111 -6dB
010000 -52.5dB 110000 -4.5dB
010001 -51dB 110001 -3dB
010010 -49.5dB 110010 -1.5dB
010011 -48dB 110011 0dB
010100 -46.5dB 110100 1.5dB
010101 -45dB 110101 3dB
010110 -43.5dB 110110 4.5dB
010111 -42dB 110111 6dB
011000 -40.5dB 111000 7.5dB
011001 -39dB 111001 9dB
011010 -37.5dB 111010 10.5dB
011011 -36dB 111011 12dB
011100 -34.5dB 111100 13.5dB
011101 -33dB 111101 15dB
011110 -31.5dB 111110 16.5dB
011111 -30dB 111111 18dB
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LM49352
TABLE 56. EQ_BAND_1 (0x8Bh)
Bits Field Description
1:0 FREQ This sets the Sub-bass shelving filter's cut-off frequency. The cut-off
frequencies shown are based on a 48kHz sample rate. Using lower sample
rates will scale down the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 60
01 80
10 100
11 120
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
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LM49352
TABLE 57. EQ_BAND_2 (0x8Ch)
Bits Field Description
1:0 FREQ This sets the Bass peak filter's center frequency. The cut-off frequencies
shown are based on a 48kHz sample rate. Using lower sample rates will scale
down the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 150
01 200
10 250
11 300
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
7 Q Programs the width of the peak filter.
Q Bandwidth
0 2/3 Octave
1 4/3 Octave
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LM49352
TABLE 58. EQ_BAND_3 (0x8Dh)
Bits Field Description
1:0 FREQ This sets the Mid peak filter's center frequency. The cut-off frequencies shown
are based on a 48kHz sample rate. Using lower sample rates will scale down
the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 600
01 800
10 1k
11 1.2k
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
7 Q This programs the width of the peak filter.
Q Bandwidth
0 2/3 Octave
1 4/3 Octave
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LM49352
TABLE 59. EQ_BAND_4 (0x8Eh)
Bits Field Description
1:0 FREQ This sets the Treble peak filter's center frequency. The cut-off frequencies
shown are based on a 48kHz sample rate. Using lower sample rates will scale
down the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 2k
01 2.7k
10 3.4k
11 4.1k
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
7 Q This programs the width of the peak filter.
Q Bandwidth
0 2/3 Octave
1 4/3 Octave
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LM49352
TABLE 60. EQ_BAND_5 (0x8Fh)
Bits Field Description
1:0 FREQ This sets the presence shelving filter's cut-off frequency. The cut-off
frequencies shown are based on a 48kHz sample rate. Using lower sample
rates will scale down the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 7k
01 9k
10 11k
11 13k
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
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LM49352
Digital Audio Compressor
The LM49352 features a digital audio compressor on both the DAC and ADC paths. The compressor works by reducing the level
of the audio signal that is higher than the level set by the audio compressor threshold level (THRESHOLD) by a fixed ratio (com-
pressor output / compressor input) that is set by a predetermined audio compression ratio (RATIO). Higher compression ratios
result in more compression as shown in Figure 24. The audio compressor can be used in conjunction with the ALC to limit audio
peaks that the ALC may not be fast enough to react to.
30072789
FIGURE 25. Audio Compressor Effect
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LM49352
Soft Knee Function
The LM49352’s audio compressor also features a soft knee function that smoothes the harsh edges found during clipping of an
audio signal. For audio signals higher than the compressor threshold level, the soft knee function gradually increases the com-
pression ratio for increasing levels of audio signal beyond the compressor threshold. To achieve the smoothing effect to prevent
hard clipping, the soft knee function initially compresses the audio signal at the smallest ratio and then incrementally increases the
compression ratio if required. The highest level of compression applied by the soft knee function is set by the compressor ratio.
The effect of the soft knee function is shown in Figure 26.
30072790
FIGURE 26. Soft Knee Example with Compression Ratio Setting of 1:3.4
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LM49352
TABLE 61. SOFTCLIP1 (0x90h)
Bits Field Description
3:0 THRESHOLD This sets the threshold level of the audio compressor. Audio signals above
the threshold will be compressed.
THRESHOLD Threshold Level (dB)
0000 -36dB
0001 -30dB
0010 -24dB
0011 -20dB
0100 -18dB
0101 -17dB
0110 -16dB
0111 -15dB
1000 -14dB
1001 -12dB
1010 -10dB
1011 -8dB
1100 -6dB
1101 -4dB
1110 -2.5dB
1111 -1dB
4 SOFT_KNEE If set, the audio compressor will automatically apply higher compression ratios
to audio signals higher than the threshold level. As the audio signal
approaches levels higher than the threshold, SOFT_KNEE will increase the
compression RATIO. The highest compression that the SOFT_KNEE
algorithm will apply is the compression that is set by RATIO.
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LM49352
TABLE 62. SOFTCLIP2 (0x91h)
Bits Field Description
4:0 RATIO This sets the ratio at which the audio is compressed to when it passes beyond
the threshold. In SOFT_KNEE mode this is the final level of compression.
RATIO Ratio
00000 1:1 (Bypass)
00001 1:1.2
00010 1:1.4
00011 1:1.7
00100 1:2.0
00101 1:2.4
00110 1:2.8
00111 1:3.4
01000 1:4.0
01001 1:4.7
01010 1:5.7
01011 1:6.7
01100 1:8.0
01101 1:9.5
01110 1:11.3
01111 1:13.5
10000 1:16.0
10001 1:19.0
10010 1:22.8
10011 1:27.0
10100 1:32.0
10101 1:37.9
10110 1:45.5
10111 1:53.9
11000 1:64.0
11001 1:75.0
11010 1:91.0
11011 1:108
11100 1:128
11101 1:152
11110 1:182
11111 1:215
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LM49352
TABLE 63. SOFTCLIP3 (0x92h)
Bits Field Description
3:0 LEVEL This sets the post compressor gain level.
LEVEL Level (dB)
00000 -22.5dB
00001 -21dB
00010 -19.5dB
00011 -18dB
00100 -16.5dB
00101 -15dB
00110 -13.5dB
00111 -12dB
01000 -10.5dB
01001 -9dB
01010 -7.5dB
01011 -6dB
01100 -4.5dB
01101 -3dB
01110 -1.5dB
01111 0dB
10000 1.5dB
10001 3dB
10010 4.5dB
10011 6dB
10100 7.5dB
10101 9dB
10110 10.5dB
10111 12dB
11000 13.5dB
11001 15dB
11010 16.5dB
11011 18dB
11100 19.5dB
11101 21dB
11110 22.5dB
11111 24dB
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LM49352
25.0 DAC Effects Registers
TABLE 64. DAC_ALC_1 (0xA0h)
Bits Field Description
2:0 DAC_SAMPLE This programs the timers on the ALC with the closest DAC sample rate.
DAC_SAMPLE Expected DAC fS
000 8kHz
001 12kHz
010 16kHz
011 24kHz
100 32kHz
101 48kHz
110 96kHz
111 192kHz
3 LIMITER If set, the circuit will never apply gain to the signal, no matter how small, but
it will attenuate the signal as soon as it reaches target and release it at the
decay rate, once signal level reduces below target. The I2C gain setting (at
the time the LIMITER is enabled) is the maximum gain that the ALC will apply.
Care should be taken when choosing the optimum I2C gain setting whenever
enabling the Limiter.
4 STEREO LINK If set, the ALC circuit uses the stereo average of the input signals to control
the gain of the stereo output. This maintains stereo imaging. If this bit is
cleared, then both channels operate as dual mono.
TABLE 65. DAC_ALC_2 (0xA1h)
Bits Field Description
3:0 NOISE_FLOOR This sets the anticipated noise floor. Signals lower than the specified noise
floor will be gated from the ALC to avoid noise pumping.
NOISE_FLOOR Noise Floor (dB)
0000 -39
0001 -42
0010 -45
0011 -48
0100 -51
0101 -54
0110 -57
0111 -60
1000 -63
1001 -66
1010 -69
1011 -72
1100 -75
1101 -78
1110 -81
1111 -84
4 NG_ENB This enables the Noise Gate
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LM49352
TABLE 66. DAC_ALC_3 (0xA2h)
Bits Field Description
4:0 TARGET_LEVEL This sets the desired output level. Signals lower than this will be amplified
and signals larger than this will be attenuated.
TARGET_LEVEL Target Level (dB)
00000 -1.5
00001 -3
00010 -4.5
00011 -6
00100 -7.5
00101 -9
00110 -10.5
00111 -12
01000 -13.5
01001 -15
01010 -16.5
01011 -18
01100 -19.5
01101 -21
01110 -22.5
01111 -24
10000 -25.5
10001 -27
10010 -28.5
10011 -30
10100 -31.5
10101 -33
10110 -34.5
10111 -36
11000 -37.5
11001 -39
11010 -40.5
11011 -42
11100 -43.5
11101 -45
11110 -46.5
11111 -48
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LM49352
TABLE 67. DAC_ALC_4 (0xA3h)
Bits Field Description
4:0 ATTACK_RATE This sets the rate at which the ALC will reduce gain if it detects the input
signal is too large.
ATTACK_RATE Time between gain steps (μs)
00000 21
00001 42
00010 83
00011 167
00100 250
00101 333
00110 417
00111 542
01000 729
01001 958
01010 1250 (Default)
01011 1604
01100 1896
01101 2208
01110 2792
01111 3708
10000 4792
10001 5688
10010 6563
10011 8396
10100 11000
10101 14167
10110 17083
10111 20000
11000 25000
11001 32000
11010 45000
11011 60000
11100 75000
11101 87500
11110 100000
11111 114583
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LM49352
TABLE 68. DAC_ALC_5 (0xA4h)
Bits Field Description
4:0 DECAY_RATE This sets the rate at which the ALC will increase gain if it detects the input
signal is too small.
DECAY_RATE Time between gain steps(us)
00000 104
00001 125
00010 167
00011 250
00100 292
00101 396
00110 500
00111 708
01000 896
01001 1250
01010 1396 (Default)
01011 2000
01100 2708
01101 3500
01110 4750
01111 6250
10000 8000
10001 11000
10010 14000
10011 18500
10100 25000
10101 32000
10110 42000
10111 55000
11000 72500
11001 100000
11010 125000
11011 160000
11100 225000
11101 300000
11110 375000
11111 500000 (0.5s)
7:5 PK_DECAY_RATE This sets how precise the ALC will track amplitude reductions of the audio
input. The shorter the length of time for PK_DECAY_RATE, the more
responsive the ALC will be when applying gain increases whenever the audio
falls below target level.
PK_DECAY_RATE Time
000 1.3ms (Default)
001 2.6ms
010 5.3ms
011 10.6ms
100 21.3ms
101 42.6ms
110 85.5ms
111 2.73secs
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TABLE 69. DAC_ALC_6 (0xA5h)
Bits Field Description
4:0 HOLD_TIME This sets how long the ALC circuit waits before increasing the gain.
HOLDTIME Time (ms)
00000 1
00001 1.25
00010 1.6
00011 2
00100 2.5
00101 3.2
00110 4
00111 5
01000 6.25
01001 8
01010 10 (Default)
01011 12.5
01100 16
01101 20
01110 25
01111 32
10000 40
10001 50
10010 64
10011 80
10100 100
10101 125
10110 160
10111 200
11000 250
11001 320
11010 400
11011 500
11100 640
11101 800
11110 1000
11111 1250
TABLE 70. DAC_ALC_7 (0xA6h)
Bits Field Description
5:0 MAX_LEVEL This sets the maximum allowed gain to the digital level control when the
ALC is used.
TABLE 71. DAC_ALC_8 (0xA7h)
Bits Field Description
5:0 MIN_LEVEL This sets the minimum allowed gain to the digital level control when the ALC
is used.
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TABLE 72. DAC_L_LEVEL (0xA8h)
Bits Field Description
5:0 DAC_L_LEVEL This sets the pre DAC digital gain.
DAC_L_LEVEL Level DAC_L_LEVEL Level
000000 -76.5dB 100000 -28.5dB
000001 -75dB 100001 -27dB
000010 -73.5dB 100010 -25.5dB
000011 -72dB 100011 -24dB
000100 -70.5dB 100100 -22.5dB
000101 -69dB 100101 -21dB
000110 -67.5dB 100110 -20.5dB
000111 -66dB 100111 -18dB
001000 -64.5dB 101000 -16.5dB
001001 -63dB 101001 -15dB
001010 -61.5dB 101010 -13.5dB
001011 -60dB 101011 -12dB
001100 -58.5dB 101100 -10.5dB
001101 -57dB 101101 -9dB
001110 -55.5dB 101110 -7.5dB
001111 -54dB 101111 -6dB
010000 -52.5dB 110000 -4.5dB
010001 -51dB 110001 -3dB
010010 -49.5dB 110010 -1.5dB
010011 -48dB 110011 0dB
010100 -46.5dB 110100 1.5dB
010101 -45dB 110101 3dB
010110 -43.5dB 110110 4.5dB
010111 -42dB 110111 6dB
011000 -40.5dB 111000 7.5dB
011001 -39dB 111001 9dB
011010 -37.5dB 111010 10.5dB
011011 -36dB 111011 12dB
011100 -34.5dB 111100 13.5dB
011101 -33dB 111101 15dB
011110 -31.5dB 111110 16.5dB
011111 -30dB 111111 18dB
6 STEREO_LINK If set, this links DAC_R_LEVEL with DAC_L_LEVEL.
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TABLE 73. DAC_R_LEVEL (0xA9h)
Bits Field Description
5:0 DAC_R_LEVEL This sets the pre DAC digital gain.
DAC_R_LEVEL Level DAC_R_LEVEL Level
000000 -76.5dB 100000 -28.5dB
000001 -75dB 100001 -27dB
000010 -73.5dB 100010 -25.5dB
000011 -72dB 100011 -24dB
000100 -70.5dB 100100 -22.5dB
000101 -69dB 100101 -21dB
000110 -67.5dB 100110 -20.5dB
000111 -66dB 100111 -18dB
001000 -64.5dB 101000 -16.5dB
001001 -63dB 101001 -15dB
001010 -61.5dB 101010 -13.5dB
001011 -60dB 101011 -12dB
001100 -58.5dB 101100 -10.5dB
001101 -57dB 101101 -9dB
001110 -55.5dB 101110 -7.5dB
001111 -54dB 101111 -6dB
010000 -52.5dB 110000 -4.5dB
010001 -51dB 110001 -3dB
010010 -49.5dB 110010 -1.5dB
010011 -48dB 110011 0dB
010100 -46.5dB 110100 1.5dB
010101 -45dB 110101 3dB
010110 -43.5dB 110110 4.5dB
010111 -42dB 110111 6dB
011000 -40.5dB 111000 7.5dB
011001 -39dB 111001 9dB
011010 -37.5dB 111010 10.5dB
011011 -36dB 111011 12dB
011100 -34.5dB 111100 13.5dB
011101 -33dB 111101 15dB
011110 -31.5dB 111110 16.5dB
011111 -30dB 111111 18dB
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TABLE 74. EQ_BAND_1 (0xABh)
Bits Field Description
1:0 FREQ This sets the Sub-bass shelving filter's cut-off frequency. The cut-off
frequencies shown are based on a 48kHz sample rate. Using lower sample
rates will scale down the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 60
01 80
10 100
11 120
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
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TABLE 75. EQ_BAND_2 (0xACh)
Bits Field Description
1:0 FREQ This sets the Bass peak filter's center frequency. The cut-off frequencies shown
are based on a 48kHz sample rate. Using lower sample rates will scale down
the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 150
01 200
10 250
11 300
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
7 Q This programs the width of the peak filter.
Q Bandwidth
0 2/3 Octave
1 4/3 Octave
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TABLE 76. EQ_BAND_3 (0xADh)
Bits Field Description
1:0 FREQ This sets the Mid peak filter's center frequency. The cut-off frequencies shown
are based on a 48kHz sample rate. Using lower sample rates will scale down
the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 600
01 800
10 1k
11 1.2k
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
7 Q This programs the width of the peak filter.
Q Bandwidth
0 2/3 Octave
1 4/3 Octave
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TABLE 77. EQ_BAND_4 (0xAEh)
Bits Field Description
1:0 FREQ This sets the Treble peak filter's center frequency. The cut-off frequencies
shown are based on a 48kHz sample rate. Using lower sample rates will scale
down the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 2k
01 2.7k
10 3.4k
11 4.1k
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
7 Q This programs the width of the peak filter.
Q Bandwidth
0 2/3 Octave
1 4/3 Octave
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TABLE 78. EQ_BAND_5 (0xAFh)
Bits Field Description
1:0 FREQ This sets the presence shelving filter's cut-off frequency. The cut-off
frequencies shown are based on a 48kHz sample rate. Using lower sample
rates will scale down the cut-off frequencies proportionately.
FREQ Frequency (Hz)
00 7k
01 9k
10 11k
11 13k
6:2 LEVEL This sets the gain at fC.
LEVEL Effect
00000 Off (0dB)
00001 -15dB
00010 -14dB
00011 -13dB
00100 -12dB
00101 -11dB
00110 -10dB
00111 -9dB
01000 -8dB
01001 -7dB
01010 -6dB
01011 -5dB
01100 -4dB
01101 -3dB
01110 -2dB
01111 -1dB
10000 0dB
10001 1dB
10010 2dB
10011 3dB
10100 4dB
10101 5dB
10110 6dB
10111 7dB
11000 8dB
11001 9dB
11010 10dB
11011 11dB
11100 12dB
11101 13dB
11110 14dB
11111 15dB
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LM49352
TABLE 79. SOFTCLIP1 (0xB0h)
Bits Field Description
3:0 TRESHOLD This sets the threshold level of the audio compressor. Audio signals above the
threshold will be compressed.
THRESHOLD Threshold Level (dB)
0000 -36dB
0001 -30dB
0010 -24dB
0011 -20dB
0100 -18dB
0101 -17dB
0110 -16dB
0111 -15dB
1000 -14dB
1001 -12dB
1010 -10dB
1011 -8dB
1100 -6dB
1101 -4dB
1110 -2.5dB
1111 -1dB
4 SOFT_KNEE If set, the audio compressor will automatically apply higher compression ratios
to audio signals higher than the threshold level. As the audio signal approaches
levels higher than the threshold, SOFT_KNEE will increase the compression
RATIO. The highest compression that the SOFT_KNEE algorithm will apply is
the compression that is set by RATIO.
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TABLE 80. SOFTCLIP2 (0xB1h)
Bits Field Description
4:0 RATIO This sets the ratio at which the audio is compressed to when it passes beyond
the threshold. In soft clip mode this is the final level of compression.
RATIO Ratio
00000 1:1 (Bypass)
00001 1:1.2
00010 1:1.4
00011 1:1.7
00100 1:2.0
00101 1:2.4
00110 1:2.8
00111 1:3.4
01000 1:4.0
01001 1:4.7
01010 1:5.7
01011 1:6.7
01100 1:8.0
01101 1:9.5
01110 1:11.3
01111 1:13.5
10000 1:16.0
10001 1:19.0
10010 1:22.8
10011 1:27.0
10100 1:32.0
10101 1:37.9
10110 1:45.5
10111 1:53.9
11000 1:64
11001 1:75.9
11010 1:91.0
11011 1:108
11100 1:128
11101 1:152
11110 1:182
11111 1:215
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TABLE 81. SOFTCLIP3 (0xB2h)
Bits Field Description
4:0 LEVEL This sets the post compressor gain level.
LEVEL Level (dB)
00000 -22.5dB
00001 -21dB
00010 -19.5dB
00011 -18dB
00100 -16.5dB
00101 -15dB
00110 -13.5dB
00111 -12dB
01000 -10.5dB
01001 -9dB
01010 -7.5dB
01011 -6dB
01100 -4.5dB
01101 -3dB
01110 -1.5dB
01111 0dB
10000 1.5dB
10001 3dB
10010 4.5dB
10011 6dB
10100 7.5dB
10101 9dB
10110 10.5dB
10111 12dB
11000 13.5dB
11001 15dB
11010 16.5dB
11011 18dB
11100 19.5dB
11101 21dB
11110 22.5dB
11111 24dB
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26.0 GPIO Registers
TABLE 82. GPIO1 (0xE0h)
Bits Field Description
5:0 GPIO_MODE This sets the mode of the GPIO Pin.
GPIO_MODE GPIO STATUS
000000 GPIO Mode is disabled .PORT2_SDO is controlled by the Port2
serial interface configuration. In all the other modes
PORT2_SDO is configured as the GPIO pin.
000001 GPIO_RX (in)
000010 CHIP ENABLE (in)
000011 CHIP ENABLE (in)
000100 ADC MUTE (in)
000101 ADC MUTE (in)
000110 HP SENSE (in)
000111 HP SENSE (in)
001000 SPARE (in)
001001 SPARE (in)
001010 GPIO TX (out)
001011 CHIP ACTIVE (out)
001100 CHIP ACTIVE (out)
001101 HP ENABLE (out)
001110 HP ENABLE (out)
001111 LS ENABLE (out)
010000 LS ENABLE (out)
010001 EP ENABLE (out)
010010 EP ENABLE (out)
010011 ADC CLIPPED (out)
010100 ADC CLIPPED (out)
010101 DAC CLIPPED (out)
010110 DAC CLIPPED (out)
010111 SOMETHING CLIPPED (out)
011000 SOMETHING CLIPPED (out)
011001 ADC NG ACTIVE (out)
011010 ADC NG ACTIVE (out)
011011 DAC NG ACTIVE (out)
011100 DAC NG ACTIVE (out)
011101 THERMAL (out)
011110 THERMAL (out)
011111 LS SHORT CCT (out)
5:0 GPIO_MODE 100000 LS SHORT CCT (out)
100001 ANALOG ERROR
Thermal or LS CCT condition (out)
100010 ANALOG ERROR (out)
100011 ERROR (out)
Thermal or LS CCT or Clipping
100100 ERROR (out)
100101 – 111111 RESERVED
6 GPIO_TX Whenever GPIO_MODE is set to '001010', the GPIO pin will output a logic level
based on this bit setting. Setting this bit high will result in a logic high GPIO output.
7 GPIO_RX This bit reports the logic level is present on the GPIO pin.
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TABLE 83. GPIO2 (0xE1h)
Bits Field Description
0 SHORT This bit will go high whenever a short circuit condition occurs on the Class D
loudspeaker amplifier outputs. Once triggered by a short circuit event, an I2C write
of 1 to this bit clear this bit.
1 TEMP This bit will go high whenever the temperature of the LM49352 reaches a critical
temperature. Once triggered by a thermal event, an I2C write of 1 to this bit clear
this bit.
TABLE 84. RESET (0xF0h)
Bits Field Description
4:0 RSVD Reserved.
5 SOFT_RESET Setting this bit resets the digital core of LM49352. SOFT_RESET does not affect
the current I2C register settings.
TABLE 85. Spread Spectrum (0xF1h)
Bits Field Description
1:0 RSVD Reserved
2 SS_DISABLE If this bit is set, Spread Spectrum mode will be disabled from the Class D amplifier.
TABLE 86. FORCE (0xFE)
Bits Field Description
0 RSVD Reserved
1 DACREF This bit determines whether the DAC reference voltage is internally generated or
externally driven.
DACREF STATUS
0 DACREF uses an internal bandgap reference.
1 DACREF is driven by an external voltage reference.
2 CP_FORCE If set, a -LS_VDD rail will be generated on HP_VSS, even if the headphone output
stage is not required.
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27.0 Schematic Diagram
30072784
FIGURE 27. Demo Board Schematic
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LM49352
28.0 Demonstration Board Layout
30072721
FIGURE 28. Top Silkscreen
30072782
FIGURE 29. Top Layer
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30072780
FIGURE 30. Inner Layer 2
30072781
FIGURE 31. Inner Layer 3
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LM49352
30072779
FIGURE 32. Bottom Layer
30072778
FIGURE 33. Bottom Silkscreen
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29.0 Revision History
Rev Date Description
1.0 05/03/10 Initial released.
1.01 06/30/10 Fixed a typo in the I2C Timing Parameters table.
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LM49352
30.0 Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD–36 Package
Order Number LM49352RL
NS Package Number RLA36MMA
X1 = 3.281±.03mm, X2 = 3.281±.03mm, X3 = 0.65±.075mm
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LM49352
Notes
LM49352 Mono Class D Audio Codec Subsystem with Ground Referenced Headphone
Amplifiers, Earpiece Driver, and Audio DSP
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