SCES394B − JUNE 2002 − REVISED MARCH 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DMember of the Texas Instruments
Widebus Family
DDOC Circuitry Dynamically Changes
Output Impedance, Resulting in Noise
Reduction Without Speed Degradation
DDynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
DControl Inputs VIH/VIL Levels are
Referenced to VCCB Voltage
DIf Either VCC Input Is at GND, Both Ports
Are in the High-Impedance State
DOvervoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
DIoff Supports Partial-Power-Down Mode
Operation
DFully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.4-V to
3.6-V Power-Supply Range
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The
A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed
to track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage
bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCB164245 is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCB164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB.
To ensure the high-impedance state during power up or power down, O E should be tied to VCCB through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND,
both ports are in the high-impedance state.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
TSSOP − DGG Tape and reel SN74AVCB164245GR AVCB164245
TVSOP − DGV Tape and reel SN74AVCB164245VR WB4245
°
°
VFBGA − GQL Tape and reel SN74AVCB164245KR
VFBGA − ZQL (Pb-Free) Tape and reel 74AVCB164245ZQLR
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC and Widebus are trademarks of Texas Instruments.
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