INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT251 8-input multiplexer; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-input multiplexer; 3-state 74HC/HCT251 The 74HC/HCT251 are the logic implementations of single-pole 8-position switches with the state of three select inputs (S0, S1, S2) controlling the switch positions. Assertion (Y) and negation (Y) outputs are both provided. The output enable input (OE) is active LOW. The logic function provided at the output, when activated, is: FEATURES * True and complement outputs * Both outputs are 3-state for further multiplexer expansion * Multifunction capability * Permits multiplexing from n-lines to one line Y = OE.(I0.S0.S1.S2 + I1.S0.S1.S2 + + I2.S0.S1.S2 + I3.S0.S1.S2 + + I4.S0.S1.S2 + I5.S0.S1.S2 + + I6.S0.S1.S2 + I7.S0.S1.S2) * Output capability: standard * ICC category: MSI Both outputs are in the high impedance OFF-state (Z) when the output enable input is HIGH, allowing multiplexer expansion by tying the outputs. GENERAL DESCRIPTION The 74HC/HCT251 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V In to Y 15 19 ns In to Y 17 19 ns Sn to Y 20 20 ns Sn to Y 21 21 ns 3.5 3.5 pF 44 46 pF CI input capacitance CPD power dissipation capacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". December 1990 HCT 2 Philips Semiconductors Product specification 8-input multiplexer; 3-state 74HC/HCT251 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 4, 3, 2, 1, 15, 14, 13, 12 I0 to I7 multiplexer inputs 5 Y multiplexer output 6 Y complementary multiplexer output 7 OE 3-state output enable input (active LOW) 8 GND ground (0 V) 11, 10, 9 S0, S1, S2 select inputs 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 8-input multiplexer; 3-state 74HC/HCT251 FUNCTION TABLE INPUTS OUTPUTS OE S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 Y Y H X X X X X X X X X X X Z Z L L L L L L L L L L L L L L H H L H X X X X L H X X X X X X X X X X X X X X X X X X X X X X X X H L H L L H L H L L L L L L L L H H H H L L H H X X X X X X X X L H X X X X L H X X X X X X X X X X X X X X X X H L H L L H L H L L L L H H H H L L L L L L H H X X X X X X X X X X X X X X X X L H X X X X L H X X X X X X X X H L H L L H L H L L L L H H H H H H H H L L H H X X X X X X X X X X X X X X X X X X X X X X X X L H X X X X L H H L H L L H L H Note 1. H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state Fig.4 Functional diagram. December 1990 Fig.5 Logic diagram. 4 Philips Semiconductors Product specification 8-input multiplexer; 3-state 74HC/HCT251 DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 -40 to +85 min. typ. max. min. max. -40 to +125 UNIT V WAVEFORMS CC (V) min. max. tPHL/ tPLH propagation delay In to Y 50 18 14 170 34 29 215 43 37 255 51 43 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay In to Y 55 20 16 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay Sn to Y 66 24 19 205 41 35 255 51 43 310 62 53 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay Sn to Y 69 25 20 205 41 35 255 51 43 310 62 53 ns 2.0 4.5 6.0 Fig.7 tPZH/ tPZL 3-state output enable time OE to Y, Y 36 13 10 140 28 24 175 35 30 210 42 36 ns 2.0 4.5 6.0 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Y, Y 39 14 11 140 28 24 170 35 30 210 42 36 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 6 and 7 December 1990 5 Philips Semiconductors Product specification 8-input multiplexer; 3-state 74HC/HCT251 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT In S0 S1, S2 OE 1.00 1.50 1.50 1.50 AC CHARACTERISTICS FOR HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. typ. -40 to +85 -40 to +125 UNIT V WAVEFORMS CC (V) max. min. max. min. max. tPHL/ tPLH propagation delay In to Y 22 35 44 53 ns 4.5 Fig.6 tPHL/ tPLH propagation delay In to Y 22 35 44 53 ns 4.5 Fig.7 tPHL/ tPLH propagation delay Sn to Y 24 44 55 66 ns 4.5 Fig.6 tPHL/ tPLH propagation delay Sn to Y 25 44 55 66 ns 4.5 Fig.7 tPZH/ tPZL 3-state output enable time OE to Y, Y 13 28 35 42 ns 4.5 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Y, Y 14 28 35 42 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7 December 1990 6 Philips Semiconductors Product specification 8-input multiplexer; 3-state 74HC/HCT251 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.6 Waveforms showing the multiplexer input (In) and select input (Sn) to output (Y) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.7 Waveforms showing the multiplexer input (In) and select input (Sn) to output (Y) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.8 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7