MM74HC595MTCX_NL - Fairchild Semiconductor

September 1983

Revised July 2004

MM74HC595 8-Bit Shift Regi sters with Output Latches

MM74HC595

8-Bit Shift Registers with Outpu t Latches

General Description

The MM74HC595 high speed shift register utilizes

advanced s ilicon- gate CM OS te chnology. This device pos-

sesses the high noise immunity and low power consump-

tion of standard CMOS integrated circuits, as well as the

ability to drive 15 LS-TTL loads.

This device contains an 8-bit serial-in, parallel-out shift reg-

ister that feeds an 8-bit D-type storage register. The stor-

age register has 8 3-STATE outputs. Separate clocks are

provide d for both the sh ift reg ister and the stora ge r egister.

The shift register has a direct-over riding clea r, ser ial input,

and serial output (standard) pins for cascading. Both the

shift register and storage register use positive-edge trig-

gered clocks. If both clocks are connected together, the

shift register state will always be one clock pulse ahead of

the storage register.

The 74H C log i c fam ily i s sp ee d, fu ncti o n, a nd pin- ou t com -

patible with the standard 74LS logic family. All inputs are

protect ed from damage d ue to static d ischarge by inter nal

diode clamps to VCC and ground.

Features

■Low quiescent current: 80 µA maximum ( 74HC S erie s)

■Low input current: 1 µA maximum

■8-bit serial-in, parallel-out shift register with storage

■Wide operat i ng voltage range: 2V–6 V

■Cascadable

■Shift register has direct clear

■Guaranteed shift frequency: DC to 30 MHz

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the ordering code.

Connection Diagram

Top View

Truth Ta ble

Order Number Package Number Package Description

MM74HC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HC595SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC595MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC595N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

RCK SCK SCLR GFunction

XX XHQ

A thru QH = 3-STATE

X X L L Shift Register cleared

Q’H = 0

X↑H L Shift Register clocked

QN = Qn-1, Q0 = SER

↑X H L Contents of Shift

Regi ster transferred

to output latches

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MM74HC595

Logic Diagram

(positive logic)

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MM74HC595

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dis sipation te mperature d erating — plas tic “N” package: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occ ur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when

designi ng with t his s upply. Worst c as e VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-

rent (IIN, ICC, and IOZ) occur fo r C M OS at the h igher vol ta ge and so th e 6. 0V values s hould be used.

Supply Voltage (VCC)−0.5 to +7.0V

DC Input Voltage (VIN)−1.5 to VCC +1.5V

DC Output Voltage (VOUT)−0 .5 to VCC +0.5V

Clamp Diode Current (IIK, IOK)±20 mA

DC Output Current, per pin (IOUT)±35 mA

DC VCC or GND Current,

per pin (ICC)±70 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package onl y 500 mW

Lead Temperature (TL)

(Solder i ng 10 seco nds) 260°C

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage

(VIN, VOUT)0V

CC V

Operating Temperature Range (TA)−40 +85 °C

Input Rise or Fall Times

(tr, tf) VCC = 2.0V 1000 ns

VCC = 4.5V 500 ns

VCC = 6.0V 400 ns

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 VInput Voltage 4.5V 3.15 3.15 3.15

6.0V 4.2 4.2 4.2

VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 VInput Voltage 4.5V 1.35 1.35 1.35

6.0V 1.8 1.8 1.8

VOH Minimum HIGH Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V4.5V 4.5 4.4 4.4 4.4

6.0V 6.0 5.9 5.9 5.9

Q’HVIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2

QA thru QHVIN = VIH or VIL

|IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2

VOL Maximum LOW Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V4.5V 0 0.1 0.1 0.1

6.0V 0 0.1 0.1 0.1

Q’HVIN = VIH or VIL

|IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4

QA thru QHVIN = VIH or VIL

|IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4

IIN Maxim um In put VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA

Current

IOZ Maxim um 3-STATE VOUT = VCC or GND 6.0V ±0.5 ±5.0 ±10 µA

Output Leakage G = VIH

ICC Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA

Supply Current IOUT = 0 µA

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MM74HC595

AC Electrical Characteristi cs

VCC = 5V, TA = 25°C, tr = tf = 6 ns

Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the stor-

age register s tate will be one clock pulse behind the sh if t re gis t er.

AC Electrical Characteristi cs

VCC = 2.0−6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)

Symbol Parameter Conditions Typ Guaranteed Units

Limit

fMAX Maximum Operating 50 30 MHz

Frequency of SCK

tPHL, tPLH Maximum Propagation CL = 45 pF 12 20 ns

Delay, SCK to Q’H

tPHL, tPLH Maximum Propagation CL = 45 pF 18 30 ns

Delay, RCK to QA thru QH

tPZH, tPZL Maximum Output Enable RL = 1 kΩ

Time from G to QA thru QHCL = 45 pF 17 28 ns

tPHZ, tPLZ Maximum Output Disable RL = kΩ15 25 ns

Time from G to QA thru QHCL = 5 pF

tSMinimum Setup Time 20 ns

from SER to SCK

tSMinimum Setup Time 20 ns

from SCLR to SCK

tSMinimum Setup Time 40 ns

from SCK to RCK

(Note 5)

tHMinimum Hold Time 0ns

from SER to SCK

tWMinimum Pulse Width 16 ns

of SCK or RCK

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

fMAX Maximum Operati ng CL = 50 pF 2.0V 10 6 4.8 4.0 MHzFrequency 4.5V 45 30 24 20

6.0V 50 35 28 24

tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 58 210 265 315 ns

Delay from SCK to Q’HCL = 150 pF 2.0V 83 294 367 441

CL = 50 pF 4.5V 14 42 53 63 ns

CL = 150 pF 4.5V 17 58 74 88

CL = 50 pF 6.0V 10 36 45 54 ns

CL = 150 pF 6.0V 14 50 63 76

tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 70 175 220 265 ns

Delay from RCK to QA thru QHCL = 150 pF 2.0V 105 245 306 368

CL = 50 pF 4.5V 21 35 44 53 ns

CL = 150 pF 4.5V 28 49 61 74

CL = 50 pF 6.0V 18 30 37 45 ns

CL = 150 pF 6.0V 26 42 53 63

tPHL, tPLH Maximum Propagation 2.0V 175 221 261 nsDelay from SCLR to Q’H4.5V 35 44 52

6.0V 30 37 44

tPZH, tPZL Maximum Output Enable RL = 1 kΩ

from G to QA thru QHCL = 50 pF 2.0V 75 175 220 265 ns

CL = 150 pF 2.0V 100 245 306 368

CL = 50 pF 4.5V 15 35 44 53 ns

CL = 150 pF 4.5V 20 49 61 74

CL = 50 pF 6.0V 13 30 37 45 ns

CL = 150 pF 6.0V 17 42 53 63

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MM74HC595

AC Electrical Characteristics (Continued)

Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current cons umptio n,

IS = CPD VCC f + ICC.

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

tPHZ, tPLZ Maximum Output Disable RL = 1 kΩ2.0V 75 175 220 265 nsTime from G to QA thru QHCL = 50 pF 4.5V 15 35 44 53

6.0V 13 30 37 45

tSMinimum Setup Time 2.0V 100 125 150 nsfrom SER to SCK 4.5V 20 25 30

6.0V 17 21 25

tRMinimum Removal Time 2.0V 50 63 75 nsfrom SCLR to SCK 4.5V 10 13 15

6.0V 9 11 13

tSMinimum Setup Time 2.0V 100 125 150 nsfrom SCK to RCK 4.5V 20 25 30

6.0V 17 21 26

tHMinimum Hold Time 2.0V 5 5 5 nsSER to SCK 4.5V 5 5 5

6.0V 5 5 5

tWMinimum Pulse Width 2.0V 30 80 100 120 nsof SCK or SCLR 4.5V 9 16 20 24

6.0V 8 14 18 22

tr, tfMaximum Input Rise and 2.0V 1000 1000 1000 nsFall Time, Clock 4.5V 500 500 500

6.0V 400 400 400

tTHL, tTLH Maximum Output 2.0V 25 60 75 90 nsRise and Fall Time 4.5V 7 12 15 18

QA–QH6.0V 6 10 13 15

tTHL, tTLH Maximum Output 2.0V 75 95 110 nsRise & Fall Time 4.5V 15 19 22

Q'H6.0V 13 16 19

CPD Power Dissipation G = VCC 90 pF

Capacitance, Outputs G = GND 150

Enabled (Note 6)

CIN Maximum Input 5 10 10 10 pF

Capacitance

COUT Maximum Output 15 20 20 20 pF

Capacitance

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Timing Diagram

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MM74HC595

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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MM74HC595

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Sma ll Outline Package (SOP), EIAJ T YPE II, 5.3mm Wide

Package Number M16D

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MM74HC595

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC16

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MM74HC595 8-Bit Shift Registers with Output Latches

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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