Freescale Semiconductor Data Sheet: Technical Data DSP56374 Rev. 4.2, 1/2007 DSP56374 Data Sheet 1 Overview The DSP56374 is a high-density CMOS device with 3.3 V inputs and outputs. NOTE This document contains information on a new product. Specifications and information herein are subject to change without notice. For software or simulation models (for example, IBIS files), contact sales or go to www.freescale.com. The DSP56374 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Semiconductor, Inc. SymphonyTM DSP family, as shown in Figure 1. Significant architectural enhancements include a barrel shifter, 24-bit addressing, and direct memory access Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Requirements . . . . . . . . . . . . . . . . . . . . . 26 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 27 DC Electrical Characteristics . . . . . . . . . . . . . . . 28 AC Electrical Characteristics. . . . . . . . . . . . . . . . 29 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 29 External Clock Operation . . . . . . . . . . . . . . . . . . 29 Reset, Stop, Mode Select, and Interrupt Timing . 32 Serial Host Interface SPI Protocol Timing. . . . . . 35 Serial Host Interface (SHI) I2C Protocol Timing . 41 Programming the Serial Clock . . . . . . . . . . . . . . 43 Enhanced Serial Audio Interface Timing. . . . . . . 44 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . . 53 (c) Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved. Overview (DMA). The DSP56374 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock. Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low "deasserted" Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/ Symbol Logic State Signal State Voltage* PIN True Asserted VIL / VOL PIN False Deasserted VIH / VOH PIN True Asserted VIH / VOH PIN False Deasserted VIL / VOL Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. DSP56374 Data Sheet, Rev. 4.2 2 Freescale Semiconductor Features 15* 5 3 12* 12 Memory Expansion Area ESAI_1 Interface Triple Timer Watch dog Timer Program RAM 6k x 24 X Data RAM 6k x 24 Y Data RAM 6k x 24 ROM 20k x 24 ROM 4k x 24 ROM 4k x 24 Address Generation Unit Six Channel DMA Unit YAB XAB PAB DAB YM_EB Expansion Area XM_EB Peripheral PIO_EB ESAI Interface PM_EB GPIO SHI Interface 24-Bit Bootstrap ROM DSP56300 Core DDB YDB XDB PDB GDB Internal Data Bus Switch Clock Gen. XTAL EXTAL RESET PINIT/NMI Power Mgmt. PLL Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 x 24+5656-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter 4 JTAG OnCE MODA/IRQA/GPIO MODB/IRQB/GPIO MODC/IRQC/GPIO MODD/IRQD/GPIO * ESAI_1 and dedicated GPIO pins are not available in the 52-pin package. Figure 1. DSP56374 Block Diagram 2 Features 2.1 DSP56300 Modular Chassis * * * * 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V Object Code Compatible with the 56K core Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmetic support Program Control with position independent code support DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 3 Features * * * * * * 2.2 * * * * * Six-channel DMA controller Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4), Output divide factor (1, 2, or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise Internal address tracing support and OnCE for Hardware/Software debugging JTAG port, supporting boundary scan, compliant to IEEE 1149.1 Very low-power CMOS design, fully static design with operating frequencies down to DC STOP and WAIT low-power standby modes On-chip Memory Configuration 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM 6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM 20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism 6Kx24 Bit Program RAM. Various memory switches are available. See memory table below. Table 1. DSP56374 Memory Switch Configurations Bit Settings 2.3 * * * * * Memory Sizes (24-bit words) MSW1 MSW0 MS Prog RAM X Data RAM Y Data RAM Prog ROM X Data ROM Y Data ROM X X 0 6K 6K 6K 20K 4K 4K 0 0 1 2K 10K 6K 20K 4K 4K 0 1 1 4K 8K 6K 20K 4K 4K 1 0 1 8K 4K 6K 20K 4K 4K 1 1 1 10K 4K 4K 20K 4K 4K Peripheral Modules Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I2S, Sony, AC97, network, and other programmable protocols. Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I2S, Sony, AC97, network and other programmable protocols. Note: Available in the 80-pin package only. Serial Host Interface (SHI): SPI and I2C protocols, 10-word receive FIFO, support for 8, 16, and 24-bit words. Three noise reduction filter modes. Triple Timer module (TEC) Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be configured as GPIO on the 80 pin package and 20 pins on the 52 pin package. DSP56374 Data Sheet, Rev. 4.2 4 Freescale Semiconductor Documentation * Hardware Watchdog Timer 2.4 Packages 80-pin and 52-pin plastic LQFP packages. 3 Documentation Table 2 lists the documents that provide a complete description of the DSP56374 and are required to design properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). Table 2. DSP56374 Documentation Document Name Description Order Number DSP56300 Family Manual Detailed description of the 56300-family architecture and the 24-bit core processor and instruction set DSP56300FM/AD DSP56374 User's Manual Detailed description of memory, peripherals, and interfaces DSP56374UM/D DSP56374 Technical Data Sheet Electrical and timing specifications; pin and package descriptions DSP56374 Product Brief Brief description of the chip 4 DSP56374 DSP56374PB/D Signal Groupings The input and output signals of the DSP56374 are organized into functional groups, which are listed in Table 3. The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 3. DSP56374 Functional Signal Groupings Number of Signals1 Detailed Description Power (VDD) 11 Table 15 Ground (GND) 9 Table 5 Scan Pins 1 Table 6 Clock and PLL 3 Table 7 Port H2 5 Table 8 SHI Port H2 5 Table 9 ESAI Port C4 12 Table 10 E5 12 Table 11 Functional Group Interrupt and mode control ESAI_1 Port DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 5 Signal Groupings Table 3. DSP56374 Functional Signal Groupings (continued) Number of Signals1 Detailed Description 15 Table 12 Timer 3 Table 13 JTAG/OnCE Port 4 Table 14 Functional Group Port G3 Dedicated GPIO Note: 1 Pins are not 5 V. tolerant unless noted. 2 Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals. 3 Port G signals are the dedicated GPIO port signals. 4 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 5 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. 4.1 Power Table 4. Power Inputs 4.2 Power Name Description PLLA_VDD (1) PLL Power-- The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter as shown in Figure 1 and Figure 2 below. See the DSP56374 technical data sheet for additional details. PLLP_VDD(1) PLL Power-- The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND. PLLD_VDD (1) PLL Power-- The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND. CORE_VDD (4) Core Power--The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate external decoupling capacitors. IO_VDD (80-pin 4) (52-pin 3) SHI, ESAI, ESAI_1, WDT and Timer I/O Power --The voltage (3.3 V) should be well-regulated, and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide adequate external decoupling capacitors. Ground Table 5. Grounds Ground Name Description PLLA_GND(1) PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND. DSP56374 Data Sheet, Rev. 4.2 6 Freescale Semiconductor Signal Groupings Table 5. Grounds (continued) 4.3 Ground Name Description PLLP_GND(1) PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND. PLLD_GND(1) PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND. CORE_GND(4) Core Ground--The Core ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. IO_GND(2) SHI, ESAI, ESAI_1, WDT and Timer I/O Ground--IO_GND is the ground for the SHI, ESAI, ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. SCAN Table 6. SCAN Signals 4.4 Signal Name Type State During Reset SCAN Input Input Signal Description SCAN--Manufacturing test pin. This pin must be connected to ground. Clock and PLL Table 7. Clock and PLL Signals Signal Name Type State during Reset EXTAL Input Input XTAL Output PINIT/NMI Input Signal Description External Clock / Crystal Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. Chip Driven Crystal Output--Connects the internal Crystal Oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. Input PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de-assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to the internal system clock. This pin has an internal pull up resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 7 Signal Groupings 4.5 Interrupt and Mode Control The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is de-asserted, these inputs are hardware interrupt request lines. Table 8. Interrupt and Mode Control Signal Name Type MODA/IRQA Input State during Reset MODA Input Signal Description Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is de-asserted. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. This pin has an internal pull up resistor. This input is 5 V tolerant. PH0 Input, output, or disconnected MODB/IRQB Input Port H0--When the MODA/IRQA is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. MODB Input Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. PH1 Input, output, or disconnected MODC/IRQC Input Port H1--When the MODB/IRQB is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. MODC Input Mode Select C/External Interrupt Request C--MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 8 Freescale Semiconductor Signal Groupings Table 8. Interrupt and Mode Control (continued) Signal Name Type PH2 Input, output, or disconnected MODD/IRQD Input State during Reset Signal Description Port H2--When the MODC/IRQC is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. MODD Input Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. PH3 Input, output, or disconnected RESET Input Port H3--When the MODD/IRQD is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. Input Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is de-asserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This pin has an internal pull up resistor. This input is 5 V tolerant. 4.6 Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 9 Signal Groupings Table 9. Serial Host Interface Signals Signal Name Signal Type State during Reset SCK Input or output Tri-stated SCL Input or output Signal Description SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VDD through an external pull-up resistor according to the I2C specifications. This signal is tri-stated during hardware, software, and individual reset. This pin has an internal pull up resistor. This input is 5 V tolerant. MISO Input or output SDA Input or open-drain output Tri-stated SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is de-asserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VDD through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This pin has an internal pull up resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 10 Freescale Semiconductor Signal Groupings Table 9. Serial Host Interface Signals (continued) Signal Name Signal Type State during Reset MOSI Input or output Tri-stated HA0 Input Signal Description SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This pin has an internal pull up resistor. This input is 5 V tolerant. SS Input Ignored Input SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept de-asserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is de-asserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. HA2 Input I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This pin has an internal pull up resistor. This input is 5 V tolerant. HREQ Input or Output Tri-stated Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and de-asserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This pin can also be programmed as GPIO. PH4 Input, output, or disconnected Port H4--When HREQ is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. This pin has an internal pull up resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 11 Signal Groupings 4.7 Enhanced Serial Audio Interface Table 10. Enhanced Serial Audio Interface Signals Signal Name Signal Type HCKR Input or output PC2 Input, output, or disconnected State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull up resistor. This input is 5 V tolerant. HCKT Input or output PC5 Input, output, or disconnected GPIO disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull up resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 12 Freescale Semiconductor Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type FSR Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC1 Input, output, or disconnected Port C1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. FST Input or output PC4 Input, output, or disconnected GPIO disconnected Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 13 Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type SCKR Input or output State during Reset GPIO disconnected Signal Description Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC0 Input, output, or disconnected Port C0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SCKT Input or output PC3 Input, output, or disconnected GPIO disconnected Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 14 Freescale Semiconductor Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type SDO5 Output SDI0 Input PC6 Input, output, or disconnected State during Reset GPIO disconnected Signal Description Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO4 Output SDI1 Input PC7 Input, output, or disconnected GPIO disconnected Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO3 Output SDI2 Input PC8 Input, output, or disconnected GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. Port C8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 15 Signal Groupings Table 10. Enhanced Serial Audio Interface Signals (continued) Signal Name Signal Type SDO2 Output SDI3 Input PC9 Input, output, or disconnected State during Reset GPIO disconnected Signal Description Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. Port C9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO1 Output PC10 Input, output, or disconnected GPIO disconnected Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO0 Output PC11 Input, output, or disconnected GPIO disconnected Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. Port C11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 16 Freescale Semiconductor Signal Groupings 4.8 Enhanced Serial Audio Interface_1 Table 11. Enhanced Serial Audio Interface_1 Signals Signal Name Signal Type HCKR_1 Input or output PE2 Input, output, or disconnected State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port E2--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. HCKT_1 Input or output PE5 Input, output, or disconnected GPIO disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port E5--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 17 Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (continued) Signal Name Signal Type FSR_1 Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Receiver_1--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR_1 pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR_1 register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR_1 register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode. PE1 Input, output, or disconnected Port E1--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant FST_1 Input or output PE4 Input, output, or disconnected GPIO disconnected Frame Sync for Transmitter_1--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST_1 is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI_1 transmit clock control register (TCCR_1). Port E4--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 18 Freescale Semiconductor Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (continued) Signal Name Signal Type SCKR_1 Input or output State during Reset GPIO disconnected Signal Description Receiver Serial Clock_1--SCKR_1 provides the receiver serial bit clock for the ESAI_1. The SCKR_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR_1 register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR_1 register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode. PE0 Input, output, or disconnected Port E0--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant SCKT_1 Input or output PE3 Input, output, or disconnected GPIO disconnected Transmitter Serial Clock_1--This signal provides the serial bit rate clock for the ESAI_1. SCKT_1 is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port E3--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 19 Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (continued) Signal Name Signal Type SDO5_1 Output SDI0_1 Input PE6 Input, output, or disconnected State during Reset GPIO disconnected Signal Description Serial Data Output 5_1--When programmed as a transmitter, SDO5_1 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0_1--When programmed as a receiver, SDI0_1 is used to receive serial data into the RX0 serial receive shift register. Port E6--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant SDO4_1 Output SDI1_1 Input PE7 Input, output, or disconnected GPIO disconnected Serial Data Output 4_1--When programmed as a transmitter, SDO4_1 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1_1--When programmed as a receiver, SDI1_1 is used to receive serial data into the RX1 serial receive shift register. Port E7--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO3_1 Output SDI2_1 Input PE8 Input, output, or disconnected GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3_1 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2_1 is used to receive serial data into the RX2 serial receive shift register. Port E8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 20 Freescale Semiconductor Signal Groupings Table 11. Enhanced Serial Audio Interface_1 Signals (continued) State during Reset Signal Name Signal Type SDO2_1 Output SDI3_1 Input Serial Data Input 3--When programmed as a receiver, SDI3_1 is used to receive serial data into the RX3 serial receive shift register. PE9 Input, output, or disconnected Port E9--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. GPIO disconnected Signal Description Serial Data Output 2--When programmed as a transmitter, SDO2_1 is used to transmit data from the TX2 serial transmit shift register. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO1_1 Output PE10 Input, output, or disconnected GPIO disconnected Serial Data Output 1--SDO1_1 is used to transmit data from the TX1 serial transmit shift register. Port E10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO0_1 Output PE11 Input, output, or disconnected GPIO disconnected Serial Data Output 0--SDO0_1 is used to transmit data from the TX0 serial transmit shift register. Port E11--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 21 Signal Groupings 4.9 Dedicated GPIO-Port G Table 12. Dedicated GPIO-Port G Signals Signal Name PG0 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port G0--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG1 Input, output, or disconnected GPIO disconnected Port G1--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG2 Input, output, or disconnected GPIO disconnected Port G2--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG3 Input, output, or disconnected GPIO disconnected Port G3--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG4 Input, output, or disconnected GPIO disconnected Port G4--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG5 Input, output, or disconnected GPIO disconnected Port G5--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG6 Input, output, or disconnected GPIO disconnected Port G6--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG7 Input, output, or disconnected GPIO disconnected Port G7--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG8 Input, output, or disconnected GPIO disconnected Port G8--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant DSP56374 Data Sheet, Rev. 4.2 22 Freescale Semiconductor Signal Groupings Table 12. Dedicated GPIO-Port G Signals (continued) Signal Name PG9 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port G9--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG10 Input, output, or disconnected GPIO disconnected Port G10--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG11 Input, output, or disconnected GPIO disconnected Port G11--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG12 Input, output, or disconnected GPIO disconnected Port G12--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG13 Input, output, or disconnected GPIO disconnected Port G13--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant PG14 Input, output, or disconnected GPIO disconnected Port G14--This signal is individually programmable as input, output, or internally disconnected. Internal Pull down resistor. This input is 5 V tolerant DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 23 Signal Groupings 4.10 Timer Table 13. Timer Signal Signal Name TIO0 Type Input or Output State during Reset Signal Description GPIO Input Timer 0 Schmitt-Trigger Input/Output--When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input. Internal Pull down resistor. This input is 5 V tolerant TIO1 Input or Output Watchdog Timer Output Timer 1 Schmitt-Trigger Input/Output--When timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 1control/status register (TCSR1). If TIO1 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input. WDT Output WDT--When this pin is configured as a hardware watchdog timer pin, this signal is asserted low when the hardware watchdog timer counts down to zero. Internal Pull down resistor. This input is 5 V tolerant TIO2 Input or Output PLOCK Output Timer 2 Schmitt-Trigger Input/Output--When timer 2 functions as an external event counter or in measurement mode, TIO2 is used as input. When timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer control/status register (TCSR2). If TIO2 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input . DSP56374 Data Sheet, Rev. 4.2 24 Freescale Semiconductor Maximum Ratings Table 13. Timer Signal (continued) Signal Name Type PLOCK Output State during Reset Signal Description PLOCK--When this pin is configured as a PLL lock pin, this signal is asserted high when the on-chip PLL enabled and locked and de-asserted when the PLL enabled and unlocked. This pin is also asserted high when the PLL is disabled. Internal Pull down resistor. This input is 5 V tolerant 4.11 JTAG/OnCE Interface Table 14. JTAG/OnCE Interface Signal Name Signal Type State during Reset TCK Input Input Signal Description Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. Internal Pull up resistor. This input is 5 V tolerant. TDI Input Input Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK. Internal Pull up resistor. This input is 5 V tolerant. TDO Output Tri-stated TMS Input Input Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK. Internal Pull up resistor. This input is 5 V tolerant. 5 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VDD). The suggested value for a pullup or pulldown resistor is 4.7 k. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 25 Power Requirements NOTE In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 15. Maximum Ratings Rating1 Value1, 2 Unit -0.3 to + 1.6 V VPLLP_VDD, VIO_VDD, VPLLA_VDD, -0.3 to + 4.0 V Tr 10 ms VIN GND - 0.3 to 6V V I 12 mA ISCK 16 mA IJTAG 24 ma TJ 80 LQFP = 105 52 LQFP = 110 C -55 to +125 C ESD protected voltage (Human Body Model) 2000 V ESD protected voltage (Machine Model) 200 V Symbol Supply Voltage VCORE_VDD, VPLLD_VDD Maximum CORE_VDD power supply ramp time4 All "5.0V tolerant" input voltages Current drain per pin excluding VDD and GND(Except for pads listed below) SCK_SCL TDO Operating temperature range3 Storage temperature TSTG Note: 1 GND = 0 V, T = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50pF J 2 Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3 Operating temperature qualified for automotive applications. T = T + x Power. Variables used were J A JA Core Current = 100 mA, I/O Current = 60 mA, Core Voltage = 1.3 V, I/O Voltage = 3.46 V, TA = 85C 4 If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneous operation. 6 Power Requirements To prevent high current conditions due to possible improper sequencing of the power supplies, the connection shown below is recommended to be made between the DSP56374 IO_VDD and Core_VDD power pins. DSP56374 Data Sheet, Rev. 4.2 26 Freescale Semiconductor Thermal Characteristics IO_VDD External Schottky Diode Core_VDD To prevent a high current condition upon power up, the IO_VDD must be applied ahead of the Core_VDD as shown below if the external Schottky is not used. Core_VDD IO_VDD For correct operation of the internal power on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms. This is shown below. Tr 1.25 V 0V Core_VDD 7 Thermal Characteristics Table 16. Thermal Characteristics Characteristic Symbol LQFP Values Unit Natural Convection, Junction-to-ambient thermal resistance1,2 RJA or JA 68 (52 LQFP) 50 (80 LQFP) C/W Junction-to-case thermal resistance3 RJC or JC 17 (52 LQFP) 11 (80 LQFP) C/W Note: 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 27 DC Electrical Characteristics 8 DC Electrical Characteristics Table 17. DC Electrical Characteristics Characteristics Symbol Min Typ Max Unit Supply voltages * Core (Core_VDD) * PLL (PLLD_VDD) VDD 1.2 1.25 1.3 V Supply voltages * I/O (IO_VDD) * PLL (PLLP_VDD) * PLL (PLLA_VDD) VDDIO 3.14 3.3 3.46 V VIH 2.0 -- VIO_VDD+2V V Input high voltage * All pins Note: All 3.3-V supplies must rise prior to the rise of the 1.25-V supplies to avoid a high current condition and possible system damage. Input low voltage * All pins VIL -0.3 -- 0.8 V Input leakage current IIN -- -- 84 A Clock pin Input Capacitance (EXTAL) CIN High impedance (off-state) input current (@ 3.46V) ITSI -10 -- 84 A Output high voltage * IOH = -5 mA * XTAL Pin IOH = -10mA VOH 2.4 -- -- V Output low voltage * IOL = 5 mA * XTAL Pin IOL = 10 mA VOL -- -- 0.4 V ICCI -- 65 100 mA ICCW -- 16 -- mA ICCS -- 1.2 -- mA CIN -- -- 10 pF Internal supply current1 (core only) at internal clock of 150 MHz * In Normal mode * In Wait mode * In Stop mode2 Input capacitance 4.7 pF Note: 1 The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.25V, VDD_IO = 3.3V at TJ = 25C. Maximum internal supply current is measured with VCORE_VDD = 1.30V, VIO_VDD) = 3.46V at TJ = 115C. 2 In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). DSP56374 Data Sheet, Rev. 4.2 28 Freescale Semiconductor AC Electrical Characteristics 9 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56374 output levels are measured with the production test machine VOL and VOH reference levels set at 1.0 V and 1.8 V, respectively. 10 Internal Clocks Table 18. INTERNAL CLOCKS1 No. Characteristics Symbol Min Typ Max Unit 5 -- 20 MHz 1 Comparison Frequency Fref 2 Input Clock Frequency FIN 3 Output clock Frequency (with PLL enabled) 2,3 4 Output clock Frequency (with PLL disabled) 2,3 5 Duty Cycle Fref*NR (Ef x MF x FM)/ (PDF x DF x OD) Condition Fref = FIN/NR NR is input divider value FOUT 75 150 MHz Tc 13.3 FOUT -- Ef 150 MHz -- 40 50 60 % FOUT=FVCO/NO where NO is output divider value ns -- FVCO=300MHz~600MHz Note: 1 See users manual for definition. 2 DF = Division Factor Ef = External Frequency Mf = Multiplication Factor PDF = Predivision Factor FM= Frequency Multiplier OD = Output Divider Tc = Internal Clock Period 3 Maximum frequency will vary depending on the ordered part number. 11 External Clock Operation The DSP56374 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; an example is shown below. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 29 External Clock Operation Suggested component values: f osc = 24.576 MHz R = 1 M 10% C (EXTAL)= 18 pF C (XTAL) = 47 pF Calculations are for a 12 - 49 MHz crystal with the following parameters: * shunt capacitance (C0) of 10 pF - 12 pF * series resistance 40 Ohm * drive level of 10 W If the DSP56374 system clock is an externally supplied square wave voltage source, it is connected to EXTAL (Figure 2.). When the external square wave source connects to EXTAL, the XTAL pin is not used. VIH Midpoint EXTAL VIL ETH ETL 6 7 8 Note: ETC The midpoint is 0.5 (VIH + VIL). Figure 2. External Clock Timing Table 19. Clock Operation No. 6 Characteristics EXTAL input high 1 Symbol Min Max Units Eth 3.33 50 ns Etl 3.33 50 ns Etc 6.67 inf ns 50 200 6.67 inf 6.67 13.33 (40% to 60% duty cycle) 7 EXTAL input low2 (40% to 60% duty cycle) 8 EXTAL cycle time * With PLL disabled * With PLL enabled 9 Instruction cycle time= ICYC = TC3 * With PLL disabled * With PLL enabled Icyc ns DSP56374 Data Sheet, Rev. 4.2 30 Freescale Semiconductor External Clock Operation Table 19. Clock Operation (continued) No. Characteristics Symbol Min Max Units Note: 1 Measured at 50% of the input transition. 2 The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 3 A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56374 being powered up. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 31 Reset, Stop, Mode Select, and Interrupt Timing 12 Reset, Stop, Mode Select, and Interrupt Timing Table 20. Reset, Stop, Mode Select, and Interrupt Timing No. Characteristics Expression Min Max Unit -- -- 11 ns * Power on, external clock generator, PLL disabled 2 xTC 13.4 -- ns * Power on, external clock generator, PLL enabled 2 x TC 13.4 -- ns 2x TC 13.4 -- ns (2xTC)+TLOCK 5.0 -- ms 10 Delay from RESET assertion to all pins at reset value3 11 Required RESET duration4 13 Syn reset deassert delay time * Minimum * Maximum (PLL enabled) 14 Mode select setup time 10.0 -- ns 15 Mode select hold time 10.0 -- ns 16 Minimum edge-triggered interrupt request assertion width 2 xTC 13.4 -- ns 17 Minimum edge-triggered interrupt request deassertion width 2 xTC 13.4 -- ns 18 Delay from interrupt trigger to interrupt code execution 10 x TC + 5 72 -- ns 19 Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)1, 2, 3 9+(128x TC) 854 -- s * PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) 25x TC 165 -- ns * PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = 0) 9+(128xTC) + TLOCK 5.7 ms * PLL is not active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) (25 x TC) + TLOCK 5 ms * PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0) 20 * Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution1 10 x TC + 3.0 69.0 ns DSP56374 Data Sheet, Rev. 4.2 32 Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Table 20. Reset, Stop, Mode Select, and Interrupt Timing (continued) No. 21 22 Characteristics Expression Min Max Unit * ESAI, ESAI_1, SHI, Timer 12 x TC -- 80.0 ns * DMA 8 x TC -- 53.0 ns * IRQ, NMI (edge trigger) 8 x TC -- 53.0 ns * IRQ (level trigger) 12 x TC -- 80.0 ns * Data read from ESAI, ESAI_1, SHI 6 x TC -- 40.0 ns * Data write to ESAI, ESAI_1, SHI 7 x TC -- 46.7 ns * Timer 2 x TC -- 13.4 ns * IRQ, NMI (edge trigger) 3 x TC -- 20.0 ns Interrupt Requests Rate1 DMA Requests Rate Note: 1 When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. 2 For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings. For PLL enable, (if bet 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms. 3 Periodically sampled and not 100% tested. 4 RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When the VDD is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. VIH RESET 11 13 10 All Pins Reset Value Figure 3. Reset Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 33 Reset, Stop, Mode Select, and Interrupt Timing IRQA, IRQB, IRQC, IRQD, NMI 19 18 a) First Interrupt Instruction Execution General Purpose I/O 20 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O Figure 4. External Fast Interrupt Timing IRQA, IRQB, IRQC, IRQD, NMI 16 IRQA, IRQB, IRQC, IRQD, NMI 17 Figure 5. External Interrupt Timing (Negative Edge-Triggered) VIH RESET 14 15 MODA, MODB, MODC, MODD, PINIT VIH VIH VIL VIL IRQA, IRQB, IRQC,IRQD, NMI Figure 6. Recovery from Stop State Using IRQA Interrupt Service DSP56374 Data Sheet, Rev. 4.2 34 Freescale Semiconductor Serial Host Interface SPI Protocol Timing 13 Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing No. Characteristics1,3,4 Mode Filter Mode Expression Min Max Unit 23 Minimum serial clock cycle = tSPICC(min) Master/Slave Bypassed 10.0 x TC + 9 76.0 -- ns Very Narrow 10.0 x TC + 9 76.0 -- ns Narrow 10.0 x TC + 133 200.0 -- ns Wide 10.0 x TC + 333 400.0 -- ns Bypassed -- -- 0 ns Very Narrow -- -- 10 ns Narrow -- -- 50 ns Wide -- -- 100 ns Bypassed -- 38.0 -- ns Very Narrow -- 38.0 -- ns Narrow -- 100.0 -- ns Wide -- 200.0 -- ns Bypassed 2.0 x TC + 19.6 33.0 -- ns Very Narrow 2.0 x TC + 19.6 33.0 -- ns Narrow 2.0 x TC + 86.6 100.0 -- ns Wide 2.0 x TC + 186.6 200.0 -- ns Bypassed -- 38.0 -- ns Very Narrow -- 38.0 -- ns Narrow -- 100.0 -- ns Wide -- 200.0 -- ns Bypassed 2.0 x TC + 19.6 33.0 -- ns Very Narrow 2.0 x TC + 19.6 33.0 -- ns Narrow 2.0 x TC + 86.6 100.0 -- ns Wide 2.0 x TC + 186.6 200.0 -- ns Master -- -- -- -- ns Slave -- -- -- 5 ns XX 24 Tolerable Spike width on data or clock in. Serial clock high period -- Master Slave 25 Serial clock low period Master Slave 26 Serial clock rise/fall time -- DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 35 Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing (continued) No. Characteristics1,3,4 Mode Filter Mode Expression Min Max Unit 27 SS assertion to first SCK edge Slave Bypassed 2.0 x TC + 12.6 26 -- ns Very Narrow 2.0 x TC + 2.6 16 -- ns Narrow 2.0 x TC - 37.45 0 -- ns Wide 2.0 x TC - 87.45 0 -- ns Bypassed -- 10 -- ns Very Narrow -- 0 -- ns Narrow -- 0 -- ns Wide -- 0 -- ns Bypassed -- 12 -- ns Very Narrow -- 22 -- ns Narrow -- 100 -- ns Wide -- 200 -- ns Bypassed -- 0 -- ns Very Narrow -- 0 -- ns Narrow -- 0 -- ns Wide -- 0 -- ns Bypassed 3.0 x TC 20 -- ns Very Narrow 3.0 x TC + 23.2 43.2 -- ns Narrow 3.0 x TC + 53.2 73.2 -- ns Wide 3.0 x TC + 80 100.0 -- ns CPHA = 0 CPHA = 1 28 29 30 Slave Last SCK edge to SS not asserted Slave Data input valid to SCK edge (data input set-up time) SCK last sampling edge to data input not valid Master /Slave Master /Slave 31 SS assertion to data out active Slave -- -- 5 -- ns 32 SS deassertion to data high impedance2 Slave -- -- -- 9 ns 33 SCK edge to data out valid (data out delay time) Master /Slave Bypassed 3.0 x TC + 26.1 -- 46.2 ns Very Narrow 3.0 x TC + 90.4 -- 110.4 ns Narrow 3.0 x TC + 116.4 -- 136.4 ns Wide 3.0 x TC + 203.4 -- 223.4 ns Bypassed 2.0 x TC 13.4 -- ns Very Narrow 2.0 x TC + 1.6 15 -- ns Narrow 2.0 x TC + 41.6 55 -- ns Wide 2.0 x TC + 91.6 105 -- ns -- -- -- 12.0 ns 34 35 SCK edge to data out not valid (data out hold time) SS assertion to data out valid (CPHA = 0) Master /Slave Slave DSP56374 Data Sheet, Rev. 4.2 36 Freescale Semiconductor Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing (continued) No. 36 37 Characteristics1,3,4 SCK edge following the first SCK sampling edge to HREQ output deassertion Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Mode Filter Mode Expression Min Max Unit Slave Bypassed 3.0 x TC + 30 50 -- ns Very Narrow 3.0 x TC + 40 60 -- ns Narrow 3.0 x TC + 80 100 -- ns Wide 3.0 x TC + 120 150 -- ns Bypassed 4.0 x TC 57.0 -- ns Very Narrow 4.0 x TC 67.0 -- ns Narrow 4.0 x TC 107.0 -- ns Wide 4.0 x TC 157.0 -- ns Slave 38 SS deassertion to HREQ output not deasserted (CPHA = 0) Slave -- 3.0 x TC + 30 50.0 -- ns 39 SS deassertion pulse width (CPHA = 0) Slave -- 2.0 x TC 13.4 -- ns 40 HREQ in assertion to first SCK edge Master Bypassed 0.5 x TSPICC + 3.0 x TC + 5 63 -- ns Very Narrow 0.5 x TSPICC + 3.0 x TC + 5 63 -- ns Narrow 0.5 x TSPICC + 3.0 x TC + 5 125 -- ns Wide 0.5 x TSPICC + 3.0 x TC + 5 225 -- ns 41 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) Master -- -- 0 -- ns 42 First SCK edge to HREQ in not asserted (HREQ in hold time) Master -- -- 0 -- ns 43 HREQ assertion width Master -- 3.0 x TC 20 -- ns Note: 1 V CORE_VDD = 1.2 5 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2 Periodically sampled, not 100% tested 3 All times assume noise free inputs. 4 All times assume internal clock frequency of 150 MHz. 5 Equation applies when the result is positive T . C DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 37 Serial Host Interface SPI Protocol Timing SS (Input) 25 23 24 26 26 SCK (CPOL = 0) (Output) 23 24 26 25 26 SCK (CPOL = 1) (Output) 29 30 MISO (Input) 30 29 MSB Valid LSB Valid 34 33 MOSI (Output) MSB LSB 40 42 HREQ (Input) 43 Figure 7. SPI Master Timing (CPHA = 0) DSP56374 Data Sheet, Rev. 4.2 38 Freescale Semiconductor Serial Host Interface SPI Protocol Timing SS (Input) 25 23 24 26 26 SCK (CPOL = 0) (Output) 24 23 26 25 26 SCK (CPOL = 1) (Output) 29 29 30 MISO (Input) 30 MSB Valid LSB Valid 33 MOSI (Output) 34 MSB LSB 40 41 42 HREQ (Input) 43 Figure 8. SPI Master Timing (CPHA = 1) DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 39 Serial Host Interface SPI Protocol Timing SS (Input) 25 23 24 26 28 26 39 SCK (CPOL = 0) (Input) 27 23 24 26 25 26 SCK (CPOL = 1) (Input) 35 33 34 31 MISO (Output) 34 32 MSB LSB 29 29 30 MOSI (Input) MSB Valid 30 LSB Valid 36 38 HREQ (Output) Figure 9. SPI Slave Timing (CPHA = 0) DSP56374 Data Sheet, Rev. 4.2 40 Freescale Semiconductor Serial Host Interface (SHI) I2C Protocol Timing SS (Input) 25 23 24 26 28 26 SCK (CPOL = 0) (Input) 27 24 26 25 26 SCK (CPOL = 1) (Input) 33 33 34 32 31 MISO (Output) MSB LSB 29 29 30 30 MSB Valid MOSI (Input) LSB Valid 37 36 HREQ (Output) Figure 10. SPI Slave Timing (CPHA = 1) Serial Host Interface (SHI) I2C Protocol Timing 14 Table 22. SHI I2C Protocol Timing Standard I2C No. XX Symbol/ Expression Characteristics1,2,3,4,5 Standard Fast-Mode Unit Min Max Min Max Filters Bypassed -- 0 -- 0 ns Very Narrow Filters enabled -- 10 -- 10 ns Narrow Filters enabled -- 50 -- 50 ns Wide Fileters enabled. -- 100 -- 100 ns Tolerable Spike Width on SCL or SDA -- 44 SCL clock frequency FSCL -- 100 -- 400 kHz 44 SCL clock cycle TSCL 10 -- 2.5 -- s 45 Bus free time TBUF 4.7 -- 1.3 -- s 46 Start condition set-up time TSUSTA 4.7 -- 0.6 -- s DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 41 Serial Host Interface (SHI) I2C Protocol Timing Table 22. SHI I2C Protocol Timing (continued) Standard I2C No. Symbol/ Expression Characteristics1,2,3,4,5 Standard Fast-Mode Unit Min Max Min Max THD;STA 4.0 -- 0.6 -- s 47 Start condition hold time 48 SCL low period TLOW 4.7 -- 1.3 -- s 49 SCL high period THIGH 4.0 -- 1.3 -- s 50 SCL and SDA rise time TR -- 5.0 -- 5.0 ns 51 SCL and SDA fall time TF -- 5.0 -- 5.0 ns 52 Data set-up time TSU;DAT 250 -- 100 -- ns 53 Data hold time THD;DAT 0.0 -- 0.0 0.9 s 54 DSP clock frequency * Filters bypassed 10.6 -- 28.5 -- MHz * Very Narrrow filters enabled 10.6 -- 28.5 -- MHz * Narrow filters enabled 11.8 -- 39.7 -- MHz * Wide filters enabled 13.1 -- 61.0 -- MHz FOSC 55 SCL low to data out valid TVD;DAT -- 3.4 -- 0.9 s 56 Stop condition setup time TSU;STO 4.0 -- 0.6 -- s 57 HREQ in deassertion to last SCL edge (HREQ in set-up time) tSU;RQI 0.0 -- 0.0 -- ns 58 First SCL sampling edge to HREQ output deassertion2 -- 57.0 -- 57.0 ns -- 77.0 -- 67.0 ns -- 157.0 -- 157.0 ns -- 257.0 -- 257.0 ns 44 -- 44 -- ns 54 -- 54 -- ns 94 -- 94 -- ns 144 -- 144 -- ns * Filters bypassed 4327 -- 927 -- ns * Very Narrow filters enabled 4317 -- 917 -- ns * Narrow filters enabled 4282 -- 877 -- ns * Wide filters enabled 4227 -- 827 -- ns 0.0 -- 0.0 -- ns * Filters bypassed * Very Narrow filters enabled * Wide filters enabled Last SCL edge to HREQ output not deasserted2 * Filters bypassed * Very Narrow filters enabled * Wide filters enabled 61 TAS;RQO 2 x TC + 30 2 x TC + 40 2 x TC + 80 2 x TC + 130 * Narrow filters enabled 60 4 x TC + 30 4 x TC + 50 4 x TC + 130 4 x TC + 230 * Narrow filters enabled 59 TNG;RQO HREQ in assertion to first SCL edge First SCL edge to HREQ is not asserted (HREQ in hold time.) TAS;RQI tHO;RQI DSP56374 Data Sheet, Rev. 4.2 42 Freescale Semiconductor Programming the Serial Clock Table 22. SHI I2C Protocol Timing (continued) Standard I2C No. Symbol/ Expression Characteristics1,2,3,4,5 Standard Min Max Fast-Mode Min Unit Max Note: 1 VCORE_VDD = 1.2 5 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2 Pull-up resistor: R P (min) = 1.5 kOhm 3 Capacitive load: C b (max) = 50 pF 4 All times assume noise free inputs 5 All times assume internal clock frequency of 150MHz 15 Programming the Serial Clock The programmed serial clock cycle, T I CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). 2 The expression for T I CCP is 2 T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] Eqn. 1 where -- HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. -- HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC (if HDM[7:0] = $02 and HRS = 1) Eqn. 2 4096 x TC (if HDM[7:0] = $FF and HRS = 0) Eqn. 3 to The programmed serial clock cycle (TI CCP ) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Table 23. 2 Table 23. SCL Serial Clock Cycle (TSCL) Generated as Master Nominal TI2CCP + 3 x TC + 45ns + TR DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 43 Enhanced Serial Audio Interface Timing 44 46 49 48 SCL 50 53 51 45 52 SDA MSB Stop Start 47 LSB 58 61 ACK Stop 55 56 57 60 59 HREQ Figure 11. I2C Timing 16 Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing Characteristics1, 2, 3 No. 62 63 64 65 66 Clock cycle5 Clock high period Expression3 Min Max Condition4 Unit tSSICC 4 x Tc 26.4 -- x ck ns 4 x Tc 26.4 -- i ck ns tSSICCH * For internal clock 2 x Tc - 0.5 12.8 -- * For external clock 2 x Tc 13.4 -- * For internal clock 2 x Tc 13.4 -- * For external clock 2 x Tc 13.4 -- -- -- 17.0 x ck -- 7.0 i ck a -- 17.0 x ck -- 7.0 i ck a -- 19.0 x ck -- 9.0 i ck a -- 19.0 x ck -- 9.0 i ck a -- 16.0 x ck -- 6.0 i ck a Clock low period tSSICCL SCKR edge to FSR out (bl) high -- SCKR edge to FSR out (bl) low -- 6 67 SCKR edge to FSR out (wr) high 68 low6 69 Symbol SCKR edge to FSR out (wr) SCKR edge to FSR out (wl) high -- -- -- ns -- -- -- -- ns ns ns ns ns DSP56374 Data Sheet, Rev. 4.2 44 Freescale Semiconductor Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing (continued) No. 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Characteristics1, 2, 3 SCKR edge to FSR out (wl) low Symbol Expression3 Min Max Condition4 Unit -- -- -- 17.0 x ck ns -- 7.0 i ck a 12.0 -- x ck 19.0 -- i ck 3.5 -- x ck 9.0 -- i ck 2.0 -- x ck 12.0 -- i ck a 2.0 -- x ck 12.0 -- i ck a 2.5 -- x ck 8.5 -- i ck a 0.0 -- x ck 19.0 -- i ck s 6.0 -- x ck 0.0 -- i ck s -- 18.0 x ck -- 8.0 i ck -- 20.0 x ck -- 10.0 i ck -- 20.0 x ck -- 10.0 i ck -- 22.0 x ck -- 12.0 i ck -- 19.0 x ck -- 9.0 i ck -- 20.0 x ck -- 10.0 i ck -- 22.0 x ck -- 17.0 i ck -- 17.0 x ck -- 11.0 i ck -- 18.0 x ck -- 13.0 i ck -- 21.0 x ck -- 16.0 i ck Data in setup time before SCKR (SCK in synchronous mode) edge -- Data in hold time after SCKR edge -- FSR input (bl, wr) high before SCKR edge 6 FSR input (wl) high before SCKR edge -- -- FSR input hold time after SCKR edge -- Flags input setup before SCKR edge -- Flags input hold time after SCKR edge -- SCKT edge to FST out (bl) high -- SCKT edge to FST out (bl) low -- SCKT edge to FST out (wr) high6 -- 6 -- SCKT edge to FST out (wr) low SCKT edge to FST out (wl) high -- SCKT edge to FST out (wl) low -- SCKT edge to data out enable from high impedance -- SCKT edge to transmitter #0 drive enable assertion -- SCKT edge to data out valid -- SCKT edge to data out high impedance 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 45 Enhanced Serial Audio Interface Timing Table 24. Enhanced Serial Audio Interface Timing (continued) No. 88 89 90 91 Characteristics1, 2, 3 Symbol Expression3 Min Max Condition4 Unit SCKT edge to transmitter #0 drive enable deassertion7 -- -- -- 14.0 x ck ns -- 9.0 i ck FST input (bl, wr) setup time before SCKT edge6 -- 2.0 -- x ck 18.0 -- i ck FST input (wl) setup time before SCKT edge -- 2.0 -- x ck 18.0 -- i ck FST input hold time after SCKT edge -- 4.0 -- x ck 5.0 -- i ck -- -- -- ns ns ns 92 FST input (wl) to data out enable from high impedance -- -- -- 21.0 -- ns 93 FST input (wl) to transmitter #0 drive enable assertion -- -- -- 14.0 -- ns 94 Flag output valid after SCKT rising edge -- -- -- 14.0 x ck ns -- 9.0 i ck 95 HCKR/HCKT clock cycle -- 2 x TC 13.4 -- ns 96 HCKT input edge to SCKT output -- -- -- 18.0 ns 97 HCKR input edge to SCKR output -- -- -- 18.0 ns Note: 1 V CORE_VDD = 1.25 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that SCKT and SCKR are the same clock) 3 bl = bit length wl = word length wr = word length relative 4 SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 5 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. 6 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7 Periodically sampled and not 100% tested. 8 ESAI_1 specs match those of ESAI. DSP56374 Data Sheet, Rev. 4.2 46 Freescale Semiconductor Enhanced Serial Audio Interface Timing 62 SCKT (Input/Output) 63 64 78 79 FST (Bit) Out 83 84 FST (Word) Out 87 87 85 88 Data Out First Bit Last Bit 92 Transmitter #0 Drive Enable 90 86 89 94 FST (Bit) In 91 94 93 FST (Word) In 95 See Note Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Figure 12 is drawn assuming positive polarity bit clock (TCKP=0) and positive frame sync polarity (TFSP=0). Figure 12. ESAI Transmitter Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 47 Enhanced Serial Audio Interface Timing 62 63 64 SCKR (Input/Output) 65 66 FSR (Bit) Out 69 70 FSR (Word) Out 72 71 Data In First Bit Last Bit 75 73 FSR (Bit) In 74 FSR (Word) In 75 76 77 Flags In Note: Figure 13 is drawn assuming positive polarity bit clock (RCKP=0) and positive frame sync polarity (RFSP=0). Figure 13. ESAI Receiver Timing DSP56374 Data Sheet, Rev. 4.2 48 Freescale Semiconductor Timer Timing HCKT SCKT (output) 95 96 Note: Figure 14 is drawn assuming positive polarity high frequency clock (THCKP=0) and positive bit clock polarity (TCKP=0). Figure 14. ESAI HCKT Timing HCKR SCKR (output) 95 97 Note: Figure 15 is drawn assuming positive polarity high frequency clock (RHCKP=0) and positive bit clock polarity (RCKP=0). Figure 15. ESAI HCKR Timing 17 Timer Timing Table 25. Timer Timing 150 MHz No. Characteristics Expression Unit Min Max 98 TIO Low 2 x TC + 2.0 15.4 -- ns 99 TIO High 2 x TC + 2.0 15.4 -- ns Note: VCORE_VDD = 1.25 V 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF TIO 98 99 Figure 16. TIO Timer Event Input Restrictions DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 49 GPIO Timing 18 GPIO Timing Table 26. GPIO Timing Characteristics1 No. 100 Expression EXTAL edge to GPIO out valid (GPIO out delay time)2 101 EXTAL edge to GPIO out not valid (GPIO out hold time) 102 GPIO In valid to EXTAL edge (GPIO in set-up time)2 2 Min Max Unit -- 7 ns -- 7 ns 2 -- ns 0 -- ns 2 103 EXTAL edge to GPIO in not valid (GPIO in hold time) 104 Minimum GPIO pulse high width TC + 13 19.7 -- ns 105 Minimum GPIO pulse low width TC + 13 19.7 -- ns 106 GPIO out rise time -- -- 13.0 ns 107 GPIO out fall time -- -- 13.0 ns Note: 1 V CORE_VDD = 1.25 V 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2 PLL Disabled, EXTAL driven by a square wave. EXTAL 100 101 GPIO (Output) 102 GPIO (Input) 103 Valid GPIO (Output) 104 106 105 107 Figure 17. GPIO Timing 19 JTAG Timing Table 27. JTAG Timing All frequencies No. 108 Characteristics TCK frequency of operation (1/(TC x 3); maximum 10 MHz) Unit Min Max -- 10.0 MHz DSP56374 Data Sheet, Rev. 4.2 50 Freescale Semiconductor JTAG Timing Table 27. JTAG Timing (continued) All frequencies No. Characteristics Unit Min Max 109 TCK cycle time in Crystal mode 100.0 -- ns 110 TCK clock pulse width measured at 1.65 V 50.0 -- ns 111 TCK rise and fall times -- 3.0 ns 112 Boundary scan input data setup time 15.0 -- ns 113 Boundary scan input data hold time 24.0 -- ns 114 TCK low to output data valid -- 40.0 ns 115 TCK low to output high impedance -- 40.0 ns 116 TMS, TDI data setup time 5.0 -- ns 117 TMS, TDI data hold time 25.0 -- ns 118 TCK low to TDO data valid -- 44.0 ns 119 TCK low to TDO high impedance -- 44.0 ns Note: 1. VCORE_VDD = 1.25 V 0.05 V; TJ = -40C to 110C (52 LQFP) / -40C to 105C (80 LQFP), CL = 50 pF 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. 109 TCK (Input) VIH 110 110 VM VM VIL 111 111 Figure 18. Test Clock Input Timing Diagram DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 51 JTAG Timing TCK (Input) VIH VIL 112 Data Inputs 113 Input Data Valid 114 Data Outputs Output Data Valid 115 Data Outputs 114 Data Outputs Output Data Valid Figure 19. Debugger Port Timing Diagram TCK (Input) VIH VIL 116 TDI TMS (Input) 117 Input Data Valid 118 TDO (Output) Output Data Valid 119 TDO (Output) 118 TDO (Output) Output Data Valid Figure 20. Test Access Port Timing Diagram DSP56374 Data Sheet, Rev. 4.2 52 Freescale Semiconductor Watchdog Timer Timing 20 Watchdog Timer Timing Table 28. Watchdog Timer Timing No. Characteristics Expression Min Max Unit 120 Delay from time-out to fall of TIO1 2 x Tc 13.4 -- ns 121 Delay from timer clear to rise of TIO1 2 x Tc 13.4 -- ns DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 53 Watchdog Timer Timing Appendix A Package Information SCKT_1_PE3 HCKR_1_PE2 HCKR_PC2 HCKT_PC5 HCKT_1_PE5 SCAN IO_Vdd 65 64 63 62 61 SCKR_1_PE0 70 66 Core_Gnd 71 67 Core_Vdd 72 SCKR_PC0 GPIO_PG14 73 SCKT_PC3 FST_1_PE4 74 68 FST_PC4 75 69 FSR_1_PE1 FSR_PC1 SDO4_PC7 78 76 SDO5_PC6 79 77 IO_Gnd 80 DSP56374 Pinout SCK_SCL 15 46 XTAL MISO_SDA 16 45 EXTAL MOSI_HA0 17 44 PLLD_Vdd GPIO_PG8 18 43 PLLD_Gnd GPIO_PG7 19 42 PLLP_Gnd IO_Gnd 20 41 PLLP_Vdd 40 IO_Vdd PLLA_Gnd 47 39 14 PLLA_Vdd PINIT_NMI SS_HA2 38 SDO0_1_PE11 48 37 49 13 GPIO_PG0 12 HREQ_PH4 GPIO_PG1 GPIO_PG9 36 SDO1_1_PE10 35 50 GPIO_PG2 11 RESET_B Core_Gnd GPIO_PG10 34 51 GPIO_PG3 10 33 Core_Vdd Core_Gnd Core_Gnd 52 32 9 Core_Vdd SDO2_1_PE9 Core_Vdd 31 53 PLOCK/TIO2 8 30 SDO3_1_PE8 GPIO_PG11 WDT/TIO1 54 29 7 TIO00 SDO0_PC11 MODD_IRQD_PH3 28 55 27 6 GPIO_PG4 SDO1_PC10 MODC_IRQC_PH2 TCK SDO2_PC9 56 26 57 5 TMS 4 GPIO_PG12 25 GPIO_PG13 TDI SDO3_PC8 24 58 TDO 3 23 SDO4_1_PE7 MODB_IRQB_PH1 22 59 GPIO_PG5 60 2 21 1 MODA_IRQA_PH0 GPIO_PG6 IO_Vdd IO_Vdd A.1 SDO5_1_PE6 1.25 V Filter 3.3 V Figure A-1. 80-Pin Vdd Connections DSP56374 Data Sheet, Rev. 4.2 54 Freescale Semiconductor HCKT_PC5 SCAN IO_Vdd 42 41 40 26 HCKR_PC2 43 PLLA_Gnd SCKR_PC0 SCKT_PC3 Core_Gnd 46 44 FST_PC4 FSR_PC1 Core_Vdd SDO4_PC7 49 47 SDO5_PC6 50 48 IO_Gnd 51 45 25 13 PLLA_Vdd 12 IO_Gnd 23 MOSI_HA0 24 11 RESET_B MISO_SDA Core_Gnd 10 22 SCK_SCL Core_Vdd 9 21 SS_HA2 20 8 PLOCK/TIO2 HREQ_PH4 WDT/TIO1 7 19 Core_Gnd TIO00 6 18 Core_Vdd TCK 5 17 MODD_IRQD_PH3 TMS 4 16 MODC_IRQC_PH2 TDI 3 15 MODB_IRQB_PH1 14 2 TDO 1 MODA_IRQA_PH0 IO_Vdd IO_Vdd 52 Watchdog Timer Timing 39 SDO3_PC8 38 SDO2_PC9 37 SDO1_PC10 36 SDO0_PC11 35 Core_Vdd 34 Core_Gnd 33 PINIT_NMI 32 XTAL 31 EXTAL 30 PLLD_Vdd 29 PLLD_Gnd 28 PLLP_Gnd 27 PLLP_Vdd 1.25 V Filter 3.3 V Figure A-2. 52-pin Vdd Connections DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 55 Watchdog Timer Timing A.2 A.2.1 Package Information 80-Pin Package . DSP56374 Data Sheet, Rev. 4.2 56 Freescale Semiconductor Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 57 Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 58 Freescale Semiconductor Watchdog Timer Timing . DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 59 Watchdog Timer Timing A.2.2 52-Pin Package DSP56374 Data Sheet, Rev. 4.2 60 Freescale Semiconductor Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 61 Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 62 Freescale Semiconductor Watchdog Timer Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 63 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com DSP56374 Rev. 4.2, 1/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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