2010 Microchip Technology Inc. DS22249A-page 1
MCP4802/4812/4822
Features
• MCP4802: Dual 8-Bit Voltage Output DAC
• MCP4812: Dual 10-Bit Voltage Output DAC
• MCP4822: Dual 12-Bit Voltage Output DAC
• Rail-to-Rail Output
• SPI Interface with 20 MHz Clock Support
• Simultaneous Latching of the Dual DACs
with LDAC pin
• Fast Settling Time of 4.5 µs
• Selectable Unity or 2x Gain Output
• 2.048V Internal Voltage Reference
•50ppm/°C V
REF Temperature Coefficient
• 2.7V to 5.5V Single-Supply Operation
• Extended Temperature Range: -40°C to +125°C
Applications
• Set Point or Offset Trimming
• Sensor Calibration
• Precision Selectable Voltage Reference
• Portable Instrumentation (Battery-Powered)
• Calibration of Optical Communication Devices
Description
The MCP4802/4812/4822 devices are dual 8-bit, 10-bit
and 12-bit buffered voltage output Digital-to-Analog
Converters (DACs), respectively. The devices operate
from a single 2.7V to 5.5V supply with SPI compatible
Serial Peripheral Interface.
The devices have a high precision internal voltage
reference (VREF = 2.048V). The user can configure the
full-scale range of the device to be 2.048V or 4.096V by
setting the Gain Selection Option bit (gain of 1 of 2).
Each DAC channel can be operated in Active or
Shutdown mode individually by setting the Configuration
register bits. In Shutdown mode, most of the internal
circuits in the shutdown channel are turned off for power
savings and the output amplifier is configured to present
a known high resistance output load (500 k typical.
The devices include double-buffered registers,
allowing synchronous updates of two DAC outputs
using the LDAC pin. These devices also incorporate a
Power-on Reset (POR) circuit to ensure reliable power-
up.
The devices utilize a resistive string architecture, with
its inherent advantages of low DNL error, low ratio
metric temperature coefficient and fast settling time.
These devices are specified over the extended
temperature range (+125°C).
The devices provide high accuracy and low noise
performance for consumer and industrial applications
where calibration or compensation of signals (such as
temperature, pressure and humidity) are required.
The MCP4802/4812/4822 devices are available in the
PDIP, SOIC and MSOP packages.
Package Types
Related Products(1)
P/N DAC
Resolution
No. of
Channels
Voltage
Reference
(VREF)
MCP4801 8 1
Internal
(2.048V)
MCP4811 10 1
MCP4821 12 1
MCP4802 8 2
MCP4812 10 2
MCP4822 12 2
MCP4901 8 1
External
MCP4911 10 1
MCP4921 12 1
MCP4902 8 2
MCP4912 10 2
MCP4922 12 2
Note 1: The products listed here have similar
AC/DC performances.
MCP48X2
8-Pin PDIP, SOIC, MSOP
1
2
3
4
8
7
6
5
CS
SCK
SDI
VDD
VSS
VOUTA
VOUTB
LDAC
MCP4802: 8-bit dual DAC
MCP4812: 10-bit dual DAC
MCP4822: 12-bit dual DAC
8/10/12-Bit Dual Voltage Output Digital-to-Analog Converter
with Internal VREF and SPI Interface
MCP4802/4812/4822
DS22249A-page 2 2010 Microchip Technology Inc.
Block Diagram
Op Amps
VDD
VSS
CS SDI SCK
Interface Logic
Input
Register A Register B
Input
DACA
Register Register
DACB
String
DACB
String
DACA
Output
Power-on
Reset
VOUTA VOUTB
LDAC
Output
Gain
Logic
Gain
Logic
2.048V
VREF
Logic
2010 Microchip Technology Inc. DS22249A-page 3
MCP4802/4812/4822
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD....................................................................... 6.5V
All inputs and outputs .......... VSS – 0.3V to VDD + 0.3V
Current at Input Pins ......................................... ±2 mA
Current at Supply Pins ....................................±50 mA
Current at Output Pins ....................................±25 mA
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied ..... -55°C to +125°C
ESD protection on all pins 4 kV (HBM), 400V (MM)
Maximum Junction Temperature (TJ)................+150°C
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V,
Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Power Requirements
Input Voltage VDD 2.7 — 5.5 V
Input Current IDD — 415 750 µA All digital inputs are grounded,
all analog outputs (VOUT) are
unloaded. Code = 0x000h
Software Shutdown Current ISHDN_SW —3.3 6 µA
Power-on Reset Threshold VPOR —2.0 — V
DC Accuracy
MCP4802
Resolution n 8 — — Bits
INL Error INL -1 ±0.125 1LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4812
Resolution n 10 — — Bits
INL Error INL -3.5 ±0.5 3.5 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4822
Resolution n12 — — Bits
INL Error INL -12 ±2 12 LSb
DNL DNL -0.75 ±0.2 +0.75 LSb Note 1
Offset Error VOS -1 ±0.02 1 % of FSR Code = 0x000h
Offset Error Temperature
Coefficient
VOS/°C — 0.16 — ppm/°C -45°C to +25°C
— -0.44 — ppm/°C +25°C to +85°C
Gain Error gE-2 -0.10 2 % of FSR Code = 0xFFFh,
not including offset error
Gain Error Temperature
Coefficient
G/°C — -3 — ppm/°C
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.
MCP4802/4812/4822
DS22249A-page 4 2010 Microchip Technology Inc.
Internal Voltage Reference (VREF)
Internal Reference Voltage VREF 2.008 2.048 2.088 V VOUTA when G = 1x and
Code = 0xFFFh
Temperature Coefficient
(Note 2)
VREF/°C — 125 325 ppm/°C -40°C to 0°C
— 0.25 0.65 LSb/°C -40°C to 0°C
— 45 160 ppm/°C 0°C to +85°C
— 0.09 0.32 LSb/°C 0°C to +85°C
Output Noise (VREF Noise) ENREF
(0.1-
10 Hz)
—290 —µV
p-p Code = 0xFFFh, G = 1x
Output Noise Density eNREF
(1 kHz)
—1.2 —µV/Hz Code = 0xFFFh, G = 1x
eNREF
(10 kHz)
—1.0 —µV/Hz Code = 0xFFFh, G = 1x
1/f Corner Frequency fCORNER —400 — Hz
Output Amplifier
Output Swing VOUT — 0.01 to
VDD – 0.04
— V Accuracy is better than 1 LSb for
VOUT = 10 mV to (VDD–40 mV)
Phase Margin PM — 66 — Degree
(°)
CL= 400 pF, RL =
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC —15 24mA
Settling Time tSETTLING — 4.5 — µs Within 1/2 LSb of final value from
1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — <10 — nV-s
Major Code Transition Glitch — 45 — nV-s 1 LSb change around major carry
(0111...1111 to
1000...0000)
Digital Feedthrough — <10 — nV-s
Analog Crosstalk — <10 — nV-s
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V,
Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.
2010 Microchip Technology Inc. DS22249A-page 5
MCP4802/4812/4822
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Power Requirements
Input Voltage VDD 2.7 — 5.5 V
Input Current
Input Curren
IDD — 440 — µA All digital inputs are grounded,
all analog outputs (VOUT) are
unloaded. Code = 0x000h.
Software Shutdown Current ISHDN_SW —5—µA
Power-On Reset threshold VPOR —1.85— V
DC Accuracy
MCP4802
Resolution n 8 — — Bits
INL Error INL — ±0.25 — LSb
DNL DNL — ±0.2 — LSb Note 1
MCP4812
Resolution n 10 — — Bits
INL Error INL — ±1 — LSb
DNL DNL — ±0.2 — LSb Note 1
MCP4822
Resolution n12 — — Bits
INL Error INL —±4 —LSb
DNL DNL — ±0.25 — LSb Note 1
Offset Error VOS — ±0.02 — % of FSR Code = 0x000h
Offset Error Temperature
Coefficient
VOS/°C — -5 — ppm/°C +25°C to +125°C
Gain Error gE— -0.10 — % of FSR Code = 0xFFFh,
not including offset error
Gain Error Temperature
Coefficient
G/°C — -3 — ppm/°C
Internal Voltage Reference (VREF)
Internal Reference Voltage VREF — 2.048 — V VOUTA when G = 1x and
Code = 0xFFFh
Temperature Coefficient
(Note 2)
VREF/°C — 125 — ppm/°C -40°C to 0°C
— 0.25 — LSb/°C -40°C to 0°C
— 45 — ppm/°C 0°C to +85°C
— 0.09 — LSb/°C 0°C to +85°C
Output Noise (VREF Noise) ENREF
(0.1 – 10 Hz)
— 290 — µVp-p Code = 0xFFFh, G = 1x
Output Noise Density eNREF
(1 kHz)
—1.2—µV/
Hz Code = 0xFFFh, G = 1x
eNREF
(10 kHz)
—1.0—µV/
Hz Code = 0xFFFh, G = 1x
1/f Corner Frequency fCORNER — 400 — Hz
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.
MCP4802/4812/4822
DS22249A-page 6 2010 Microchip Technology Inc.
Output Amplifier
Output Swing VOUT — 0.01 to
VDD – 0.04
— V Accuracy is better than 1 LSb
for
VOUT = 10 mV to (VDD –
40 mV)
Phase Margin PM — 66 — Degree (°) CL= 400 pF, RL =
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC —17—mA
Settling Time tSETTLING — 4.5 — µs Within 1/2 LSb of final value
from 1/4 to 3/4 full-scale range
Dynamic Performance (Note 2)
DAC-to-DAC Crosstalk — <10 — nV-s
Major Code Transition
Glitch
— 45 — nV-s 1 LSb change around major
carry (0111...1111 to
1000...0000)
Digital Feedthrough — <10 — nV-s
Analog Crosstalk — <10 — nV-s
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C.
Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Schmitt Trigger High-Level
Input Voltage
(All digital input pins)
VIH 0.7 VDD ——V
Schmitt Trigger Low-Level
Input Voltage
(All digital input pins)
VIL ——0.2V
DD V
Hysteresis of Schmitt Trigger
Inputs
VHYS —0.05V
DD —V
Input Leakage Current ILEAKAGE -1 — 1 ALDAC = CS = SDI = SCK =
VDD or VSS
Digital Pin Capacitance
(All inputs/outputs)
CIN,
COUT
—10—pFV
DD = 5.0V, TA = +25°C,
fCLK = 1 MHz (Note 1)
Clock Frequency FCLK ——20MHzT
A = +25°C (Note 1)
Clock High Time tHI 15 — — ns Note 1
Clock Low Time tLO 15 — — ns Note 1
CS Fall to First Rising CLK
Edge
tCSSR 40 — — ns Applies only when CS falls with
CLK high. (Note 1)
Data Input Setup Time tSU 15 — — ns Note 1
Data Input Hold Time tHD 10 — — ns Note 1
SCK Rise to CS Rise Hold
Time
tCHS 15 — — ns Note 1
Note 1: This parameter is ensured by design and not 100% tested.
ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATURE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by design over all codes.
2: This parameter is ensured by design, and not 100% tested.
2010 Microchip Technology Inc. DS22249A-page 7
MCP4802/4812/4822
FIGURE 1-1: SPI Input Timing Data.
TEMPERATURE CHARACTERISTICS
CS High Time tCSH 15 — — ns Note 1
LDAC Pulse Width tLD 100 — — ns Note 1
LDAC Setup Time tLS 40 — — ns Note 1
SCK Idle Time before CS Fall tIDLE 40 — — ns Note 1
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP JA —211—°C/W
Thermal Resistance, 8L-PDIP JA —90—°C/W
Thermal Resistance, 8L-SOIC JA —150—°C/W
Note 1: The MCP4802/4812/4822 devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the maximum junction temperature
of +150°C.
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 to +125°C.
Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: This parameter is ensured by design and not 100% tested.
CS
SCK
SDI
LDAC
tCSSR
tHD
tSU
tLO
tCSH
tCHS
LSb in
MSb in
tIDLE
Mode 1,1
Mode 0,0
tHI
tLD
tLS
MCP4802/4812/4822
DS22249A-page 8 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22249A-page 9
MCP4802/4812/4822
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-1: DNL vs. Code (MCP4822).
FIGURE 2-2: DNL vs. Code and
Temperature (MCP4822).
FIGURE 2-3: Absolute DNL vs.
Temperature (MCP4822).
FIGURE 2-4: INL vs. Code and
Temperature (MCP4822).
FIGURE 2-5: Absolute INL vs.
Temperature (MCP4822).
FIGURE 2-6: INL vs. Code (MCP4822).
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 1024 2048 3072 4096
Code (Decimal)
DNL (LSB)
-0.2
-0.1
0
0.1
0.2
0 1024 2048 3072 4096
Code (Decimal)
DNL (LSB)
125C 85C 25C
0.075
0.0752
0.0754
0.0756
0.0758
0.076
0.0762
0.0764
0.0766
-40-20 0 20406080100120
Ambient Temperature (ºC)
Absolute DNL (LSB)
Note: Single device graph for illustration of 64
code effect.
-5
-4
-3
-2
-1
0
1
2
3
4
5
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
125C 85 25
Ambient Temperature
0
0.5
1
1.5
2
2.5
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Absolute INL (LSB)
-6
-4
-2
0
2
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
MCP4802/4812/4822
DS22249A-page 10 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-7: DNL vs. Code and
Temperature (MCP4812).
FIGURE 2-8: INL vs. Code and
Temperature (MCP4812).
FIGURE 2-9: DNL vs. Code and
Temperature (MCP4802).
FIGURE 2-10: INL vs. Code and
Temperature (MCP4802).
FIGURE 2-11: Full-Scale VOUTA vs.
Ambient Temperature and VDD. Gain = 1x.
FIGURE 2-12: Full-Scale VOUTA vs.
Ambient Temperature and VDD. Gain = 2x.
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 128 256 384 512 640 768 896 1024
Code
DNL (LSB)
- 40oC
+25oC to +125oC
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
0 128 256 384 512 640 768 896 1024
Code
INL (LSB)
25oC
85oC
125oC
- 40oC
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0 32 64 96 128 160 192 224 256
Code
DNL (LSB)
34
Temperature: - 40oC to +125o
C
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0 326496128160192224256
Code
INL (LSB)
-
40
oC
25oC
85oC
125oC
2.040
2.041
2.042
2.043
2.044
2.045
2.046
2.047
2.048
2.049
2.050
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
Full Scale VOU T (V)
VDD: 4V
VDD: 3V
VDD: 2.7V
4.076
4.080
4.084
4.088
4.092
4.096
4.100
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
Full Scale VOUT (V)
VDD: 5.5V
VDD: 5V
2010 Microchip Technology Inc. DS22249A-page 11
MCP4802/4812/4822
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-13: Output Noise Voltage
Density (VREF Noise Density) vs. Frequency.
Gain = 1x.
FIGURE 2-14: Output Noise Voltage
(VREF Noise Voltage) vs. Bandwidth. Gain = 1x.
FIGURE 2-15:
I
DD
vs. Temperature and V
DD
.
FIGURE 2-16: IDD Histogram (VDD = 2.7V).
FIGURE 2-17: IDD Histogram (VDD = 5.0V).
1.E-07
1.E-06
1.E-05
1.E-04
1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 1E+5
Frequency (Hz)
Output Noise Voltage Density
(µV/Hz)
0.1
1 10 100 1k 10k 100k
100
10
1
0.1
1.E-05
1.E-04
1.E-03
1.E-02
1E+2 1E+3 1E+4 1E+5 1E+6
Bandwidth (Hz)
Output Noise Voltage (mV)
100 1k 10k 100k 1M
Eni (in VRMS)
10.0
1.00
0.10
0.01
Eni (in VP-P)
Maximum Measurement Time = 10s
180
200
220
240
260
280
300
320
340
-40-20 0 20406080100120
Ambient Temperature (°C)
IDD (µA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0
5
10
15
20
25
380
385
390
395
400
405
410
415
420
425
430
435
440
IDD (µA)
Occurrence
0
2
4
6
8
10
12
14
16
18
20
22
385
390
395
400
405
410
415
420
425
430
435
IDD (µA)
Occurrence
MCP4802/4812/4822
DS22249A-page 12 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-18: Software Shutdown Current
vs. Temperature and VDD.
FIGURE 2-19: Offset Error vs. Temperature
and VDD.
FIGURE 2-20: Gain Error vs. Temperature
and VDD.
FIGURE 2-21: VIN High Threshold vs.
Temperature and VDD.
FIGURE 2-22: VIN Low Threshold vs.
Temperature and VDD.
1
1.5
2
2.5
3
3.5
4
-40-20 0 20406080100120
Ambient Temperature (ºC)
ISHDN_SW (µA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
-0.03
-0.01
0.01
0.03
0.05
0.07
0.09
0.11
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Offset Error (%)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
-0.5
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
Gain Error (%)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
1
1.5
2
2.5
3
3.5
4
-40-200 20406080100120
Ambient Temperature (ºC)
VIN Hi Threshold (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VIN Low Threshold (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
2010 Microchip Technology Inc. DS22249A-page 13
MCP4802/4812/4822
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-23: Input Hysteresis vs.
Temperature and VDD.
FIGURE 2-24: VOUT High Limit
vs.Temperature and VDD.
FIGURE 2-25: VOUT Low Limit vs.
Temperature and VDD.
FIGURE 2-26: IOUT High Short vs.
Temperature and VDD.
FIGURE 2-27: IOUT vs. VOUT
. Gain = 2x.
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
-40-20 0 20406080100120
Ambient Temperature (ºC)
VIN_SPI Hysteresis (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0.015
0.017
0.019
0.021
0.023
0.025
0.027
0.029
0.031
0.033
0.035
-40-20 0 20406080100120
Ambient Temperature (ºC)
VOUT_HI Limit (VDD-Y)(V)
VDD
4.0V
3.0V
2.7V
0.0010
0.0012
0.0014
0.0016
0.0018
0.0020
0.0022
0.0024
0.0026
0.0028
-40-20 0 20406080100120
Ambient Temperature (ºC)
VOUT_LOW Limit (Y-AVSS)(V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
10
11
12
13
14
15
16
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
IOUT_HI_SHORTED (mA)
V
DD
5.5V
4
.0V
5.0V
3
.0V
2
.7V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0246810121416
IOUT (mA)
VOUT (V)
VREF = 4.096V
Output Shorted to VSS
Output Shorted to VDD
MCP4802/4812/4822
DS22249A-page 14 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2x, RL = 5 k, CL = 100 pF.
FIGURE 2-28: VOUT Rise Time.
FIGURE 2-29: VOUT Fall Time.
FIGURE 2-30: VOUT Rise Time.
FIGURE 2-31: VOUT Rise Time.
FIGURE 2-32: VOUT Rise Time Exit
Shutdown.
FIGURE 2-33: PSRR vs. Frequency.
VOUT
SCK
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
Time (1 µs/div)
VOUT
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Ripple Rejection (dB)
Frequency (Hz)
2010 Microchip Technology Inc. DS22249A-page 15
MCP4802/4812/4822
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Tab l e 3- 1 .
3.1 Supply Voltage Pins (VDD, VSS)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS and can range from
2.7V to 5.5V. The power supply at the VDD pin should
be as clean as possible for a good DAC performance.
It is recommended to use an appropriate bypass
capacitor of about 0.1 µF (ceramic) to ground. An
additional 10 µF capacitor (tantalum) in parallel is also
recommended to further attenuate high-frequency
noise present in application boards.
VSS is the analog ground pin and the current return path
of the device. The user must connect the VSS pin to a
ground plane through a low-impedance connection. If
an analog ground path is available in the application
Printed Circuit Board (PCB), it is highly recommended
that the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
3.2 Chip Select (CS)
CS is the Chip Select input pin, which requires an
active-low to enable serial clock and data functions.
3.3 Serial Clock Input (SCK)
SCK is the SPI compatible serial clock input pin.
3.4 Serial Data Input (SDI)
SDI is the SPI compatible serial data input pin.
3.5 Latch DAC Input (LDAC)
LDAC (latch DAC synchronization input) pin is used to
transfer the input latch registers to their corresponding
DAC registers (output latches, VOUT). When this pin is
low, both VOUTA and VOUTB are updated at the same
time with their input register contents. This pin can be
tied to low (VSS) if the VOUT update is desired at the
rising edge of the CS pin. This pin can be driven by an
external control device such as an MCU I/O pin.
3.6 Analog Outputs (VOUTA, VOUTB)
VOUTA is the DAC A output pin, and VOUTB is the DAC
B output pin. Each output has its own output amplifier.
The full-scale range of the DAC output is from
VSS to G* VREF
, where G is the gain selection option
(1x or 2x). The DAC analog output cannot go higher
than the supply voltage (VDD).
TABLE 3-1: PIN FUNCTION TABLE FOR MCP4802/4812/4822
MCP4802/4812/4822
Symbol Description
MSOP, PDIP, SOIC
1V
DD Supply Voltage Input (2.7V to 5.5V)
2CSChip Select Input
3 SCK Serial Clock Input
4 SDI Serial Data Input
5LDAC
Synchronization Input. This pin is used to transfer DAC settings
(Input Registers) to the output registers (VOUT)
6V
OUTB DACB Output
7V
SS Ground reference point for all circuitry on the device
8V
OUTA DACA Output
MCP4802/4812/4822
DS22249A-page 16 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22249A-page 17
MCP4802/4812/4822
4.0 GENERAL OVERVIEW
The MCP4802, MCP4812 and MCP4822 are dual
voltage output 8-bit, 10-bit and 12-bit DAC devices,
respectively. These devices include rail-to-rail output
amplifiers, internal voltage reference, shutdown and
reset-management circuitry. The devices use an SPI
serial communication interface and operate with a sin-
gle supply voltage from 2.7V to 5.5V.
The DAC input coding of these devices is straight
binary. Equation 4-1 shows the DAC analog output
voltage calculation.
EQUATION 4-1: ANALOG OUTPUT
VOLTAGE (VOUT)
The ideal output range of each device is:
• MCP4802 (n = 8)
(a) 0.0V to 255/256 * 2.048V when gain setting = 1x.
(b) 0.0V to 255/256 * 4.096V when gain setting = 2x.
• MCP4812 (n = 10)
(a) 0.0V to 1023/1024 * 2.048V when gain setting = 1x.
(b) 0.0V to 1023/1024 * 4.096V when gain setting = 2x.
• MCP4822 (n = 12)
(a) 0.0V to 4095/4096 * 2.048V when gain setting = 1x.
(b) 0.0V to 4095/4096 * 4.096V when gain setting = 2x.
1 LSb is the ideal voltage difference between two
successive codes. Tab le 4 -1 illustrates the LSb
calculation of each device.
4.0.1 INL ACCURACY
Integral Non-Linearity (INL) error for these devices is
the maximum deviation between an actual code transi-
tion point and its corresponding ideal transition point
once offset and gain errors have been removed. The
two end points method (from 0x000 to 0xFFF) is used
for the calculation. Figure 4-1 shows the details.
A positive INL error represents transition(s) later than
ideal. A negative INL error represents transition(s)
earlier than ideal.
FIGURE 4-1: Example for INL Error.
Note:
See the output swing voltage specification in
Section 1.0 “Electrical Characteristics”
.
VOUT
2.048V Dn

2n
----------------------------------- G=
Where:
2.048V = Internal voltage reference
Dn= DAC input code
G = Gain selection
=2 for <GA
> bit = 0
=1 for <GA> bit = 1
n = DAC Resolution
=8 for MCP4802
= 10 for MCP4812
= 12 for MCP4822
TABLE 4-1: LSb OF EACH DEVICE
Device Gain
Selection LSb Size
MCP4802
(n = 8)
1x 2.048V/256 = 8 mV
2x 4.096V/256 = 16 mV
MCP4812
(n = 10)
1x 2.048V/1024 = 2 mV
2x 4.096V/1024 = 4 mV
MCP4822
(n = 12)
1x 2.048V/4096 = 0.5 mV
2x 4.096V/4096 = 1 mV
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
INL < 0
Ideal Transfer
Function
INL < 0
DAC Output
MCP4802/4812/4822
DS22249A-page 18 2010 Microchip Technology Inc.
4.0.2 DNL ACCURACY
A Differential Non-Linearity (DNL) error is the measure
of variations in code widths from the ideal code width.
A DNL error of zero indicates that every code is exactly
1 LSb wide.
FIGURE 4-2: Example for DNL Error.
4.0.3 OFFSET ERROR
An offset error is the deviation from zero voltage output
when the digital input code is zero.
4.0.4 GAIN ERROR
A gain error is the deviation from the ideal output,
VREF – 1 LSb, excluding the effects of offset error.
4.1 Circuit Descriptions
4.1.1 OUTPUT AMPLIFIERS
The DAC’s outputs are buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
offset voltage and low noise. The output stage enables
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for the analog output voltage range
and load conditions.
In addition to resistive load-driving capability, the
amplifier will also drive high capacitive loads without
oscillation. The amplifier’s strong outputs allow VOUT to
be used as a programmable voltage reference in a
system.
4.1.1.1 Programmable Gain Block
The rail-to-rail output amplifier has two configurable
gain options: a gain of 1x (<GA> = 1) or a gain of 2x
(<GA> = 0). The default value for this bit is a gain
of 2 (<GA> = 0). This results in an ideal full-scale
output of 0.000V to 4.096V due to the internal
reference (VREF = 2.048V).
4.1.2 VOLTAGE REFERENCE
The MCP4802/4812/4822 devices utilize internal
2.048V voltage reference. The voltage reference has a
low temperature coefficient and low noise
characteristics. Refer to Section 1.0 “Electrical Char-
acteristics” for the voltage reference specifications.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
Ideal Transfer
Function
Narrow Code, <1 LSb
DAC Output
Wide Code, >1 LSb
2010 Microchip Technology Inc. DS22249A-page 19
MCP4802/4812/4822
4.1.3 POWER-ON RESET CIRCUIT
The internal Power-on Reset (POR) circuit monitors the
power supply voltage (VDD) during the device
operation. The circuit also ensures that the DAC
powers up with high output impedance (<SHDN> = 0,
typically 500 k. The devices will continue to have a
high-impedance output until a valid write command is
received and the LDAC pin meets the input low
threshold.
If the power supply voltage is less than the POR
threshold (VPOR = 2.0V, typical), the DACs will be held
in their Reset state. The DACs will remain in that state
until VDD > VPOR and a subsequent write command is
received.
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the VDD pin, can
provide additional transient immunity.
FIGURE 4-3: Typical Transient Response.
4.1.4 SHUTDOWN MODE
The user can shut down each DAC channel selectively
using a software command (<SHDN> = 0). During
Shutdown mode, most of the internal circuits in the
channel that was shut down are turned off for power
savings. The internal reference is not affected by the
shutdown command. The serial interface also remains
active, thus allowing a write command to bring the
device out of the Shutdown mode. There will be no
analog output at the channel that was shut down and
the VOUT pin is internally switched to a known resistive
load (500 k typical. Figure 4-4 shows the analog
output stage during the Shutdown mode.
The device will remain in Shutdown mode until the
<SHDN> bit = 1 is latched into the device. When a
DAC channel is changed from Shutdown to Active
mode, the output settling time takes < 10 µs, but
greater than the standard active mode settling time
(4.5 µs).
FIGURE 4-4: Output Stage for Shutdown
Mode.
Transients above the curve
will cause a reset
Transients below the curve
will NOT cause a reset
5V
Time
Supply Voltages
Transient Duration
VPOR
VDD - VPOR
TA = +25°C
Transient Duration (µs)
10
8
6
4
2
012345
VDD - VPOR (V)
500 k
Power-Down
Control Circuit
Resistive
Load
VOUT
Op
Amp
Resistive String DAC
MCP4802/4812/4822
DS22249A-page 20 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22249A-page 21
MCP4802/4812/4822
5.0 SERIAL INTERFACE
5.1 Overview
The MCP4802/4812/4822 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, available on many microcontrollers, and
supports Mode 0,0 and Mode 1,1. Commands and data
are sent to the device via the SDI pin, with data being
clocked-in on the rising edge of SCK. The
communications are unidirectional and, thus, data
cannot be read out of the MCP4802/4812/4822
devices. The CS pin must be held low for the duration
of a write command. The write command consists of
16 bits and is used to configure the DAC’s control and
data latches. Register 5-1 to Register 5-3 detail the
input register that is used to configure and load the
DACA and DACB registers for each device. Figure 5-1
to Figure 5-3 show the write command for each device.
Refer to Figure 1-1 and SPI Timing Specifications
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
5.2 Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the selected DAC’s input registers.
The MCP4802/4812/4822 devices utilize a double-
buffered latch structure to allow both DACA’s and
DACB’s outputs to be synchronized with the LDAC pin,
if desired.
By bringing down the LDAC pin to a low state, the con-
tents stored in the DAC’s input registers are transferred
into the DAC’s output registers (VOUT), and both VOUTA
and VOUTB are updated at the same time.
All writes to the MCP4802/4812/4822 devices are
16-bit words. Any clocks after the first 16th clock will be
ignored. The Most Significant four bits are
Configuration bits. The remaining 12 bits are data bits.
No data can be transferred into the device with CS
high. The data transfer will only occur if 16 clocks have
been transferred into the device. If the rising edge of
CS occurs prior, shifting of data into the input registers
will be aborted.
MCP4802/4812/4822
DS22249A-page 22 2010 Microchip Technology Inc.
REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4822 (12-BIT DAC)
REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4812 (10-BIT DAC)
REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4802 (8-BIT DAC)
Where:
bit 15 A/B: DACA or DACB Selection bit
1 = Write to DACB
0 = Write to DACA
bit 14 — Don’t Care
bit 13 GA: Output Gain Selection bit
1 =1x (V
OUT = VREF * D/4096)
0 =2x (V
OUT = 2 * VREF * D/4096), where internal VREF = 2.048V.
bit 12 SHDN: Output Shutdown Control bit
1 = Active mode operation. VOUT is available.
0 = Shutdown the selected DAC channel. Analog output is not available at the channel that was shut down.
VOUT pin is connected to 500 ktypical)
bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored.
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
2010 Microchip Technology Inc. DS22249A-page 23
MCP4802/4812/4822
FIGURE 5-1: Write Command for MCP4822 (12-bit DAC).
FIGURE 5-2: Write Command for MCP4812 (10-bit DAC).
FIGURE 5-3: Write Command for MCP4802 (8-bit DAC).
SDI
SCK
CS
021
A/B —GA SHDN D11 D10
config bits 12 data bits
LDAC
3 4
D9
567
D8 D7 D6
8 9 10 12
D5 D4 D3 D2 D1 D0
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
SDI
SCK
CS
021
A/B —GA SHDN D9 D8
config bits 12 data bits
LDAC
3 4
D7
5 6 7
D6 D5 D4
8910 12
D3 D2 D1 D0 X X
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
Note: X = “don’t care” bits.
SDI
SCK
CS
021
A/B —GA SHDN
config bits 12 data bits
LDAC
3 4 567
X
D7 D6
8 9 10 12
D5 D4 D3 D2 D1 D0
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
XX
X
Note: X = “don’t care” bits.
MCP4802/4812/4822
DS22249A-page 24 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22249A-page 25
MCP4802/4812/4822
6.0 TYPICAL APPLICATIONS
The MCP4802/4812/4822 family of devices are
general purpose DACs for various applications where
a precision operation with low-power and internal
voltage reference is required.
Applications generally suited for the devices are:
• Set Point or Offset Trimming
• Sensor Calibration
• Precision Selectable Voltage Reference
• Portable Instrumentation (Battery-Powered)
• Calibration of Optical Communication Devices
6.1 Digital Interface
The MCP4802/4812/4822 devices utilize a 3-wire
synchronous serial protocol to transfer the DAC’s setup
and input codes from the digital devices. The serial
protocol can be interfaced to SPI or Microwire
peripherals that is common on many microcontroller
units (MCUs), including Microchip’s PIC® MCUs and
dsPIC® DSCs.
In addition to the three serial connections (CS, SCK
and SDI), the LDAC signal synchronizes the two DAC
outputs. By bringing down the LDAC pin to “low”, all
DAC input codes and settings in the two DAC input reg-
isters are latched into their DAC output registers at the
same time. Therefore, both DACA and DACB outputs
are updated at the same time. Figure 6-1 shows an
example of the pin connections. Note that the LDAC pin
can be tied low (VSS) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16 clock transmission has been received and the CS
pin has been raised.
6.2 Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter out the noise in the power supply
traces. The noise can be induced onto the power
supply's traces from various events such as digital
switching or as a result of changes on the DAC's
output. The bypass capacitor helps to minimize the
effect of these noise sources. Figure 6-1 illustrates an
appropriate bypass strategy. In this example, two
bypass capacitors are used in parallel: (a) 0.1 µF
(ceramic) and (b)10 µF (tantalum). These capacitors
should be placed as close to the device power pin
(VDD) as possible (within 4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS of the device should reside on the analog plane.
6.3 Output Noise Considerations
The voltage noise density (in µV/Hz) is illustrated in
Figure 2-13. This noise appears at VOUTX, and is
primarily a result of the internal reference voltage.
Its 1/f corner (fCORNER) is approximately 400 Hz.
Figure 2-14 illustrates the voltage noise (in mVRMS or
mVP-P). A small bypass capacitor on VOUTX is an
effective method to produce a single-pole Low-Pass
Filter (LPF) that will reduce this noise. For instance, a
bypass capacitor sized to produce a 1 kHz LPF would
result in an ENREF of about 100 µVRMS. This would be
necessary when trying to achieve the low DNL error
performance (at G = 1) that the MCP4802/4812/4822
devices are capable of. The tested range for stability is
.001µF through 4.7 µF.
FIGURE 6-1: Typical Connection
Diagram.
6.4 Layout Considerations
Inductively-coupled AC transients and digital switching
noises can degrade the output signal integrity, and
potentially reduce the device performance. Careful
board layout will minimize these effects and increase
the Signal-to-Noise Ratio (SNR). Bench testing has
shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs and
isolated outputs with proper decoupling, is critical for
the best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
VDD
VDD VDD
AVSS
AVSS VSS
VOUTA
VOUTB
PIC® Microcontroller
VOUTA
VOUTB
SDI
SDI
CS1
SDO
SCK
LDAC
CS0
1µF
1µF
MCP48x2
MCP48x2
C1 = 10 µF
C2 = 0.1 µF C1 C2 C2
C1
C1 C2
MCP4802/4812/4822
DS22249A-page 26 2010 Microchip Technology Inc.
6.5 Single-Supply Operation
The MCP4802/4812/4822 family of devices are rail-to-
rail voltage output DAC devices designed to operate
with a VDD range of 2.7V to 5.5V. Its output amplifier is
robust enough to drive small-signal loads directly.
Therefore, it does not require any external output buffer
for most applications.
6.5.1 DC SET POINT OR CALIBRATION
A common application for the devices is a digitally-
controlled set point and/or calibration of variable
parameters, such as sensor offset or slope. For
example, the MCP4822 provides 4096 output steps. If
G = 1 is selected, the internal 2.048V VREF would
produce 500 µV of resolution. If G = 2 is selected, the
internal 2.048 VREF would produce 1 mV of resolution.
6.5.1.1 Decreasing Output Step Size
If the application is calibrating the bias voltage of a
diode or transistor, a bias voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common methods to achieve a 0.8V range are to either
reduce VREF to 0.82V (using the MCP49XX family
device that uses external reference) or use a voltage
divider on the DAC’s output.
Using a VREF is an option if the VREF is available with
the desired output voltage range. However,
occasionally, when using a low-voltage VREF
, the noise
floor causes SNR error that is intolerable. Using a
voltage divider method is another option and provides
some advantages when VREF needs to be very low or
when the desired output voltage is not available. In this
case, a larger value VREF is used while two resistors
scale the output range down to the precise desired
level.
Example 6-1 illustrates this concept. Note that the
bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the environ-
ment.
EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION
VDD
SPI
3-wire
VTRIP
R1
R20.1 µF
Comparator
VOUT 2.048 G Dn
2N
------

=
VCC+
VCC–
VOUT
Vtrip VOUT
R2
R1R2
+
--------------------



=
VDD
RSENSE
DAC
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
MCP4822
G = Gain selection (1x or 2x)
Dn= Digital value of DAC (0-255) for MCP4801/MCP4802
= Digital value of DAC (0-1023) for MCP4811/MCP4812
= Digital value of DAC (0-4095) for MCP4821/MCP4822
N = DAC bit resolution
2010 Microchip Technology Inc. DS22249A-page 27
MCP4802/4812/4822
6.5.1.2 Building a “Window” DAC
When calibrating a set point or threshold of a sensor,
typically only a small portion of the DAC output range is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
If the threshold is not near VREF
, 2VREF or VSS, then
creating a “window” around the threshold has several
advantages. One simple method to create this
“window” is to use a voltage divider network with a pull-
up and pull-down resistor. Example 6-2 shows this
concept.
EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC
DAC
VDD
SPI
3-wire
VTRIP
R1
R20.1 µF
Comparator
R3
VCC-
VCC+ VCC+
VCC-
VOUT
R23
R2R3
R2R3
+
-------------------=
V23
VCC+R2
VCC-R3
+
R2R3
+
------------------------------------------------------=
Vtrip
VOUTR23 V23 R1
+
R1R23
+
---------------------------------------------=
R1
R23
V23
VOUT VO
Thevenin
Equivalent
RSENSE
VOUT 2.048 G Dn
2N
------

=
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
MCP4822
G = Gain selection (1x or 2x)
Dn= Digital value of DAC (0-255) for MCP4801/MCP4802
= Digital value of DAC (0-1023) for MCP4811/MCP4812
= Digital value of DAC (0-4095) for MCP4821/MCP4822
N = DAC bit resolution
MCP4802/4812/4822
DS22249A-page 28 2010 Microchip Technology Inc.
6.6 Bipolar Operation
Bipolar operation is achievable using the
MCP4802/4812/4822 family of devices by utilizing an
external operational amplifier (op amp). This
configuration is desirable due to the wide variety and
availability of op amps. This allows a general purpose
DAC, with its cost and availability advantages, to meet
almost any desired output voltage range, power and
noise performance.
Example 6-3 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC's output to a selected
offset. Note that R4 can be tied to VDD, instead of VSS,
if a higher offset is desired. Also note that a pull-up to
VDD could be used instead of R4, or in addition to R4, if
a higher offset is desired.
EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE
6.6.1 DESIGN EXAMPLE: DESIGN A
BIPOLAR DAC USING EXAMPLE 6-3
WITH 12-BIT MCP4822 OR
MCP4821
An output step magnitude of 1 mV, with an output range
of ±2.05V, is desired for a particular application.
Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V.
Step 2: Calculate the resolution needed:
4.1V/1 mV = 4100
Since 212 = 4096, 12-bit resolution is
desired.
Step 3:The amplifier gain (R2/R1), multiplied by full-
scale VOUT (4.096V), must be equal to the
desired minimum output to achieve bipolar
operation. Since any gain can be realized by
choosing resistor values (R1+R2), the VREF
value must be selected first. If a VREF of 4.096V
is used (G=2), solve for the amplifier’s gain by
setting the DAC to 0, knowing that the output
needs to be -2.05V.
The equation can be simplified to:
Step 4: Next, solve for R3 and R4 by setting the DAC to
4096, knowing that the output needs to be
+2.05V.
DAC
VDD
VDD
SPI
3-wire
VOUT R3
R4
R2
R1
VIN+
0.1 µF
VCC+
VCC–
VIN+
VOUTR4
R3R4
+
--------------------=
VO
VOVIN+ 1R2
R1
------+


VDD
R2
R1
------


–=
VOUT 2.048 G Dn
2N
------

=
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
MCP4822
G = Gain selection (1x or 2x)
Dn= Digital value of DAC (0-255) for MCP4801/MCP4802
= Digital value of DAC (0-1023) for MCP4811/MCP4812
= Digital value of DAC (0-4095) for MCP4821/MCP4822
N = DAC bit resolution
R2
–
R1
---------2.05–
4.096V
-----------------=
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
R2
R1
------1
2
---=
R4
R3R4
+
------------------------2.05V 0.5 4.096V
+
1.5 4.096V
------------------------------------------------------- 2
3
---==
If R4 = 20 k, then R3 = 10 k
2010 Microchip Technology Inc. DS22249A-page 29
MCP4802/4812/4822
6.7 Selectable Gain and
Offset Bipolar Voltage Output
Using a Dual Output DAC
In some applications, precision digital control of the
output range is desirable. Example 6-4 illustrates how
to use the MCP4802/4812/4822 family of devices to
achieve this in a bipolar or single-supply application.
This circuit is typically used for linearizing a sensor
whose slope and offset varies.
The equation to design a bipolar “window” DAC would
be utilized if R3, R4 and R5 are populated.
EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET
VDD
R3
R4
R2
VO
DACA
VDD
R1
(DACA for Gain Adjust)
(DACB for Offset Adjust)
SPI
3
R5
VCC+
Thevenin
Bipolar “Window” DAC using R4 and R5
0.1 µF
VCC–
VCC+
VCC–
VOUTA
VOUTB
VIN+
VOUTBR4VCC-R3
+
R3R4
+
-------------------------------------------------=
VOVIN+ 1R2
R1
------+


VOUTA
R2
R1
------


–=
Equivalent V45
VCC+R4VCC-R5
+
R4R5
+
---------------------------------------------=R
45
R4R5
R4R5
+
-------------------=
VIN+
VOUTBR45 V45R3
+
R3R45
+
------------------------------------------------=V
OVIN+ 1R2
R1
------+


VOUTA
R2
R1
------


–=
Offset Adjust Gain Adjust
Offset Adjust Gain Adjust
DACB
VOUTA 2.048 GA
Dn
2N
------

=
VOUTB 2.048 GB
Dn
2N
------

=
VIN+
Dual Output DAC:
MCP4802
MCP4812
MCP4822
G = Gain selection (1x or 2x)
N = DAC bit resolution
DA , DB= Digital value of DAC (0-255) for MCP4802
= Digital value of DAC (0-1023) for MCP4812
= Digital value of DAC (0-4095) for MCP4822
MCP4802/4812/4822
DS22249A-page 30 2010 Microchip Technology Inc.
6.8 Designing a Double-Precision
DAC Using a Dual DAC
Example 6-5 illustrates how to design a single-supply
voltage output capable of up to 24-bit resolution from a
dual 12-bit DAC (MCP4822). This design is simply a
voltage divider with a buffered output.
As an example, if an application similar to the one
developed in Section 6.6.1 “Design Example:
Design a Bipolar DAC Using Example 6-3 with 12-
bit MCP4822 or MCP4821” required a resolution of
1 µV instead of 1 mV, and a range of 0V to 4.1V, then
12-bit resolution would not be adequate.
Step 1: Calculate the resolution needed:
4.1V/1 µV = 4.1 x 106. Since 222 =4.2x10
6,
22-bit resolution is desired. Since
DNL = ±0.75 LSb, this design can be done
with the 12-bit MCP4822 DAC.
Step 2: Since DACB’s VOUTB has a resolution of 1 mV,
its output only needs to be “pulled” 1/1000 to
meet the 1 µV target. Dividing VOUTA by 1000
would allow the application to compensate for
DACB’s DNL error.
Step 3: If R2 is 100, then R1 needs to be 100 k.
Step 4: The resulting transfer function is shown in the
equation of Example 6-5.
EXAMPLE 6-5: SIMPLE, DOUBLE-PRECISION DAC WITH MCP4822
VDD
R2
VO
VDD
R1
(DACA for Fine Adjustment)
(DACB for Course Adjustment)
SPI
3-wire
R1 >> R2
VO
VOUTAR2VOUTBR1
+
R1R2
+
------------------------------------------------------=
0.1 µF
VCC+
VCC–
VOUTA
VOUTB
VOUTA 2.048 GA
DA
212
-------

=
VOUTB 2.048 GB
DB
212
-------

=
MCP4822
MCP4822
Gx= Gain selection (1x or 2x)
Dn= Digital value of DAC (0-4096)
2010 Microchip Technology Inc. DS22249A-page 31
MCP4802/4812/4822
6.9 Building Programmable Current
Source
Example 6-6 shows an example of building a
programmable current source using a voltage follower.
The current sensor (sensor resistor) is used to convert
the DAC voltage output into a digitally-selectable
current source.
Adding the resistor network from Example 6-2 would
be advantageous in this application. The smaller
RSENSE is, the less power dissipated across it.
However, this also reduces the resolution that the
current can be controlled with. The voltage divider, or
“window”, DAC configuration would allow the range to
be reduced, thus increasing resolution around the
range of interest. When working with very small sensor
voltages, plan on eliminating the amplifier’s offset error
by storing the DAC’s setting under known sensor
conditions.
EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE
DAC
RSENSE
Ib
Load
IL
VDD
SPI
3-wire
VCC+
VCC–
VOUT
IL
VOUT
Rsense
---------------
1+
-------------
=
Ib
IL
----=
Common-Emitter Current Gainwhere
VDD or VREF
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
MCP4822
G = Gain selection (1x or 2x)
Dn= Digital value of DAC (0-255) for MCP4801/MCP4802
= Digital value of DAC (0-1023) for MCP4811/MCP4812
= Digital value of DAC (0-4095) for MCP4821/MCP4822
N = DAC bit resolution
MCP4802/4812/4822
DS22249A-page 32 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22249A-page 33
MCP4802/4812/4822
7.0 DEVELOPMENT SUPPORT
7.1 Evaluation and Demonstration
Boards
The Mixed Signal PICtail™ Demo Board supports the
MCP4802/4812/4822 family of devices. Refer to
www.microchip.com for further information on this
product’s capabilities and availability.
MCP4802/4812/4822
DS22249A-page 34 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22249A-page 35
MCP4802/4812/4822
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP4802
E/P ^ 256
1009
MCP4812E
SN^^ 1009
256
8-Lead MSOP Example:
XXXXXX
YWWNNN 4822E
009256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
MCP4802/4812/4822
DS22249A-page 36 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS22249A-page 37
MCP4802/4812/4822
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP4802/4812/4822
DS22249A-page 38 2010 Microchip Technology Inc.
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b
e
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c
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2010 Microchip Technology Inc. DS22249A-page 39
MCP4802/4812/4822
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MCP4802/4812/4822
DS22249A-page 40 2010 Microchip Technology Inc.
/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@
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2010 Microchip Technology Inc. DS22249A-page 41
MCP4802/4812/4822
APPENDIX A: REVISION HISTORY
Revision A (April 2010)
• Original Release of this Document.
MCP4802/4812/4822
DS22249A-page 42 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22249A-page 43
MCP4802/4812/4822
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: MCP4802: Dual 8-Bit Voltage Output DAC
MCP4802T: Dual 8-Bit Voltage Output DAC
(Tape and Reel, MSOP and SOIC only)
MCP4812: Dual 10-Bit Voltage Output DAC
MCP4812T: Dual 10-Bit Voltage Output DAC
(Tape and Reel, MSOP and SOIC only)
MCP4822: Dual 12-Bit Voltage Output DAC
MCP4822T: Dual 12-Bit Voltage Output DAC
(Tape and Reel, MSOP and SOIC only)
Temperature
Range:
E= -40C to +125C (Extended)
Package: MS = 8-Lead Plastic Micro Small Outline (MSOP)
P = 8-Lead Plastic Dual In-Line (PDIP)
SN = 8-Lead Plastic Small Outline - Narrow, 150 mil
(SOIC)
Examples:
a) MCP4802-E/MS: Extended temperature,
MSOP package.
b) MCP4802T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
c) MCP4802-E/P: Extended temperature,
PDIP package.
d) MCP4802-E/SN: Extended temperature,
SOIC package.
e) MCP4802T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
a) MCP4812-E/MS: Extended temperature,
MSOP package.
b) MCP4812T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
c) MCP4812-E/P: Extended temperature,
PDIP package.
d) MCP4812-E/SN: Extended temperature,
SOIC package.
e) MCP4812T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
a) MCP4822-E/MS: Extended temperature,
MSOP package.
b) MCP4822T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
c) MCP4822-E/P: Extended temperature,
PDIP package.
d) MCP4822-E/SN: Extended temperature,
SOIC package.
e) MCP4822T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
MCP4802/4812/4822
DS22249A-page 44 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22249A-page 45
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-128-4
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22249A-page 46 2010 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
01/05/10