6175M–ATARM–26 - Oct-12
Features
•Incorporates the ARM7TDMI® ARM® Thu mb® Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
•Internal High-speed Flash
– 512 Kbytes (SAM7S512) Organized in Two Contiguous Banks of 1024 Pages of 256
Bytes (Dual Plane)
– 256 Kbytes (SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane)
– 128 Kbytes (SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane)
– 64 Kbytes (SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane)
– 32 Kbytes (SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane)
– 16 Kbytes (SAM7S161/16) Organized in 256 Pages of 64 Bytes (Single Plane)
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Loc k Capabi lities, Flash
Security Bit
– Fast Flash Programming Interface for High Volume Production
•Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 64 Kbytes (SAM7S512/256)
– 32 Kbytes (SAM7S128)
– 16 Kbytes (SAM7S64)
– 8 Kbytes (SAM7S321/32)
– 4 Kbytes (SAM7S161/16)
•Memory Controller (MC)
– Embedded Flash Con troller, Abort Status and Misalignment Detection
•Reset Controller (RSTC)
– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector
– Provides External Reset Signal Shaping and Reset Sour ce Status
•Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and on e PLL
•Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500
Hz) and Idle Mode
– Three Programmable External Clock Signals
•Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two (SAM7S512/256/128/64/321/161) or One (SAM7S32/16) External Interrupt Source(s)
and One Fast Interrupt Source, Spurious Interrupt Protected
AT91SAM
ARM-based Flash MCU
SAM7S512 SAM7S256 SAM7S128 SAM7S64
SAM7S321 SAM7S32 SAM7S161 SAM7S16
2
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
•Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention
– Mode for General Purpose 2-wire UART Serial Communication
•Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
•Windowed Watchdog (WDT)
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
•Real-time Timer (RTT)
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
•One Parallel Input/Output Controller (PIOA)
– Thirty-two (SAM7S512/256/128/64/321/161) or twenty-one (SAM7S32/16) Programmable I/O Lines Multiplexed with up to
Two P e rip heral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-u p resistor and Synchronous Output
•Eleven (SAM7S512/256/128/64/321/161) or Nine (SAM7S32/16) Peripheral DMA Controller (PDC) Channels
•One USB 2.0 Full Speed (12 Mbits per Second) Device Port (Except for the SAM7S32/16).
– On-chip Transceiver, 328-byte Configurable Integrated FIFOs
•One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Contin u ous Data Stream Capabilities with 32-bit Data Transfer
•Two (SAM7S512/256/128/64/321/161) or One (SAM7S32/16) Universal Synchronous/Asynchronous Receiver Transmitters
(USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demo dulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Line Support on USART1 (SAM7S512/256/128/64/321/161)
•One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
•One Three-channel 16-bit Timer/Counter (TC)
– Three External Cloc k Input an d Two Multi-purpose I/O Pins per Channel (SAM7S512/256/128/64/321/161)
– One External Clock Input and Two Multi-purpose I/O Pins for the first Two Channels Only (SAM7S32/16)
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
•One Four-channel 16-bit PWM Controller (PWMC)
•One Two-wire Interface (TWI)
– Master Mode Support Only, All Two-wire Atmel EEPROMs and I2C Compatible Devices Supported
(SAM7S512/256/128/64/321/32)
– Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs and I2C Compatible Devices Supported
(SAM7S161/16)
•One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
•SAM-BA™ Boot Assistant
– Default Boot program
– Interface with SAM-BA Graphic User Interface
•IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
•5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each (SAM7S161/16 I/Os Not 5V-tolerant)
•Power Supplies
– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components
– 3.3V or 1.8V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply
– 1.8V VDDCORE Core P ower Supply with Brown-out Detector
3
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
•Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions
•Available in 64-lead LQFP Green or 64-pad QFN Green Package (SAM7S512/256/128/64/321/161) and 48-lead LQFP Green or
48-pad QFN Green Package (SAM7S32/16)
1. Description
Atmel’s SAM7S is a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It fea-
tures a high-speed Flash and an SRAM, a large set of peripherals, including a USB 2.0 device (except for the
SAM7S32 and SAM7S16), and a complete set of system functions minimizing the number of external components.
The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and
extended memory.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface
on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from acci-
dental overwrite and preserves its confidentiality.
The SAM7S Series system controller includes a reset controller capable of managing the power-on sequence of
the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout
detector and a watchdog running off an integrated RC oscillator.
The SAM7S Series are general-purpose microcontrollers. Their integrated USB Device port makes them ideal devices
for peripheral applications requiring connectivity to a PC or cellular phone. Their aggressive price point and high level of
integration pushes their scope of use far into the cost-sensitive, high-volume consumer market.
1.1 Configuration Summary of the SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321,
SAM7S32, SAM7S161 and SAM7S16
The SAM7S512, SAM7S256, SAM7S128, SAM7S64, SAM7S321, SAM7S32, SAM7S161 and SAM7S16 differ in
memory size, peripheral set and package. Table 1-1 summarizes the configuration of the six devices.
Except for the SAM7S32/16, all other SAM7S devices are package and pinout compatible.
Notes: 1. Fractional Baud Rate.
2. Full modem line support on USART1.
3. Only two TC channels are accessible through the PIO.
Table 1-1. Configuration Summary
Device Flash TWI Flash
Organization SRAM
USB
Device
Port USART
External
Interrupt
Source PDC
Channels TC
Channels I/O 5V
Tolerant I/O
Lines Package
SAM7S512 512 Kbytes Master dual plane 64 Kbytes 1 2(1) (2) 2113Yes32
LQFP/
QFN 64
SAM7S256 256 Kbytes Master single plane 64 Kbytes 1 2(1) (2) 2113Yes32
LQFP/
QFN 64
SAM7S128 128 Kbytes Master single plane 32 Kbytes 1 2(1) (2) 2113Yes32
LQFP/
QFN 64
SAM7S64 64 Kbytes Master single plane 16 Kbytes 1 2(2) 2113Yes32
LQFP/
QFN 64
SAM7S321 32 Kbytes Master single plane 8 Kbytes 1 2(2) 2113Yes32
LQFP/
QFN 64
SAM7S32 32 Kbytes Master single plane 8 Kbytes not
present 11 9 3
(3) Yes 21 LQFP/
QFN 48
SAM7S161 16 Kbytes Master/
Slave single plane 4 Kbytes 1 2(2) 2 11 3 No 32 LQFP
SAM7S16 16 Kbytes Master/
Slave single plane 4 Kbytes not
present 11 9 3
(3) No 21 LQFP/
QFN 48
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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
2. Block Diagram
Figure 2-1. SAM7 S512/256/128/64/321/161 Block Diagram
TDI
TDO
TMS
TCK
NRST
FIQ
IRQ0-IRQ1
PCK0-PCK2
PMC
Peripheral Bridge
Peripheral Data
Controller
AIC
PLL
RCOSC
SRAM
64/32/16/8/4 Kbytes
ARM7TDMI
Processor
ICE
JTAG
SCAN
JTAGSEL
PIOA
USART0
SSC
Timer Counter
RXD0
TXD0
SCK0
RTS0
CTS0
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
Flash
512/256/
128/64/32/16 Kbytes
Reset
Controller
DRXD
DTXD
TF
TK
TD
RD
RK
RF
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Memory Controller
Abort
Status
Address
Decoder
Misalignment
Detection
PIO
PIO
APB
POR
Embedded
Flash
Controller
AD0
AD1
AD2
AD3
ADTRG
PLLRC
11 Channels
PDC
PDC
USART1
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
PDC
PDC
PDC
PDC
SPI
PDC
ADC
ADVREF
PDC
PDC
TC0
TC1
TC2
TWD
TWCK
TWI
OSC
XIN
XOUT
VDDIN
PWMC
PWM0
PWM1
PWM2
PWM3
1.8 V
Voltage
Regulator
USB Device
FIFO DDM
DDP
Transceiver
GND
VDDOUT
BOD
VDDCORE
VDDCORE
AD4
AD5
AD6
AD7
VDDFLASH
Fast Flash
Programming
Interface
ERASE
PIO
PGMD0-PGMD15
PGMNCMD
PGMEN0-PGMEN2
PGMRDY
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
VDDIO
TST
DBGU
PDC
PDC
PIO
PIT
WDT
RTT
System Controller
VDDCORE
SAM-BA
ROM
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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
Figure 2-2. SAM7S32/16 Block Diagram
ROM
TDI
TDO
TMS
TCK
NRST
FIQ
IRQ0
PCK0-PCK2
JTAGSEL
RXD0
TXD0
SCK0
RTS0
CTS0
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
DRXD
DTXD
TF
TK
TD
RD
RK
RF
TCLK0
TIOA0
TIOB0
TIOA1
TIOB1
AD0
AD1
AD2
AD3
ADTRG
PLLRC
9 Channels
ADVREF
TWD
TWCK
XIN
XOUT
VDDIN
PWM0
PWM1
PWM2
PWM3
GND
VDDOUT
VDDCORE
VDDCORE
AD4
AD5
AD6
AD7
VDDFLASH
ERASE
PGMD0-PGMD7
PGMNCMD
PGMEN0-PGMEN2
PGMRDY
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
VDDIO
TST
VDDCORE
SRAM
8/4 Kbytes
ARM7TDMI
Processor
Flash
32/16 Kbytes
APB
SAM-BA
PMC
Peripheral Bridge
Peripheral DMA
Controller
AIC
PLL
RCOSC
ICE
JTAG
SCAN
PIOA
USART0 SSC
Timer Counter
Reset
Controller
Memory Controller
Abort
Status
Address
Decoder
Misalignment
Detection
PIO
PIO
POR
Embedded
Flash
Controller
PDC
PDC
PDC
PDC
SPI
PDC
ADC
PDC
PDC
TC0
TC1
TC2
TWI
OSC
PWMC
1.8 V
Voltage
Regulator
BOD
Fast Flash
Programming
Interface
PIO
DBGU PDC
PDC
PIO
PIT
WDT
RTT
System Controller
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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
3. Signal Description
Table 3-1. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDIN Voltage and ADC Regulator Power Supply
Input Power 3.0 to 3.6V
VDDOUT Voltage Regulator Output Power 1.85V nominal
VDDFLASH Flash Power Supply Power 3.0V to 3.6V
VDDIO I/O Lines Power Supply Power 3.0V to 3.6V or 1.65V to 1.95V
VDDCORE Core Power Supply Power 1.65V to 1.95V
VDDPLL PLL Power 1.65V to 1.95V
GND Ground Ground
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
PLLRC PLL Filter Input
PCK0 - PCK2 Programmable Clock Output Output
ICE and JTAG
TCK Test Clock Input No pull-up resistor
TDI Test Data In Input No pull-up resistor
TDO Test Data Out Output
TMS Test Mode Select Input No pull-up resistor
JTAGSEL JTAG Selection Input Pull-down resistor(1)
Flash Memory
ERASE Flash and NVM Configuration Bits Erase
Command Input High Pull-down resistor(1)
Reset/Test
NRST Microcontroller Reset I/O Low Open-drain with pull-Up resistor
TST Test Mode Select Input High Pull-down resistor(1)
Debug Unit
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
AIC
IRQ0 - IRQ1 External Interrupt Inputs Input IRQ1 not present on SAM7S32/16
FIQ Fast Interrupt Input Input
PIO
PA0 - PA31 Parallel IO Controller A I/O Pulled-up input at reset
PA0 - PA20 only on SAM7S32/16
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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
USB Device Port
DDM USB Device Port Data - Analog not present on SAM7S32/16
DDP USB Device Port Data + Analog not present on SAM7S32/16
USART
SCK0 - SCK1 Serial Clock I/O SCK1 not present on SAM7S32/16
TXD0 - TXD1 Transmit Data I/O TXD1 not present on SAM7S32/16
RXD0 - RXD1 Receive Data Input RXD1 not present on SAM7S32/16
RTS0 - RTS1 Request To Send Output RTS1 not present on SAM7S32/16
CTS0 - CTS1 Clear To Send Input CTS1 not present on SAM7S32/16
DCD1 Data Carrier Detect Input not present on SAM7S32/16
DTR1 Data Terminal Ready Output not present on SAM7S32/16
DSR1 Data Set Ready Input not present on SAM7S32/16
RI1 Ring Indicator Input not present on SAM7S32/16
Synchronous Serial Controller
TD Transmit Data Output
RD Receive Data Input
TK Transmit Clock I/O
RK Receive Clock I/O
TF Transmit Frame Sync I/O
RF Receive Frame Sync I/O
Timer/Counter
TCLK0 - TCLK2 External Clock Inputs Input TCLK1 and TCLK2 not present on
SAM7S32/16
TIOA0 - TIOA2 I/O Line A I/O TIOA2 not present on SAM7S32/16
TIOB0 - TIOB2 I/O Line B I/O TIOB2 not present on SAM7S32/16
PWM Controller
PWM0 - PWM3 PWM Channels Output
SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
NPCS0 SPI Peripheral Chip Select 0 I/O Low
NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3 Output Low
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
8
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
Note: 1. Refer to Section 6. “I/O Lines Considerations” on page 14.
Two-Wire Interface
TWD Two-wire Serial Data I/O
TWCK Two-wire Serial Clock I/O
Analog-to-Digital Converter
AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset
AD4-AD7 Analog Inputs Analog Analog Inputs
ADTRG ADC Trigger Input
ADVREF ADC Reference Analog
Fast Flash Programming Interface
PGMEN0-PGMEN2 Programming Enabling Input
PGMM0-PGMM3 Programming Mode Input
PGMD0-PGMD15 Programming Data I/O PGMD0-PGMD7 only on SAM7S32/16
PGMRDY Programming Ready Output High
PGMNVALID Data Direction Output Low
PGMNOE Programming Read Input Low
PGMCK Programming Clock Input
PGMNCMD Programming Command Input Low
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
9
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
4. Package and Pinout
The SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package.
The SAM7S161 is available in a 64-Lead LQFP package.
The SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package.
4.1 64-lead LQFP and 64-pad QFN Package Outlines
Figure 4-1 and Figure 4-2 show the orientation of the 64-lead LQFP and the 64-pad QFN package. A detailed
mechanical description is given in the section Mechanical Characteristics of the full datasheet.
Figure 4-1. 64-lead LQFP Package (Top View)
Figure 4-2. 64-pad QFN Package (Top View)
116
17
32
3348
49
64
3348
161
49
64
32
17
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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
4.2 64-lead LQFP and 64-pad QFN Pinout
Note: 1. The bottom pad of the QFN package must be connected to ground.
Table 4-1. SAM7S512/256/128/64/321/161 Pinout(1)
1 ADVREF 17 GND 33 TDI 49 TDO
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS
4 AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK
6 AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE
8 VDDOUT 24 VDDCORE 40 TST 56 DDM
9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 DDP
10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA21/PGMD9 27 PA12/PGMD0 43 PA3 59 VDDFLASH
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT
14 PA22/PGMD10 30 PA9/PGMM1 46 GND 62 XIN/PGMCK
15 PA23/PGMD11 31 PA8/PGMM0 47 PA1/PGMEN1 63 PLLRC
16 PA20/PGMD8/AD3 32 PA7/PGMNVALID 48 PA0/PGMEN0 64 VDDPLL
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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
4.3 48-lead LQFP and 48-pad QFN Package Outlines
Figure 4-3 and Figure 4-4 show the orientation of the 48-lead LQFP and the 48-pad QFN package. A detailed
mechanical description is given in the section Mechanical Characteristics of the full datasheet.
Figure 4-3. 48-lead LQFP Package (Top View)
Figure 4-4. 48-pad QFN Package (Top View)
4.4 48-lead LQFP and 48-pad QFN Pinout
Note: 1. The bottom pad of the QFN package must be connected to ground.
112
13
24
2536
37
48
2536
121
37
48
24
13
Table 4-2. SAM7S32/16 Pinout(1)
1 ADVREF 13 VDDIO 25 TDI 37 TDO
2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL
3 AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS
4 AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK
5 AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE
6 AD7 18 VDDCORE 30 TST 42 ERASE
7 VDDIN 19 PA12/PGMD0 31 PA3 43 VDDFLASH
8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 GND
9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT
10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/PGMCK
11 PA19/PGMD7/AD2 23 PA8/PGMM0 35 PA1/PGMEN1 47 PLLRC
12 PA20/AD3 24 PA7/PGMNVALID 36 PA0/PGMEN0 48 VDDPLL
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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
5. Power Considerations
5.1 Power Supplies
The SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be
supplied with only one voltage. The six power supply pin types are:
zVDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
zVDDOUT pin. It is the output of the 1.8V voltage regulator.
zVDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V
to 3.6V, 3.3V nominal or from 1.65V to 1.95V, 1.8V nominal. Note that supplying less than 3.0V to VDDIO prevents
any use of the USB transceivers.
zVDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges
from 3.0V to 3.6V, 3.3V nominal.
zVDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be
connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its
embedded Flash, to operate correctly.
During startup, core supply voltage (VDDCORE) slope must be superior or equal to 6V/ms.
zVDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin.
No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be
connected as shortly as possible to the system ground plane.
In order to decrease current consumption, if the voltage regulator and the ADC are not used, VDDIN, ADVREF, AD4,
AD5, AD6 and AD7 should be connected to GND. In this case VDDOUT should be left unconnected.
5.2 Power Consumption
The SAM7S Series has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage
regulator and the power-on reset. When the brown-out detector is activated, 20 µA static current is added.
The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under
the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.
5.3 Voltage Regulator
The SAM7S Series embeds a voltage regulator that is managed by the System Controller.
In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current.
The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1
mA of output current.
Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to
achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between
VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected
between VDDOUT and GND.
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage
drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in
parallel: 100 nF NPO and 4.7 µF X7R.
5.4 Typical Powering Schematics
The SAM7S Series supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its
output feeds VDDCORE and the VDDPLL. Figure 5-1 shows the power schematics to be used for USB bus-powered
systems.
13
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
Figure 5-1. 3.3V System Single Power Supply Schematic
Power Source
ranges
from 4.5V (USB)
to 18V
3.3V
VDDIN
Voltage
Regulator
VDDOUT
VDDIO
DC/DC Converter
VDDCORE
VDDFLASH
VDDPLL
14
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
6. I/O Lines Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not
integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates
a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
6.2 Test Pin
The TST pin is used for manufacturing test, fast programming mode or SAM-BA Boot Recovery of the SAM7S Series
when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left
unconnected for normal operations.
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low.
To enter SAM-BA Boot Recovery, the TST pin and the PA0, PA1 and PA2 pins should be tied high for at least 10
seconds. Then a power cycle of the board is mandatory.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
6.3 Reset Pin
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be
driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller.
There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length.
This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to
reset all the components of the system.
The NRST pin integrates a permanent pull-up resistor to VDDIO.
6.4 ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down
resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
6.5 PIO Controller A Lines
zAll the I/O lines PA0 to PA31on SAM7S512/256/128/64/321 (PA0 to PA20 on SAM7S32) are 5V-tolerant and all
integrate a programmable pull-up resistor.
zAll the I/O lines PA0 to PA31 on SAM7S161 (PA0 to PA20 on SAM7S16) are not 5V-tolerant and all integrate a
programmable pull-up resistor.
Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.
5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven wit h a voltage of up to
5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled will
create a current path through the pull-up resistor from the I/O line to VDDIO. Care should be taken, in particular at reset,
as all the I/O lines default to input with the pull-up resistor enabled at reset.
6.6 I/O Line Drive Levels
The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently.
The remaining I/O lines can draw only 8 mA.
However, the total current drawn by all the I/O lines cannot exceed 150 mA (100 mA for SAM7S32/16).
15
SAM7S Series [DATASHEET]
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16
SAM7S Series [DATASHEET]
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7. Processor and Architecture
7.1 ARM7TDMI Processor
zRISC processor based on ARMv4T Von Neumann architecture
zRuns at up to 55 MHz, providing 0.9 MIPS/MHz
zTwo instruction sets
zARM® high-performance 32-bit instruction set
zThumb® high code density 16-bit instruction set
zThree-stage pipeline architecture
zInstruction Fetch (F)
zInstruction Decode (D)
zExecute (E)
7.2 Debug and Test Features
zIntegrated EmbeddedICE™ (embedded in-circuit emulator)
zTwo watchpoint units
zTest access port accessible through a JTAG protocol
zDebug communication channel
zDebug Unit
zTwo-pin UART
zDebug communication channel interrupt handling
zChip ID Register
zIEEE1149.1 JTAG Boundary-scan on all digital pins
7.3 Memory Controller
zBus Arbiter
zHandles requests from the ARM7TDMI and the Peripheral DMA Controller
zAddress decoder provides selection signals for
zThree internal 1 Mbyte memory areas
zOne 256 Mbyte embedded peripheral area
zAbort Status Registers
zSource, Type and all parameters of the access leading to an abort are saved
zFacilitates debug by detection of bad pointers
zMisalignment Detector
zAlignment checking of all data accesses
zAbort generation in case of misalignment
zRemap Command
zRemaps the SRAM in place of the embedded non-volatile memory
zAllows handling of dynamic exception vectors
zEmbedded Flash Controller
zEmbedded Flash interface, up to three programmable wait states
zPrefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states
zKey-protected program, erase and lock/unlock sequencer
zSingle command for erasing, programming and locking operations
zInterrupt generation in case of forbidden operation
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7.4 Peripheral DMA Controller
zHandles data transfer between peripherals and memories
zEleven channels: SAM7S512/256/128/64/321/161
zNine channels: SAM7S32/16
zTwo for each USART
zTwo for the Debug Unit
zTwo for the Serial Synchronous Controller
zTwo for the Serial Peripheral Interface
zOne for the Analog-to-digital Converter
zLow bus arbitration overhead
zOne Master Clock cycle needed for a transfer from memory to peripheral
zTwo Master Clock cycles needed for a transfer from peripheral to memory
zNext Pointer management for reducing interrupt latency requirements
zPeripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):
Receive DBGU
Receive USART0
Receive USART1
Receive SSC
Receive ADC
Receive SPI
Transmit DBGU
Transmit USART0
Transmit USART1
Transmit SSC
Transmit SPI
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8. Memories
8.1 SAM7S512
z512 Kbytes of Flash Memory, dual plane
z2 contiguous banks of 1024 pages of 256 bytes
zFast access time, 30 MHz single-cycle access in Worst Case conditions
zPage programming time: 6 ms, including page auto-erase
zPage programming without auto-erase: 3 ms
zFull chip erase time: 15 ms
z10,000 write cycles, 10-year data retention capability
z32 lock bits, protecting 32 sectors of 64 pages
zProtection Mode to secure contents of the Flash
z64 Kbytes of Fast SRAM
zSingle-cycle access at full speed
8.2 SAM7S256
z256 Kbytes of Flash Memory, single plane
z1024 pages of 256 bytes
zFast access time, 30 MHz single-cycle access in Worst Case conditions
zPage programming time: 6 ms, including page auto-erase
zPage programming without auto-erase: 3 ms
zFull chip erase time: 15 ms
z10,000 write cycles, 10-year data retention capability
z16 lock bits, protecting 16 sectors of 64 pages
zProtection Mode to secure contents of the Flash
z64 Kbytes of Fast SRAM
zSingle-cycle access at full speed
8.3 SAM7S128
z128 Kbytes of Flash Memory, single plane
z512 pages of 256 bytes
zFast access time, 30 MHz single-cycle access in Worst Case conditions
zPage programming time: 6 ms, including page auto-erase
zPage programming without auto-erase: 3 ms
zFull chip erase time: 15 ms
z10,000 write cycles, 10-year data retention capability
z8 lock bits, protecting 8 sectors of 64 pages
zProtection Mode to secure contents of the Flash
z32 Kbytes of Fast SRAM
zSingle-cycle access at full speed
8.4 SAM7S64
z64 Kbytes of Flash Memory, single plane
z512 pages of 128 bytes
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zFast access time, 30 MHz single-cycle access in Worst Case conditions
zPage programming time: 6 ms, including page auto-erase
zPage programming without auto-erase: 3 ms
zFull chip erase time: 15 ms
z10,000 write cycles, 10-year data retention capability
z16 lock bits, protecting 16 sectors of 32 pages
zProtection Mode to secure contents of the Flash
z16 Kbytes of Fast SRAM
zSingle-cycle access at full speed
8.5 SAM7S321/32
z32 Kbytes of Flash Memory, single plane
z256 pages of 128 bytes
zFast access time, 30 MHz single-cycle access in Worst Case conditions
zPage programming time: 6 ms, including page auto-erase
zPage programming without auto-erase: 3 ms
zFull chip erase time: 15 ms
z10,000 write cycles, 10-year data retention capability
z8 lock bits, protecting 8 sectors of 32 pages
zProtection Mode to secure contents of the Flash
z8 Kbytes of Fast SRAM
zSingle-cycle access at full speed
8.6 SAM7S161/16
z16 Kbytes of Flash Memory, single plane
z256 pages of 64 bytes
zFast access time, 30 MHz single-cycle access in Worst Case conditions
zPage programming time: 6 ms, including page auto-erase
zPage programming without auto-erase: 3 ms
zFull chip erase time: 15 ms
z10,000 write cycles, 10-year data retention capability
z8 lock bits, protecting 8 sectors of 32 pages
zProtection Mode to secure contents of the Flash
z4 Kbytes of Fast SRAM
zSingle-cycle access at full speed
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Figure 8-1. SAM7S512/256/128/64/321/32/161/16 Memory Mapping
0x1000 0000
0x0000 0000
0x0FFF FFFF
0xF000 0000
0xEFFF FFFF
0xFFFF FFFF
256M Bytes
256 MBytes
14 x 256 MBytes
3,584 MBytes
0x000F FFF
0x0010 0000
0x001F FFF
0x0020 0000
0x002F FFF
0x0030 0000
0x0000 0000
1 MBytes
1 MBytes
1 MBytes
253 MBytes
0xFFFA 0000
0xFFFA 3FFF
0xFFFA 4000
0xF000 0000
0xFFFB 8000
0xFFFC 0000
0xFFFC 3FFF
0xFFFC 4000
0xFFFC 7FFF
0xFFFD 4000
0xFFFD 7FFF
0xFFFD 3FFF
0xFFFD FFFF
0xFFFE 0000
0xFFFE 3FFF
0xFFFF EFFF
0xFFFE 4000
0xFFFF FFFF
0xFFFF F000
0xFFFB 4000
0xFFFB 7FFF
0xFFF9 FFFF
0xFFFC FFFF
0xFFFD 8000
0xFFFD BFFF
0xFFFC BFFF
0xFFFC C000
0xFFFB FFFF
0xFFFB C000
0xFFFB BFFF
0xFFFA FFFF
0xFFFB 0000
0xFFFB 3FFF
0xFFFD 0000
0xFFFD C000
0xFFFC 8000
16 Kbytes
(Reserved on
SAM7S32/16)
16 Kbytes
(Reserved on
SAM7S32/16)
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
0x0FFF FFFF
512 Bytes/
128 registers
512 Bytes/
128 registers
256 Bytes/
64 registers
16 Bytes/
4 registers
16 Bytes/
4 registers
16 Bytes/
4 registers
16 Bytes/
4 registers
256 Bytes/
64 registers
4 Bytes/
1 register
512 Bytes/
128 registers
0xFFFF F000
0xFFFF F200
0xFFFF F1FF
0xFFFF F3FF
0xFFFF FBFF
0xFFFF FCFF
0xFFFF FEFF
0xFFFF FFFF
0xFFFF F400
0xFFFF FC00
0xFFFF FD0F
0xFFFF FC2F
0xFFFF FC3F
0xFFFF FD4F
0xFFFF FC6F
0xFFFF F5FF
0xFFFF F600
0xFFFF FD00
0xFFFF FF00
0xFFFF FD20
0xFFFF FD30
0xFFFF FD40
0xFFFF FD60
0xFFFF FD70
Internal Memories
Undefined
(Abort)
(1) Can be Flash or SRAM
depending on REMAP.
Flash before Remap
SRAM after Remap
Internal Flash
Internal SRAM
Reserved
Address Memory Space
Internal Memory Mapping
Note:
TC0, TC1, TC2
USART0
USART1
PWMC
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TWI
SSC
SPI
UDP
ADC
AIC
DBGU
PIOA
Reserved
PMC
MC
WDT
PIT
RTT
RSTC
VREG
Peripheral Mapping
System Controller Mapping
Internal Peripherals
Reserved
SYSC
Reserved
(1)
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8.7 Memory Mapping
8.7.1 Internal SRAM
zThe SAM7S512 embeds a high-speed 64-Kbyte SRAM bank.
zThe SAM7S256 embeds a high-speed 64-Kbyte SRAM bank.
zThe SAM7S128 embeds a high-speed 32-Kbyte SRAM bank.
zThe SAM7S64 embeds a high-speed 16-Kbyte SRAM bank.
zThe SAM7S321 embeds a high-speed 8-Kbyte SRAM bank.
zThe SAM7S32 embeds a high-speed 8-Kbyte SRAM bank.
zThe SAM7S161 embeds a high-speed 4-Kbyte SRAM bank.
zThe SAM7S16 embeds a high-speed 4-Kbyte SRAM bank
After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After
Remap, the SRAM also becomes available at address 0x0.
8.7.2 Internal ROM
The SAM7S Series embeds an Internal ROM. The ROM contains the FFPI and the SAM-BA program.
The internal ROM is not mapped by default.
8.7.3 Internal Flash
zThe SAM7S512 features two contiguous banks (dual plane) of 256 Kbytes of Flash.
zThe SAM7S256 features one bank (single plane) of 256 Kbytes of Flash.
zThe SAM7S128 features one bank (single plane) of 128 Kbytes of Flash.
zThe SAM7S64 features one bank (single plane) of 64 Kbytes of Flash.
zThe SAM7S321/32 features one bank (single plane) of 32 Kbytes of Flash.
zThe SAM7S161/16 features one bank (single plane) of 16 Kbytes of Flash.
At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before
the Remap Command.
Figure 8-2. Internal Me mory Mapping
256 MBytes
Flash Before Remap
SRAM After Remap
Undefined Areas
(Abort)
0x000F FFFF
0x001F FFFF
0x002F FFFF
0x0FFF FFFF
1 MBytes
1 MBytes
1 MBytes
253 MBytes
Internal Flash
Internal SRAM
0x0000 0000
0x0010 0000
0x0020 0000
0x0030 0000
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SAM7S Series [DATASHEET]
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8.8 Embedded Flash
8.8.1 Flash Overview
zThe Flash of the SAM7S512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes
are organized in 32-bit words.
zThe Flash of the SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The 262,144 bytes are
organized in 32-bit words.
zThe Flash of the SAM7S128 is organized in 512 pages (single plane) of 256 bytes. The 131,072 bytes are
organized in 32-bit words.
zThe Flash of the SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The 65,536 bytes are organized
in 32-bit words.
zThe Flash of the SAM7S321/32 is organized in 256 pages (single plane) of 128 bytes. The 32,768 bytes are
organized in 32-bit words.
zThe Flash of the SAM7S161/16 is organized in 256 pages (single plane) of 64 bytes. The 16,384 bytes are
organized in 32-bit words.
zThe Flash of the SAM7S512/256/128 contains a 256-byte write buffer, accessible through a 32-bit interface.
zThe Flash of the SAM7S64/321/32/161/16 contains a 128-byte write buffer, accessible through a 32-bit interface.
The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code
corruption during power supply changes, even in the worst conditions.
When Flash is not used (read or write access), it is automatically placed into standby mode.
8.8.2 Embedded Flash Controller
The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading
the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB.
The User Interface allows:
zprogramming of the access parameters of the Flash (number of wait states, timings, etc.)
zstarting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc.
zgetting the end status of the last command
zgetting error status
zprogramming interrupts on the end of the last commands or on errors
The Embedded Flash Controller also provides a dual 32-bit prefetch buffer that optimizes 16-bit access to the Flash. This
is particularly efficient when the processor is running in Thumb mode.
Two EFCs are embedded in the SAM7S512 to control each bank of 256 Kbytes. Dual plane organization allows
concurrent Read and Program. Read from one memory plane may be performed even while program or erase functions
are being executed in the other memory plane.
One EFC is embedded in the SAM7S256/128/64/32/321/161/16 to control the single plane 256/128/64/32/16 Kbytes.
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SAM7S Series [DATASHEET]
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8.8.3 Lock Regions
8.8.3.1 SAM7S512
Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash
erasing or programming commands. The SAM7S512 contains 32 lock regions and each lock region contains 64 pages of
256 bytes. Each lock region has a size of 16 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR
register rises and the interrupt line rises if the LOCKE bit has been written at 1 in the MC_FMR register.
The 16 NVM bits (or 32 NVM bits) are software programmable through the corresponding EFC User Interface. The
command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.8.3.2 SAM7S256
The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash a gainst inadvertent flash erasing
or programming commands. The SAM7S256 contains 16 lock regions and each lock region contains 64 pages of 256
bytes. Each lock region has a size of 16 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR
register rises and the interrupt line rises if the LOCKE bit has been written at 1 in the MC_FMR register.
The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.8.3.3 SAM7S128
The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or
programming commands. The SAM7S128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes.
Each lock region has a size of 16 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR
register rises and the interrupt line rises if the LOCKE bit has been written at 1 in the MC_FMR register.
The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.8.3.4 SAM7S64
The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash a gainst inadvertent flash erasing
or programming commands. The SAM7S64 contains 16 lock regions and each lock region contains 32 pages of 128
bytes. Each lock region has a size of 4 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR
register rises and the interrupt line rises if the LOCKE bit has been written at 1 in the MC_FMR register.
The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.8.3.5 SAM7S321/32
The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or
programming commands. The SAM7S321/32 contains 8 lock regions and each lock region contains 32 pages of 128
bytes. Each lock region has a size of 4 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR
register rises and the interrupt line rises if the LOCKE bit has been written at 1 in the MC_FMR register.
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SAM7S Series [DATASHEET]
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The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.8.3.6 SAM7S161/16
The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or
programming commands. The SAM7S161/16 contains 8 lock regions and each lock region contains 32 pages of 64
bytes. Each lock region has a size of 2 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR
register rises and the interrupt line rises if the LOCKE bit has been written at 1 in the MC_FMR register.
The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
Table 8-1 summarizes the configuration of the eight devices.
8.8.4 Security Bit Feature
The SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the
Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the
confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the
security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the
security bit is deactivated, all accesses to the flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 50 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is
safer to connect it directly to GND for the final application.
8.8.5 Non-volatile Brownout Detector Control
Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a
power loss, the brownout detector operations remain in their state.
These two GPNVM bits can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and
“Set General-purpose NVM Bit” of the EFC User Interface.
GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it
disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.
The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1
enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset.
Asserting ERASE disables the brownout reset by default.
Table 8-1. Flash Configuration Summary
Device Number of Lock Bits Number of Pages in the Lock Region Page Size
SAM7S512 32 64 256 bytes
SAM7S256 16 64 256 bytes
SAM7S128 8 64 256 bytes
SAM7S64 16 32 128 bytes
SAM7S321/32 8 32 128 bytes
SAM7S161/16 8 32 64 bytes
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SAM7S Series [DATASHEET]
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8.8.6 Calibration Bits
Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured
and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
8.9 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through
a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
The Fast Flash Programming Interface is enabled and the Fa st Programming Mode is entered when the TST pin and the
PA0 and PA1 pins are all tied high and PA2 is tied low.
8.10 SAM-BA Boot Assistant
The SAM-BA® Boot Recovery r est or es th e SAM - BA Boo t in th e fir st t wo s ec tor s o f th e o n -ch ip Flash me m or y. T h e
SAM-BA Boot recover y is performe d when the TST pin an d the PA0, PA1 and PA2 pins ar e all ti ed high f or 10 sec-
onds. Then, a power cycle of the board is mandatory.
The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash
memory.
The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. (The
SAM7S32/16 have no USB Device Port.)
zCommunication through the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-
detection.
zCommunication through the USB Device Port is limited to an 18.432 MHz crystal. (
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
9. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.
The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF
F000 and 0xFFFF FFFF.
Figure 9-1 on page 26 and Figure 9-2 on page 27 show the product specific System Controller Block Diagrams.
Figure 8-1 on page 20 shows the mapping of the of the User Interface of the System Controller peripherals. Note that the
memory controller configuration user interface is also mapped within this address space.
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SAM7S Series [DATASHEET]
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Figure 9- 1. System Controller Block Diagram (SAM7S512/256/128/64/321/161)
NRST
SLCK
Advanced
Interrupt
Controller
Real-Time
Timer
Periodic
Interval
Timer
Reset
Controller
PA0-PA31
periph_nreset
System Controller
Watchdog
Timer
wdt_fault
WDRPROC
PIO
Controller
POR
BOD
RCOSC
gpnvm[0]
cal
en
Power
Management
Controller
OSC
PLL
XIN
XOUT
PLLRC
MAINCK
PLLCK
pit_irq
MCK
proc_nreset
wdt_irq
periph_irq{2]periph_nreset
periph_clk[2..14]
PCK
MCK
pmc_irq
UDPCK
nirq
nfiq
rtt_irq
Embedded
Peripherals
periph_clk[2]
pck[0-2]
in
out
enable
ARM7TDMI
SLCK
SLCK
irq0-irq1
fiq
irq0-irq1
fiq
periph_irq[4..14]
periph_irq[2..14]
int
int
periph_nreset
periph_clk[4..14]
Embedded
Flash
flash_poe
jtag_nreset
flash_poe
gpnvm[0..1]
flash_wrdis
flash_wrdis
proc_nreset
periph_nreset
dbgu_txd
dbgu_rxd
pit_irq
rtt_irq
dbgu_irq
pmc_irq
rstc_irq
wdt_irq
rstc_irq
SLCK
gpnvm[1]
Boundary Scan
TAP Controller
jtag_nreset
debug
PCK
debug
idle
debug
Memory
Controller
MCK
proc_nreset
bod_rst_en
proc_nreset
idle
Debug
Unit
dbgu_irq
MCK
dbgu_rxd
periph_nreset force_ntrst
dbgu_txd
USB Device
Port
UDPCK
periph_nreset
periph_clk[11]
periph_irq[11]
usb_suspend
usb_suspend
Voltage
Regulator
standby
Voltage
Regulator
Mode
Controller
security_bit
cal
power_on_reset
force_ntrst
cal
power_on_reset
power_on_reset
power_on_reset
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Figure 9- 2. System Controller Blo c k Diagram (SA M7S32/16)
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9.1 Reset Controller
The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset,
indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. In addition,
it controls the internal resets and the NRST pin open-drain output. It allows to shape a signal on the NRST line,
guaranteeing that the length of the pulse meets any requirement.
Note that if NRST is used as a reset output signal for external devices during power-off, the brownout detector must be
activated.
9.1.1 Brownout Detector and Power-on Reset
The SAM7S Series embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor
VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down
sequences or if brownouts occur on the VDDCORE power supply.
The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until
VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the
device.
The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It secures
system operations in the most difficult environments and prevents code corruption in case of brownout on the
VDDCORE.
Only VDDCORE is monitored.
When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot-, defined as
Vbot - hyst/2), the brownout output is immediately activated.
When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2), the reset is released. The
brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than
about 1µs.
The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the
brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated.
The brownout detector is low-power, as it consumes less than 20 µA static current. However, it can be deactivated to
save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of
the Flash.
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9.2 Clock Generator
The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following
characteristics:
zRC Oscillator ranges between 22 kHz and 42 kHz
zMain Oscillator frequency ranges between 3 and 20 MHz
zMain Oscillator can be bypassed
zPLL output ranges between 80 and 220 MHz
It provides SLCK, MAINCK and PLLCK.
Figure 9-3. Clock Generator Bloc k Diagram
9.3 Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide:
zthe Processor Clock PCK
zthe Master Clock MCK
zthe USB Clock UDPCK (not present on SAM7S32/16)
zall the peripheral clocks, independently controllable
zthree programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption
while waiting for an interrupt.
Embedded
RC
Oscillator
Main
Oscillator
PLL and
Divider
Clock Generator
Power
Management
Controller
XIN
XOUT
PLLRC
Slow Clock
SLCK
Main Clock
MAINCK
PLL Clock
PLLCK
Control
Status
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Figure 9-4. Power Ma na ge me nt Co ntroller Block Diagram
9.4 Advanced Interrupt Controller
zControls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
zIndividually maskable and vectored interrupt sources
zSource 0 is reserved for the Fast Interrupt Input (FIQ)
zSource 1 is reserved for system peripherals RTT, PIT, EFC, PMC, DBGU, etc.)
zOther sources control the peripheral interrupts or external interrupts
zProgrammable edge-triggered or level-sensitive internal sources
zProgrammable positive/negative edge-triggered or high/low level-sensitive external sources
z8-level Priority Controller
zDrives the normal interrupt of the processor
zHandles priority of the interrupt sources
zHigher priority interrupts can be served during service of lower priority interrupt
zVectoring
zOptimizes interrupt service routine branch and execution
zOne 32-bit vector register per interrupt source
zInterrupt vector register reads the corresponding current interrupt vector
zProtect Mode
zEasy debugging by preventing automatic operations
zFast Forcing
zPermits redirecting any interrupt source on the fast interrupt
zGeneral Interrupt Mask
zProvides processor synchronization on events without triggering an interrupt
MCK
periph_clk[2..14]
int
UDPCK
usb_suspend
SLCK
MAINCK
PLLCK Prescaler
/1,/2,/4,...,/64
PCK
Processor
Clock
Controller
Idle Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
USB Clock Controller
ON/OFF
SLCK
MAINCK
PLLCK Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
PLLCK Divider
/1,/2,/4
pck[0..2]
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9.5 Debug Unit
zComprises:
zOne two-pin UART
zOne Interface for the Debug Communication Channel (DCC) support
zOne set of Chip ID Registers
zOne Interface providing ICE Access Prevention
zTwo-pin UART
zImplemented features are compatible with the USART
zProgrammable Baud Rate Generator
zParity, Framing and Overrun Error
zAutomatic Echo, Local Loopback and Remote Loopback Channel Modes
zDebug Communication Channel Support
zOffers visibility of COMMRX and COMMTX signals from the ARM Processor
zChip ID Registers
zIdentification of the device revision, sizes of the embedded memories, set of peripherals
zChip ID is 0x270B0A40 for AT91SAM7S512 Rev A
zChip ID is 0x270B0A4F for AT91SAM7S512 Rev B
zChip ID is 0x270D0940 for AT91SAM7S256 Rev A
zChip ID is 0x270B0941 for AT91SAM7S256 Rev B
zChip ID is 0x270B0942 for AT91SAM7S256 Rev C
zChip ID is 0x270B0943 for AT91SAM7S256 Rev D
zChip ID is 0x270C0740 for AT91SAM7S128 Rev A
zChip ID is 0x270A0741 for AT91SAM7S128 Rev B
zChip ID is 0x270A0742 for AT91SAM7S128 Rev C
zChip ID is 0x270A0743 for AT91SAM7S128 Rev D
zChip ID is 0x27090540 for AT91SAM7S64 Rev A
zChip ID is 0x27090543 for AT91SAM7S64 Rev B
zChip ID is 0x27090544 for AT91SAM7S64 Rev C
zChip ID is 0x27080342 for AT91SAM7S321 Rev A
zChip ID is 0x27080340 for AT91SAM7S32 Rev A
zChip ID is 0x27080341 for AT91SAM7S32 Rev B
zChip ID is 0x27050241 for AT9SAM7S161 Rev A
zChip ID is 0x27050240 for AT91SAM7S16 Rev A
Note: Refer to the errata section of the datasheet for updates on chip ID.
9.6 Periodic Interval Timer
z20-bit programmable counter plus 12-bit interval counter
9.7 Watchdog Timer
z12-bit key-protected Programmable Counter running on prescaled SCLK
zProvides reset or interrupt signals to the system
zCounter may be stopped while the processor is in debug state or in idle mode
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9.8 Real-time Ti mer
z32-bit free-running counter with alarm running on prescaled SCLK
zProgrammable 16-bit prescaler for SLCK accuracy compensation
9.9 PIO Controller
zOne PIO Controller, controlling 32 I/O lines (21 for SAM7S32/16)
zFully programmable through set/clear registers
zMultiplexing of two peripheral functions per I/O line
zFor each I/O line (whether assigned to a peripheral or used as general-purpose I/O)
zInput change interrupt
zHalf a clock period glitch filter
zMulti-drive option enables driving in open drain
zProgrammable pull-up on each I/O line
zPin data status register, supplies visibility of the level on the pin at any time
zSynchronous output, provides Set and Clear of several I/O lines in a single write
9.10 Voltage Regulator Controller
The aim of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or
Standby Mode (bit 0 is set).
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10. Peripherals
10.1 User Interface
The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each
peripheral is allocated 16 Kbytes of address space.
A complete memory map is provided in Figure 8-1 on page 20.
10.2 Peripheral Identifiers
The SAM7S Series embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the
SAM7S512/256/128/64/321/161. Table 10-2 defines the Peripheral Identifiers of the SAM7S32/16. A peripheral identifier
is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the
peripheral clock with the Power Management Controller.
Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller
is continuously clocked. The ADC clock is automatically started for the first conversion. In Sleep Mode the
ADC clock is automatically stopped after each conversion.
Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller
is continuously clocked. The ADC clock is automatically started for the first conversion. In Sleep Mode the
ADC clock is automatically stopped after each conversion.
Table 10-1. Peripheral Identifiers (SAM7S512/256/128/64/321/161)
Peripheral
ID Peripheral
Mnemonic Peripheral
Name External
Interrupt
0 AIC Advanced Interrupt Controller FIQ
1 SYSC(1) System
2 PIOA Parallel I/O Controller A
3 Reserved
4 ADC(1) Analog-to Digital Converter
5 SPI Serial Peripheral Interface
6 US0 USART 0
7 US1 USART 1
8 SSC Synchronous Serial Controller
9 TWI Two-wire Interface
10 PWMC PWM Controller
11 UDP USB Device Port
12 TC0 Timer/Counter 0
13 TC1 Timer/Counter 1
14 TC2 Timer/Counter 2
15 - 29 Reserved
30 AIC Advanced Interrupt Controller IRQ0
31 AIC Advanced Interrupt Controller IRQ1
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10.3 Peripheral Multiplexing on PIO Lines
The SAM7S Series features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set.
PIO Controller A controls 32 lines (21 lines for SAM7S32/16). Each line can be assigned to one of two peripheral
functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller.
Table 10-3, “Multiplexing on PIO Controller A (SAM7S512/256/128/64/321/161),” on page 35 and Table 10-4,
“Multiplexing on PIO Controller A (SAM7S32/16),” on page 36 define how the I/O lines of the peripherals A, B or the
analog inputs are multiplexed on the PIO Controller A. The two columns “Function” and “Comments” have been inserted
for the user’s own comments; they may be used to track how pins are defined in an application.
Note that some peripheral functions that are output only may be duplicated in the table.
All pins reset in their Parallel I/O lines function are configured as input with the programmable pull-up enabled, so that the
device is maintained in a static state as soon as a reset is detected.
Table 10-2. Peripheral Identifiers (SAM7S32/16)
Peripheral
ID Peripheral
Mnemonic Peripheral
Name External
Interrupt
0 AIC Advanced Interrupt Controller FIQ
1 SYSC(1) System
2 PIOA Parallel I/O Controller A
3 Reserved
4 ADC(1) Analog-to Digital Converter
5 SPI Serial Peripheral Interface
6 US USART
7 Reserved
8 SSC Synchronous Serial Controller
9 TWI Two-wire Interface
10 PWMC PWM Controller
11 Reserved
12 TC0 Timer/Counter 0
13 TC1 Timer/Counter 1
14 TC2 Timer/Counter 2
15 - 29 Reserved
30 AIC Advanced Interrupt Controller IRQ0
31 Reserved
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10.4 PIO Controller A Multiplexing
Table 10-3. Multiplexing on PIO Controller A (SAM7S512/256/128/64/321/161)
PIO Controller A Application Usage
I/O Line Peripheral A Peripheral B Comments Function Comments
PA0 PWM0 TIOA0 High-Drive
PA1 PWM1 TIOB0 High-Drive
PA2 PWM2 SCK0 High-Drive
PA3 TWD NPCS3 High-Drive
PA4 TWCK TCLK0
PA5 RXD0 NPCS3
PA6 TXD0 PCK0
PA7 RTS0 PWM3
PA8 CTS0 ADTRG
PA9 DRXD NPCS1
PA10 DTXD NPCS2
PA11 NPCS0 PWM0
PA12 MISO PWM1
PA13 MOSI PWM2
PA14 SPCK PWM3
PA15 TF TIOA1
PA16 TK TIOB1
PA17 TD PCK1 AD0
PA18 RD PCK2 AD1
PA19 RK FIQ AD2
PA20 RF IRQ0 AD3
PA21 RXD1 PCK1
PA22 TXD1 NPCS3
PA23 SCK1 PWM0
PA24 RTS1 PWM1
PA25 CTS1 PWM2
PA26 DCD1 TIOA2
PA27 DTR1 TIOB2
PA28 DSR1 TCLK1
PA29 RI1 TCLK2
PA30 IRQ1 NPCS2
PA31 NPCS1 PCK2
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Table 10-4. Multiplexing on PIO Controller A (SAM7S32/16)
PIO Controller A Application Usage
I/O Line Peripheral A Peripheral B Comments Function Comments
PA0 PWM0 TIOA0 High-Drive
PA1 PWM1 TIOB0 High-Drive
PA2 PWM2 SCK0 High-Drive
PA3 TWD NPCS3 High-Drive
PA4 TWCK TCLK0
PA5 RXD0 NPCS3
PA6 TXD0 PCK0
PA7 RTS0 PWM3
PA8 CTS0 ADTRG
PA9 DRXD NPCS1
PA10 DTXD NPCS2
PA11 NPCS0 PWM0
PA12 MISO PWM1
PA13 MOSI PWM2
PA14 SPCK PWM3
PA15 TF TIOA1
PA16 TK TIOB1
PA17 TD PCK1 AD0
PA18 RD PCK2 AD1
PA19 RK FIQ AD2
PA20 RF IRQ0 AD3
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10.5 Serial Peripheral Interface
Supports communication with external serial devices
Four chip selects with external decoder allow communication with up to 15 peripherals
Serial memories, such as DataFlash® and 3-wire EEPROMs
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
External co-processors
Master or slave serial peripheral bus interface
8- to 16-bit programmable data length per chip select
Programmable phase and polarity per chip select
Programmable transfer delays between consecutive transfers and between clock and data per chip select
Programmable delay between consecutive transfers
Selectable mode fault detection
Maximum frequency at up to Master Clock
10.6 Two-wire Interface
Master Mode only (SAM7S512/256/128/64/321/32)
Master, Multi-Master and Slave Mode support (SAM7S161/16)
General Call supported in Slave Mode (SAM7S161/16)
Compatibility with I2C compatible devices (refer to the TWI sections of the datasheet)
One, two or three bytes internal address registers for easy Serial Memory access
7-bit or 10-bit slave addressing
Sequential read/write operations
10.7 USART
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
1, 1.5 or 2 stop bits in Asynchronous Mode
1 or 2 stop bits in Synchronous Mode
Parity generation and error detection
Framing error detection, overrun error detection
MSB or LSB first
Optional break generation and detection
By 8 or by 16 over-sampling receiver frequency
Hardware handshaking RTS - CTS
Modem Signals Management DTR-DSR-DCD-RI on USART1 (not present on SAM7S32/16)
Receiver time-out and transmitter timeguard
Multi-drop Mode with address generation and detection
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
NACK handling, error counter with repetition and iteration limit
IrDA modulation and demodulation
Communication at up to 115.2 Kbps
Test Modes
Remote Loopback, Local Loopback, Automatic Echo
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10.8 Serial Synchronous Controller
Provides serial synchronous communication links used in audio and telecom applications
Contains an independent receiver and transmitter and a common clock divider
Offers a configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame
sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
10.9 Timer Counter
Three 16-bit Timer Counter Channels
Two output compare or one input capture per channel (except for SAM7S32/16 which have only two
channels connected to the PIO)
Wide range of functions including:
Frequency measurement
Event counting
Interval measurement
Pulse generation
Delay timing
Pulse Width Modulation
Up/down capabilities
Each channel is user-configurable and contains:
Three external clock inputs (The SAM7S32/16 have one)
Five internal clock inputs, as defined in Table 10-5
Two multi-purpose input/output signals
Two global registers that act on all three TC channels
10.10 PWM Controller
Four channels, one 16-bit counter per channel
Common clock generator, providing thirteen different clocks
One Modulo n counter providing eleven clocks
Two independent linear dividers working on modulo n counter outputs
Independent channel programming
Independent enable/disable commands
Independent clock selection
Independent period and duty cycle, with double buffering
Programmable selection of the output waveform polarity
Table 10-5. Timer Counter Clocks Assignment
TC Clock Input Clock
TIMER_CLOCK1 MCK/2
TIMER_CLOCK2 MCK/8
TIMER_CLOCK3 MCK/32
TIMER_CLOCK4 MCK/128
TIMER_CLOCK5 MCK/1024
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Programmable center or left aligned output waveform
10.11 USB Device Port (Does not pertain to SAM7S32/16)
USB V2.0 full-speed compliant, 12 Mbits per second.
Embedded USB V2.0 full-speed transceiver
Embedded 328-byte dual-port RAM for endpoints
Four endpoints
Endpoint 0: 8 bytes
Endpoint 1 and 2: 64 bytes ping-pong
Endpoint 3: 64 bytes
Ping-pong Mode (two memory banks) for isochronous and bulk endpoints
Suspend/resume logic
10.12 Analog-to-digital Converter
8-channel ADC
10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register ADC
±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity
Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
External voltage reference for better accuracy on low voltage inputs
Individual enable and disable of each channel
Multiple trigger source
Hardware or software trigger
External trigger pin
Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
Sleep Mode and conversion sequencer
Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels
Four of eight analog inputs shared with digital signals
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11. A RM7TDMI Processor Over view
11.1 Overview
The ARM7TDMI core executes both the 32 -bit ARM® and 16-bit Thumb® instruction sets, allowing the user to trade
off between high perform ance and high code d ensity.The ARM7TDMI processor implem ents Von Neuman archi-
tecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages.
The main features of t he ARM7TDMI processor are:
• ARM7TDMI Based on ARMv4T Architecture
• Two Instruction Sets
–ARM
® High-performa nc e 32 -b it In struction Set
–Thumb
® High Code Density 16-bit Instruction Set
• Three-Stage Pipeline Architecture
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
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11.2 ARM7TDMI Processor
For further details on ARM7TDMI, refer to the following ARM documents:
ARM Architecture Reference Manual (DDI 0100E)
ARM7TDMI Technical Reference Manual (DDI 0210B)
11.2.1 Instruction Type
Instructions are eithe r 32 bits long (in ARM state) or 16 bi ts long (in THUMB state).
11.2.2 Data Type
ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-
byte boundaries and half words to two-byte boundaries.
Unaligned data access beh avior depends on which instruction is used where.
11.2.3 ARM7TDMI Operating Mode
The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:
User: The normal ARM program execution state
FIQ: Designed to support high-speed data transfer or channel process
IRQ: Used for general-purpose interrupt handling
Supervisor: Protected mode for the operating system
Abort mode: Implements virtual memory and/or memory protection
System: A privileged user mode for the operating system
Undefined: Supports software emulation of hardware coprocessors
Mode changes may be made under software control, or may be brought about by external interrupts or exception
processing. Mo st application progra ms execute in User mo de. The non-user mod es, or privileged modes, ar e
entered in order to service interrupts or exceptions, or to access protecte d resources.
11.2.4 ARM7TDMI Registers
The ARM7TDMI proc essor has a total of 37registers:
• 31 general-purpose 32-bit registers
• 6 status registers
These registers are not accessible at the same time. The processor state and operating mode determine which
registers are available to the programmer.
At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception
processing.
Register 15 is the Prog ram Counter (PC) and can be used in all instructions to re ference data relative t o the current
instruction.
R14 holds the return add ress after a subrout ine call.
R13 is used (by software convention) as a stack pointer.
Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-bit physical regis-
ter in all proc es so r m od e s. T h ey ar e ge ne r al- pu rp o se re gisters, with no sp e cia l uses managed b y th e ar ch ite ctu re ,
and can be used wherever an inst ruction allows a general-purpose register to be specified.
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Registers R8 to R14 are banked registers. This means that each of them depend s on the current mode of the
processor.
11.2.4.1 Modes and Exception Handling
All exceptions have banked re gisters for R14 and R13.
After an exception, R14 holds the return address for exception processing. This address is used to return after the
exception is processed, as well as to address the instruction tha t caused the exception.
R13 is banked across exception modes to provide each exception handler with a private stack poin ter.
The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save
these registe rs.
A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers.
System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of
exceptions.
11.2.4.2 Status Registers
All other processor st ate s are held in status reg ister s. Th e current ope ratin g pr ocessor sta tu s is in the Current Pro-
gram Status Register (CPSR). The CPSR holds:
• four ALU flags (Negative, Zero, Carry, and Overflow)
Table 11-1. ARM7TDMI ARM Modes and Registers Layout
User and
System Mode Supervisor
Mode Abort Mode Undefined
Mode Interrupt
Mode Fast Interrupt
Mode
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7
R8 R8 R8 R8 R8 R8_FIQ
R9 R9 R9 R9 R9 R9_FIQ
R10 R10 R10 R10 R10 R10_FIQ
R11 R11 R11 R11 R11 R11_FIQ
R12 R12 R12 R12 R12 R12_FIQ
R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ
R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ
PC PC PC PC PC PC
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ
Mode-specific banked registers
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• two interrupt disable bits (one for each type of interrupt)
• one bit to indicate ARM or Thumb execution
• five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task
immediately pr ec ed in g the exception.
11.2.4.3 Exception Types
The ARM7TDMI supports five types of exception and a privileged processing mode for each type. The types of
exceptions ar e:
• fast interrupt (FIQ)
• normal interrupt (IRQ)
• memory aborts (used to implement memory protection or virtual memory)
• attempted execution of an undefined instruction
• software interrupts (SWIs)
Exceptions are gene rated by internal and exte rnal sources.
More than one exception can occur in the same time.
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save
state.
To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be
done in two ways:
• b y using a data-proce ssing instruction with the S-bit set, and the PC as the destination
• by using the Load Multiple with Restore CPSR instruction (LDM)
11.2.5 ARM Instruction Set Overview
The ARM instruction set is divided into:
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]).
Table 11-2 gives the ARM instruction mnemonic list.
Table 11-2. ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
MOV Move CDP Coprocessor Data Processing
ADD Add MVN Move Not
SUB Subtract ADC Add with Carry
RSB Reverse Subtract SBC Subtract with Carry
CMP Compare RSC Reverse Subtract with Carry
TST Test CMN Compare Negated
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11.2.6 Thumb Instruction Set Overview
The Thumb instruction set is a re-en coded subset of the ARM instructio n set.
The Thumb instruction set is divided into:
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store Multiple instructions
• Exception-generating instruction
In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as
R0 to R7 when executing ARM instructions. Some Thumb inst ructions also access to the Program Counter (ARM
Register 15), the Link Register (ARM Register 14) and the Stack Pointer (ARM Register 13). Further instructions
allow limited access to the ARM regis ter s 8 to 15 .
Table 11-3 gives the Thumb instruction mne mo n ic list.
AND Logical AND TEQ Test Equivalence
EOR Logical Exclusive OR BIC Bit Clear
MUL Multiply ORR Logical (inclusive) OR
SMULL Sign Long Multiply MLA Multiply Accumulate
SMLAL Signed Long Multiply Accumulate UMULL Unsigned Long Multiply
MSR Move to Status Register UMLAL Unsigned Long Multiply Accumulate
B Branch MRS Move From Status Register
BX Branch and Exchange BL Branch and Link
LDR Load Word SWI Software Interrupt
LDRSH Load Signed Halfword STR Store Word
LDRSB Load Signed Byte STRH Store Half Word
LDRH Load Half Word STRB Store Byte
LDRB Load Byte STRBT Store Register Byte with Translation
LDRBT Load Register Byte with Translation STRT Store Register with Translation
LDRT Load Register with Translation STM Store Multiple
LDM Load Multiple SWPB Swap Byte
SWP Swap Word MRC Move From Coprocessor
MCR Move To Coprocessor STC Store From Coprocessor
LDC Load To Coprocessor
Table 11-2. ARM Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
Table 11-3. Thumb Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
MOV Move MVN Move Not
ADD Add ADC Add with Carry
SUB Subtract SBC Subtract with Carry
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CMP Compare CMN Compare Negated
TST Test NEG Negate
AND Logical AND BIC Bit Clear
EOR Logical Exclusive OR ORR Logical (inclusive) OR
LSL Logical Shift Left LSR Logical Shift Right
ASR Arithmetic Shift Right ROR Rotate Right
MUL Multiply
B Branch BL Branch and Link
BX Branch and Exchange SWI Software Interrupt
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRB Load Byte STRB Store Byte
LDRSH Load Signed Halfword LDRSB Load Signed Byte
LDMIA Load Multiple STMIA Store Multiple
PUSH Push Register to stack POP Pop Register from stack
Table 11-3. Thumb Instruction Mnemonic List
Mnemonic Operation Mnemonic Operation
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12. Debug and Test Features
12.1 Description
The SAM7S Series Microcontrollers feature a number of complementary debug and test capabilities. A common
JTAG/ICE (EmbeddedICE) port is used for standard deb ugging functions, such as downloading code and single-
stepping through pr ograms. The Debug Unit pro vides a two-pin UART that can b e used to upload an application
into internal SRAM. It manages the inter rupt handling of the int ernal COMMTX and COM MRX signals that trace t he
activity of the Debug Communication Channe l.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test
environment.
12.2 Block Diagram
Figure 12-1. Debug and Test Block Diagram
ICE
PDC DBGU
PIO
DRXD
DTXD
TST
TMS
TCK
TDI
JTAGSEL
TDO
Boundary
TAP
ICE/JTAG
TAP
ARM7TDMI
Reset
and
Test
POR
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12.3 Application Examples
12.3.1 Debug Environment
Figure 12-2 on page 48 shows a complete debug environment example. The ICE/JTAG interface is used for stan-
dard debugging functions, such as downloading code and single-stepping through the progr am.
Figure 12-2. Application Debug Environment Example
ICE/JTAG
Interface
Host Debugger
ICE/JTAG
Connector
Terminal
RS232
Connector
SAM7S
SAM7S-based Application Board
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12.3.2 Test Environment
Figure 12-3 on page 49 shows a test environment example. Test vectors are sent and interpreted by the tester. In
this example, the “board in test” is designed using a n umber of JTAG-compliant devices. These devices can be
connected to form a single scan chain.
Figure 12-3. Application Test Environment Example
JTAG
Interface
ICE/JTAG
Connector
Test Adaptor
Chip 2Chip n
Chip 1
SAM7S
Tester
SAM7S-based Application Board In Test
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12.4 Debug and Test Pin Description
Table 12-1. Debug and Test Pin List
Pin Name Function Type Acti ve Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Mode Select Input High
ICE and JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Sele ct Input
JTAGSEL JTAG Selection Input
Debug Unit
DRXD Debug Receiv e Data Input
DTXD Debug Transmit Data Output
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12.5 Functional Description
12.5.1 Tes t Pin
One dedicat ed pin, T ST, is used to d ef ine t he de vice opera ti ng mod e. Th e use r must ma ke sure t hat t his pin is t ied
at low level to ensure normal operat ing condition s. Other va lues associated with th is pin are reserved f or manuf ac-
turing test.
12.5.2 EmbeddedICE™ (Embedded In-circuit Emulator)
The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is exam-
ined through an ICE/JTAG port.
The ARM7TDMI proc essor contains hardware extensions for advanced debugging features:
• In halt mode, a store-multiple (STM) can be inser ted into the instruction pipeline. This exports the contents of
the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system.
• In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor
program running on the ARM7TDMI processor.
There are three scan chains inside the ARM 7TDMI proc essor that su pport te sting, debu gging, and programmin g of
the Embedded ICE. The scan chains are controlled by the ICE/JTAG port.
EmbeddedICE mode is select ed when JT AGSEL is low. It is no t possible to switch dir ectly bet wee n ICE and JTAG
operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the EmbeddedICE, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).
12.5.3 Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace pur-
poses and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover,
the association with two peripheral data controller channels permits packet handling of these tasks with processor
time reduce d to a minimum.
The Debug Unit also manag es the interrupt handling of the COM MTX and COMMRX signals that come fro m the
ICE and that trace the act ivit y of the Debug Comm unicatio n Ch an nel. The De bug Unit allo ws blo ckage of ac ce ss to
the system thro ug h the ICE int er fa ce .
A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal
configuration.
Table 12-2. SAM7S Series Debug Unit Chip ID
Chip Name Chip ID
AT91SAM7S16 Rev A 0x27050240
AT91SAM7S161 Rev A 0x27050241
AT91SAM7S32 Rev A 0x27080340
AT91SAM7S32 Rev B 0x27080341
AT91SAM7S321 Rev A 0x27080342
AT91SAM7S64 Rev A 0x27090540
AT91SAM7S64 Rev B 0x27090543
AT91SAM7S64 Rev C 0x27090544
AT91SAM7S128 Rev A 0x270C0740
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For further details on the Debug Unit, see the Debug Unit section.
12.5.4 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundar y Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS func-
tions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies
the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG an d ICE operations. A chip reset must be performed after JTAG-
SEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up t esting.
12.5.4.1 JTAG Boundary-scan Register
The Boundary-scan Regist er (BSR) contains 96 bits that correspond to acti ve pins and associated control signals.
Each SAM7Sxx input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that
can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit
selects the direction of the pad.
AT91SAM7S128 Re v B 0x270A0741
AT91SAM7S128 Re v C 0x270A0742
AT91SAM7S128 Re v D 0x270A0743
AT91SAM7S256 Rev A 0x270D0940
AT91SAM7S256 Re v B 0x270B0941
AT91SAM7S256 Re v C 0x270B0942
AT91SAM7S256 Re v D 0x270B0943
AT91SAM7S512 Rev A 0x270B0A40
AT91SAM7S512 Rev B 0x270B0A4F
Table 12-2. SAM7S Series Debug Unit Chip ID (Continued)
Table 12-3. SAM7Sxx JTAG Boundary Scan Register
Bit Number Pin Name Pin Type Associated BSR
Cells
96
PA17/PGMD5/AD0 IN/OUT
INPUT
95 OUTPUT
94 CONTROL
93
PA18/PGMD6/AD1 IN/OUT
INPUT
92 OUTPUT
91 CONTROL
90
PA21/PGMD9* IN/OUT*
INPUT(1)
89 OUTPUT(1)
88 CONTROL(1)
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87
PA19/PGMD7/AD2 IN/OUT
INPUT
86 OUTPUT
85 CONTROL
84
PA20/PGMD8/AD3 IN/OUT
INPUT
83 OUTPUT
82 CONTROL
81
PA16/PGMD4 IN/OUT
INPUT
80 OUTPUT
79 CONTROL
78
PA15/PGM3 IN/OUT
INPUT
77 OUTPUT
76 CONTROL
75
PA14/PGMD2 IN/OUT
INPUT
74 OUTPUT
73 CONTROL
72
PA13/PGMD1 IN/OUT
INPUT
71 OUTPUT
70 CONTROL
69
PA22/PGMD10* IN/OUT*
INPUT(1)
68 OUTPUT(1)
67 CONTROL(1)
66
PA23/PGMD11* IN/OUT*
INPUT(1)
65 OUTPUT(1)
64 CONTROL(1)
63
PA24/PGMD12* IN/OUT*
INPUT(1)
62 OUTPUT(1)
61 CONTROL(1)
60
PA12/PGMD0 IN/OUT
INPUT
59 OUTPUT
58 CONTROL
57
PA11/PGMM3 IN/OUT
INPUT
56 OUTPUT
55 CONTROL
54
PA10/PGMM2 IN/OUT
INPUT
53 OUTPUT
52 CONTROL
Table 12-3. SAM7Sxx JTAG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR
Cells
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51
PA9/PGMM1 IN/OUT
INPUT
50 OUTPUT
49 CONTROL
48
PA8/PGMM0 IN/OUT
INPUT
47 OUTPUT
46 CONTROL
45
PA7/PGMNVALID IN/OUT
INPUT
44 OUTPUT
43 CONTROL
42
PA6/PGMNOE IN/OUT
INPUT
41 OUTPUT
40 CONTROL
39
PA5/PGMRDY IN/OUT
INPUT
38 OUTPUT
37 CONTROL
36
PA4/PGMNCMD IN/OUT
INPUT
35 OUTPUT
34 CONTROL
33
PA25/PGMD13 IN/OUT
INPUT(1)
32 OUTPUT(1)
31 CONTROL(1)
30
PA26/PGMD14 IN/OUT
INPUT(1)
29 OUTPUT(1)
28 CONTROL(1)
27
PA27/PGMD15 IN/OUT
INPUT(1)
26 OUTPUT(1)
25 CONTROL(1)
24
PA28 IN/OUT
INPUT(1)
23 OUTPUT(1)
22 CONTROL(1)
21
PA3 IN/OUT
INPUT
20 OUTPUT
19 CONTROL
18
PA2 IN/OUT
INPUT
17 OUTPUT
16 CONTROL
Table 12-3. SAM7Sxx JTAG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR
Cells
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Note: 1. Does not pert ain to SAM7S32.
15
PA1/PGMEN1 IN/OUT
INPUT
14 OUTPUT
13 CONTROL
12
PA0/PGMEN0 IN/OUT
INPUT
11 OUTPUT
10 CONTROL
9
PA29 IN/OUT
INPUT(1)
8OUTPUT(1)
7CONTROL(1)
6
PA30 IN/OUT
INPUT(1)
5OUTPUT(1)
4CONTROL(1)
3
PA31 IN/OUT
INPUT(1)
2OUTPUT(1)
1CONTROL(1)
0 ERASE IN INPUT
Table 12-3. SAM7Sxx JTAG Boundary Scan Register (Continued)
Bit Number Pin Name Pin Type Associated BSR
Cells
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12.5.5 ID Code Register
Access: Read-only
The JTAG D is used in the IEEE 1149.1 JTAG Boundary Scan.
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Par t Number
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1.
Set to 0x1.
31 30 29 28 27 26 25 24
VERSION PART NUMBER
23 22 21 20 19 18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PART NUMBER MANUFACTURER IDENTITY
76543210
MANUFA CTURER IDENTITY 1
Chip Name Chip ID
AT91SAM7S16 0x5B22
AT91SAM7S161 0x5B1F
AT91SAM7S32 0x5B07
AT91SAM7S321 0x5B12
AT91SAM7S64 0x5B06
AT91SAM7S128 0x5B09
AT91SAM7S256 0x5B0A
AT91SAM7S512 0x5B1A
Chip Name JTA G ID Code
AT91SAM7S16 05B2_203F
AT91SAM7S161 05B1_F03F
AT91SAM7S32 05B0_703F
AT91SAM7S321 05B1_203F
AT91SAM7S64 05B0_603F
AT91SAM7S128 05B0_A03F
AT91SAM7S256 05B0_903F
AT91SAM7S512 05B1_A03F
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13. Reset Controller (RSTC)
13.1 Overview
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any
external components. It reports which reset occurred last.
The Reset Controller also drives indepen dently or simulta neously the extern al reset and the perip heral an d proces-
sor resets.
A brownout detection is also available to prevent the processor from falling into an unpredictable state.
13.2 Block Diagram
Figure 13-1. Reset Controller Block Diagram
NRST
Startup
Counter
proc_nreset
wd_fault
periph_nreset
SLCK
Reset
State
Manager
Reset Controller
brown_out
bod_rst_en
rstc_irq
NRST
Manager exter_nreset
nrst_out
Main Supply
POR
WDRPROC
user_reset
Brownout
Manager bod_reset
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13.3 Functional Description
13.3.1 Reset Controller Overview
The Reset Controller is mad e up of an NRST Manager , a Brown out Mana ger, a St artup Coun ter and a Reset State
Manager. It runs at Slow Clock and generates the following reset sig nals:
• proc_nreset: Processor reset line. It also resets the Watchdog Timer.
• periph_nreset: Affects the whole set of embedded peripherals.
• nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Con troller, either on external events or on software action. The
Reset State Mana ger contr ols the gener ation of rese t sig nals and provides a signal to the NRST Ma nager when an
assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device
resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator
startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical
Characteristics section of the product documentation.
13.3.2 NRST Manager
The NRST Manager sample s the NRST input pin and drives this pin low when required by the Reset State Man-
ager. Figure 13-2 shows the block diagram of the NRST Manager.
Figure 13-2. NRST Manager
13.3.2.1 NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is
reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writ-
ing the bit URSTEN at 0 in RSTC_MR disables the User Re set trigger.
The level of the pin NRST can be rea d at any tim e in t he bit NRSTL (NRST level) in RSTC_SR. As soon as th e pin
NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
The Reset Controlle r can also be prog ram med to ge ner at e a n inte rr upt in stea d o f g ene ra ting a re se t. To do so , the
bit URSTIEN in RSTC_MR must be written at 1.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset
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13.3.2.2 NRST Exter na l Rese t Co ntr o l
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, th e “nrst_out”
signal is driven low by th e NRST Mana ge r for a ti me pr ogrammed by the field ERSTL in RSTC_MR. This assertion
duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate
duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the
NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is
driven low for a time compliant with potential external devices connected on the system reset.
13.3.3 Brownout Manager
Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below
a certain level. When VDDCORE drops below the brownou t threshold, the br owno ut m ana ger r equest s a browno ut
reset by asserting the bod_reset signal.
The programmer can disa ble t he br ownout reset by setti ng low the bo d_rst_ en input sig nal, i.e .; by lockin g th e co r-
responding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed.
Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when
RSTC_SR is read.
The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR.
At factory, the brownout reset is disabled.
Figure 13-3. Brownout Manager
rstc_irq
brown_out
bod_reset
bod_rst_en
BODIEN
RSTC_MR
BODSTS
RSTC_SR
Other
interrupt
sources
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13.3.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports
the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is per-
formed when the processor reset is released.
13.3.4.1 Power-up Reset
When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates
at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the
device.
The startup time, as shown in F igure 13-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After
the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset.
When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately.
Figure 13-4. Power-up Reset
SLCK
periph_nreset
proc_nreset
Main Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
Startup Time
MCK
Processor Startup
= 3 cycles
Any
Freq.
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13.3.4.2 User Reset
The User Reset is entered when a low le vel is det ected on the NRST pin an d the bi t URSTEN in RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to insure proper behavior of th e system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral
Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-cycle processor
startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with
the value 0x4, indicating a User Reset.
The NRST Manager guarante es that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock
cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH
because it is driven low externally, the internal r eset lines remain asserted un til NRST actually rises.
Figure 13-5. User Reset State
SLCK
periph_nreset
proc_nreset
NRST
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
MCK
Processor Startup
= 3 cycles
Any
Freq.
Resynch.
2 cycles
RSTTYP Any XXX
Resynch.
2 cycles
0x4 = User Reset
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13.3.4.3 Brownout Reset
When the brown_out/bod_reset signal is asser ted, the Re set State Manager immediately enters the Brownout
Reset. In this state, the processor, the peripheral and the external reset lines are asserted.
The Brownout Reset is left Y Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle
resynchronization. An external reset is also triggered.
When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating
that the last reset is a Brownout Reset.
Figure 13-6. Brownout Reset State
SLCK
periph_nreset
proc_nreset
brown_out
or bod_reset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x5 = Brownout Reset
Resynch.
2 cycles
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13.3.4.4 Softw are Reset
The Reset Controller offers several com mands used to assert the different reset signals. These commands ar e
performed by writing the Control Register (RST C_CR) with the following bits at 1:
• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
• PERRST: Writing PERRST at 1 resets all the embedded peripher als, including the memory system, and, in
particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
Except for Debug purposes, PERRST must al ways be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously.)
• EXTRST: Writing EXT RST at 1 asserts low the NRST pin during a time defined b y the field ERSTL in the Mode
Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be per-
formed independen tly or simultane ously. The software reset lasts Y Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the
resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the
Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the
Status Register ( RSTC_ SR) . It is cle ar ed as so on as the so ft war e re set is le ft. N o o th er so ftw ar e r es et can b e p er -
formed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.
Figure 13-7. Software Reset
13.3.4.5 Watc hd o g Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts Y Slow Clock cycles.
When in Watchdog Rese t, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:
SLCK
periph_nreset
if PERRST=1
proc_nreset
if PROCRST=1
Write RSTC_CR
NRST
(nrst_out)
if EXTRST=1 EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x3 = Software Reset
Resynch.
1 cycle
SRCMP in RSTC_SR
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• If WDRPROC is 0, the Processor Reset and the P eripheral Reset are asserted. The NRST line is also asserted ,
depending on the pr ogramming of th e field ERSTL. However, th e resulting low leve l on NRST does not result in
a User Reset state.
• If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by
default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the wat chdo g fa ult has no imp act on the re set contro lle r.
Figure 13-8. Watchdog Reset
Only if
WDRPROC = 0
SLCK
periph_nreset
proc_nreset
wd_fault
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 3 cycles
Any
Freq.
RSTTYP Any XXX 0x2 = Watchdog Reset
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13.3.5 Reset State Pr iorities
The Reset State Manager manages the following priorities between the different reset sources, given in descend-
ing order:
•Power-up Reset
•Brownout Reset
• Watchdog Reset
• Software Reset
• User Reset
Particular cases are listed below:
• When in User Reset:
– A wat chdog event is impossible because t he Watchdog Timer is b eing r eset by t he pr oc_n re set sig nal .
– A software reset is impossible, since the processor reset is being activated.
• When in Software Reset:
– A watchdog event has priority over the current state.
– The NRST has no effect.
• When in Watchdog Reset:
– The processor reset is active and so a Software Reset cannot be programmed.
– A User Reset cannot be entered.
13.3.6 Reset Contr oller Status Regi ster
The Reset Controller status register (RSTC_SR) provides several status fields:
• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
• SRCMP bit: This field indicates that a Softw are Reset Command is in progress an d that no further software
reset should be performed until the end of the current one. This bit is automatically cleared at the end of the
current software reset.
• NRSTL bit: The NRSTL bit of t he Status Register gives t he level of the NRST pin sampled on each MCK rising
edge.
• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This
transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-9). If the User Reset is
disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the
URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the
interrupt.
• BODSTS bit: This bit indica te s a br ownout dete ctio n wh en the brownout rese t is disa bled (bod_rst _e n = 0). It
triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR
register resets the BODSTS bit and clears the interrupt.
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Figure 13-9. Reset Controller Statu s an d In te rru p t
MCK
NRST
NRSTL
2 cycle
resynchronization 2 cycle
resynchronization
URSTS
read
RSTC_SR
Peripheral Access
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)
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13.4 Reset Controller (RSTC) User Interface
Table 13-1. Register Mapping
Offset Register Name Access Reset
0x00 Control Register RSTC_CR Write-only -
0x04 Status Register RSTC_SR Read-only 0x0000_0000
0x08 Mode Register RSTC_MR Read-write 0x0000_0000
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13.4.1 Reset Controller Control Register
Register Name: RSTC_CR
Access Type: Write-only
• PROCRST: Processor Reset
0 = No effect.
1 = If KEY is correct, resets t he processor.
• PERRST: Peripheral Reset
0 = No effect.
1 = If KEY is correct, resets t he peripherals.
• EXTRST: External Reset
0 = No effect.
1 = If KEY is correct, asserts the NRST pin .
•KEY: Password
Should be written at value 0xA5. Writing any other value in t his field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––EXTRSTPERRST–PROCRST
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13.4.2 Reset Contr oller Status Regi ster
Register Name: RSTC_SR
Access Type: Read-only
• URSTS: User Reset Status
0 = No high-to- low edge on NRST happened since the last read of RSTC_SR.
1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• BODSTS: Brownout Detection Status
0 = No brownout high-to-low transition happened since the last read of RSTC_SR.
1 = A brownout high-to-low transi tion has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0 = No software command is bein g performed by the reset cont roller. The reset controller is ready for a software co mmand.
1 = A software reset command is being performed by the reset controller. The reset controller is busy.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––SRCMPNRSTL
15 14 13 12 11 10 9 8
––––– RSTTYP
76543210
––––––BODSTSURSTS
RSTTYP Reset Type Comments
0 0 0 Power-up Reset VDDCORE rising
0 1 0 Watchdog Reset Watchdog fault occurred
0 1 1 Software Reset Processor reset required by the software
1 0 0 User Reset NRST pin detected low
1 0 1 Brownout Reset BrownOut reset occurred
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13.4.3 Reset Controller Mode Register
Register Name: RSTC_MR
Access Type: Read/Write
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• BODIEN: Brownout Detection Interrupt Enable
0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq.
• ERSTL: External Reset Length
This field de fines the exter nal reset le ngth. The external re set is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This
allows assertion du ration to be programmed between 60 µs and 2 seconds.
•KEY: Password
Should be written at value 0xA5. Writing any other value in t his field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
–––––––BODIEN
15 14 13 12 11 10 9 8
–––– ERSTL
76543210
–––URSTIEN–––URSTEN
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14. R eal-time Timer (RTT)
14.1 Overview
The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic
interrupt or/and triggers an alarm on a programmed value.
14.2 Block Diagram
Figure 14-1. Real-time Timer
14.3 Functional Description
The Real-time Timer is used to count ela psed seconds. It is built ar ound a 32- bit counte r fed by Slow Clock divided
by a programmabl e 16-bit va lue. Th e value can be p rogramm ed in the f ield RTPRES o f the Rea l-time Mode Regis-
ter (RTT_MR ).
Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow
Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then
roll over to 0.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is
achieved by writing RTPRES to 3. Programm ing RTPRES to 1 or 2 is possible, but may result in losing status
events because the status register is cleared two Slow Clock cycles aft er read. Thus if the RTT is configure d to trig-
ger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several
executions of the int errupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the
status register is clear.
The Real-time Ti mer value (CRTV) can be read at any time in t he register RTT_VR (Real-time Value Register). As
this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the
same value to improve accuracy of the returned value.
SLCK
RTPRES
RTTINC
ALMS
16-bit
Divider
32-bit
Counter
ALMV =
CRTV
RTT_MR
RTT_VR
RTT_AR
RTT_SR
RTTINCIEN
RTT_MR
0
10
ALMIEN
rtt_int
RTT_MR
set
set
RTT_SR
read
RTT_SR
reset
reset
RTT_MR
reload
rtt_alarm
RTTRST
RTT_MR
RTTRST
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The current value of th e cou nter is com pared with the valu e writ ten in t he al ar m regist er RTT_AR (Rea l-t ime Alarm
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This b it can be used to
start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow
Clock equal to 32.768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fi elds.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed
value. This also resets the 32-bit counter.
Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):
1) The restart of the counter and the reset of the RT T_VR current value register is effective only 2 slow clock cycles
after the write of the RTTRST bit in the RTT_MR register.
2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status
Register).
Figure 14-2. RTT Counting
Prescaler
ALMVALMV-10 ALMV+1
0
RTPRES - 1
RTT
APB cycle
read RTT_SR
ALMS (RTT_SR)
APB Interface
MCK
RTTINC (RTT_SR)
ALMV+2 ALMV+3
...
APB cycle
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14.4 Real-time Timer (RTT) User Interface
Table 14-1. Register Mapping
Offset Register Name Access Reset
0x00 Mode Register RTT_MR Read-wri te 0x0000_8000
0x04 Alarm Register R TT_AR Read-write 0xFFFF_FFFF
0x08 Value Register RTT_VR Read-only 0x0000_0000
0x0C Status Register RTT_SR Read-only 0x0000_0000
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14.4.1 Real-time Timer Mode Register
Register Name: RTT_MR
Access Type: Read-write
• RTPRES: Real-time Timer Prescale r Value
Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows:
RTPRES = 0: The Prescaler Period is equal t o 216
RTPRES ≠ 0: The Prescaler Period is equal to RTPRES.
• ALMIEN: Alarm Interrupt Enable
0 = The bit ALMS in RTT_SR has no effect on interrupt.
1 = The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable
0 = The bit RTTINC in RTT_SR ha s no effect on interrupt.
1 = The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Timer Restart
1 = Reloads and restarts the clock divider with the new programm ed value. This also resets the 32-bit counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––RTTRSTRTTINCIENALMIEN
15 14 13 12 11 10 9 8
RTPRES
76543210
RTPRES
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14.4.2 Real-time Timer Ala rm Register
Register Name: RTT_AR
Access Type: Read-write
• ALMV: Alarm Value
Defines the alarm value (ALMV+1) compared with the Real- time Timer.
31 30 29 28 27 26 25 24
ALMV
23 22 21 20 19 18 17 16
ALMV
15 14 13 12 11 10 9 8
ALMV
76543210
ALMV
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14.4.3 Real-time Timer Value Register
Register Name: RTT_VR
Access Type: Read-only
• CRTV: Current Real-time Value
Returns the current value of the Real-time Timer.
31 30 29 28 27 26 25 24
CRTV
23 22 21 20 19 18 17 16
CRTV
15 14 13 12 11 10 9 8
CRTV
76543210
CRTV
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14.4.4 Real-time Timer Status Register
Register Name: RTT_SR
Access Type: Read-only
• ALMS: Real-time Ala rm Stat us
0 = The Real-time Alarm has not occurred since the last read of RTT_SR.
1 = The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Real-time Timer Incre ment
0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.
1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––RTTINCALMS
80
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15. Periodic Interval Timer (PIT)
15.1 Overview
The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maxi-
mum accuracy and efficient management, ev en for systems with long response time.
15.2 Block Diagram
Figure 15-1. Periodic Interval Timer
20-bit
Counter
MCK/16
PIV
PIT_MR
CPIV PIT_PIVR PICNT
12-bit
Adder
0
0
read PIT_PIVR
CPIV PICNT
PIT_PIIR
PITS
PIT_SR
set
reset
PITIEN
PIT_MR
pit_irq
1
0
10
MCK
Prescaler
= ?
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15.3 Functional Description
The Periodic Interval Timer aims at providing pe riodic interrupts for use by op erating systems.
The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a
20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.
The first 20-bit CPIV counter increments from 0 up to a prog rammable overflow value set in the field PIV of the
Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic
Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises a nd triggers an interrupt, pro-
vided the interrupt is enabled (PITIEN in PIT_MR).
Writing a new PIV value in PIT_MR does not reset/restart the counters.
When CPIV and PICNT values are obtained by reading the Periodic Interval Value R egister (PIT _PIVR), the over -
flow counter (PI CNT ) is re se t an d the PIT S is cl eare d, thus acknowled gin g th e int er ru p t. Th e valu e of PICNT give s
the number of periodic intervals elapsed since the last read of PIT_PIVR.
When CPIV and PICNT value s are obt ained by read ing the Peri odic Interv al Image Register (PIT_PIIR), there is no
effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without
clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.
The PIT may be en abled/disabled using the PITEN b it in the PIT_MR re gister (disabled on reset). The PITEN bit
only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit
is reset (PITEN= 0), the CPIV goes on cou nting until the PIV value is r eached, and is then reset. PIT restar ts count-
ing, only if the PITEN is set again.
The PIT is stopped when the core ente rs debug state.
Figure 15-2. Enabling/Disabling PIT with PITEN
MCK Prescaler
PIVPIV - 10
PITEN
10
0
15
CPIV 1
restarts MCK Prescaler
01
APB cycle
read PIT_PIVR
0
PICNT
PITS (PIT_SR)
MCK
APB Interface
APB cycle
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15.4 Periodic Interval Timer (PIT) User Interface
Table 15-1. Register Mapping
Offset Register Name Access Reset
0x00 Mode Register PIT_MR Read-write 0x000F_FFFF
0x04 Status Register PIT_SR Read-only 0x0000_0000
0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000
0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000
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15.4.1 Periodic Interval Timer Mode Register
Register Name: PIT_MR
Access Type: Read-write
• PIV: Periodic Interval Value
Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to
(PIV + 1).
• PITEN: Period Interval Timer Enabled
0 = The Periodic Interval Timer is disabled when the PIV value is reached.
1 = The Periodic Interval Timer is enab led.
• PITIEN: Periodic Interval Timer Interrupt Enable
0 = The bit PITS in PIT_SR has no effect on interrupt.
1 = The bit PITS in PIT_SR asserts interrupt.
31 30 29 28 27 26 25 24
––––––PITIENPITEN
23 22 21 20 19 18 17 16
–––– PIV
15 14 13 12 11 10 9 8
PIV
76543210
PIV
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15.4.2 Periodic Interval Timer Status Register
Register Name: PIT_SR
Access Type: Read-only
• PITS: Periodic Interval Timer Status
0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.
1 = The Periodic Interva l ti me r ha s re ac he d PIV since the last read of PIT_PIVR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––PITS
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15.4.3 Periodic Interval Timer Value Regis t er
Register Name: PIT_PIVR
Access Type: Read-only
Reading this register clears PITS in PIT_SR.
• CPIV: Current Periodic Interval Value
Returns the current value of the period ic interval timer.
• PICNT: Pe ri odic Inte rval Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
31 30 29 28 27 26 25 24
PICNT
23 22 21 20 19 18 17 16
PICNT CPIV
15 14 13 12 11 10 9 8
CPIV
76543210
CPIV
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15.4.4 Pe ri odi c Inte r val Timer Image Registe r
Register Name: PIT_PIIR
Access Type: Read-only
• CPIV: Current Periodic Interval Value
Returns the current value of the period ic interval timer.
• PICNT: Pe ri odic Inte rval Counter
Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
31 30 29 28 27 26 25 24
PICNT
23 22 21 20 19 18 17 16
PICNT CPIV
15 14 13 12 11 10 9 8
CPIV
76543210
CPIV
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16. Watchdog Timer (WDT)
16.1 Overview
The Watchdog Timer can be use d to prevent system lock-up if the software be comes trapped in a deadlock. It fea-
tures a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can
generate a general reset or a processo r reset only. In addition, it can be stopped while the processor is in debug
mode or idle mode.
16.2 Block Diagram
Figure 16-1. Watchdog Timer Block Diagra m
=0
10
set
reset
read WDT_SR
or
reset
wdt_fault
(to Reset Controller)
set
reset
WDFIEN
wdt_int
WDT_MR
SLCK
1/128
12-bit Down
Counter
Current
Value
WDD
WDT_MR
<= WDD
WDV
WDRSTT
WDT_MR
WDT_CR
reload
WDUNF
WDERR
reload
write WDT_MR
WDT_MR
WDRSTEN
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16.3 Functional Description
The Watchdog Timer can be used to prevent system lock-up if the softwa re becomes trapped in a deadlock. It is
supplied with VDDCORE. It restarts with initial values on processor reset.
The Watchdog is built around a 12-bit down counter, which is loaded with the value defin ed in the field WDV of t he
Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establi sh the maximum
Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
After a Proc esso r Res et, t he v alue of WD V is 0x FFF , co rres pond ing to the max imum valu e of the cou nter wit h the
external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watch-
dog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if
he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires.
If the watchdog is restarted by writing into WDT_CR register, the WDT_MR register must not be programmed dur-
ing a period of time of 3 slow clock period following the WDT_CR write access. In any case, programming a new
value in WDT_MR automatically initiates a restart instruction.
The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the
WDT_MR register reloads the timer with the newly programmed mode parameters.
In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writ-
ing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately
reloaded fro m WDT _MR an d r est arte d, an d t he Slow Clock 128 divide r is r eset an d r estart ed. T he WDT_ CR regis-
ter is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an
underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the
Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR).
To prevent a software deadlock that continuously trigge rs the Watchdog, the reload of the Watchdog must occur
while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Reg-
ister WDT_MR.
Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog
error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault” signal to
the Reset Controller is asserted.
Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In
such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not gener-
ate an error. This is the de fault configuration on reset (the WDD and WDV values are equal).
The status bits WDUNF (Wat ch dog Under fl ow) an d WDERR ( Watchdog Error) tr igger an inte rr upt, pr ovided th e bit
WDFIEN is set in the mo de register. The signal “wdt_fault” to the rese t controller causes a Watchdog reset if th e
WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the proces-
sor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault”
signal to the reset contr oller is deasserted.
Writing the WDT_MR reloads and restar ts the down counter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on the value pro-
grammed for the bit s WDIDLEHLT and WDDBGHLT in the WDT_MR.
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Figure 16-2. Watchdog Behavior
0
WDV
WDD
WDT_CR = WDRSTT
Watchdog
Fault
Normal behavior
Watchdog Error Watchdog Underflow
FFF if WDRSTEN is 1
if WDRSTEN is 0
Forbidden
Window
Permitted
Window
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16.4 Watchdog Timer (WDT) User Interface
16.4.1 Watchdog Timer Cont rol Register
Register Name: WDT_CR
Access Type: Write-only
• WDRSTT: Watchdog Restart
0: No effect.
1: Restarts the Watchdog.
•KEY: Password
Should be written at value 0xA5. Writing any other value in t his field aborts the write operation.
Table 16-1. Register Mapping
Offset Register Name Access Reset
0x00 Control Register WDT_CR Write-only -
0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF
0x08 Status Register WDT_SR Read-only 0x0000_0000
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––WDRSTT
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16.4.2 Watchdog Timer Mode Register
Register Name: WDT_MR
Access Type: Read-write Once
• WDV: Wa tchdog Counter Value
Defines the value loaded in the 12-bit Watchdog Counter.
• WDFIEN: Wa tchdog Fault Interrupt Enable
0: A Watchdog fault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable
0: A Watchdog fault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a Watchdog reset.
• WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.
• WDD: Watchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.
If the Watchdog Timer valu e is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.
• WDDBGHLT: Watchdog Debug Halt
0: The Watchdog runs when the processor is in debug state.
1: The Watchdog stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt
0: The Watchdog runs when the system is in idle mode.
1: The Watchdog stops when the system is in idle state.
• WDDIS: Watchdog Disable
0: Enables the Watchdog Timer.
1: Disables the Watchdog Timer.
31 30 29 28 27 26 25 24
– – WDIDLEHLT WDDBGHLT WDD
23 22 21 20 19 18 17 16
WDD
15 14 13 12 11 10 9 8
WDDIS WDRPROC WDRSTEN WDFIEN WDV
76543210
WDV
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16.4.3 Watchdog Timer Sta tus Register
Register Name: WDT_SR
Access Type: Read-only
• WDUNF: Watchdog Underflow
0: No Watchdog underflow occurred since the last read of WDT_SR.
1: At least one Watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error
0: No Watchdog error occurred since the last read of WDT_SR.
1: At least one Watchdog error occurred since the last read of WDT_SR.
Note:The W DD and WDV value s must no t be m odified within a p eriod o f time of 3 slo w clock p eriods following a restar t of
the watchdog performed by means of a write access in the WDT_CR register, else the wa tchdog may trigger an end of
period earlier than expected.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––WDERRWDUNF
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17. Voltage Regulator Mode Controller (VREG)
17.1 Overview
The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register.
Its offset is 0x60 with respect to the System Controller offset.
This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby
Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal
Mode.
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17.2 Voltage Regulator Power Contr oller (VREG) User Interface
17.2.1 Voltage Regulator Mode Register
Register Name: VREG_MR
Access Type: Read-write
• PSTDBY: Periodic Interval Value
0 = Voltage regulator in normal mode.
1 = Voltage regulator in standby mo de (low-power mode ).
Table 17-1. Register Mapping
Offset Register Name Access Reset
0x60 Voltage Regulator Mode Register VREG_MR Read-write 0x0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––PSTDBY
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18. Memory Controller (MC)
18.1 Overview
The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the
ARM7TDMI processor and the Per iph er al DMA Con tr oller. It f eat ur es a simple bus arbit er, an address decod er, an
abort status, a misali gnment detector and an Embe dded Flash Controller.
18.2 Block Diagram
Figure 18-1. Memory Controller Block Diagram
18.3 Functional Description
The Memory Controller handles the internal ASB bus and arbitrates the accesses of both masters.
ARM7TDMI
Processor
Bus
Arbiter
Peripheral
DMA
Controller
Memory Controller
Abort
ASB
Abort
Status
Address
Decoder
User
Interface
Peripheral 0
Peripheral 1
Internal
RAM
APB
APB
Bridge
Misalignment
Detector
From Master
to Slave
Peripheral N
Embedded
Flash
Controller
Internal
Flash
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It is made up of:
• A bus arbiter
• An address decoder
• An abort status
• A misalignment detector
• An Embedded Flash Controller
The MC handles only little-endian mode accesses. The masters work in litt le-endian mode only.
18.3.1 Bus Arbiter
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the
two masters. The Peripheral DMA Controller has the highest priority; the ARM pro cessor has the lowest one.
18.3.2 Address Decoder
The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address
bus and defines th ree separate areas:
• One 256-Mbyte address space for the internal memories
• One 256-Mbyte address space reserved for the embedded peripherals
• An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if
accessed
Figure 18-2 shows the assignment of the 256-Mbyte memo ry areas.
Figure 18-2. Memory Areas
18.3.2.1 Internal Memory Mapping
Within the Internal Memory address space, the Address Decoder of the Memory Controller deco des eight more
address bits to allocate 1-Mbyte address spaces for the embedded memories.
The allocated memories ar e accessed all along the 1- Mbyt e addr ess space and so are rep eated n time s within this
address space, n equaling 1M byte s divided by the size of the memory.
When the address of the access is undefined within the internal mem ory area, the Address Decoder returns an
Abort to the master.
0x0000 0000
0x0FFF FFFF
0x1000 0000
0xEFFF FFFF
0xF000 0000
0xFFFF FFFF
256M Bytes
256M Bytes
14 x 256MBytes
3,584 Mbytes
Internal Memories
Undefined
(Abort)
Peripherals
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If an access is done in the address area 0x0030 000 to 0x003F FFFF, no abort is generated.
Figure 18-3. Internal Memory Mapping
18.3.2.2 Internal Memory Area 0
The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in part icular, the Reset
Vector at address 0x0.
Before execution of the remap command, the on-chip Flash is mapped into Internal Memory Area 0, so that the
ARM7TDMI reaches an executa ble instruction co ntained in Flash. After the remap command , the internal SRAM at
address 0x0020 0000 is ma pped into In ternal Memo ry Area 0. T he memory mapp ed into Inter nal Memory Ar ea 0 is
accessible in both its original location and at address 0x0.
18.3.3 Remap Command
After execution, the Remap Command causes the Internal SRAM to be accessed through the Internal Memory
Area 0.
As the ARM vector s ( Re set, Ab o rt, Da ta Ab or t, Pr e fet ch Ab or t, Undefined Instr uctio n, In ter rup t, a n d Fast I nt erru pt )
are mapped from address 0x0 to address 0x20, the Remap Command allows the user to redefine dynamically
these vectors under software control.
The Remap Command is accessible through the Memory Controller User Interface by writing the MC_RCR
(Remap Control Register) RCB field to one.
The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling com-
mand. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the
same configuration as after a reset.
18.3.4 Abort Status
There are three reasons for an abort to occur:
• access to an undefined address
• an access to a misaligned address.
When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access.
However, only the ARM7TDMI can take an abort signal into account, and only under the condition that it was gen-
erating an access. The Peripheral DMA Controller does not handle the abort input signal. Note th at the connection
is not represented in Figure 18-1.
256M Bytes
Internal Memory Area 0
Undefined Areas
(Abort)
0x0000 0000
0x000F FFFF
0x0010 0000
0x001F FFFF
0x0020 0000
0x002F FFFF
0x0FFF FFFF
1M Bytes
1M Bytes
1M Bytes
253M bytes
Internal Memory Area 1
Internal Flash
Internal Memory Area 2
Internal SRAM
0x0030 0000
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To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status
register set.
The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and
include:
• the size of the request (field ABTSZ)
• the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)
• whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned address (bit
MISADD)
• the source of the access leading to the last abort (bits MST0 and MST1)
• whether or n ot an a bort occurred f or each master since th e last re ad of the re gister (b it SVMST0 an d SVMST1)
unless this inf ormation is loaded in MST bits
In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as search-
ing for which address generated the abort would require disassembling the instructions and full knowledge of the
processor context.
In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM pro-
cessor. The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is
probable that several ab or ts have occur red durin g t his time. Thus, in t his case, it is p refe rable t o u se th e conte nt of
the Abort Link register of the ARM processor.
18.3.5 Embedded Flash Controller
The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the Flash block
with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buf-
fers. It also manages with the programming, era sing, locking and unlocking sequences thanks to a full set of
commands.
18.3.6 Misalignment Detector
The Memory Controller features a Misalignment Detector that checks the consistency of the accesses.
For each access, regard less of the master, the size of the access and the bits 0 and 1 of the address bus a re
checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-
word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the
accesses of the ARM pro ce sso r wh en it is fetchin g instr uc tions ar e no t ch ecked.
The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particu-
larly difficult to detect in the debug phase.
As the requested address is saved in the Abort Status Register and the address of the instruction generating the
misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bug is
simplified.
18.4 Memor y Controller (MC) User Interface
Base Address: 0xFFFFFF00
Table 18-1. Register Mapping
Offset Register Name Access Reset
0x00 MC Remap Control Register MC_RCR Write-only
0x04 MC Abort Status Register MC_ASR Read-only 0x0
0x08 MC Abort Address Status Register MC_AASR Read-only 0x0
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Note: 1. SAM7S512 only.
0x0C-0x5C Reserved – – –
0x60 EFC0 Configuration Registers See Section 19. “Embedded Flash Controller (EFC)” on page 105.
0x70 EFC1 Configuration Registers (1)
Table 18-1. Register Mapping
Offset Register Name Access Reset
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18.4.1 MC Remap Control Register
Register Name:MC_RCR
Access Type: Write-only
Offset:0x00
• RCB: Remap Command Bit
0: No effect.
1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero
memory devices.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RCB
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18.4.2 MC Abort Status Register
Register Name:MC_ASR
Access Type: Read-only
Reset Value:0x0
Offset:0x04
• UNDADD: Undefined Address Abort Status
0: The last abort was not due to the access of an undefined address in the address space.
1: The last abort was due to the access of an undefined address in the address space.
• MISADD: Misaligned Address Abort Status
0: The last aborted access was not due to an address misalignment.
1: The last aborted access was due to an address misalignment.
• ABTSZ: Abort Size Status.
• ABTTYP: Abort Type Status.
• MST0: PDC Abort Source
0: The last aborted access was not due to the PDC.
1: The last aborted access was due to the PDC.
• MST1: ARM7TDMI Abort Source
31 30 29 28 27 26 25 24
––––––SVMST1SVMST0
23 22 21 20 19 18 17 16
––––––MST1MST0
15 14 13 12 11 10 9 8
– – – – ABTTYP ABTSZ
76543210
––––––MISADDUNDADD
ABTSZ Abort Size
00 Byte
0 1 Half-word
10 Word
11 Reserved
ABTTYP Abort Type
0 0 Data Re a d
0 1 Data Write
1 0 Code Fetch
11 Reserved
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0: The last aborted access was not due to the ARM7TDMI.
1: The last aborted access was due to the ARM7TDMI.
• SVMST0: Saved PDC Abort Source
0: No abort due to the PDC occurred.
1: At least one abort due to the PDC occurred.
• SVMST1: Saved ARM7TDMI Abort Source
0: No abort due to the ARM7TDMI occurred.
1: At least one abort due to the ARM7TDMI occurred.
18.4.3 MC Abort Address Status Register
Register Name: MC_AASR
Access Type: Read-only
Reset Value:0x0
Offset:0x08
• ABTADD: Abort Address
This field contains the address of the last aborted access.
31 30 29 28 27 26 25 24
ABTADD
23 22 21 20 19 18 17 16
ABTADD
15 14 13 12 11 10 9 8
ABTADD
76543210
ABTADD
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19. Embedded Flash Controller (EFC)
19.1 Overview
The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the interface of the Flash
block with the 32-b it internal bus. It increases per formance in Thu mb Mode for Code Fet ch with its system of 32-bit
buffers. It also manages the progra mming, erasing, locking an d unlocking sequences using a full se t of commands.
The SAM7S512 is equipped with two EFCs, EFC0 and EFC1. EFC1 does not feature the Security bit and GPNVM
bit. The Security and GPNVM bits embedded on ly on EFC0 appl y to the two blocks in t he SAM7S512.
19.2 Functional Description
19.2.1 Embedded Flash Organization
The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several interfaces:
• One memory plane organized in several pages of the same size
• Two 32-bit read buffers used for code read optimization (see “Read Operations” on page 107).
• One write buffer that manages page programming . The write buffer size is equal to the page size. This buffer is
write-only and accessible all along the 1 MByte address space, so that each word can be written to its final
address (see “Write Operations” on pa ge 10 9 ).
• Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of
several consecutive pages, and each lock region has its associated lock bit.
• Several general- purpose NVM bits. Each bit controls a specific feature in the device. Refer to the product
definition section to get the GPNVM assignment.
The Embedded Flash size, the page size and the lock region organization are described in the product definition
section.
Table 19-1. Product Specific Lock and General-purpose NVM Bits
SAM7S512 SAM7S256 SAM7S128 SAM7S64 SAM7S321 SAM7S32 SAM7S161 SAM7S16 Denomination
2 2 2 2 2 2 2 2 Number of GPNVM bits
32 16 8 16 8 8 8 8 Number of Lock Bits
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Figure 19-1. Embedded Flash Memory Mapping
Lock Region 0
Lock Region
(n-1)
Page 0
Page (m-1)
Start Address
32-bit wide
Flash Memory
Page ( (n-1)*m )
Page (n*m-1)
Lock Bit 0
Lock Region 1 Lock Bit 1
Lock Bit n-1
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19.2.2 Read Operations
An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start
access at following add ress d ur ing th e second r ea d, t hus i ncreasing per f orman ce when t he processo r is ru nning in
Thumb mode (16-bit instruction set). See Figure 19-2, Figure 19-3 and Figure 19-4.
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be programmed in the
field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see “MC Flash Mo de Reg ister ” on page 115).
Defining FWS to be 0 enables the single-cycle access of the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded
Flash wraps around the address space and appears to be repeated within it.
Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0
Note: When FWS is equal to 0, all accesses are performed in a single-cycle access.
Figure 19-3. Code Read Optimization in Thumb Mode for FWS = 1
Note: When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the
first one).
Flash Access
Buffer (32 bits)
Master Clock
ARM Request (16-bit)
Code Fetch
Data To ARM
Bytes 0-3 Bytes 4-7
Bytes 0-3
Bytes 0-1 Bytes 2-3 Bytes 4-5 Bytes 6-7 Bytes 8-9 Bytes 10-11 Bytes 12-13
@Byte 0 @Byte 2 @Byte 4 @Byte 6 @Byte 8 @Byte 10 @Byte 12 @Byte 14 @Byte 16
Bytes 14-15
Bytes 4-7
Bytes 8-11
Bytes 8-11
Bytes 12-15 Bytes 16-19
Bytes 12-15
Flash Access
Buffer (32 bits)
Master Clock
ARM Request (16-bit)
Code Fetch
Data To ARM
Bytes 0-3 Bytes 4-7
Bytes 0-3
Bytes 2-3 Bytes 4-5 Bytes 6-7 Bytes 8-9 Bytes 10-11
@Byte 0 @Byte 4 @Byte 6 @Byte 8 @Byte 10 @Byte 12 @Byte 14
Bytes 4-7
Bytes 8-11
Bytes 8-11
Bytes 12-15
1 Wait State Cycle
Bytes 0-1
1 Wait State Cycle 1 Wait State Cycle 1 Wait State Cycle
@Byte 2
Bytes 12-13
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Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3
Note: When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles , the second access one cycle , the
third access FWS cycles, the f ourth access one cycle, etc.
Flash Access
Master Clock
Data To ARM 0-1
@Byte 0 @2
Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15
Bytes 0-3
2-3 6-7
@4
8-9 10-11
4-5
@8 @12
Bytes 4-7
3 Wait State Cycles
Buffer (32 bits)
ARM Request (16-bit)
Code Fetch
Bytes 8-11
3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles
@6 @10
12-13
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19.2.3 Write Operations
The internal memory area reserved for the embedded Flash can also be written through a write-only latch buffer.
Write operations take int o account only the 8 lowest address bits and thus wrap around within the internal memory
area address space and appear to be repeated 1024 times within it.
Write operations can be prevented by programming the Memory Protection Unit of the product.
Writing 8-bit and 16-bit data is not allowed and may lead to unpredicta ble data corruption.
Write operations are performed in the number of wait states equal to the number of wait states for read operations
+ 1, except for FW S = 3 (see “MC Flash Mode Register” on page 115).
19.2.4 Flash Commands
The EFC offers a command set to manage programming the memory flash, locking and unlocking lock sectors,
consecutive programming and locking, and full Flash erasing.
To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command num-
ber. As soon as the MC_FCR register is written, the FRDY flag is automatically cleared. Once the current
command is achieved, then the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit
FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.
All the commands are protected by the same keyword, which has to be written in the eight highest bits of the
MC_FCR register.
Writing MC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on
the memory plane; however, the PROGE flag is set in the MC_FSR register. This flag is automatically cleared by a
read access to the MC_FSR register.
When the current command writes or erases a page in a locked region, the command has no effect on the whole
memory plane; however, the LOCKE flag is set in the MC_FSR register. This flag is automatically cleared b y a read
access to the MC_FSR register.
Table 19-2. Set of Commands
Command Value Mnemonic
Write page 0x01 WP
Set Lock Bit 0x02 SLB
Write Page and Lock 0x03 WPL
Clear Lock Bit 0x04 CLB
Erase al l 0x08 EA
Set General-purpose NVM Bit 0x0B SGPB
Clear General-purpose NVM Bit 0x0D CGPB
Set Security Bit 0x0F SSB
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Figure 19-5. Command State Chart
In order to guar an te e va lid opera tio ns on th e Flash me mory , the fie ld Flash Microsec on d Cycle Number (F MCN) in
the Flash Mode Register MC_FMR must be correctly programmed (see “MC Flash Mode Register” on page 115).
19.2.4.1 Flash Programming
Several commands can be used to program the Flash.
The Flash technology requires that an erase must be done before programming. The entire memory plane can be
erased at the same time, or a page can be automatically erased by clearing the NEBP bit in the MC_FMR register
before writing the comm and in the MC_FCR register.
By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if it has been erased
before (see Figure 19-6).
Check if FRDY flag set No
Yes
Read Status: MC_FSR
Write FCMD and PAGENB in MC_FCR
Check if LOCKE flag set
Check if FRDY flag set No
Read Status: MC_FSR
Yes
Yes Locking region violation
No
Check if PROGE flag set Yes
No
Bad keyword violation and/or Invalid command
Command Successful
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Figure 19-6. Example of Partial Page Programming
The Partial Programming mode works only with 32-bit (or higher) boundaries. It cannot be used with boundaries
lower than 32 bits (8 or 16-bit for example).
After programming, the page (the whole lock region) can be locked to p revent miscellaneous write or erase
sequences. The lock bit can be automatically set after page progra mming using WPL.
Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size.
The latch buffer wraps around within the internal memory area address space and appears to be repeated by the
number of pages in it.
Note: Writi ng of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Data are written to the latch buffer before the programming command is written to the Flash Command Register
MC_FCR. The sequence is as follows:
• Write the full page, at any page address, with in the internal memory area address space using only 32-bit
access.
• Programming starts as soon as the page number and the programming command are written to the Flash
Command Register. The FRDY bit in the Flash Programming Status Register (MC_FSR) is automatically
cleared.
• When programming is completed, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If
an interrupt was enabled by setti ng the bit FRDY in MC_FMR, the interrupt line of the Me mory Controller is
activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register.
• Lock Error: The page to be programmed belongs to a locked region. A command must be previously run to
unlock the corresponding region.
19.2.4.2 Erase All Command
The entire memory can be erased if the Erase All Command (EA) in the Flash Command Register MC_FCR is
written.
Erase All operation is allowed only if there are no lock bits set. Thus, if at least one lock region is locked, the bit
LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written at 1 in MC_FMR, the
interrupt line rises.
Erase All Flash Programming of the second part of Page 7 Programming of the third part of Page 7
32 bits wide 32 bits wide 32 bits wide
16 words
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
...
CA FE CA FE
CA FE CA FE
CA FE CA FE
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF CA FE CA FE
CA FE CA FE
CA FE CA FE
DE CA DE CA
DE CA DE CA
DE CA DE CA
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
Step 1. Step 2. Step 3.
...
...
...
...
...
...
...
...
...
...
...
(NEBP = 1) (NEBP = 1)
16 words
16 words
16 words
Page 7 erased
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When programming is complete, th e bit FRDY bit in the Fla sh Progr amm ing St atus Registe r (MC_ FSR) rises. I f an
interrupt has been enabled by setting the bit FRDY in M C_FMR, the interrupt line of the Memory Controller is
activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register.
• Lock Error: At least one lock region to be erased is protected. The erase command has been refused and no
page has been era sed. A Clear Lock Bit command must be executed previously to unlock the corresponding
lock regions.
19.2.4.3 Lock Bit Protection
Lock bits are associated wit h several pag es in t he embe dd ed Fla sh me mor y p lane . Th is defin es lock regio ns in the
embedded Flash memory plane. They prevent writing/erasing protected pages.
After production, the device may h ave some embedded Flash lock r egions locked. These locked regions a re
reserved for a default application. Refer to the product definition section for the default embedded Flash mapping.
Locked sectors can be unlocked to be erased and then programmed with another application or other data.
The lock sequence is:
• The Flash Command register must be written with the following value:
(0x5A << 24) | (lockPageNumber << 8 & PAGEN) | SLB
lock PageNumber is a page of the corresponding lock region.
• When locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an
interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is
activated.
A progr amming e rror, where a bad keyword an d/or an invalid comma nd have bee n written in the MC_F CR regist er,
may be detected in the MC_FSR register after a programming seque nce.
It is possible to clear lock bits that were set previously. Then the locked region can be erased or programmed. The
unlock sequence is:
• The Flash Command register must be written with the following value:
(0x5A << 24) | (lockPageNumber << 8 & PAGEN) | CLB
lockPageNumb er is a page of the corresponding lock region.
• When the unlock completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises . If an
interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is
activated.
A programming error, where a bad keyword and/or an invalid command have been written in the MC_FCR register,
may be detected in the MC_FSR register after a programming seque nce.
The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR reads 0. The Lock
command programs the lock bit t o 0; the corresponding bit LOCKSx in MC_FSR reads 1.
Note: Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed.
19.2.4.4 General-purpose NVM Bits
General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not apply to EFC1 on
the SAM7S512.) These general-purpose bits are dedicated to protect other parts of the product. They can be set
(activated) or cleared individually. Refer to the product definition section for the general-purp ose NVM bit action.
The activation sequence is:
• Start the Set General Purpose Bit command (SGPB) by writing the Flash Command Regist er with the SEL
command and the number of the general-purpose bit to be set in the PAGEN field.
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• When the bit is set, the bit FRDY in the Flash Programming Statu s Register (MC_FSR) rises . If an interrupt has
been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activa ted.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register
• If the general-purpose bit number is great er than the total number of general-purpose bits, then the command
has no effect.
It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is:
• Start the Clear Gener al-purpose Bit command (CGPB) b y writing the Flash Command Reg ister with CGPB and
the number of the general-purpose bit to be cleared in the PAGEN field.
• When the clear completes , the bit FRDY in the Flash Prog ramming Status Register (MC_FSR) rises. If an
interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is
activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: a bad keyword and/or an invalid command have been written in the MC_FCR register
• If the number of the ge neral-purpose bit set in the PAGEN field is greater than the total number of general-
purpose bits, then the command has no effect.
The Clear General-purpose Bit command programs the general-purpose NVM bit to 0; the corresponding bit
GPNVM0 to GPNVMx in MC_FSR reads 0. The Set General-pur pose Bit co mma nd pr og ra ms the gen er al- pur po se
NVM bit to 1; the corresponding bit GPNVMx in MC_FSR reads 1.
Note: Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit command is
performed.
19.2.4.5 Security Bit
The goal of the secu rity bit is to prevent exte rnal access to the inter nal bus system. (Does not ap ply to EFC1 on
theSAM7S512.) JTAG, Fast Flash Programming and Flash Serial Test Interface features are disabled. Once set,
this bit can be reset only by an external hardware ERASE request to the chip. Refer to the product definition sec-
tion for the pin name that controls the ERASE. In this case, the full memory plane is erased an d all lock and
general-purpose NVM bits are cleared. The security bit in the MC_FSR is cleared only after these operations. The
activation sequence is:
• Start the Set Security Bit command (SSB) by writing the Flash Command Register.
• When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an
interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is
activated.
When the security bit is active, the SECURITY bit in the MC_FSR is set.
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19.3 Embedded Flash Controller (EFC) User Interface
The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00.
The SAM7S512 is equippe d with two EFCs, EFC0 and EFC1, as describe d in the Register Mapping ta bles and Register
descriptions that follow.
Table 19-3. (EFC0) Register Mapping
Offset Register Name Access Reset
0x60 MC Flash Mode Register MC_FMR Read-write 0x0
0x64 MC Flash Command Register MC_FCR Write-only –
0x68 MC Flash Status Register MC_FSR Read-only –
0x6C Reserved – – –
Table 19-4. (EFC1) Register Mapping
Offset Register Name Access Reset
0x70 MC Flash Mode Register MC_FMR Read-write 0x0
0x74 MC Flash Command Register MC_FCR Write-only –
0x78 MC Flash Status Register MC_FSR Read-only –
0x7C Reserved – – –
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19.3.1 MC Flash Mode Register
Register Name:MC_FMR
Access Type: Read-write
Offset: (EFC0) 0x60
Offset: (EFC1) 0x70
• FRDY: Flash Ready Interrupt Enable
0: Flash Ready does not generate an interrupt .
1: Flash Ready generates an interrupt.
• LOCKE: Lock Error Interrupt Enable
0: Lock Error does not generate a n interrupt.
1: Lock Error generates an int errupt.
• PROGE: Programming Error Interrupt Enable
0: Programming Error does not generate an interrupt.
1: Programming Error generates an interrupt.
• NEBP: No Erase Before Programming
0: A page erase is performed before programming.
1: No erase is performed before programming.
• FWS: Flash Wait State
This field defines the number of wait states for read and write operations:
• FMCN: Flash Microsecond Cycle Number
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
FMCN
15 14 13 12 11 10 9 8
–––––– FWS
76543210
NEBP – – – PROGE LOCKE – FRDY
FWS Read Operations Write Operations
0 1 cycle 2 cycles
1 2 cycles 3 cycles
2 3 cycles 4 cycles
3 4 cycles 4 cycles
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Before writing Non Volatile Memory bits (Lock bi ts, General Purpose NVM bi t and Securi ty bits), th is field mu st be set t o the
number of Master Clock cycles in one microsecond.
When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number
must be rounded up.
Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds.
Warning: In order to guarantee valid operations on the flash memory, the field Flash Microsecond Cycle Number (FMCN)
must be correctly programmed.
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19.3.2 MC Flash Command Register
Register Name:MC_FCR
Access Type: Write-only
Offset: (EFC0) 0x64
Offset: (EFC1) 0x74
• FCMD: Flash Command
This field defines the Flash commands:
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
–––––– PAGEN
15 14 13 12 11 10 9 8
PAGEN
76543210
–––– FCMD
FCMD Operations
0000 No command.
Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR.
0001 Write Page Command (WP):
Starts the programming of the page specified in the PAGEN field.
0010 Set Lock Bit Command (SLB):
Starts a set lock bit sequence of the lock region specified in the PAGEN field.
0011 Write Page and Lock Command (WPL):
The lock sequence of the lock region associated with the page specified in the field PAGEN
occurs automatically after completion of the programming sequence.
0100 Clear Lock Bit Command (CLB):
Starts a clear lock bit sequence of the lock region specified in the PAGEN field.
1000 Erase All Command (EA):
Starts the erase of the entire Flash.
If at least one page is locked, the command is cancelled.
1011 Set General-purpose NVM Bit (SGPB):
Activates the general-purpose NV M bit corresponding to the number specified in the PAGEN
field.
1101 Clear General Purpose NVM Bit (CGPB):
Deactivates the general-pur pose NVM bit corresponding to the number specified in the
PAGEN field.
1111 Set Security Bit Command (SSB):
Sets security bit.
Others Reserved.
Raises the Programming Error Status flag in the Flash Status Register MC_FSR.
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•PAGEN: Page Number
Note: Depending on the command, all the possible unused bits of PAGEN are meaningless.
• KEY: Write Protection Key
This field shou ld be writte n with the va lue 0x5A to enable the command defined b y the bit s of th e register . If th e field is writ-
ten with a different value, the write is not performed and no action is started.
Command PAGEN Description
Write Page Command PAGEN defines the page number to be written.
Write Pa ge and Lock Comm and PAGEN defines the page number to be written and its associated
lock region.
Erase All Command This field is meaningless
Set/Clear Lock Bit Command PAGEN defines one page number of the lock region to be locked or
unlocked.
Set/Clear General Purpose NVM Bit Command PAGEN defines the general-purpose bit number.
Set Security Bit Command This field is meaningless
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19.3.3 MC Flash Status Register
Register Name:MC_FSR
Access Type: Read-only
Offset: (EFC0) 0x68
Offset: (EFC1) 0x78
• FRDY: Flash Ready Status
0: The EFC is busy and the application must wait before running a new command.
1: The EFC is ready to run a new command.
• LOCKE: Lock Error Status
0: No programming of at least one locked lock region has happened since the last read of MC_FSR.
1: Programming of at least one locked lock region has happened since the last read of MC_FSR.
• PROGE: Programming Error Status
0: No invalid commands and no bad keywords were written in the Flash Command Register MC_FCR.
1: An invalid command and/or a bad keyword was/were written in the Flash Comma nd Register MC_FCR.
• SECURITY: Security Bit Status (Does not apply to EFC1 on the SAM7S512.)
0: The security bit is inactive.
1: The security bit is active.
• GPNVMx: General-purpose NVM Bit Status (Does not apply to EFC1 on the SAM7S512.)
0: The corresponding general-purpose NVM bit is inactive.
1: The corresponding general-purpose NVM bit is active.
• EFC LOCKSx: Lock Region x Lock Status
0: The corresponding lock region is not locked.
1: The corresponding lock region is locked.
LOCKS 8-15 do not apply to SAM7S128/321/32/161/16.
31 30 29 28 27 26 25 24
LOCKS15 LOCKS14 LOCKS13 LOCKS12 LOCKS11 LOCKS10 LOCKS9 LOCKS8
23 22 21 20 19 18 17 16
LOCKS7 LOCKS6 LOCKS5 LOCKS4 LOCKS3 LOCKS2 LOCKS1 LOCKS0
15 14 13 12 11 10 9 8
– – – – – – GPNVM1 GPNVM0
76543210
– – – SECURITY PROGE LOCKE – FRDY
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MC_FSR, LOCKSx Product Specific Map
The SAM7S512 manages 16 lock bits on EF0 and 16 on EFC1 = 32.
SAM7S512 SAM7S256 SAM7S128 SAM7S64 SAM7S321 SAM7S32 SAM7S161 SAM7S16 Denomination
32() 168168 8 8 8
Number of Lock
Bits
LOCKS0 LOCKS0 LOCKS0 LOCKS0 LOCKS0 LOCKS0 LOCKS0 LOCKS0 Lock Region 0
Lock Status
LOCKS1 LOCKS1 LOCKS1 LOCKS1 LOCKS1 LOCKS1 LOCKS1 LOCKS1 Lock Region 1
Lock Status
LOCKS2 LOCKS2 LOCKS2 LOCKS2 LOCKS2 LOCKS2 LOCKS2 LOCKS2 Lock Region 2
Lock Status
LOCKS3 LOCKS3 LOCKS3 LOCKS3 LOCKS3 LOCKS3 LOCKS3 LOCKS3 Lock Region 3
Lock Status
LOCKS4 LOCKS4 LOCKS4 LOCKS4 LOCKS4 LOCKS4 LOCKS4 LOCKS4 Lock Region 4
Lock Status
LOCKS5 LOCKS5 LOCKS5 LOCKS5 LOCKS5 LOCKS5 LOCKS5 LOCKS5 Lock Region 5
Lock Status
LOCKS6 LOCKS6 LOCKS6 LOCKS6 LOCKS6 LOCKS6 LOCKS6 LOCKS6 Lock Region 6
Lock Status
LOCKS7 LOCKS7 LOCKS7 LOCKS7 LOCKS7 LOCKS7 LOCKS7 LOCKS7 Lock Region 7
Lock Status
LOCKS8 LOCKS8 – LOCKS8 – – – – Lock Region 8
Lock Status
LOCKS9 LOCKS9 – LOCKS9 – – – – Lock Region 9
Lock Status
LOCKS10 LOCKS10 – LOCKS10 – – – – Lock Region 10
Lock Status
LOCKS11 LOCKS11 – LOCKS11 – – – – Lock Region 11
Lock Status
LOCKS12 LOCKS12 – LOCKS12 – – – – Lock Region 12
Lock Status
LOCKS13 LOCKS13 – LOCKS13 – – – – Lock Region 13
Lock Status
LOCKS14 LOCKS14 – LOCKS14 – – – – Lock Region 14
Lock Status
LOCKS15 LOCKS15 – LOCKS15 – – – – Lock Region 15
Lock Status
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20. Fast Flash Programming Interface (FFPI)
20.1 Overview
The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-volume programming
using a standard g an g prog ra mme r. The para llel in te rface is f ully ha ndsh aked and t he d evice is considere d to b e a
standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash func-
tionalities. The serial interface uses the standard IEEE 1149.1 JTAG protocol. It offers an optimized access to all
the embedded Flash functionalities.
Although the Fast Flash Programming Mode is a dedicat ed mode for high volume programming, this mode is not
designed for in-situ programming.
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20.2 Parallel Fast Flash Programming
20.2.1 Device Configuration
In Fast Flash Programming Mod e, the device is in a specific test mode. Only a certain set of pins is significant.
Other pins must be left unconnected.
Figure 20-1. SAM7S512/256/128/64/321/161 Parallel Programming Interface
Figure 20-2. SAM7S32/16 Parallel Pr ogramming Interface
NCMD PGMNCMD
RDY PGMRDY
NOE PGMNOE
NVALID PGMNVALID
MODE[3:0] PGMM[3:0]
DATA[15:0] PGMD[15:0]
XIN
TST
VDDIO PGMEN0
PGMEN1
0 - 50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
VDDFLASH
GND
GND
VDDIO
PGMEN2
NCMD PGMNCMD
RDY PGMRDY
NOE PGMNOE
NVALID PGMNVALID
MODE[3:0] PGMM[3:0]
DATA[7:0] PGMD[7:0]
XIN
TST
VDDIO PGMEN0
PGMEN1
0 - 50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
VDDFLASH
GND
GND
VDDIO
PGMEN2
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Notes: 1. DATA [7:0] pertai ns to the SAM7S32/16.
2. PGMD[7:0] pertains to the SAM7S32/16.
Table 20-1. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDFLASH Flash Power Supply Power
VDDIO I/O Lines P ower Supply Po wer
VDDCORE Core Po wer Supply Po wer
VDDPLL PLL Power Supply Power
GND Ground Ground
Clocks
XIN Main Clock Input.
This input can be tied to GND. In this case, the
device is clocked by the internal RC oscillator. Input 32KHz to 50MHz
Test
TST Test Mode Select Input High Must be connected to VDDIO
PGMEN0 Test Mode Select Input High Must be connected to VDDIO
PGMEN1 Test Mode Select Input High Must be connected to VDDIO
PGMEN2 Test Mode Select Input Low Must be connected to GND
PIO
PGMNCMD Valid command available Input Low P ulled-up input at reset
PGMRDY 0: Device is busy
1: Device is ready for a new command Output High Pulled -u p input at reset
PGMNOE Output Enable (active high) Input Low Pulled-up input at reset
PGMNVALID 0: DATA[15:0] or DATA[7:0](1) is in input mode
1: DATA[15:0] or DATA[7:0](1) is in output mode Output Low Pulled-up input at reset
PGMM[3:0] Specifies DATA type (See Table 20-2) Input Pulled-up input at reset
PGMD[15:0 ] or [7:0](2) Bi-directional data bus Input/Output Pulled-up input at reset
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20.2.2 Signal Names
Depending on the MODE settings, DATA is latched in diffe rent internal registers.
When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] or DATA[7:0] signals) is stored in
the command register.
Note: DATA[7:0] pertains to the SAM7S32/16.
Notes: 1. DATA[7:0] pertains to the SAM7S32/16.
2. Applies to SAM7S512.
Table 20-2. Mode Coding
MODE[3:0] Symbol Data
0000 CMDE Command Register
0001 ADDR0 Address Register LSBs
0010 ADDR1
0011 ADDR2
0100 ADDR3 Address Register MSBs
0101 DATA Data Register
Default IDLE No register
Table 20-3. Command Bit Coding
DATA[15:0]
DATA[7:0](1) Symbol Command Executed
0x0011 READ Read Flash
0x0012 WP Write Page Flash
0x0022 WPL Write Page and Lock Flash
0x0032 EWP Erase Page and Write Page
0x0042 EWPL Erase Page and Write Page then Lock
0x0013 EA Erase All
0x0014 SLB Set Lock Bit
0x0024 CLB Clear Lock Bit
0x0015 GLB Get Lock Bit
0x0034 SGPB Set General Purpose NVM bit
0x0044 CGPB Clear General Purpose NVM bit
0x0025 GGPB Get General Purpose NVM bit
0x0054 SSE Set Security Bit
0x0035 GSE Get Security Bit
0x001F WRAM Write Memory
0x0016 SEFC Select EFC Controller(2)
0x001E GVE Get Version
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20.2.3 Entering Programming Mode
The following algorithm puts the device in Parallel Programming Mode:
• Apply GND, VDDIO , VDDCORE, VDDFLASH and VDDPLL.
• Apply XIN clock within TPOR_RESET if an external clock is available.
•Wait for T
POR_RESET
• Star t a read or write handshaking.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock (> 32
kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher
frequency on XIN speeds up the programmer handshake.
20.2.4 Programmer Handshaking
An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY
signal set), the progr ammer sta rts t he handsh ake by cl earing the NCMD si gnal. The h andsh aking is a chieved once
NCMD signal is high and RDY is high.
20.2.4.1 Write Handshaking
For details on the write handshaking sequence, refer to Figure 20-3, Figure 20-4 and Table 20-4.
Figure 20-3. SAM7S512/256/128/64/321/16 1Parallel Programming Timing, Write Sequence
Figure 20-4. SAM7S32/16 Parallel Programming Timing, Write Sequence
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
NCMD
RDY
NOE
NVALID
DATA[7:0]
MODE[3:0]
1
2
3
4
5
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20.2.4.2 Read Handshaking
For details on the read handshaking sequence, refer to Figur e 20-5, Figure 20-6 and Table 20-5.
Figure 20-5. SAM7S542/256/128/321/161 Paralle l Programming Timing, Read Sequence
Figure 20-6. SAM7S32/16 Parallel Programming Timing, Read Sequence
Table 20-4. Write Handshake
Step Programmer Action Devi ce Acti on Data I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latches MODE and D ATA Input
3 Waits for RDY low Clears RDY signal Input
4 Releases MODE and DATA signals Executes command and polls NCMD high Input
5 Sets NCMD signal Executes command and polls NCMD high Input
6 Waits for RDY high Sets RDY Input
NCMD
RDY
NOE
NVALID
DATA[15:0]
MODE[3:0]
1
2
3
4
5
6
7
9
8
ADDR
Adress IN Z Data OUT
10
11
XIN
12
13
NCMD
RDY
NOE
NVALID
DATA[7:0]
MODE[3:0]
1
2
3
4
5
6
7
9
8
ADDR
Adress IN Z Data OUT
10
11
XIN
12
13
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Table 20-5. Read Handshake
Step Programmer Action Device Action DATA I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latch MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
4 Sets DATA signal in tristate Waits for NOE Low Input
5 Clears NOE signal Tristate
6 Waits for NVALID low Sets DATA bus in output mode and outputs the
flash cont en ts. Output
7 Clears NVALID signal Output
8 Reads value on DATA Bus Waits for NOE high Output
9 Sets NOE signal Output
10 Waits for NVALID high Sets DATA bus in input mode X
11 Sets DATA in output mode Sets NVALID signal Input
12 Sets NCMD signal W aits for NCMD high Input
13 Waits for RDY high Sets RDY signal Input
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20.2.5 Device Operations
Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page
126. Each command is driven by the programmer through the parallel interface running several read/write hand-
shaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command
after a write automatically flushes the load buffer in the Flash.
In the following tables, 21-6 through 21-18
• D ATA[15:0] pertains to SAM7S512/256/128/64/321/161
• D ATA[7:0] pertains to SAM7S32/16
20.2.5.1 Flash Read Command
This command is used to read the contents of the Flash memory. The read command can start at any valid
address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an inter-
nal address buffer is automatically increased.
Table 20-6. Read Command
Step Handshake Se quence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE READ
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Read handshaking DATA *Memory Address++
5 Read handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handsha king ADDR1 Memor y Addre s s
n+2 Read handshaking DATA *Memory Address++
n+3 Read handshaking DATA *Memory Address++
... ... ... ...
Table 20-7. Read Command
Step Handshake Sequence MODE[3:0] DATA[7:0]
1 Write handshaking CMDE READ
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking ADDR2 Memory Address
5 Write handshaking ADDR3 Memory Address
6 Read handshaking DATA *Memory Address++
7 Read handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handsha king ADDR1 Memor y Addre s s
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20.2.5.2 Flash Write Command
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corre-
sponds to a Flash memory page. The load buffer is automatically flushed to th e Flash:
• before access to any page other than the curren t on e
• when a new command is validated (MODE = CMDE)
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an inter-
nal address buffer is automatically increased.
n+2 Write handsha king ADDR2 Memor y Addre s s
n+3 Write handsha king ADDR3 Memor y Addre s s
n+4 Read handshaking DATA *Memory Address++
n+5 Read handshaking DATA *Memory Address++
... ... ... ...
Table 20-7. Read Command (Continue d)
Step Handshake Sequence MODE[3:0] DATA[7:0]
Table 20-8. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WP or WPL or EWP or EWPL
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Memory Address++
5 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handsha king DATA *Memory Address++
n+3 Write handsha king DATA *Memory Address++
... ... ... ...
Table 20-9. Write Command
Step Handshake Sequence MODE[3:0] DATA[7:0]
1 Write handshaking CMDE WP or WPL or EWP or EWPL
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking ADDR2 Memory Address
5 Write handshaking ADDR3 Memory Address
6 Write handshaking DATA *Memory Address++
7 Write handshaking DATA *Memory Address++
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The Flash command Wr ite Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock
bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of
the lock region using a Flash write and lock command .
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before
programming the load buffer, the page is erased.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.
20.2.5.3 Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the
erase command is aborted and no page is erased.
20.2.5.4 Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command
(SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the com-
mand. When bit 0 of the bit mask is set, then the first lock bit is activated.
In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the
EA command.
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handshaking ADDR2 Memory Address
n+3 Write handshaking ADDR3 Memory Address
n+4 Write handshaking DATA *Memory Address++
n+5 Write handshaking DATA *Memory Address++
... ... ... ...
Table 20-9. Write Command (Continued)
Step Handshake Sequence MODE[3:0] DATA[7:0]
Table 20-10. Full Erase Command
Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0]
1 Write handshaking CMDE EA
2 Write handshaking DATA 0
Table 20-11. Set and Clear Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0]
1 Write handshaking CMDE SLB or CLB
2 Write handshaking DATA Bit Mask
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Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask
is set..
20.2.5.5 Flash General-purpose NVM Comm a nd s
General-purpose NVM bits (GP NVM bits) can be set usin g the Set GPNVM command (SGPB). This command
also activates GP NVM bits. A bit mask is p rovided as arg ument to the comman d. When bit 0 of t he bit mask is set ,
then the first GP NVM bit is activated.
In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. All the gener al-
purpose NVM bits are also cleared by the EA command. The general-purpose NVM b it is deactivated when the
corresponding bit in the pattern value is set to 1.
General-purpose NVM b its can be read u sing the Get GPNVM Bit command (GGPB). The nth GP NVM bit is active
when bit n of the bit mas k is set..
20.2.5.6 Flash Security Bit Comma nd
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash
programming is d isabled . No oth er comma nd can b e run. An e vent on the Erase pin can er ase the secur ity bit on ce
the contents of the Flash have been erased.
The SAM7S512 security bit is controlled by the EFC0. To use the Set Security Bit command, the EFC0 must be
selected using the Select EFC command
Once the security bit is s et, it is not p ossible to access FFPI. The only way to erase t he sec urity b it is to erase the
Flash.
In order to erase the Flash, the user must perform the following:
Table 20-12. Get Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0]
1 Write handshaking CMDE GLB
2 Read handshaking DATA Lock Bit Mask Status
0 = Lock bi t is cleare d
1 = Loc k bi t i s set
Table 20-13. Set/Clear GP NVM Command
Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0]
1 Write handshaking CMDE SGPB or CGPB
2 Write handshaking DATA GP NVM bit pattern value
Table 20-14. Get GP NVM Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0]
1 Write handshaking CMDE GGPB
2 Read handshaking DATA GP NVM Bit Mask Status
0 = GP NVM bit is cleared
1 = GP NVM bit is set
Table 20-15. Set Security Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SSE
2 Write handshaking DATA 0
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• Power-off the chip
• Power-on the chip with TST = 0
• Assert Erase during a period of more than 220 ms
• Power-off the chip
Then it is possible o return to FFPI mode and check that Flash is erased.
20.2.5.7 SAM7S512 Select EFC Command
The commands WPx, EA, xLB, xFB are exe cuted using the current EFC controller. The defa ult EFC controller is
EFC0. The Select EFC command (SEFC) allows selection of the current EFC controller.
20.2.5.8 Memory Wr ite Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
Table 20-16. Select EFC Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshakin g CMDE SEFC
2 Write handshakin g DATA 0 = Select EFC0
1 = Select EFC1
Table 20-17. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WRAM
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Memory Address++
5 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handsha king DATA *Memory Address++
n+3 Write handsha king DATA *Memory Address++
... ... ... ...
Table 20-18. Write Command
Step Handshake Sequence MODE[3:0] DATA[7:0]
1 Write handshaking CMDE WRAM
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking ADDR2 Memory Address
5 Write handshaking ADDR3 Memory Address
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20.2.5.9 Get Version Com m a nd
The Get Version (GVE) command retrieves the version of the FFPI interface.
6 Write handshaking DATA *Memory Address++
7 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Wr ite handshaking ADDR1 Memory Address
n+2 Wr ite handshaking ADDR2 Memory Address
n+3 Wr ite handshaking ADDR3 Memory Address
n+4 Write handshaking DATA *Memory Address++
n+5 Write handshaking DATA *Memory Address++
... ... ... ...
Table 20-18. Write Command (Continued)
Step Handshake Sequence MODE[3:0] DATA[7:0]
Table 20-19. Get Version Command
Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0]
1 Write handshaking CMDE GVE
2 Write handshaking DATA Version
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20.3 Serial Fast Flash Programming
The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and
Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a
description of the TAP controller states.
In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG inter-
face of the device.
20.3.1 Device Configuration
In Serial Fast Flash Programming Mode, the device is in a specific test mode. Only a distinct set of pins is signifi-
cant. Other pins must be left unconnected.
Figure 20-7. Serial Programming
TDI
TDO
TMS
TCK
XIN
TST
VDDIO PGMEN0
PGMEN1
0-50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
VDDFLASH
GND
VDDIO
GND PGMEN2
Table 20-20. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDFLASH Flash Power Supply Power
VDDIO I/O Lines P ower Supply Po wer
VDDCORE Core Po wer Supply Power
VDDPLL PLL Power Supply Power
GND Ground Ground
Clocks
XIN
Main Clock Input.
This input can be tie d to GND. In thi s
case, the device is cloc ked by the internal
RC oscillator.
Input 32 kHz to 50 MHz
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20.3.2 Entering Serial Programming Mode
The following algor ith m puts the devic e in Seri al Pro gra mm in g Mo d e:
• Apply GND, VDDIO , VDDCORE, VDDFLASH and VDDPLL.
• Apply XIN clock within TPOR_RESET + 32(TSCLK) if an external clock is available.
•Wait for T
POR_RESET.
• Reset the TAP controller clocking 5 TCK pulses with TMS set.
• Shift 0x2 into the IR register (IR is 4 bits long, LSB first) without going through the Run-Test-Idle state.
• Shift 0x2 into the DR reg iste r (DR is 4 bits long , LSB firs t) with o ut goin g th ro ug h th e Ru n- Te st -Id l e state.
• Shift 0xC into the IR register (IR is 4 bits long, LSB first) without goin g through the Run-Test-Idle state.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock (> 32
kHz) is connected to XIN, then the de vice will s witch on the external clock. Else, XIN input is not considered. An higher
frequency on XIN speeds up the programmer handshake.
20.3.3 Read/Write Handshake
The read/write handshake is done by carrying out read/write operations on two registers of the device that are
accessible through the JTAG:
• Debug Comms Control Register: DCC R
• Debug Comms Data Register: DCDR
Test
TST Test Mode Select Input High Must be connected to VDDIO.
PGMEN0 Test Mode Select Input High Must be conn ected to VDDIO
PGMEN1 Test Mode Select Input High Must be conn ected to VDDIO
PGMEN2 Test Mode Select Input Low Mu st be connected to GND
JTAG
TCK JTAG TCK Input - Pulled-up input at reset
TDI JTAG Test Data In Input - Pulled-up inpu t at reset
TDO JTAG Test Data Out Output -
TMS JTAG Test Mode Sele ct Input - Pulled-up inpu t at reset
Table 20-20. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
Table 20-21. Reset TAP Controller and Go to Select-DR-Scan
TDI TMS TAP Controller State
X1
X1
X1
X1
X 1 Test-Logic Reset
X 0 Run-Test/Idle
Xt 1 Select-DR-Scan
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Access to these registe rs is done t hr ough t h e TAP 38-b it DR re giste r compr isin g a 32-bit da ta fiel d, a 5 -b it a ddr ess
field and a read/write bit. The data to be written is scanned into the 32-bit data field with the ad dre ss of the register
to the 5-bit addr ess fie ld an d 1 to t he read / writ e bit. A regist er is r ead by scan ning its ad dr ess into th e ad dress f ield
and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data.
Refer to the ARM7TDMI reference manuel for more information on Comm channel operations.
Figure 20-8. TAP 8-bit DR Register
A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE 1149.1 for more
details on JTAG operations.
• The address of the Debug Comms Control Register is 0x04.
• The address of the Debug Comm s Data Register is 0x05.
The Deb ug Comms Control Register is read-only and allo ws synchro nized h andshaking betw een the processor
and the debugger.
– Bit 1 (W): Denot es whether the progr ammer can read a d ata through th e Debug Comms Data Regist er .
If the device is busy W = 0, then the programmer must poll until W = 1.
– Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data Register . If R
= 1, data previously placed there through the scan chain has not been collected b y the device and so
the programmer must wait.
The write handshake is done by polling the Debug Comms Control Register until the R bit is cleared. Once cleared,
data can be written to the Debug Comms Data Register.
The read handshake is done by polling the Debug Comms Control Register until the W bit is set. Once set, data
can be read in the Debu g Co mm s Da ta Regis te r.
20.3.4 Device Operations
Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page
126. Commands are run by th e programmer through the serial interface that is readin g and writing the Debug
Comms Registers.
TDI TDO
40
r/w Address 31 Data 0
Address
Decoder
Debug Comms Control Register
Debug Comms Data Register
32
5
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20.3.4.1 Flash Read Command
This command is used to read the Fla sh content s. The me mory map is accessible t hrough this command. Memory
is seen as an array of words (32-bit wide). The re ad command can start at any valid address in the memory plane.
This address must be word-aligned. The address is automatically incremented.
20.3.4.2 Flash Write Command
This command is used to write the Flash contents. The address transmitted must be a va lid Flash address in the
memory plane.
The Flash memory p lane is organized into several pages. Data to be written is stor ed in a load buffer that corre-
sponds to a Flash memory page. The load buffer is automatically flushed to th e Flash:
• before ac cess to any page than the current one
• at the end of the number of words transmitted
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an inter-
nal address buffer is automatically increased.
Flash Write Page and Lock command (WPL) is equiv alent t o the Flash Write Co mmand. How ever, t he loc k bit is
automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the pro-
grammer writes to the first pages of the lock region using Flash write commands and writes to the last page of the
lock region using a Flash write and lock com m an d .
Flash Erase Page and Write command (EWP) is equivalent to the Flash Write Command. However, before pro-
gramming the load buffer, the page is erased.
Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL comm ands .
20.3.4.3 Flash Full Erase Command
This command is used to erase the Flash memory planes.
Table 20-22. Read Command
Read/Write DR Data
Write (Number of Words to Read) << 16 | READ
Write Address
Read Memory [address]
Read Memory [address+4]
... ...
Read Memory [address+(Number of Words to Read - 1)* 4]
Table 20-23. Write Command
Read/Write DR Data
Write (Number of Words to Write) << 16 | (WP or WPL or EWP or EWPL)
Write Address
Write Memory [address]
Write Memory [address+4]
Write Memory [address+8]
Write Memory [address+(Number of Words to Write - 1)* 4]
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All lock bits must be deactivated be fore using the Full Erase command. This can be done by using the CLB
command.
20.3.4.4 Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command
(SLB). With this command, several lock bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the
first lock bit and so on.
In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits can also be cleared by
the EA command.
Lock bits can be read using Get Lock Bit command (GLB). When a bit set in the Bit Mask is returned, then the cor-
responding lock bit is active.
20.3.4.5 Flash General-purpose NVM Comm a nd s
General-purpos e NVM bits (GP NVM) can be set with the Set GPNVM command (SGPB). Using this command,
several GP NVM bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the first GPNVM bit and
so on.
In the same way, the Clear GPNVM command (CGPB) is used to clear GP NVM bits. All th e general-purp ose NVM
bits are also cleared by the EA command.
GP NVM bits can be read using Get GPNVM Bit command (GGPB). When a bit set in the Bit Mask is returned,
then the corresponding GPNVM bit is set.
Table 20-24. Full Erase Command
Read/Write DR Data
Write EA
Table 20-25. Set and Clear Lock Bit Command
Read/Write DR Data
Write SLB or CLB
Write Bit Mask
Table 20-26. Get Lock Bit Command
Read/Write DR Data
Write GLB
Read Bit Mask
Table 20-27. Set and Clear General-purpose NVM Bi t Command
Read/Write DR Data
Write SGPB or CGPB
Write Bit Mask
Table 20-28. Get General-purpose NVM Bit Command
Read/Write DR Data
Write GGPB
Read Bit Mask
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20.3.4.6 Flash Security Bit Comma nd
Security bits can be set usin g Set Security Bit command (SSE). Once the security bit is active, the Fast Flash pro-
gramming is disabled. No other command can be run. Only an event on the Erase pin can erase the security bit
once the contents of the Flash have bee n erased.
The SAM7S512 security bit is controlled by the EFC0. To use the Set Security Bit command, the EFC0 must be
selected using the Select EFC co mmand.
Once the security bit is s et, it is not p ossible to access FFPI. The only way to erase t he sec urity b it is to erase the
Flash.
In order to erase the Flash, the user must perform the following:
• Power-off the chip
• Power-on the chip with TST = 0
• Assert Erase during a period of more than 220 ms
• Power-off the chip
Then it is possible to ret urn to FFPI mode and check that Flash is erased.
20.3.4.7 SAM7S512 Select EFC Command
The commands WPx, EA, xLB, xFB are exe cuted using the current EFC controller. The defa ult EFC controller is
EFC0. The Select EFC command (SEFC) allows selection of the current EFC controller.
Table 20-29. Set Security Bit Command
Read/Write DR Data
Write SSE
Table 20-30. Select EFC Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SEFC
2 Write handshaking DATA 0 = Select EFC0
1 = Select EFC1
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20.3.4.8 Memory Wr ite Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. An internal address buffer is automati-
cally increased.
20.3.4.9 Get Version Com m a nd
The Get Version (GVE) command retrieves the version of the FFPI interface.
Table 20-31. Write Command
Read/Write DR Data
Write (Number of Words to Write) << 16 | (WRAM)
Write Address
Write Memory [address]
Write Memory [address+4]
Write Memory [address+8]
Write Memory [address+(Number of Words to Write - 1)* 4]
Table 20-32. Get Version Command
Read/Write DR Data
Write GVE
Read Version
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21. SAM7 Boot Program
21.1 Description
The Boot Program integrates different programs permitting download and/or upload into the different memories of
the product.
First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port.
SAM-BA® Boot is then executed. It waits for transactions either on the USB device or on the DBGU serial port.
21.2 Flow Diagram
The Boot Program implements the algorithm shown in Figure 21-1 or Figure 21-2.
Figure 21-1. Boot Program Algorithm Flow Diagram with USB
Figure 21-2. Boot Program Algorithm Flow Diagram without USB
Device
Setup
AutoBaudrate
Sequence Successful ?
Run SAM-BA Boot Run SAM-BA Boot
USB Enumeration
Successful ?
Yes Yes
No
No
Device
Setup Run SAM-BA Boot
AutoBaudrate
Sequence Successful ? Yes
No
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21.3 Device Initialization with USB
Initialization follows the steps described below:
1. FIQ initialization
1. Stack setup for ARM supervisor mode
2. Setup the Embedded Flash Controller
3. External Clock detection
4. Main oscillator frequency detection if no external clock detected
5. Switch Master Clock on Main Oscillator
6. Copy code into SRAM
7. C variable initialization
8. PLL setup: PLL is initia lized to gene rate a 48 MHz clock necessary to use the USB Device
9. Disable of the Watchdog and enable of the user reset
10. Initialization of the USB Device Por t
11. Jump to SAM-BA Boot sequence (see “SAM-BA Boot” on page 145)
21.4 Device Initialization without USB
Initialization follows the steps described below:
1. FIQ initialization
1. Stack setup for ARM supervisor mode
2. Setup the Embedded Flash Controller
3. External Clock detection
4. Main oscillator frequency detection if no external clock detected
5. Switch Master Clock on Main Oscillator
6. Copy code into SRAM
7. C variable initialization
8. PLL setup: PLL is initia lized to gene rate a 48 MHz clock
9. Disable of the Watchdog and enable of the user reset
10. Jump to SAM-BA Boot sequence (see “SAM-BA Boot” below)
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21.5 SAM-BA Boot
The SAM-BA boot principle is to:
– Check if USB Device enumeration has occurred
– Check if the Auto Baudrate sequence has succeeded (see Fig ure 21-3)
Figure 21-3. Auto Baudrate Flow Diagram
Device
Setup
Character '0x80'
received ? No
Yes
Character '0x80'
received ? No
Yes
Character '#'
received ?
Yes
Run SAM-BA Boot
Send Character '>'
No
1st measurement
2nd measurement
Test Communication
UART operational
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– Once the communication interface is identified, the application runs in an infinite loop waiting for
different commands as shown in Table 21-1.
• Write commands: Write a byte (O), a halfword (H) or a word (W) to the target.
–Address: Address in hexadecimal.
–Value: Byte, halfword or word to write in hexadecimal.
–Output: ‘>’.
• Read commands: Read a byte (o), a halfword (h) or a word (w) from the target.
–Address: Address in hexadecimal
–Output: The byte, halfword or word read in hexadecimal following by ‘>’
• Send a file (S): Send a file to a specified address
–Address: Address in hexadecimal
–Output: ‘>’.
Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command
execution.
• Receive a file (R): Receive data into a file from a specified address
–Address: Address in hexadecimal
–NbOfBytes: Number of bytes in hexadecimal to re ceive
–Output: ‘>’
•Go (G): Jump to a specified address and execute the code
–Address: Address to jump in hexadecimal
–Output: ‘>’
• Get Version (V): Return the SAM-BA boot version
–Output: ‘>’
Table 21-1. Commands Available through the SAM-BA Boot
Command Action Argument(s) Example
Owrite a by te Address, Value# O200001,CA#
oread a byte Address,# o200001,#
Hwrite a half wo rd Address , Value# H200002,CAFE#
hread a half word Address,# h200002,#
Wwrite a word Address, Value# W200000,CAFEDECA#
wread a word Address,# w200000,#
Ssend a file Address,# S200000,#
Rreceive a file Address, NbOfBytes# R200000,1234#
Ggo Address# G200200#
Vdisplay version No argument V#
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21.5.1 DBGU Serial Port
Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this
protocol can be used to send the application file to the target. The size of the binary file to send depends on the
SRAM size embedded in the pr oduct. In all cases, the size of the binary file must be lower than the SRAM size
because the Xmodem protocol requires some SRAM memory to work.
21.5.2 Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. Th is protocol uses a two-character CRC-16 to guar-
antee detection of a maximum bit err or.
Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each
block of the transfer looks like:
<SOH><blk #><255-blk #><--128 data bytes--><checksum> in which:
– <SOH> = 01 hex
– <blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
– <255-blk #> = 1’s complement of the blk#.
– <checksum> = 2 bytes CRC1 6
Figure 21-4 shows a transmission using this protocol.
Figure 21-4. Xmodem Transfer Example
21.5.3 USB Device Port
A 48 MHz USB clock is necessary to use the USB Device port. It has been pro grammed earlier in the device initial-
ization procedure with PLLB configuration.
Host Device
SOH 01 FE Data[128] CRC CRC
C
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
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The device uses the USB commu nication device class (CDC) dr ivers to take advant age of the in stalled PC RS- 232
software to talk over the USB. T he CDC class is implemented in all releases of Windows®, from Windows98SE to
WindowsXP. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN
modems and virtual COM por ts.
The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host
operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence
between vendor ID and product ID.
21.5.3.1 Enumeration Process
The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the
device through the control endpoint. The device handles standard requests as defined in the USB Specif ication.
The device also handles some class requests defined in the CDC class.
Unhandled requests are STALLed.
21.5.3.2 Communication Endpoints
There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-
byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the
host through the endpoint 1. If required, the message is split by the host into several data payloads by the host
driver.
If the command requir es a response, the host can send IN transactio ns to pick up the response.
Table 21-2. Handled Standard Requests
Request Definition
GET_DESCRIPTOR Returns the current device configuration value.
SET_ADDRESS Sets the devic e address for all future device access.
SET_CONFIGURATION Sets the device configuration.
GET_CONFIGURATION Retur ns the current device configuration value.
GET_STATUS Retur ns status for the specified recipient.
SET_FEATURE Used to set or enable a specific feature.
CLEAR_FEATURE Used to clear or disable a specific feature.
Table 21-3. Handled Class Requests
Request Definition
SET_LINE_CODING Configures DTE rate, stop bits, parity and number of
character bits.
GET_LINE_CODING Requests current DTE rate, stop bits, parity and number
of character bits.
SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE
de vice is no w pre s e n t.
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21.6 Hardware and Software Constraints
• SAM-BA boot copies itse lf in the SRAM and uses a block of internal SRAM for variables and stacks. The
remaining available sizes for the user codes are as follows: 57344 b yt es for SAM7S512, 57344 bytes for
SAM7S256, 24576 b ytes f or SAM7S128, 8 192 b ytes f or SAM7S64, 204 8 b ytes f or SAM7S321 and SAM7S32,
3840 bytes for SAM7S161 and SAM7S16.
• USB requirements: (Does not pertain to SAM7S32/16)
– 18.432 MHz Quartz
– PIOA16 dedicated to the USB Pull-up
Table 21-4. User Area Addresses
Device Start Address End Address Size (bytes)
SAM7S512 0x202000 0x210000 57344
SAM7S256 0x202000 0x210000 57344
SAM7S128 0x202000 0x208000 24576
SAM7S64 0x202000 0x204000 8192
SAM7S321 0x202000 0x210000 2048
SAM7S32 0x201400 0x201C00 2048
SAM7S161 0x200000 0200F00 3840
SAM7S16 0x200000 0200F00 3840
Table 21-5. Pins Driven during Boot Program Execution
Peripheral Pin PIO Line
DBGU DRXD PA9
DBGU DTXD PA10
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22. Peripheral DMA Controller (PDC)
22.1 Overview
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART,
USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Contr oller avoids processor
intervention and removes the processor interrupt-handling overhead. This significantly reduces the number of
clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and
makes it more power efficient.
The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in
the pair is dedicated to th e receivin g channel and one to the tran smitting channel of each UART, USART, SSC and
SPI.
The user interface of a PDC channel is integrated in the memory spa ce of each peripheral. It co ntains:
• two 32-bit memory pointer registers (send and receive)
• two 16-bit transfer count registers (send and r eceive)
• two 32-bit registers for next memory pointer (send and receive)
• two 16-bit registe rs for next transfer count (send and re ce ive)
The peripheral triggers PDC transfers using transmit and receive signals. When the programmed data is trans-
ferred, an end of transfer interrup t is generated by the corresponding peripheral.
22.2 Block Diagram
Figure 22-1. Block Diagram
Control
PDC Channel 0
PDC Channel 1
THR
RHR
Control Status & Control
Peripheral Peripheral DMA Controller
Memory
Controller
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22.3 Functional Description
22.3.1 Configuration
The PDC channels user interface enables the user to configure and control the data transfers for each channel.
The user interface of a PDC chan nel is int egra ted in to the user int erf ace of t he p eriph era l (o ff set 0x10 0) , which it is
related to.
Per peripheral, it contains four 32-bit Po inter Registers (RPR, RNPR, TPR, and TNPR) and four 16-bit Counte r
Registers (RCR, RNCR, TCR, and TNCR).
The size of the buf fer (numb er of transfe rs) is configure d in an interna l 16-bit transfer counter regist er, and it is pos-
sible, at any moment, to read the number of transfers left for each channel.
The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to
access in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the
number of remaining transfers. The PDC has dedicated status registers which indicate if the transfer is enabled or
disabled for each channel. The sta tus for each channel is located in the p eripheral stat us register. Transfers can be
enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register. These
control bits enable reading the pointer and counter registers safely with out any risk of their changing between both
reads.
The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX, RXBUFF, and
TXBUFE).
ENDRX flag is set when the PERIPH_RCR register reaches zero.
RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
ENDTX flag is set when the PERIPH_TCR register reaches zero.
TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
These status flags are described in the peripheral status register.
22.3.2 Memory Pointers
Each peripheral is connected to the PDC by a receiver data channel and a transmit ter data channel. Each channel
has an interna l 32-bit memory poin ter. Each memory poin ter points to a loca tion anywhere in the m emory space
(on-chip memory or external bus inte rface memory).
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4,
respectively for peripher al transfers.
If a memory pointer is reprogrammed while the PDC is in operation, the transfer address is changed, and the PDC
performs transfers using the new a ddress.
22.3.3 Transfer Counters
There is one inter nal 16-bit tr ansfer count er for each channel used to count the size of the block a lready transferred
by its associated channel. These counters are decremented after each data transfer. When the counter reaches
zero, the transfer is complete and the PDC stops transferring data.
If the Next Counte r Register is equal to zero , the PDC disables the trig ger while activating the re lated peripheral
end flag.
If the counter is repr ogrammed while the PDC is operating , the number of transfers is updated and the PDC count s
transfers from th e ne w valu e .
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Programming the Next Coun ter/Pointer re gisters chains the buf fers. T he counte rs are d ecremente d afte r each da ta
transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are
loaded into the Counter/Pointer registers in order to re-enable the triggers.
For each channel, two status bits indicate the end of the current buffer (ENDRX, ENDTX) and the end of both cur-
rent and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can
trigger an interrupt request to the AIC.
The peripheral end flag is automatically cleared when one of the counter-registers (Counter or Next Counter Reg-
ister) is written.
Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.
22.3.4 Data Transfers
The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.
When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then
requests access to th e system bus. Wh en access is grant ed, the PDC st arts a read of the p eripheral Receive Hold-
ing Register (RHR) and then triggers a wr ite in the memory.
After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decre-
mented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops.
The same procedure is follo wed, in reverse, for t ransmit transfers.
22.3.5 Priority of PDC Transfer Requests
The Peripheral DMA Con troller handles transfer requests from the channel according to priorities fixed for each
product.These pr iorities are defined in the product datasheet.
If simultaneous req uests of the same type (rece iver or transmitter) oc cur on identical peripherals, th e priority is
determined by the numbering of the peripherals.
If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers
are handled first and then followed by transmitter requests.
22.4 Peripheral DMA Controller (PDC) User Interface
Note: 1. PERIPH: Ten registers are mapped in the peripheral memor y space at the same offset. These can be defined by the user
according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc).
Table 22-1. Register Mapping
Offset Register Register Name Access Reset
0x100 Receive Pointer Register PERIPH(1)_RPR Read-write 0x0
0x104 Receive Counter Register PERIPH_RCR Read-write 0x0
0x108 Transmit Pointer Register PERIPH_TPR Read-write 0x0
0x10C Transmit Counter Register PERIPH_TCR Read -write 0x0
0x110 Receive Next Pointer Register PERIPH_RNPR Read-write 0x0
0x114 Receive Next Counter Register PERIPH_RNCR Read -write 0x0
0x118 Transmit Next Pointer Register PERIPH_TNPR Read-write 0x0
0x11C Transmit Next Counter Register PERIPH_TNCR Read-write 0x0
0x120 PDC Transfer Control Register PERIPH_PTCR Write-only -
0x124 PDC Transfer Status Register PERIPH_PTSR Read-only 0x0
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22.4.1 PDC Receive Pointer Register
Register Name: PERIPH_RPR
Access Type: Read-write
• RXPTR: Receive Pointer Address
Address of the next receive transfer.
22.4.2 PDC Receive Counter Register
Register Name: PERIPH_RCR
Access Type: Read-write
• RXCTR: Receive Counter Value
Number of receive transfers to be performed.
31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
76543210
RXPTR
31 30 29 28 27 26 25 24
--
23 22 21 20 19 18 17 16
--
15 14 13 12 11 10 9 8
RXCTR
76543210
RXCTR
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22.4.3 PDC Transmit Pointer Register
Register Name: PERIPH_TPR
Access Type: Read-write
• TXPTR: Transmit Pointer Address
Address of the transmit buffer.
22.4.4 PDC Transmit Counter Register
Register Name: PERIPH_TCR
Access Type: Read-write
• TXCTR: Transmit Counter Value
TXCTR is the size of the tran smit transfer to be performed. At zero, the peripheral data transfer is stopped.
31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
76543210
TXPTR
31 30 29 28 27 26 25 24
--
23 22 21 20 19 18 17 16
--
15 14 13 12 11 10 9 8
TXCTR
76543210
TXCTR
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22.4.5 PDC Receive Next Pointer Register
Register Name: PERIPH_RNPR
Access Type: Read-write
• RXNPTR: Receive Next Pointer Address
RXNPTR is the address of the next buffer to fill with received data when the current buffer is full.
22.4.6 PDC Receive Next Counter Register
Register Name: PERIPH_RNCR
Access Type: Read-write
• RXNCR: Receive Next Counter Value
RXNCR is the size of the next buffer to receive.
31 30 29 28 27 26 25 24
RXNPTR
23 22 21 20 19 18 17 16
RXNPTR
15 14 13 12 11 10 9 8
RXNPTR
76543210
RXNPTR
31 30 29 28 27 26 25 24
--
23 22 21 20 19 18 17 16
--
15 14 13 12 11 10 9 8
RXNCR
76543210
RXNCR
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22.4.7 PDC Transmit Next Pointer Register
Register Name: PERIPH_TNPR
Access Type: Read-write
• TXNPTR: Transmit Next Pointer Address
TXNPTR is the address of the next buffer to transmit when the current buffer is empty.
22.4.8 PDC Transmit Next Counter Register
Register Name: PERIPH_TNCR
Access Type: Read-write
• TXNCR: Transmit Next Counter Value
TXNCR is the size of the next buffer to transmit.
31 30 29 28 27 26 25 24
TXNPTR
23 22 21 20 19 18 17 16
TXNPTR
15 14 13 12 11 10 9 8
TXNPTR
76543210
TXNPTR
31 30 29 28 27 26 25 24
--
23 22 21 20 19 18 17 16
--
15 14 13 12 11 10 9 8
TXNCR
76543210
TXNCR
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22.4.9 PDC Transfer Control Register
Register Name: PERIPH_PTCR
Access Type: Write-only
• RXTEN: Receiver Transfer Enable
0 = No effect.
1 = Enables the receiver PDC transfer requests if RXTDIS is not set.
• RXTDIS: Receiver Transfer Disable
0 = No effect.
1 = Disables the receiver PDC transfer request s.
• TXTEN: Transmitter Transfer Enable
0 = No effect.
1 = Enables the transmit ter PDC transfer requests.
• TXTDIS: Transmitter Transfer Disable
0 = No effect.
1 = Disables the transmitter PDC transfer requests
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––TXTDISTXTEN
76543210
––––––RXTDISRXTEN
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22.4.10 PDC Transfer Status Register
Register Name: PERIPH_PTSR
Access Type: Read-only
• RXTEN: Receiver Transfer Enable
0 = Receiver PDC transfer requests are disabled.
1 = Receiver PDC transfer requests are enabled.
• TXTEN: Transmitter Transfer Enable
0 = Transmitter PDC transfer requests are disabled.
1 = Transmitter PDC transfer requests are enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––TXTEN
76543210
–––––––RXTEN
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23. Advanced Interrupt Controller (AIC)
23.1 Overview
The Advanced Interrupt Controller (AIC) is an 8-level priority, in dividually maskable, vectored interrupt controller,
providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-
time overhead in handling internal and external interrupts.
The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM pro-
cessor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's
pins.
The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher
priority interrupts to be serviced even if a lower priority interrupt is being treated.
Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources
can be programmed to be positive-edge or negative-edge triggered or high-level or low-level sensitive.
The fast forcing fe ature redirects any inter nal or external interrupt source to provide a fast inter rupt rather than a
normal interrupt.
23.2 Block Diagram
Figure 23-1. Block Diagram
AIC
APB
ARM
Processor
FIQ
IRQ0-IRQn
Embedded
PeripheralEE
Peripheral
Embedded
Peripheral
Embedded
Up to
Thirty-two
Sources nFIQ
nIRQ
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23.3 Application Block Diagram
Figure 23-2. Description of the Application Block
23.4 AIC Detailed Block Diagram
Figure 23-3. AIC Detailed Block Diagram
23.5 I/O Line Description
Advanced Interrupt Controller
Embedded Peripherals External Peripherals
(External Interrupts)
Standalone
Applications RTOS Drivers Hard Real Time Tasks
OS-based Applications
OS Drivers
General OS Interrupt Handler
FIQ
PIO
Controller
Advanced Interrupt Controller
IRQ0-IRQn PIOIRQ
Embedded
Peripherals
External
Source
Input
Stage
Internal
Source
Input
Stage
Fast
Forcing Interrupt
Priority
Controller
Fast
Interrupt
Controller
ARM
Processor
nFIQ
nIRQ
Power
Management
Controller
Wake UpUser Interface
APB
Processor
Clock
Table 23-1. I/O Line Description
Pin Name Pin Description Type
FIQ Fast Interrupt Input
IRQ0 - IRQn Interrupt 0 - Interrupt n Input
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23.6 Product Dependencies
23.6.1 I/O Lines
The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on
the features of the PIO controller used in the product, the pins must be programmed in accordance with their
assigned interrupt fu nction. This is not applicable when the PIO cont roller use d in th e produ ct is t ranspar en t on the
input path.
23.6.2 Power Management
The Advanced In terrup t Cont roller is co ntinuously clocked. The Powe r Manage ment Cont roller ha s no ef fect on t he
Advanced Interrupt Controller behavior.
The assertio n of the Advanced In terrupt Contro ller outputs, either nIR Q or nFIQ, wakes up the ARM proc essor
while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without
asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
23.6.3 Interrupt Sources
The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0
cannot be used.
The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system
peripheral interrupt lines, such as the System Timer, the Real Time Clock, the Power Management Controller and
the Memory Controller. When a system inter rupt occurs, the service routin e must first dist inguish the cause of the
interrupt. This is performed by reading successively the status registers of the above mentioned system
peripherals.
The interrup t so urce s 2 to 3 1 can e ith er be conn ected to t he inte rrupt outpu ts of an em bedded user periph eral or to
external interrupt lines. The external interrupt lines can be connected d irectly, or through the PIO Controller.
The PIO Controllers are co nsidered as user peripherals in the scope of interrupt handling. Accordingly, the PIO
Controller interrupt lines are connected to the Interrupt Sou rces 2 to 31.
The periphe ral ide ntif icatio n def ined a t th e pro duct level co rrespo nds t o th e inter rupt sour ce nu mber (as well as the
bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional opera-
tions and th e user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.
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23.7 Functional Description
23.7.1 Interrupt Source Control
23.7.1.1 Interrupt Source Mode
The Advanced Interr upt Controller in dependentl y programs each int errupt source. Th e SRCTYPE field of the corre-
sponding AIC_SMR (Source Mode Register) selects t he interrupt cond ition of each source.
The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed
either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important
for the user.
The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in
positive edge-triggered or negative edge -triggered modes.
23.7.1.2 Interrupt Source Enabling
Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers;
AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set
of registers cond ucts enablin g or disabling in on e instructio n. The interru pt mask can be read in the AIC_IMR reg-
ister. A disabled interrupt does not affect servicing of other interrupts.
23.7.1.3 Interrupt Clearing and Setting
All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or
cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources pro-
grammed in level-sensitive mode has no effect.
The clear operation is perfunctory, as the software must perform an action to reinitialize the “memoriza tion” cir-
cuitry activated when the source is pro grammed in edge-trigg ered mode. However, th e set operatio n is available
for auto-test or software debug pu rposes. It can also be used to execute an AIC-implementation of a software
interrupt.
The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read.
Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See “Pri-
ority Controller” on page 167. ) The automatic clear reduces the oper ations required by the interrupt service routine
entry code to r eading t he AIC_ IVR. Note that the a utomati c inter rupt clea r is disab led if t he inte rrup t so urce h as the
Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, See “Fast Forcing”
on page 171.)
The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.
23.7.1.4 Interrupt Status
For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR
(Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not.
The AIC_ISR register reads the number of the current interrupt (see “P riority Controller” on page 167) and the reg-
ister AIC_CISR gives an image of th e signals nIRQ and nFIQ driven on the processor.
Each status referred to above can be used to opti mize the interrupt ha ndling of the systems.
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23.7.1.5 Internal Interrupt Source Input Stage
Figure 23-4. Internal Interrupt Source Input Stage
23.7.1.6 External Int er rupt Sourc e In pu t S tag e
Figure 23-5. External Interrupt Source I nput Stage
Edge
Detector
ClearSet
Source i AIC_IPR
AIC_IMR
AIC_IECR
AIC_IDCR
AIC_ISCR
AIC_ICCR
Fast Interrupt Controller
or
Priority Controller
FF
Level/
Edge
AIC_SMRI
(SRCTYPE)
Edge
Detector
ClearSet
Pos./Neg.
AIC_ISCR
AIC_ICCR
Source i
FF
Level/
Edge
High/Low AIC_SMRi
SRCTYPE
AIC_IPR
AIC_IMR
AIC_IECR
AIC_IDCR
Fast Interrupt Controller
or
Priority Controller
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23.7.2 Interrupt Latencies
Global interrupt latencies depend on severa l parameters, including:
• The time the software masks the interrupts.
• Occurrence, either at the processor level or at the AIC level.
• The execution time of the instruction in progress when the interrupt occurs.
• The treatment of higher priority interrupts and the resynchronization of the hardware signals.
This section addresses only the hardware resynchronizations. It gives details of the latency times between the
event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt
source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the
programming of t he interrupt sour ce and on its type (i nternal or exte rnal). For th e standard inte rrupt, resynch roniza-
tion times are given assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.
23.7.2.1 External Interrupt Edge Triggered Source
Figure 23-6. External Interrupt Edge Triggered Source
23.7.2.2 External Interrupt Level Sensitive Source
Figure 23-7. External Inte rrupt Level Sensitive Source
Maximum FIQ Latency = 4 Cycles
Maximum IRQ Latency = 4 Cycles
nFIQ
nIRQ
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge)
Maximum IRQ
Latency = 3 Cycles
Maximum FIQ
Latency = 3 cycles
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
nFIQ
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23.7.2.3 Internal Interrupt Edge Triggered Source
Figure 23-8. Internal I nterrupt Edge Triggered Source
23.7.2.4 Internal Interrupt Level Sensitive Source
Figure 23-9. Internal Interrupt Level Sensitive Source
23.7.3 Normal Interrupt
23.7.3.1 Priority Controller
An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring
on the interrupt sources 1 to 31 (except for those pr ogrammed in Fast Forcing).
Each interrupt source h as a programmable pr iority level of 7 to 0, which is user-defin able by writing the PRIOR f ield
of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest.
As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Regis-
ter), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since
the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Inter-
rupt Vector Reg ister) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the
AIC to consider that the interrupt has been taken into account by the software.
The current priority level is defined as the pr iority level of the curren t interrupt.
If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with
the lowest interr up t sou r ce nu m be r is ser vice d first.
The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If
an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the soft-
ware indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command
Register). The write of AIC_EOICR is the exit point of the interrupt handling.
MCK
nIRQ
Peripheral Interrupt
Becomes Active
Maximum IRQ Latency = 4.5 Cycles
MCK
nIRQ
Maximum IRQ Latency = 3.5 Cycles
Peripheral Interrupt
Becomes Active
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23.7.3.2 Interrupt Nesting
The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service
of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the inter-
rupt at the processo r level.
When an interrupt of a high er priority happ ens during an already occurrin g interrupt service routine, the nIRQ line is
re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt
service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed
into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing
is finished and the AIC_EOICR is written.
The AIC is equipped with an 8 -leve l wide h ardwar e stack in or der to sup port up t o ei gh t inte rr upt n estin gs pursua nt
to having eight priority levels.
23.7.3.3 Interrupt Vectoring
The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1
to AIC_SVR31 (Source Vector Register 1 to 31). When the processo r reads AIC_IVR (Interrupt Vector Register),
the value written into AIC_SVR corresponding to the current interrupt is returned.
This feature offers a wa y to b ranch in one single instr uction to t he handler corresponding to the cu rrent int errupt, as
AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at
address 0x0000 0018 through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus
branching the execution on the correct interrupt handler.
This feature is often not used when the application is based on an operating system (either real time or not). Oper-
ating systems often have a single entry point for all the interrupts and the first task performed is to discern the
source of the interrupt.
However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt
vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operat-
ing system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt
to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt han-
dler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software
peripheral handling) to b e handled efficiently and independen tly of the application running under an operatin g
system.
23.7.3.4 Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the
programmer und erstands the ar chitecture o f the ARM processor, an d especially th e processo r interru pt modes and
the associated status bits.
It is assumed that:
1. The Advanced Interrupt Controller has been pr ogra mmed, AIC_SVR registers are loaded with corre-
sponding interrupt service routine addresses and interrupts are enabled.
2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
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1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link
register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch
at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four.
2. The ARM core enters Interrupt mode, if it has not already done so.
3. When the instruction loaded at address 0x18 is executed, th e progr am counter is loaded with the v alue
read in AIC_IVR. Reading the AIC_IVR has the following effects:
– Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current
lev el is the priority level of the current interrupt.
– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in
order to de-assert nIRQ.
– Automatica lly clears the interrupt, if it has been programmed to be edge-triggered.
– Pushes the current level and the current interrupt number on to the stack.
– Returns the value written in the AIC_SVR corresponding to the current interrupt.
4. The previous step has the effect of branching to the corresponding interrupt service routine. This should
start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four
when it is saved if it is to be restored direct ly into the program counter at the end of the interrupt. For
example, the instr uc tion SUB PC, LR, #4 may be used.
5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ
to be tak en into account by the co re . This can hap pen if an int errupt with a higher priority than the curren t
interr u pt oc cu rs.
6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring
them at the end. During this phase, an interrupt of higher priority than the current level will restart the
sequence from step 1.
Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.
7. The “I” bit in CPSR must be set in order to mask interrupts bef ore exiting to ensure that the interrupt is
completed in an orderly manner.
8. The End of I nt errupt Comman d Re gist er (AI C _EOICR) must b e written in or der to ind i cate t o th e AIC t ha t
the current interrupt is finished. This causes the current level to be popped from the stack, restoring the
previous curr en t level if one exists on the stack. I f anot her inter rupt is pen ding, wit h lower or equ al priority
than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted,
but the interrupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is
restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of
returning from the interrupt to whatever was being executed before, and of loading the CPSR with the
stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.
Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt
when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (inter-
rupt is masked).
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23.7.4 Fast Interrupt
23.7.4.1 Fast Interrupt Source
The interrupt source 0 is the on ly source which can raise a fast int errupt request to the pr ocessor except if fast forc-
ing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a
PIO Controller.
23.7.4.2 Fast Interrupt Control
The fast interrupt logic of the AIC has no priority contr oller. The mode of interrupt source 0 is programmed with the
AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRC-
TYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge
triggered or high-level sensitive or low- level sensitive
Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command
Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indi-
cates whether the fast interrupt is enabled or disabled.
23.7.4.3 Fast Interrupt Vectoring
The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into
this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in
one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and
thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus
branching the execution on the fast interrupt handler. It also autom atically performs the clear of the fast interrupt
source if it is programmed in edge-triggered mode.
23.7.4.4 Fast Interrupt Handlers
This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the
programmer und erstands the ar chitecture o f the ARM processor, an d especially th e processo r interru pt modes and
associated status bits.
Assuming that:
1. The Advanced In te rrupt Controller has bee n p rogrammed, AI C_SVR0 is loa ded with t he fast interrupt ser-
vice routine address, and the interrupt source 0 is enabled.
2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt:
LDR PC, [PC, # -&F20]
3. The user does not need nested fast interrupts.
When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is:
1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link regis-
ter (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at
address 0x20, the ARM core ad justs R14_fiq, decrementin g it by four.
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value
read in AIC_FVR. Reading the AIC_FVR has effect of automa tically clearing the fast interrupt, if it has
been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor.
4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to
save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed.
5. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13
because FIQ mode has its own dedicated registers and the user R8 to R13 ar e bank ed. The other regis-
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ters, R0 to R7, must be sa v ed b ef or e being used, an d restored at the en d (before the next step). Note that
if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during
this phase in order to de-assert the interrupt source 0.
6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction
SUB PC, LR, #4 f o r example). This has the effect of returning from the int errupt to whatever w as bein g
executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depend-
ing on the state saved in the SPSR.
Note: The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when
the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ
is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector
0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning
of the handler op eration. However, this method saves the execution of a branch instruction.
23.7.4.5 Fast Forcing
The Fast Forcing featur e of the ad vanced inte rrupt cont roller pr ovides re direction of a ny normal I nterr upt source on
the fast interrupt controller.
Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forc-
ing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status
Register (AIC_FFSR) that controls the feature for each internal or external interrupt source.
When Fast Forcing is disabled, t he interrupt sources are handled as described in the previous pages.
When Fast Forcing is enabled , the edge/level programming and , in certain cases, edge detection of the interru pt
source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority
handler.
If the interr upt source is progra mmed in level-sensitive mode and an active level is sampled, Fast Forcing results in
the assertion of the nFIQ line to the core.
If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results
in the assertion of the nFIQ line to the core.
The Fast Forcing feature does not affect the Source 0 pending bit in the Inter rupt Pending Register (AIC_IPR).
The FIQ Vector Re gister (AIC_FVR) read s the contents of the Source Vector Re gister 0 (AIC_SVR0), what ever the
source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature
is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register
(AIC_ICCR).
All enabled and pending inte rrupt sources that have the fast forcing feature enabled and that are prog rammed in
edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are
cleared independently and thus lost interrupts are prevented.
The read of AIC_IVR does not clear the source that has t he fast forcing featur e enabled.
The source 0, reserved to the fast inter rupt, continues operating normally an d becomes one of the Fast Interrupt
sources.
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Figure 23-10. Fast Forcing
Source 0 _ FIQ Input Stage
Automatic Clear
Input Stage
Automatic Clear
Source n
AIC_IPR
AIC_IMR
AIC_FFSR
AIC_IPR
AIC_IMR
Priority
Manager
nFIQ
nIRQ
Read IVR if Source n is the current interrupt
and if Fast Forcing is disabled on Source n.
Read FVR if Fast Forcing is
disabled on Sources 1 to 31.
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23.7.5 Protect Mode
The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic oper-
ations. This is necessary when working with a debug system. When a debugger, working either with a Debug
Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the
AIC User Interface and thus the IVR. This has undesirable consequences:
• If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
• If there is no enabled pending interrupt, the spurious vector is returned.
In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC.
This operation is generally not performed by the debug system as the debug system would become strongly intru-
sive and cause the application to enter an undesired state.
This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register) at 0x1 enables
the Protect Mode.
When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on
the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to th e AIC_IVR just after reading
it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the
current interrupt only when AIC_IVR is written.
An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra
AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the
read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC
context.
To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC:
1. Calculates active i nterrupt (higher than current or spurious).
2. Determines and returns the vector of the active interrupt.
3. Memorizes the interrupt.
4. Pushes the current priority level onto the inte rnal stack.
5. Acknowledges the interrupt.
However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Opera-
tions 4 and 5 ar e only performed by the AIC when AIC_IVR is written.
Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without mod-
ification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.
23.7.6 Spurious Interrupt
The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as
being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when
AIC_IVR is read. This is most prone to occur when:
• An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short
time.
• An internal interrupt source is programmed in level sensitive and the ou tput signal of the corresponding
embedded peripheral is activated for a short time. (As in the case for the Watchdog.)
• An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the
interrupt source.
The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending.
When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register).
The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to
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enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs
a return from interrupt.
23.7.7 General Interrupt Mask
The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ
and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set.
However, this mask does not prevent waking up the proces sor if it has entered Idle Mode. This function facilitates
synchronizing the processor on a next even t and, as soon as the ev ent occurs, performs sub sequent operation s
without having t o handle an interrupt. It is strongly recommended to use this mask with caution.
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23.8 Adv anced Interrupt Controller (AIC) User Interface
23.8.1 Base Address
The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring fea-
ture, as the PC-relative load/store instructions of the ARM processor supp ort only an ± 4-Kbyte offset.
Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset,
thus not pending.
2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet.
23.8.2 AIC Source Mode Register
Register Name: AIC_SMR0..AIC_SMR31
Table 23-2. Register Mapping
Offset Register Name Access Reset
0000 Source Mode Register 0 AIC_SMR0 Read/Write 0x0
0x04 Source Mode Register 1 AIC_SMR1 Read/Write 0x0
--- --- --- --- ---
0x7C Source Mode Register 31 AIC_SMR31 Read/Write 0x0
0x80 Source Vector Register 0 AIC_SVR0 Read/Write 0x0
0x84 Source Vector Register 1 AIC_SVR1 Read/Write 0x0
--- --- --- --- ---
0xFC Source Vector Register 31 AIC_SVR31 Read/Write 0x0
0x100 Interrupt Vector Register AIC_IVR Read-only 0x0
0x104 FIQ Interrupt Vector Regi ster AIC_FVR Read-only 0x0
0x108 Interrupt Status Register AIC_ISR Read-only 0x0
0x10C Interrupt Pending Register(2) AIC_IPR Read-only 0x0(1)
0x110 Interrupt Mask Register(2) AIC_IMR Read-only 0x0
0x114 Core Interrupt Status Register AIC_CISR Read-only 0x0
0x118 Reserved --- --- ---
0x11C Reserved --- --- ---
0x120 Interrupt Enable Command Register(2) AIC_IECR Write-only ---
0x124 Interrupt Disable Command Register(2) AIC_IDCR Write-only ---
0x128 Interrupt Clear Command Regi ster(2) AIC_ICCR Write-only ---
0x12C Interrupt Set Command Register(2) AIC_ISCR Write-only ---
0x130 End of Interrupt Command Register AIC_EOICR Write-only ---
0x134 Spurious Interrupt Vecto r Register AIC_SPU Read/Write 0x0
0x138 Debug Control Register AIC_DCR Read/Write 0x0
0x13C Reserved --- --- ---
0x140 Fast Forcing Enable Register(2) AIC_FFER Write-only ---
0x144 Fast Forcing Disable Register(2) AIC_FFDR Write-only ---
0x148 Fast Forcing Status Register(2) AIC_FFSR Read-only 0x0
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Access Type: Read/Write
Reset Value: 0x0
• PRIOR: Priority Level
Programs the priori ty level for all sources except FIQ source (source 0).
The priority level can be bet ween 0 (lowest) and 7 (highest).
The priority level is not used for the FIQ in the related SMR register AIC_SMRx.
• SRCTYPE: Inter r upt Source Type
The active level or e dge is not programmable f or the internal interrupt sources.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– SRCTYPE – – PRIOR
SRCTYPE Internal Interrupt Sources External Interrupt Sources
0 0 High level Sensitive Low lev e l Sensitive
0 1 Positive edge triggered Negative edge triggered
1 0 High level Sensitive High level Sensitive
1 1 Positive edge triggered Positive edge triggered
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23.8.3 AIC Source Vector Register
Register Name: AIC_SVR0..AIC_SVR31
Access Type: Read/Write
Reset Value: 0x0
• VECTOR: Source Vector
The user may store in these registers the addresses of the corresponding handler for each interrupt source.
23.8.4 AIC Interrupt Vector Register
Register Name: AIC_IVR
Access Type: Read-only
Reset Value: 0x0
• IRQV: Interrupt Vector Register
The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to
the current interr u pt .
The Source Vector Register i s indexed using the current interrupt number when the Interrupt Vector Register is read.
When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU.
31 30 29 28 27 26 25 24
VECTOR
23 22 21 20 19 18 17 16
VECTOR
15 14 13 12 11 10 9 8
VECTOR
76543210
VECTOR
31 30 29 28 27 26 25 24
IRQV
23 22 21 20 19 18 17 16
IRQV
15 14 13 12 11 10 9 8
IRQV
76543210
IRQV
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23.8.5 AIC FIQ Vector Register
Register Name: AIC_FVR
Access Type: Read-only
Reset Value: 0 x0
• FIQV: FIQ Vector Register
The FIQ Vector Register contains the vecto r programmed by the user in the Source Vector Register 0. When the re is no
fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.
23.8.6 AIC Interrupt Status Register
Register Name: AIC_ISR
Access Type: Read-only
Reset Value: 0x0
• IRQID: Current Interrupt Identifier
The Interrupt Status Register retur ns the current interrupt source number.
31 30 29 28 27 26 25 24
FIQV
23 22 21 20 19 18 17 16
FIQV
15 14 13 12 11 10 9 8
FIQV
76543210
FIQV
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––– IRQID
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23.8.7 AIC Interrupt Pending Register
Register Name: AIC_IPR
Access Type: Read-only
Reset Value: 0x0
• FIQ , SYS, PID2-PID31: Interrupt Pending
0 = Corresponding interrupt is not pending.
1 = Corresponding interrupt is pending.
23.8.8 AIC Interrupt Mask Register
Register Name: AIC_IMR
Access Type: Read-only
Reset Value: 0x0
• FIQ , SYS, PID2-PID31: Interrupt Mask
0 = Corresponding interrupt is disabled.
1 = Corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
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23.8.9 AIC Core Interrupt Status Register
Register Name: AIC_CISR
Access Type: Read-only
Reset Value: 0x0
• NFIQ: NFIQ Status
0 = nFIQ line is deactivated.
1 = nFIQ line is active.
• NIRQ: NIRQ Status
0 = nIRQ line is deactivated.
1 = nIRQ line is active.
23.8.10 AIC Interrupt Enable Command Register
Register Name: AIC_IECR
Access Type: Write-only
• FIQ , SYS, PID2-PID3: Interrupt Enable
0 = No effect.
1 = Enables corresponding int errupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––NIRQNIFQ
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
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23.8.11 AIC Interrupt Disable Command Register
Register Name: AIC_IDCR
Access Type: Write-only
• FIQ , SYS, PID2-PID31: Interrupt Disable
0 = No effect.
1 = Disables corresponding interrupt.
23.8.12 AIC Interrupt Clear Command Register
Register Name: AIC_ICCR
Access Type: Write-only
• FIQ , SYS, PID2-PID31: Interrupt Clear
0 = No effect.
1 = Clears corresponding interrupt.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
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23.8.13 AIC Interrupt Set Command Register
Register Name: AIC_ISCR
Access Type: Write-only
• FIQ , SYS, PID2-PID31: Interrupt Set
0 = No effect.
1 = Sets corresponding in terrupt.
23.8.14 AIC End of Interrupt Command Register
Register Name: AIC_EOICR
Access Type: Write-only
The End of Interrupt Command Register is used by the inter rupt routine to indicate that the interrupt treatment is complete.
Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt
treatment.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––––
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23.8.15 AIC Spurious Interrupt Vector Register
Register Name: AIC_SPU
Access Type: Read/Write
Reset Value: 0x0
• SIVR: Spurious Interrupt Vector Register
The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in
case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
23.8.16 AIC Debug Control Register
Register Name: AIC_DEBUG
Access Type: Read/Write
Reset Value: 0x0
• PROT: Protection Mode
0 = The Protection Mode is disabled.
1 = The Protection Mode is enabled .
• GMSK: General Mask
0 = The nIRQ and nFIQ lines are nor mally controlled by the AIC.
1 = The nIRQ and nFIQ lines are tie d to their inactive state.
31 30 29 28 27 26 25 24
SIVR
23 22 21 20 19 18 17 16
SIVR
15 14 13 12 11 10 9 8
SIVR
76543210
SIVR
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––GMSKPROT
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23.8.17 AIC F ast Forcing Enable Register
Register Name: AIC_FFER
Access Type: Write-only
• SYS, PID2-PID31: Fast Forcing Enable
0 = No effect.
1 = Enables the fast forcing feature on t he corresponding interrupt.
23.8.18 AIC Fast Forcing Disable Regis ter
Register Name: AIC_FFDR
Access Type: Write-only
• SYS, PID2-PID31: Fast Forcing Disable
0 = No effect.
1 = Disables the Fast Forcing feature on the correspon ding interrupt.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS –
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS –
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23.8.19 AIC Fast Forcing Status Register
Register Name: AIC_FFSR
Access Type: Read-only
• SYS, PID2-PID31: Fast Forcing Status
0 = The Fast Forcing feature is disabled on the corresponding interrupt.
1 = The Fast Forcing feature is enabled on the corresponding interrupt.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 SYS –
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24. Clock Generator
24.1 Overview
The Clock Generator is made up of 1 PLL, a Main Oscillator, as well as an RC Oscillator.
It provides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Oscillator
• PLLCK is the output of the Divider and PLL block
The Clock Generator User Interface is e mbedded within t he Power Manag ement Contro ller one and is describ ed in
Section 25.9. However, the Clock Generator registers are named CKGR_.
24.2 Slow Clock RC Oscillator
The user has to take into account the possible drifts of the RC Oscillator. More details are given in the section “DC
Characteristics” of the product data sheet.
24.3 Main Oscillator
Figure 24-1 shows the Main Oscillator block diagram.
Figure 24-1. Main Oscillator Block Diagram
24.3.1 M ai n Osc illa tor Conne ct ions
The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typi-
cal crystal connection is illustrated in Figure 24- 2. For further details on the electrical characteristics of the Main
Oscillator, see the section “DC Characteristics” of the product datasheet.
XIN
XOUT
MOSCEN
Main
Oscillator
Counter
OSCOUNT
MOSCS
MAINCK
Main Clock
Main Clock
Frequency
Counter
MAINF
MAINRDY
SLCK
Slow Clock
Main
Oscillator
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Figure 24-2. Typical Crystal Connection
24.3.2 Main Oscillator Startup Time
The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The
startup time depends on the crystal frequency and decreases when the frequency rises.
24.3.3 Main Oscillator Control
To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is
selected.
The software enable s or di sables t he main oscillator so as to reduce power consumption by clearing the MOSCEN
bit in the Main Oscillator Register (CKGR_MOR).
When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is
automatically cleared , indicating the main clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to
the startup time of the oscillator. This startup time depends on the crystal frequency connected to the m ain
oscillator.
When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS
bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8
from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62
ms.
When the counte r reaches 0, the MOSCS bit is set, ind icati ng that the main clock is valid. Setting the MOSCS bit in
PMC_IMR can trigger an interrupt to the processor.
24.3.4 Main Clock Frequency Counter
The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency connected to the
Main Oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to
configure the device with the correct clock speed, independently of the application.
The Main Clock frequency counter starts incrementing at the Main Clock speed after the next rising edge of the
Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS bit is set. Then, at the 16th falling
edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter
stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock
cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can
be determined.
1K
XIN XOUT GND
SAM7S Microcontroller
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24.3.5 Main Oscillator Bypass
The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the
external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the
product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the
MOSCEN bit to 0 in the Main OSC register (CKGR_ MOR) for the external clock to operate properly.
24.4 Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must
respect the PLL minimum input frequency when programming t he divider.
Figure 24-3 shows the block diagram of the divider and PLL block.
Figure 24-3. Divider and PLL Block Diagram
24.4.1 PLL Filter
The PLL requires connection to an external second-order filter through the PLLRC pin. Figure 24-4 shows a sche-
matic of these filters.
Figure 24-4. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input fre-
quency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal
overshoot and startup time.
24.4.2 Divider and Phase Lock Loop Programming
The divider can be set betwee n 1 an d 25 5 in st ep s of 1. Wh en a divid er fie l d (DIV) is set to 0, t he o utput of th e cor-
responding divider and t he PLL output is a continuous sig nal at level 0. On reset, each DIV field is set to 0, thus the
corresponding PLL input clock is set to 0.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal ha s a frequency that depends on the
respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal
Divider
PLLRC
DIV
PLL
MUL
PLLCOUNT
LOCK
OUT
SLCK
MAINCK PLLCK
PLL
Counter
GND
C1
C2
PLL
PLLRC
R
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frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consump-
tion is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR is automatically
cleared. The values written in the PLLCOUNT field in CKGR_PLLR are loaded in the PLL counter. The PLL coun-
ter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR
and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to
cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial
state of the PLL and its target frequency can be calculated using a specif ic tool provided by Atmel.
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25. Power Management Controller (PMC)
25.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user periph-
eral clocks. The PMC enables/d isables the clock inputs to many of the peripherals and the ARM Processor.
The Power Management Controller provides the following clocks:
• MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequen cy of th e
device. It is available to the modules running permanently, such as the AIC and the Memory Controller.
• Processor Clock (PCK), switched off when entering processor in idle mode.
• Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI,
etc.) and independently controllable. In order to redu ce the number of clock names in a product, the Peripheral
Clocks are named MCK in the produc t da tas he e t.
• UDP Clock (UDPCK), required by USB Device Port operations. (Does not pertain to SAM7S32/16.)
• Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on
the PCKx pins.
25.2 Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided
to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock
provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLL.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master
Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The
PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to def ine a new Master Clock, the MCKRDY bit is clear ed in PMC_SR. It reads 0
until the Master Clock is est ablished. Then, the MCKRDY bit is set and can trig ger an interrupt to the pro cessor.
This feature is useful when switching from a high-speed clock to a lower one to inform the software when the
change is actually done.
Figure 25-1. Master Clock Cont roller
25.3 Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Proce ssor Idle Mode. The Processor
Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at
least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR).
SLCK Master Clock
Prescaler MCK
PRESCSS
MAINCK
PLLCK
To the Processor
Clock Controller (PCK)
PMC_MCKR PMC_MCKR
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The Processor Clock PCK is enabled after a reset and is automatically re-e nabled by any enabled interrupt. The
Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does
not prevent data tra nsf er s fro m othe r mas ter s of th e sys tem bu s.
25.4 USB Clock Controller
Note: The USB Clock Controller does not pertain to SAM7S32/16.
The USB Source Clock is the PLL output. If using the USB, the user must program the PLL to generate a 48 MHz,
a 96 MHz or a 192 MHz signal with an accuracy of ± 0.25% depending on the USBDIV bit in CKGR_PLLR.
When the PLL output is stable, i.e., the LOCK bit is set:
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral
when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity
of this cloc k. Th e USB device port require bot h the 48 MHz sign al and the Ma ster Cloc k. T he Maste r Cloc k may
be controlled via the Master Clock Controller.
Figure 25-2. USB Clock Controller
25.5 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral
Clock Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into
the Peripheral Clock Ena ble (PMC_PCER) and Peripher al Clock Disable ( PMC_PCDR) register s. The sta tus of the
peripheral clock activity can be read in the Peri pheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically dis-
abled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its
last programmed operat ion be fore disablin g the clock. This is t o avoid data co rrup tio n or err oneous be havior of the
system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the
Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source
number assigned to the pe ripheral.
25.6 Programmabl e Clock Output Controller
The PMC controls 3 signals to b e output on external pins PCKx . Each signal can be independen tly programmed
via the PMC_PCKx registers.
PCKx can be independen tly selected between the Slow clock, the PLL output and the main clock by writing the
CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the
PRES (Prescaler) field in PMC_PCKx.
USB
Source
Clock UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/4
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Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of
PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been
programmed in the Programmable Clock registers.
As the Programmable Clock Cont roller does no t mana ge with g litch pr evention when switching clocks, it is strongly
recommended to disable the Programmable Clock before any configuration change and to re-enable it after the
change is actually performed.
25.7 Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may
be advantageous to define a start-up tim e. This can be achieved by writing a value in the OSCOUNT field in
the CKGR_MOR register.
Once this regis ter has been corr ectly configured , the user must wait fo r MOSCS field in the PM C_SR register
to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the
associated interrupt to MOSCS has been enabled in the PMC_IER register.
Code Example:
write_register(CKGR_MOR,0x00000701)
Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles.
So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.
2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main oscillator frequency. This measure can
be accomplished via the CKGR _MCFR register.
Once the MAINRD Y field is se t in CKGR_ MCF R re gister , th e us er ma y re ad t he M AINF field in C KGR_M CFR
register. This provides the number of main clock cycles within sixteen slow clock cycles.
3. Setting PLL and divider:
All parameters needed to configure PLL and the divider are located in the CKGR_PLLR register.
The DIV field is use d to con trol divider it se lf. A va lue b etw een 0 a nd 255 can be p ro gramme d. Divider ou tput is
divider input divided by DIV parameter. By default DIV parameter is set to 0 which means that divider is turned
off.
The OUT field is used to select the PLL B output frequency range.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and 2047. If MUL is
set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input frequency multiplied by (MUL +
1).
The PLLCOUNT field sp ecifies t he num ber o f slow clock cycle s befo re LOCK b it is se t in the PMC_SR r egister
after CKGR_PLLR register has been written.
Once the PMC_PLL re gister has been written, th e user must wait for the LO CK bit to be set in the PMC_SR
register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the
associated interrupt to LOCK has been enabled in the PMC_IER register. All parameters in CKGR_PLLR can
be programmed in a single write ope ration. If a t some stag e one of th e following par ameters, MUL, DIV is mod-
ified, LOCK bit will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again.
The user is constrained to wait fo r LOCK bit to be set before using the PLL output clock.
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The USBDIV field is used t o control the additiona l divider by 1, 2 or 4, which g enerat es the USB clock( s) (Do es
not pertain to SAM7S3 2 /16.)
Code Example:
write_register(CKGR_PLLR,0x00040805)
If PLL and divider are en abled, th e PLL inp ut clo ck is the main clock. PLL output clock is PLL input clo ck mult i-
plied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after eight slow clock cycles.
4. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the Master Clock divider source. By default, the selected clock sourc e is slow
clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between different values
(1, 2, 4, 8, 16, 32, 64). Ma ster Clock output is prescaler input d ivided by PRES parameter. By default, PRES
parameter is set to 1 which means that master clock is equa l to slow clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the
PMC_SR register. This can be d on e eith er by polling t h e status register or by waiting for the interrupt line to be
raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER regist er.
The PMC_MCKR register must no t be programmed in a single write opera tion. The preferred programming
sequence for the PMC_MCKR reg ister is as follows:
• If a new value for CSS field corresponds to PLL Clock,
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_M CKR re gister.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
• If a new value for CSS field corresponds to Main Clock or Slow Clock,
– Program the CSS field in the PMC_M CKR re gister.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to
indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit
to be set again before using the Master and Processor Clocks.
Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR the
MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set.
While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. F or further information, see
Section 25.8.2. “Clock Switching Waveforms” on page 197.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
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wait (MCKRDY=1)
The Master Clock is main clock divide d by 16.
The Processor Clock is the Master Clock.
5. Selection of Programmable clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers.
Depending on the system used, 3 Programmable clocks can be enabled or disabled. The PMC_SCSR p ro-
vides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are
disabled.
PMC_PCKx registers are used to configure Programmable clocks.
The CSS field is used to select the Programmable clock divider source. Four clock options are available: main
clock, slow clock, PLLCK. By default, the clock source selected is slow clock.
The PRES field is used to cont ro l the Pro gra mmable clock pr esca ler. I t is possible to ch oose betw een diffe re nt
values (1, 2, 4, 8, 16, 32, 64). Program mable clock output is prescaler input divided by PRES p arameter. By
default, the PRES parameter is set to 1 which means that master clock is equal t o slow clock.
Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be
enabled and the user is const rained to wait for the PCK RDYx bit to be set in th e PMC_SR register. This can be
done either by polling t he status regist er or by waiting the interrupt line to be raised if the associat ed interrupt to
PCKRDYx has been enabled in the PMC_I ER regist er . All parameters in PMC_PCKx can be progr amme d in a
single write operation.
If the CSS and PRES parameters are to be modified, the corresponding Progra mmable clock must be disa bled
first. The par ameters can t hen be modifie d. Once t his has been do ne, the user mu st re-ena ble the Progr amma-
ble clock and wait for the PCKRDYx bit to be set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
6. Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via
registers PMC_PCER and PMC_PCDR.
Depending on the system used, SAM7S512/256/12 8/64/321, 12 and for SAM7 S32/16, 10 per ipheral clocks
can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled.
Note: Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
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write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
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25.8 Clock Switching Details
25.8.1 Master Clock Switching Timings
Table 25-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another
one. This is in the event th at the pr escaler is de- activa ted. Wh en the pr escaler is act ivated, a n additi onal time of 64
clock cycles of the new selected clock has to be added.
25.8.2 Clock Switching Waveforms
Figure 25-3. Switch Master Clock from Slow Clock to PLL Clock
Table 25-1. Clock Switching Timings (Worst Case)
From Main Clock SLCK PLL Clock
To
Main Clock – 4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK 0.5 x Main Clock +
4.5 x SLCK –3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Slow Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
PLL Clock
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Figure 25-4. Switch Master Clock from Main Clock to Slow Clock
Figure 25-5. Change PLL Programming
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
Main Clock
Main Clock
PLL Clock
LOCK
MCKRDY
Master Clock
Write CKGR_PLLR
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Figure 25-6. Programmable Clock Output Programming
PLL Clock
PCKRDY
PCKx Output
Write PMC_PCKx
Write PMC_SCER
Write PMC_SCDR PCKx is disabled
PCKx is enabled
PLL Clock is selected
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25.9 Power Management Controller (PMC) User Interface
Notes: 1. UDP bit of this register doe not pertain to SAM7S32/16.
2. USBDIV bit of this register does not pertain to SAM7S32/16
Table 25-2. Register Mapping
Offset Register Name Access Reset
0x0000 System Clock Enable Register PMC_SCER(1) Write-only –
0x0004 System Clock Disable Register PMC_SCDR(1) Write-only –
0x0008 System Clock Status Register PMC _SCSR(1) Read-only 0x01
0x000C Reserved – – –
0x0010 Peripheral Clock Enable Register PMC _PCER Write-only –
0x0014 Peripheral Clock Disable Register PMC_PCDR Write-only –
0x0018 Peripheral Clock Status Register PMC_PCSR Read-only 0x0
0x001C Reserved – – –
0x0020 Main Oscillator Register CKGR_MOR Read-write 0x0
0x0024 Main Clock Frequency Regi ster CKGR_MCFR Read-only 0x0
0x0028 Reserved – – –
0x002C PLL Register CKGR_PLLR(2) Read-write 0x3F00
0x0030 Master Clock Register PMC_MCKR Read-write 0x0
0x0038 Reserved – – –
0x003C Reserved – – –
0x0040 Programmable Clock 0 Register PMC_PCK0 Read-write 0x0
0x0044 Programmable Clock 1 Register PMC_PCK1 Read-write 0x0
0x0048 Programmable Clock 2 Register PMC_PCK2 Read-write 0x0
... ... ... ... ...
0x0060 Interrupt Enable Register PMC_IER Write-only --
0x0064 Interrupt Disable Register PMC_IDR Write-only --
0x0068 Status Register PMC_SR Read-only 0x08
0x006C Interrupt Mask Register PMC_IMR Read-only 0x0
0x0070 - 0x007C Reserved – – –
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25.9.1 PMC System Clock Enable Registe r
Register Name: PMC_SCER
Access Type: Write-only
• PCK: Pr ocessor Clock Enable
0 = No effect.
1 = Enables the Processor clock.
• UDP: USB Device Port Clock Enable
0 = No effect.
1 = Enables the 48 MHz clock of the USB Device Port.
(Does not pertain to SAM7S32/16.)
• PCKx: Programmable Clock x Output Enable
0 = No effect.
1 = Enables the corresponding Programmable Clock output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP––––––PCK
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25.9.2 PMC System Clock Disable Register
Register Name: PMC_SCDR
Access Type: Write-only
• PCK: Processor Clock Disable
0 = No effect.
1 = Disables the Processor clock. This is used to enter the processor in Idle Mode.
• UDP: USB Device Port Clock Disable
0 = No effect.
1 = Disables the 48 MHz clock of the USB Device Port.
(Does not pertain to SAM7S32/16.)
• PCKx: Programmable Clock x Output Disable
0 = No effect.
1 = Disables the corresponding Programmable Clock output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP––––––PCK
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25.9.3 PMC System Clock Status Register
Register Name: PMC_SCSR
Access Type: Read-only
• PCK: Processor Clock Status
0 = The Processor clock is disabled.
1 = The Processor clock is enabled.
• UDP: USB Device Port Clock Status
0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled.
1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled .
(Does not pertain to SAM7S32/16.)
• PCKx: Programmable Clock x Output Status
0 = The corresponding Programmable Clock output is disabled.
1 = The corresponding Programmable Clock output is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCK2PCK1PCK0
76543210
UDP––––––PCK
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25.9.4 PMC Peripheral Clock Enable Register
Register Name: PMC_PCER
Access Type: Write-only
• PIDx: Peripheral Clock x Enable
0 = No effect.
1 = Enables the corresponding peripheral clock.
Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
25.9.5 PMC Peripheral Clock Dis able Register
Register Name: PMC_PCDR
Access Type: Write-only
• PIDx: Peripheral Clock x Disable
0 = No effect.
1 = Disables the corresponding peripheral clock.
Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 - -
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 - -
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25.9.6 PMC P eripheral Cl ock Status Register
Register Name: PMC_PCSR
Access Type: Read-only
• PIDx: Peripheral Clock x Status
0 = The corresponding peripheral clock is disabled.
1 = The corresponding peripheral clock is enabled.
Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
PID7 PID6 PID5 PID4 PID3 PID2 – –
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25.9.7 PMC Clock Generator Main Oscillator Register
Register Name: CKGR_MOR
Access Type: Read-write
• MOSCEN: Main Oscillator Enable
A crystal must be connected between XIN and XOUT.
0 = The Main Oscillator is disabled.
1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0.
When MOSCEN is set, the MOSCS flag is set once the Main Oscillator startup time is achieved.
• OSCBYPASS: Oscillator Bypass
0 = No effect.
1 = The Main Oscillator is bypassed. MOSCEN must be set to 0. An external clock must be connected on XIN.
When OSCBYPASS is set, the MOSCS flag in PMC _SR is automatically set.
Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag.
• OSCOUNT: Main Oscillator Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
OSCOUNT
76543210
––––––OSCBYPASSMOSCEN
207
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25.9.8 PMC Clock Generat or Main Clock Frequency Register
Register Name: CKGR_MCFR
Access Type: Read-only
• MAINF: Main Clock Frequency
Gives the numb er of Main Clock cycles within 16 Slow Clock pe riods.
• MAINRDY: Main Clock Ready
0 = MAINF value is not valid or the Main Oscillator is disabled.
1 = The Main Oscillator has been enabled previously and MAINF value is available.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––MAINRDY
15 14 13 12 11 10 9 8
MAINF
76543210
MAINF
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25.9.9 PMC Clock Generator PLL Register
Register Name: CKGR_PLLR
Access Type: Read-write
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
•DIV: Divider
• PLLCOUNT: PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• OUT: PLL Cloc k Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.
• USBDIV: Divider for USB Clock (Does not Pertain to SAM73S2/16
31 30 29 28 27 26 25 24
– – USBDIV – MUL
23 22 21 20 19 18 17 16
MUL
15 14 13 12 11 10 9 8
OUT PLLCOUNT
76543210
DIV
DIV Divider Selected
0 Divider output is 0
1 Divider is bypassed
2 - 255 Divider output is the selected clock divided by DIV.
USBDIV Divider for USB Clock(s)
0 0 Divider output is PLL clock output.
0 1 Divider output is PLL clock output divided by 2.
1 0 Divider output is PLL clock output divided by 4.
1 1 Reserved.
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25.9.10 PMC Master Clock Register
Register Name: PMC_MCKR
Access Type: Read-write
• CSS: Master Clock Selection
• PRES: Processor Clock Prescaler
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – PRES CSS
CSS Clock Source Selection
0 0 Slow Clock is selected
0 1 Main Clock is selected
10Reserved
1 1 PLL Clock is selected.
PRES Processor Clock
0 0 0 Selected clock
0 0 1 Selected clock divided by 2
0 1 0 Selected clock divided by 4
0 1 1 Selected clock divided by 8
1 0 0 Selected clock divided by 16
1 0 1 Selected clock divided by 32
1 1 0 Selected clock divided by 64
111Reserved
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25.9.11 PMC Programmable Clock Register
Register Name: PMC_PCKx
Access Type: Read-write
• CSS: Master Clock Selection
• PRES: Programmable Clock Prescaler
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – PRES CSS
CSS Clock Source Selection
0 0 Slow Clock is selected
0 1 Main Clock is selected
10Reserved
1 1 PLL Clock is selected
PRES Programmable Clock
0 0 0 Selected clock
0 0 1 Selected clock divided by 2
0 1 0 Selected clock divided by 4
0 1 1 Selected clock divided by 8
1 0 0 Selected clock divided by 16
1 0 1 Selected clock divided by 32
1 1 0 Selected clock divided by 64
111Reserved
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25.9.12 PMC Interrupt Enable Register
Register Name: PMC_IER
Access Type: Write-only
• MOSCS: Main Oscillator Status Interrupt Enable
• LOCK: PLL Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• PCKRDYx: Programmab le Cloc k Ready x Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDYLOCK–MOSCS
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25.9.13 PMC Interrupt Disable Register
Register Name: PMC_IDR
Access Type: Write-only
• MOSCS: Main Oscillator Status Interrupt Disable
• LOCK: PLL Lo ck Interru p t Dis able
• MCKRDY: Master Clock Ready Interrupt Disable
• PCKRDYx: Programmab le Cloc k Ready x Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY
LOCK – MOSCS
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25.9.14 PMC Status Register
Register Name: PMC_SR
Access Type: Read-only
• MOSCS: MOSCS Flag Status
0 = Main oscillator is not stabilized.
1 = Main oscillator is stabilized.
• LOCK: PLL Lock Status
0 = PLL is not locked
1 = PLL is locked.
• MCKRDY: Master Clock Status
0 = Master Clock is not ready.
1 = Master Clock is ready.
• PCKRDYx: Programmable Clock Ready Status
0 = Programmable Clock x is not ready.
1 = Programmable Clock x is ready.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY
LOCK – MOSCS
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25.9.15 PMC Interrupt Mask Register
Register Name: PMC_IMR
Access Type: Read-only
• MOSCS: Main Oscillator Status Interrupt Mask
• LOCK: PLL Lo ck Interr u p t Ma s k
• MCKRDY: Master Clock Ready Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
0 = The corresponding interrupt is enabled.
1 = The corresponding interrupt is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––PCKRDY2PCKRDY1PCKRDY0
76543210
––––MCKRDY
LOCK – MOSCS
215
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26. Debug Unit (DBGU)
26.1 Overview
The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s
ARM-based systems.
The Debug Unit features a two-pin UART that can be used for seve ral debug and trace purposes and offers an
ideal medium for in-situ programm ing solutions and debu g monitor communica tions. Moreover, the a ssociation
with two peripheral da ta contro ller channels pe rmits packet h andling for t hese tasks with pro cessor ti me reduced to
a minimum.
The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator
of the ARM proces sor visible t o the sof tware. Th ese sign als indica te the sta t us of th e DCC r ead an d write r eg ist ers
and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control.
Chip Identifier registers per mit recognit ion of t he device an d its re vision. Th ese re giste rs inform as to the sizes and
types of the on-chip memor ies, as well as the set of embedded peripherals.
Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent
access to the syste m via the In-cir cu it Emu lator. This permits pro tec tio n of th e co de , sto re d in ROM.
216
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26.2 Block Diagram
Figure 26-1. Debug Unit Function al Block Diagram
Debug Unit Application Example
Peripheral DMA Controller
Baud Rate
Generator
DCC
Handler
ICE
Access
Handler
Transmit
Receive
Chip ID
Interrupt
Control
Peripheral
Bridge
Parallel
Input/
Output
DTXD
DRXD
Power
Management
Controller
ARM
Processor
force_ntrst
COMMRX
COMMTX
MCK
nTRST
Power-on
Reset
dbgu_irq
APB Debug Unit
R
Table 26-1. Debug Unit Pin Description
Pin Name Description Type
DRXD De bug Receive Data Input
DTXD Debug Transmit Data Output
Debug Unit
RS232 Drivers
Programming Tool Trace Console Debug Console
Boot Program Debug Monitor Trace Manager
217
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26.3 Product Dependencies
26.3.1 I/O Lines
Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the pro-
grammer must first conf igure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
26.3.2 Power Management
Depending on product int egra tio n, th e Debu g Unit clock may be cont rollable throu gh t he Powe r Mana gem ent Con-
troller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the
peripheral identif ier used for this purpose is 1.
26.3.3 Interrupt Source
Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the
Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug
Unit. Usually, the Debug Unit interrupt line connects to the interrupt sour ce 1 of the AIC, which may be shar ed with
the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 26-
1. This sharing requires the pro grammer to determine the source of the interrupt when the source 1 is triggered.
26.4 UART Operations
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with
parity). It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common
baud rate generator. Receiver timeout an d transmitter time guard are not implemented. However, all the imple-
mented features are compatible with those of a standard USART.
26.4.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the
transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate
Generator Register). If DBGU_BRGR is set to 0 , the baud rate clock is disabled and the Debug Unit's UART
remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud
rate is Master Clock divided by (16 x 65536).
Figure 26-2. Baud Rate Generator
Baud Rate MCK
16 CD×
----------------------=
MCK 16-bit Counter
0
Baud Rate
Clock
CD
CD
OUT
Divide
by 16
0
1
>1
Receiver
Sampling Clock
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6175M–ATARM–26-Oct-12
26.4.2 Receiver
26.4.2.1 Receiver Reset, Enable and Disable
After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can
be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts
looking for a start bit.
The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. I f the receiver is waiting for
a start bit, it is immediately stopped. However, if the rece iver has already detected a start bit and is receiving the
data, it waits for the stop bit before actually stopping its operation.
The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing
so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is
applied when data is bein g processed, this data is lost.
26.4.2.2 Star t De tectio n an d Data Samp ling
The Debug Unit only su ppo rts asynchr onous o per ation s, a nd this affects only its receiver. T he De bug Unit r eceiver
detects the start of a received chara cter by sampling the DRXD signal until it detects a va lid start bit. A low level
(space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock,
which is 16 times the baud rat e. Hence, a spac e that is long er than 7/16 of the bit period is detected as a valid start
bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid sta rt bit has bee n detec ted, the re ceiver sa mples the DR XD at the th eoretica l midpoin t of each bit . It
is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles
(0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the fall-
ing edge of the start bit was detect ed.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 26-3. Start Bit Detection
Figure 26-4. Character Reception
26.4.2.3 Receiver Ready
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in
DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register
DBGU_RHR is read.
Sampling Clock
DRXD
True Start
Detection D0
Baud Rate
Clock
D0 D1 D2 D3 D4 D5 D6 D7
DRXD
True Start Detection
Sampling Parity Bit Stop Bit
Example: 8-bit, parity enabled 1 stop
1 bit
period
0.5 bit
period
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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
Figure 26-5. Receiver Ready
26.4.2.4 Receiver Overrun
If DBGU_RHR has not been read b y the software (or the Peripheral Data Controller) since the last transfer, the
RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared
when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.
Figure 26-6. Receiver Overrun
26.4.2.5 Parity Error
Each time a character is received, the rec eiver calculates the parity of the received data bits, in accor dance with
the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit
PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control reg ister
DBGU_CR is written with the bit RSTSTA (R eset Status) at 1. If a new charact er is receive d before th e reset st atus
command is written, the PARE bit remains at 1.
Figure 26-7. Parity Error
26.4.2.6 Receiver Framing Error
When a start bit is detect ed, it ge nerat es a charact er rece ption wh en all th e data bit s have been sampled. The st op
bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same
time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit
RSTSTA at 1.
D0 D1 D2 D3 D4 D5 D6 D7 PS SD0 D1 D2 D3 D4 D5 D6 D7 P
DRXD
Read DBGU_RHR
RXRDY
D0 D1 D2 D3 D4 D5 D6 D7 PS SD0 D1 D2 D3 D4 D5 D6 D7 P
DRXD
RSTSTA
RXRDY
OVRE
stop stop
stop
D0 D1 D2 D3 D4 D5 D6 D7 PS
DRXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit
220
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6175M–ATARM–26-Oct-12
Figure 26-8. Receiver Framing Error
26.4.3 Transmitter
26.4.3.1 Transmitter Reset, Enable and Disable
After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmit-
ter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. Fro m this co mma nd, th e transmit t er
waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the
transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. Howe ver, if a character is being processed into the Shift Register and/or a
character has been written in the Transmit Holding Regist er, the charac ters are comp leted b efore the t ransmitte r is
actually stopped.
The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1.
This immediately stops the transmitter, whet her or not it is processing char acters.
26.4.3.2 Transmit Format
The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the
format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8
data bits, from the lowest to the highest bit, on e optional pari ty bit and on e stop bit at 1 ar e consecutively shif ted out
as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity
bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed
space or mark bit.
Figure 26-9. Character Tran sm iss ion
26.4.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transm itter Ready) is set in the status register DBGU_SR. The
transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the writ-
ten character is transferre d from DBGU_THR to the Shift Register. The b it TXRDY remains high until a second
character is written in DBGU_THR. As soon as the first character is completed, the last character written in
DBGU_THR is transferred into the shift register and TXRDY rises again, showing th at the holding registe r is empty.
When both the Shift Registe r and the DBGU_THR are empty, i.e., all th e characters written in DBGU_THR have
been processed, the bit TXEMPTY rises after the last stop bit has been completed.
D0 D1 D2 D3 D4 D5 D6 D7 PS
DRXD
RSTSTA
RXRDY
FRAME
Stop Bit
Detected at 0
stop
D0 D1 D2 D3 D4 D5 D6 D7
DTXD
Start
Bit Parity
Bit Stop
Bit
Example: Parity enabled
Baud Rate
Clock
221
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6175M–ATARM–26-Oct-12
Figure 26-10. Transmitter Control
26.4.4 Peripheral Data Controller
Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Con-
troller (PDC) chan ne l.
The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user
interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can
generate an inte rr up t.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in
DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a
data in DBGU_THR.
26.4.5 Test Modes
The Debug Unit supports three tests modes. These modes of operation are programmed by using the field
CHMODE (Channel Mode) in the mo de register DBGU_MR.
The Automatic Echo mode allows bit-by-bit retransm ission. When a bit is received on the DRXD line, it is sent to
the DTXD line. The transmitter operates normally, but has no ef fect on the DTXD line.
The Local Loopback mode allows the transmitte d characters to be received. DTXD and DRXD pins are not used
and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no
effect and the DTXD line is held high, as in idle state.
The Remote Lo opback mode direct ly connects the DRXD p in to the DTXD line. The tr ansmitter and the r eceiver
are disabled and have no effect. This mode allows a bit-by-bit retransmission.
DBGU_THR
Shift Register
DTXD
TXRDY
TXEMPTY
Data 0 Data 1
Data 0
Data 0
Data 1
Data 1S SPP
Write Data 0
in DBGU_THR Write Data 1
in DBGU_THR
stop
stop
222
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
Figure 26-11. Test Modes
26.4.6 Debug Communication Channel Support
The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel
of the ARM Processo r an d ar e dr ive n by the In -cir cu it Emu la tor .
The Debug Commun ication Channel contains two register s that are accessible through the ICE Breaker on the
JTAG side and through the coprocessor 0 on the ARM Processor side.
As a reminder, the following instructions are used to read and write the Debug Communication Channel:
MRC p14, 0, Rd, c1, c0, 0
Returns the debug communication data read register into Rd
MCR p14, 0, Rd, c1, c0, 0
Writes the value in Rd to the debug communication data write register.
The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the
debugger but not yet read by the processor, and that the write register has been written by the processor and not
yet read by the debugger , are wired on the two highe st bit s of th e statu s regi ster DBGU_SR. Th ese bits can g ener-
ate an interrupt. This f eature permits ha ndling under interrup t a debug link between a debug monitor running on the
target system and a debugger.
26.4.7 Chip Identifier
The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension
ID). Both registers contain a hard-wired value that is read-only. The fir st register contains the following fields:
Receiver
Transmitter Disabled
RXD
TXD
Receiver
Transmitter Disabled
RXD
TXD
VDD
Disabled
Receiver
Transmitter Disabled
RXD
TXD
Disabled
Automatic Echo
Local Loopback
Remote Loopback VDD
223
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6175M–ATARM–26-Oct-12
• EXT - shows the use of the extension identifier register
• NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
• ARCH - identifies the set of embedded peripheral
• SRAMSIZ - indicates the size of the embedded SRAM
• EPROC - indicates the embedded ARM processor
• VERSION - gives the revision of the silicon
The second register is device-dependent and reads 0 if the bit EXT is 0.
26.4.8 ICE Access Prevention
The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature
is implemented via the regist er Force NT RST (DBG U_FNR), that allows assertion of the NTRST signal of the ICE
Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller.
On standard devices, the FNTRST bit resets to 0 and thus does not prevent ICE access.
This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be
visible.
224
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6175M–ATARM–26-Oct-12
26.5 Debug Unit (DBGU) User Interface
Table 26-2. Memory Mapping
Offset Register Name Access Reset
0x0000 Control Regi ste r DBGU_CR Write-only –
0x0004 Mode Register DBGU_MR Read-write 0x0
0x0008 Interrupt Enable Register DBGU_IER Write-only –
0x000C Interrupt Disable Register DBGU_IDR Write-only –
0x0010 Interr upt Mask Register DBGU_IMR Read-only 0x0
0x0014 Status Register DBGU_SR Read-only –
0x0018 Receive Holding Register DBGU_RHR Read-only 0x0
0x001C Transmit Holding Register DBGU_THR Write-only –
0x0020 Baud Rate Generator Register DBGU_BRGR Read-write 0x0
0x0024 - 0x003C Reserved – – –
0x0040 Chip ID Reg ister DBGU_CIDR Read-only –
0x0044 Chip ID Exte nsion Register DBGU_EXID Read-only –
0x0048 Force NTRST Register DBGU_FNR Read-wr ite 0x0
0x004C - 0x00FC Reserved – – –
0x0100 - 0x0124 PDC Area – – –
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26.5.1 Debug Unit Control Register
Name: DBGU_CR
Access Type: Write-only
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset and disabled. If a character is being received, the re ception is aborted.
• RSTTX: Rese t Trans mit te r
0 = No effect.
1 = The transmitter logic is reset and disabled. If a charact er is being transmitted, the transmissio n is aborted.
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Dis able
0 = No effect.
1 = The receive r is di sa bled. If a char acte r is being pr ocessed and RSTRX is not set, the character is completed before the
receiver is stopped.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and
RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––
RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX ––
226
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26.5.2 Debug Unit Mode Register
Name: DBGU_MR
Access Type: Read-write
• PAR: Parity Type
• CHMODE: Channel Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CHMODE –– PAR –
76543210
––––––––
PAR Parity Type
0 0 0 Even parity
001Odd parity
0 1 0 Space: parity forced to 0
0 1 1 Mark: parity forced to 1
1 x x No parity
CHMODE Mode Description
00Normal Mode
0 1 Automatic Echo
1 0 Local Loopback
1 1 Remote Loopback
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26.5.3 Debug Unit Interrupt Enable Register
Name: DBGU_IER
Access Type: Write-only
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PA RE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• TXBUFE: Enable Buffer Empty Interrupt
• RXBUFF: Enable Buffer Full Interrupt
• COMMTX: Enable COMMTX (from ARM) Interrupt
• COMMRX: Enable COMMRX (from ARM) Interrupt
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
COMMRX COMMTX ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
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26.5.4 Debug Unit Interrupt Disable Register
Name: DBGU_IDR
Access Type: Write-only
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• TXBUFE: Disable Buffer Empty Interrupt
• RXBUFF: Disable Buffer Full Interrupt
• COMMTX: Disable COMMTX (from ARM) Interrupt
• COMMRX: Disable COMMRX (from ARM) Interrupt
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
COMMRX COMMTX ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
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26.5.5 Debug Unit Interrupt Mask Register
Name: DBGU_IMR
Access Type: Read-only
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Mask End of Receive Transfer Interrupt
• ENDTX: Mask End of Transmit Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
• TXBUFE: Mask TXBUFE Interrupt
• RXBUFF: Mask RXBUFF Interrupt
• COMMTX: Mask COMMTX Interrupt
• COMMRX: Mask COMMRX Interrupt
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
COMMRX COMMTX ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
230
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26.5.6 Debug Unit Status Re gi st er
Name: DBGU_SR
Access Type: Read-only
• RXRDY: Receiver Ready
0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
1 = At least one co mplete character has been received, transferred to DBGU_RHR and not yet read.
• TXRDY: Transmitter Ready
0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
1 = There is no character written to DBGU_THR not yet transferred to the Shift Register.
• ENDRX: End of Receiver Transfer
0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active.
• ENDTX: End of Transmitter Transfer
0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the transmitter Peri pheral Data Controller channel is active.
• OVRE: Overrun Error
0 = No overrun erro r ha s occ ur re d sin ce the las t RS TSTA.
1 = At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0 = No framing error has occurred since the last RSTSTA.
1 = At least one framin g error has occurred since the last RSTSTA.
• PA RE: Parity Error
0 = No parity error ha s occurred since the last RSTSTA.
1 = At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled.
1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter.
• TXBUFE: Transmission Buffer Empty
31 30 29 28 27 26 25 24
COMMRX COMMTX ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
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0 = The buffer empty signal from the transmitter PDC channel is ina ctive.
1 = The buffer empty signal from the transmitter PDC channel is active.
• RXBUFF: Receive Buffer Full
0 = The buffer full signal from the receiver PDC channel is inactive.
1 = The buffer full signal from the receiver PDC channel is active.
• COMMTX: Debug Communication Channel Write Status
0 = COMMTX from the ARM processor is inactive.
1 = COMMTX from the ARM processor is active.
• COMMRX: Debug Communication Channel Rea d Status
0 = COMMRX from the ARM processor is inactive.
1 = COMMRX from the ARM processor is active.
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26.5.7 Debug Unit Receiver Holding Register
Name: DBGU_RHR
Access Type: Read-only
• RXCHR: Received Character
Last received character if RXRDY is set.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
RXCHR
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26.5.8 Debug Unit Transmit Holding Register
Name: DBGU_THR
Access Type: Write-only
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current charac ter if TXRDY is not set.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TXCHR
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26.5.9 Debug Unit Baud Rate Generator Register
Name: DBGU_BRGR
Access Type: Read-write
• CD: Clock Divisor
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CD
76543210
CD
CD Baud Rate Clock
0 Disabled
1MCK
2 to 65535 MCK / (CD x 16)
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26.5.10 Debug Unit Chip ID Register
Name: DBGU_CIDR
Access Type: Read-only
• VERSION: Version of the Device
• EPROC: Embedded Processor
• NVPSIZ: Non volatile Program Memory Size
31 30 29 28 27 26 25 24
EXT NVPTYP ARCH
23 22 21 20 19 18 17 16
ARCH SRAMSIZ
15 14 13 12 11 10 9 8
NVPSIZ2 NVPSIZ
76543210
EPROC VERSION
EPROC Processor
0 0 1 ARM946ES™
0 1 0 ARM7TDMI®
100ARM920T
™
1 0 1 ARM926EJS™
NVPSIZ Size
0000None
00018K bytes
001016K bytes
001132K bytes
0100Reserved
010164K bytes
0110Reserved
0111128K bytes
1000Reserved
1001256K bytes
1010512K bytes
1011Reserved
11001024K bytes
1101Reserved
11102048K bytes
1111Reserved
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• NVPSIZ2 Second Nonvolatile Program Memory Size
• SRAMSIZ: Internal SRAM Size
NVPSIZ2 Size
0000None
00018K bytes
001016K bytes
001132K bytes
0100Reserved
010164K bytes
0110Reserved
0111128K bytes
1000Reserved
1001256K bytes
1010512K bytes
1011Reserved
11001024K bytes
1101Reserved
11102048K bytes
1111Reserved
SRAMSIZ Size
0000Reserved
00011K bytes
00102K bytes
00116K bytes
0100112K bytes
01014K bytes
011080K bytes
0111160K bytes
10008K bytes
100116K bytes
101032K bytes
101164K bytes
1100128K bytes
1101256K bytes
111096K bytes
1111512K bytes
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• ARCH: Architecture Identifier
• NVPTYP: Nonvolatile Program Memory Type
• EXT: Extension Flag
0 = Chip ID has a single register definition without extension
1 = An extended Chip ID exists.
ARCH
ArchitectureHex Bin
0x19 0001 1001 AT91SAM9xx Series
0x29 0010 1001 AT91SAM9XExx Series
0x34 0011 0100 AT91x34 Series
0x37 0011 0111 CAP7 Series
0x39 0011 1001 CAP9 Series
0x3B 0011 1011 CAP11 Series
0x40 0100 0000 AT91x40 Series
0x42 0100 0010 AT91x42 Series
0x55 0101 0101 AT91x55 Series
0x60 0110 0000 AT91SAM7Axx Series
0x61 0110 0001 AT91SAM7AQxx Series
0x63 0110 0011 AT91x63 Series
0x70 0111 0000 AT91SAM7Sxx Series
0x71 0111 0001 AT91SAM7XCxx Series
0x72 0111 0010 AT91SAM7SExx Series
0x73 0111 0011 AT91SAM7Lxx Series
0x75 0111 0101 AT91SAM7Xxx Series
0x92 1001 0010 AT91x92 Series
0xF0 1111 0000 AT75Cxx Series
NVPTYP Memory
000ROM
0 0 1 ROMless or on-chip Flash
1 0 0 SRAM emulating ROM
0 1 0 Embedded Flash Memory
011
ROM and Embedded Flash Memory
NVPSIZ is ROM size
NVPSIZ2 is Flash size
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26.5.11 Debug Unit Ch ip ID Extension Register
Name: DBGU_EXID
Access Type: Read-only
• EXID: Chip ID Extension
Reads 0 if the bit EXT in DBGU_CIDR is 0.
26.5.12 Debug Unit Force NTRST Register
Name: DBGU_FNR
Access Type: Read-write
• FNTRST: Force NTRST
0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal.
1 = NTRST of the ARM processor’s TAP controller is held low.
31 30 29 28 27 26 25 24
EXID
23 22 21 20 19 18 17 16
EXID
15 14 13 12 11 10 9 8
EXID
76543210
EXID
31 30 29 28 27 26 25 24
––––––– –
23 22 21 20 19 18 17 16
––––––– –
15 14 13 12 11 10 9 8
––––––– –
7654321 0
–––––––
FNTRST
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27. Parallel Input/Output Controller (PIO)
27.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output
lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of
an embedded peripheral. This assures effective optimization of the pins of a product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User
Interface.
Each I/O line of the PIO Controller features:
• An input change interrupt enabling level change dete ction on any I/O line.
• A glitch filter providing rejection of pulses lower than one-half of clock cycle.
• Multi-drive capability similar to an open drain I/O line.
• Control of the pull-up of the I/O line.
• Input visibility and output control.
The PIO Controller also featu res a synchronou s output pr oviding up to 32 bi ts of data ou tput in a
single write operation.
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27.2 Block Diagram
Figure 27-1. Block Diagram
Figure 27-2. Application Block Diagram
Embedded
Peripheral
Embedded
Peripheral
PIO Interrupt
PIO Controller
Up to 32 pins
PMC
Up to 32
peripheral IOs
Up to 32
peripheral IOs
PIO Clock
APB
AIC
Data, Enable
PIN 31
PIN 1
PIN 0
Data, Enable
On-Chip Peripherals
PIO Controller
On-Chip Peripheral Drivers
Control & Command
Driver
Keyboard Driver
Keyboard Driver General Purpose I/Os External Devices
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27.3 Product Dependencies
27.3.1 Pin Multiplexing
Each pin is configurab le, according to product de finition as either a gene ral-purpose I/O line
only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hard-
ware-defined and thus product-dependent, the hardware designer and programmer must
carefully determine the configuration of the PIO controllers required by their application. When
an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of
the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Con-
troller can contro l how th e pin is drive n by th e pr od u ct.
27.3.2 External Interrupt Lines
The interrupt signals FIQ and IRQ0 to IRQn are most gen erally multiplexed through the PIO
Controllers. However, it is no t necessary to assign the I/O line to the interrupt function as th e
PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as
inputs.
27.3.3 Power Management
The Power Management Controller controls the PIO Controller clock in order to save power.
Writing any of the registers of the user interface does not require the PIO Controller clock to be
enabled. This means th at the configuration o f the I/O lines does not requir e the PIO Controller
clock to be enabled.
However, when the clock is disabled, not all of the features of the PIO Controller are available.
Note that the Input Change Interrupt and the read of the pin level require the clock to be
validated.
After a hardware reset, the PIO clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line
information.
27.3.4 Interrupt Generation
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that
the PIO Co ntroller inter rupt lines are connected am ong the interr upt sources 2 to 31. Refe r to the
PIO Controller peripheral id entifier in the product description to identify the interrupt sources
dedicated to the PIO Con tro lle rs.
The PIO Controller inte rrupt can be generated only if the PIO Contr oller clock is enabled.
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27.4 Functional Description
The PIO Contro ller features u p to 32 fully-pro grammable I/O lines. Most of t he control logic asso-
ciated to each I/O is represented in Figure 27-3. In this description each signal shown
represents but one of up to 32 possible indexes.
Figure 27-3. I/O Line Control Logic
1
0
1
0
1
0
Glitch
Filter
Peripheral B
Input
Peripheral A
Input
1
0
PIO_IFDR[0]
PIO_IFSR[0]
PIO_IFER[0]
Edge
Detector
PIO_PDSR[0] PIO_ISR[0]
PIO_IDR[0]
PIO_IMR[0]
PIO_IER[0]
PIO Interrupt
(Up to 32 possible inputs)
PIO_ISR[31]
PIO_IDR[31]
PIO_IMR[31]
PIO_IER[31]
Pad
1
0
PIO_PUDR[0]
PIO_PUSR[0]
PIO_PUER[0]
PIO_MDDR[0]
PIO_MDSR[0]
PIO_MDER[0]
PIO_CODR[0]
PIO_ODSR[0]
PIO_SODR[0]
PIO_PDR[0]
PIO_PSR[0]
PIO_PER[0]
1
0
1
0
PIO_BSR[0]
PIO_ABSR[0]
PIO_ASR[0]
Peripheral B
Output Enable
Peripheral A
Output Enable
Peripheral B
Output
Peripheral A
Output
PIO_ODR[0]
PIO_OSR[0]
PIO_OER[0]
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27.4.1 Pull-up Resistor Control
Each I/O line is design ed with a n emb edded pu ll-up re sistor . The p ull-up resistor can be e nabled
or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-
up Disable Resistor). Wr iting in the se regist ers resu lts in sett ing or clear ing the corr esponding bit
in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is dis-
abled and readin g a 0 me a ns the pu ll-u p is enab le d.
Control of the pull-up resistor is possible regardless of the configurat ion of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.
27.4.2 I/O Line or Peripheral Func tion Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with
the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The regis-
ter PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates
whether the pin is co ntrolled by the cor respond ing perip heral or by the PIO Contr oller. A va lue of
0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO
controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral),
PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR
resets at 1. However, in some events, it is important that PIO lines are controlled by the periph-
eral (as in the case of memory chip select lines that must be driven inactive after reset or for
address lines that must be driven low for booting out of an external memory). Thu s, the reset
value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
27.4.3 Peripheral A or B Selection
The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The
selection is performed by writing PIO_ASR (A Select Register) an d PIO_BSR (Select B Re gis-
ter). PIO_ABSR (AB Sele ct Stat us Registe r) indicat es which periph eral l ine is curr ently selecte d.
For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corre-
sponding bit at level 1 indicates t hat peripheral B is selected.
Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral
input lines are always co nn ec te d to th e pin inpu t.
After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A.
However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line
mode.
Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the
pin. Howeve r, assignm ent of a pin to a pe ripheral f unction r equires a wr ite in the co rrespond ing
peripheral selection register (PIO_A SR or PIO_BSR) in addition t o a write in PIO_PDR.
27.4.4 Output ControlWhen the I/0 line is assigned to a peripheral func tio n, i.e. t he correspond ing bit in PIO_PSR is at
0, the drive of the I/O line is co ntrolled by the peripheral. Peripheral A or B, dependin g on the
value in PIO_ABSR, determines whether the pin is driven or not.
When the I/O line is cont ro lled by th e PI O contr oller, th e pi n can be con figur ed t o be d riven . T his
is done by writing PIO_ OER (Output Enable Register) and PIO_ODR (Output Disable Register).
The results of these write operations are detected in PIO_OSR (Output Status Register). When
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a bit in this r egister is at 0, the corresponding I/O line is used as an input only. When the bit is at
1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data
Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set
and clear PIO_ODSR (Ou tput Data Status Re gister), wh ich represents the d ata driven on the I /O
lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whet her the pin is configured to
be controlled by the PIO controller or assigned to a peripheral function. This enables configura-
tion of the I/O line prior to setti ng it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it
defines the first level driven on the I/O line.
27.4.5 Synchronous Data Output
Controlling all parallel busses using several PIOs requires two successive write operations in the
PIO_SODR and PIO_CODR registers. This may lead to un expected transient values. The PIO
controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output
Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are
written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable
Register) and cleared by writing to PIO_OWDR (Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at
0x0.
27.4.6 Multi Drive Control (Open Drain)
Each I/O can be independently progr ammed in Open Drain by using the Multi Drive feature. This
feature permits several drivers to be connected on the I/O line which is driven low only by each
device. An ext ernal pull- up resist or (or ena bling of th e interna l one) is ge nerally requir ed to gua r-
antee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and
PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line
is controlled by the PIO contro ller or assigne d to a peripher al function. PI O_MDSR (Multi-dr iver
Status Register) indicates the pins that are configured t o support external drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
27.4.7 Output Line Timings
Figure 27-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by
directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is
set. Figure 27-4 also shows when the feedback in PIO_PDSR is available.
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Figure 27-4. Output Line Timings
27.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
27.4.9 Input Glitch Filtering
Optional input glitch fil te rs are ind epe ndent ly pr ogra mmab le on each I/O line . When t he glitch f il-
ter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically
rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse
durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not
be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be
visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its
duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle
latency if the pin level change occurs before a rising edge. However, this latency does not
appear if the pin level change occurs before a falling edge. This is illustrated in Figure 27-5.
The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals.
It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The
glitch filters require that the PIO Contro ller clock is enabled.
2 cycles
APB Access
2 cycles
APB Access
MCK
Write PIO_SODR
Write PIO_ODSR at 1
PIO_ODSR
PIO_PDSR
Write PIO_CODR
Write PIO_ODSR at 0
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Figure 27-5. Input Glitch Filter Timing
27.4.10 Input Change Interrupt
The PIO Controller can be program med to generat e an interru pt when it detects an inp ut change
on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable
Register) and PIO_IDR (Int errupt Disable Register), which respectively e nable and disable the
input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask
Register). As Inp ut chang e de tect ion is possib le on ly by comp aring t wo su ccessive samplin gs of
the input of the I/O line, the PIO Cont roller clo ck must be enabled . The In put Ch ang e In terr upt is
available, rega rdless of the configuration of the I/O line, i.e. configured as an input only, con-
trolled by the PIO Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. The interrupt signals of the thirty-two channels are ORed-wire d together to gen-
erate a single interru pt signal to the Advanced Interrupt Controller.
When the software re ads PIO_ISR, all t he interrupts ar e automaticall y cleared. T his signifies that
all the interrupts that are pending when PIO_ISR is read must be handled.
Figure 27-6. Input Change Interrupt Timings
27.5 I/O Lines Programming Example
The programing example as shown in Table 27-1 below is used to define the following
configuration.
• 4-bit output po rt on I/O lines 0 to 3, (should be written in a single write operation), open-drain,
with pull-up resistor
MCK
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle 1 cycle 1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles up to 2 cycles
1 cycle
1 cycle
MCK
Pin Level
Read PIO_ISR APB Access
PIO_ISR
APB Access
247
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
• Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no
pull-up resistor
• Four input signa ls on I/O lines 8 to 11 (to read push-b utton states for example), with pull-up
resistors, glitch filters and input change interrupts
• F our input signals on I /O line 12 to 15 t o read an external de vice st atus (polle d, thus no inp ut
change interrupt), no pull-up resistor, no glitch filter
• I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
• I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor
• I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor
Table 27-1. Programming Example
Register Value to be Written
PIO_PER 0x0000 FFFF
PIO_PDR 0x0 FFF 0000
PIO_OER 0x0000 00FF
PIO_ODR 0x0FFF FF00
PIO_IFER 0x0000 0F00
PIO_IFDR 0x0FFF F0FF
PIO_SODR 0x0000 0000
PIO_CODR 0x0FFF FFFF
PIO_IER 0x0F00 0F00
PIO_IDR 0x00FF F0FF
PIO_MDER 0x0000 000F
PIO_MDDR 0x0FFF FFF0
PIO_PUDR 0x00F0 00F0
PIO_PUER 0x0F0F FF0F
PIO_ASR 0x0F0F 0000
PIO_BSR 0x00F0 0000
PIO_O WER 0x0000 000F
PIO_OWDR 0x0FFF FFF0
248
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6 Programmabl e Multibit ECC Error Location (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Control-
ler User Interface reg isters. Each register is 32 bits wide. If a parallel I/O lin e is not defined,
writing to the corr esponding bits ha s no effect. Undefined b its read zer o. If the I/ O line is not mul-
tiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns
1 systematically.
Table 27-2. Register Mapping
Offset Register Name Access Reset
0x0000 PIO Enable Register PIO_PER Write-only –
0x0004 PIO Disable Register PIO_PDR Write-only –
0x0008 PIO Status Register PIO_PSR Read-only (1)
0x000C Reserved
0x0010 Output Enable Register PIO_OER Write-only –
0x0014 Output Disable Register PIO_ODR Write-only –
0x0018 Output Status Register PIO_OSR Read-only 0x0000 0000
0x001C Reserved
0x0020 Glitch Input Filte r Enable Register PIO_IFER Write-only –
0x0024 Glitch Input Filte r Disable Register PIO_IFDR Write-only –
0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000
0x002C Reserved
0x0030 Set Output Data Register PIO_SODR Write-only –
0x0034 Clear Output Data Register PIO_CODR Write-only
0x0038 Output Data Status Register PIO_ODSR Read-only
or(2)
Read-write –
0x003C Pin Data Status Register PIO_PDSR Read-only (3)
0x0040 Interrupt Enable Register PIO_IER Write-only –
0x0044 Interrupt Disable Register PIO_IDR Write-only –
0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000
0x004C Interrupt Status Register(4) PIO_ISR Read-only 0x00000000
0x0050 Multi-driver Enable Register PIO_MDER Write-only –
0x0054 Multi-driver Disable Register PIO_MDDR Write-only –
0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000
0x005C Reserved
0x0060 Pull-up Disa ble Register PIO_PUDR Write-only –
0x0064 Pull-up Ena ble Register PIO_PUER Write-only –
0x0068 Pad Pull-up Status Register PIO_PUSR Read-only 0x00000000
0x006C Reserved
249
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
Notes: 1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second
register.
0x0070 P eripheral A Select Register(5) PIO_ASR Write-only –
0x0074 P eripheral B Select Register(5) PIO_BSR Write-only –
0x0078 AB Status Register(5) PIO_ABSR Read-only 0x00000000
0x007C
to
0x009C Reserved
0x00A0 Output Write Enable PIO_OWER Write-only –
0x00A4 Output Write Disable PIO_OWDR Write-only –
0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000
0x00AC Reserved
Table 27-2. Register Mapping (Continued)
Offset Register Name Access Reset
250
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.1 PIO Controller PIO Enable Register
Name: PIO_PER
Access Type: Write-only
• P0-P31: PIO Enable
0 = No effect.
1 = Enables the PIO to contr ol the corresponding pin (disables peripheral control of the pin).
27.6.2 PIO Controller PIO Disable Register
Name: PIO_PDR
Access Type: Write-only
• P0-P31: PIO Disable
0 = No effect.
1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
251
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.3 PIO Controller PIO Status Register
Name: PIO_PSR
Access Type: Read-only
• P0-P31: PIO Status
0 = PIO is inactive on the corresponding I/O line (peripheral is active).
1 = PIO is active on the corresponding I/O line (peripheral is inactive).
27.6.4 PIO Controller Output Enable Register
Name: PIO_OER
Access Type: Write-only
• P0-P31: Output Enabl e
0 = No effect.
1 = Enables the output on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
252
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.5 PIO Controller Output Disable Register
Name: PIO_ODR
Access Type: Write-only
• P0-P31: Output Disable
0 = No effect.
1 = Disables the output on the I/O line.
27.6.6 PIO Controller Output Status Register
Name: PIO_OSR
Access Type: Read-only
• P0-P31: Output Status
0 = The I/O line is a pure input.
1 = The I/O line is enabled in output.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
253
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.7 PIO Controller Input Filter Enable Register
Name: PIO_IFER
Access Type: Write-only
• P0-P31: Input Filter Enable
0 = No effect.
1 = Enables the input gli tch filter on the I/O line.
27.6.8 PIO Controller Input Filter Disable Register
Name: PIO_IFDR
Access Type: Write-only
• P0-P31: Input Filter Disable
0 = No effect.
1 = Disables the input glitch filter on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
254
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.9 PIO Controller Input Filter Status Register
Name: PIO_IFSR
Access Type: Read-only
• P0-P31: Input Filer Status
0 = The input glitch filter is disabled on the I/O line.
1 = The input glitch filter is en abled on the I/O line.
27.6.10 PIO Controller Set Output Data Register
Name: PIO_SODR
Access Type: Write-only
• P0-P31: Set Output Data
0 = No effect.
1 = Sets the data to be driven on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
255
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.11 PIO Controller Clear Output Data Register
Name: PIO_CODR
Access Type: Write-only
• P0-P31: Set Output Data
0 = No effect.
1 = Clears the data to be driven on the I/ O line.
27.6.12 PIO Controller Output Data Status Register
Name: PIO_ODSR
Access Type: Read-only or Read-write
• P0-P31: Output Da ta Status
0 = The data to be driven on the I/O line is 0.
1 = The data to be driven on the I/O line is 1.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
256
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.13 PIO Controller Pin Data Status Register
Name: PIO_PDSR
Access Type: Read-only
• P0-P31: Output Da ta Status
0 = The I/O line is at level 0.
1 = The I/O line is at level 1.
27.6.14 PIO Controller Interrupt Enable Register
Name: PIO_IER
Access Type: Write-only
• P0-P31: Input Change Interrupt Enable
0 = No effect.
1 = Enables the Input Change Interrupt on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
257
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.15 PIO Controller Interrupt Disable Register
Name: PIO_IDR
Access Type: Write-only
• P0-P31: Input Change Interrupt Disable
0 = No effect.
1 = Disables the Input Change Interrupt on the I/O line.
27.6.16 PIO Controller Interrupt Mask Register
Name: PIO_IMR
Access Type: Read-only
• P0-P31: Input Change Interrupt Mask
0 = Input Change Interrupt is disabled on the I/O line.
1 = Input Change Interrupt is enabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
258
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.17 PIO Controller Interrupt Status Register
Name: PIO_ISR
Access Type: Read-only
• P0-P31: Input Change Interrupt Status
0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
1 = At least one In put Change has been detected on the I/O line since PIO_ISR was last read or since re set.
27.6.18 PIO Multi-driver Enable Register
Name: PIO_MDER
Access Type: Write-only
• P0-P31: Multi Drive Enable.
0 = No effect.
1 = Enables Multi Drive on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
259
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.19 PIO Multi-driver Disable Regi st er
Name: PIO_MDDR
Access Type: Write-only
• P0-P31: Multi Drive Disable.
0 = No effect.
1 = Disables Multi Drive on the I/ O line.
27.6.20 PIO Multi-driver Status Register
Name: PIO_MDSR
Access Type: Read-only
• P0-P31: Multi Drive Status.
0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level.
1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
260
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.21 PIO Pull Up Disable Register
Name: PIO_PUDR
Access Type: Write-only
• P0-P31: Pull Up Disable.
0 = No effect.
1 = Disables the pull up resistor on the I/O line.
27.6.22 PIO Pull Up Enable Register
Name: PIO_PUER
Access Type: Write-only
• P0-P31: Pull Up Enable.
0 = No effect.
1 = Enables the pull up resistor on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
261
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.23 PIO Pull Up Status Register
Name: PIO_PUSR
Access Type: Read-only
• P0-P31: Pull Up Status.
0 = Pull Up resistor is enabled on the I/O line.
1 = Pull Up resistor is disabled on the I/O line.
27.6.24 PIO Peripheral A Select Register
Name: PIO_ASR
Access Type: Write-only
• P0-P31: Peripheral A Select.
0 = No effect.
1 = Assigns the I/O line to the Peripheral A function.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
262
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.25 PIO Peripheral B Select Register
Name: PIO_BSR
Access Type: Write-only
• P0-P31: Peripheral B Select.
0 = No effect.
1 = Assigns the I/O line to the peripheral B function.
27.6.26 PIO Peripheral A B Status Register
Name: PIO_ABSR
Access Type: Read-only
• P0-P31: Peripheral A B Status.
0 = The I/O line is assigned to the Peripheral A.
1 = The I/O line is assigned to the Peripheral B.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
263
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.27 PIO Output Write Enable Register
Name: PIO_OWER
Access Type: Write-only
• P0-P31: Output Write Enable.
0 = No effect.
1 = Enables writing PIO_ODSR for t he I/O line.
27.6.28 PIO Output Write Disable Register
Name: PIO_OWDR
Access Type: Write-only
• P0-P31: Output Write Disable.
0 = No effect.
1 = Disables writing PIO_ODSR for the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
264
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
27.6.29 PIO Output Write Status Register
Name: PIO_OWSR
Access Type: Read-only
• P0-P31: Output Write Status.
0 = Writing PIO_ODSR does not affect the I/O line.
1 = Writing PIO_ODSR affects the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
265
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12