SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 Timing From Microseconds to Hours Astable or Monostable Operation Adjustable Duty Cycle TTL-Compatible Output Can Sink or Source Up To 200 mA description/ordering information These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. NE555 . . . D, P, PS, OR PW PACKAGE SA555 . . . D OR P PACKAGE SE555 . . . D, JG, OR P PACKAGE (TOP VIEW) GND TRIG OUT RESET 1 8 2 7 3 6 4 5 VCC DISCH THRES CONT SE555 . . . FK PACKAGE (TOP VIEW) NC GND NC VCC NC D D D D NC TRIG NC OUT NC 4 3 2 1 20 19 18 5 17 6 16 NC DISCH NC THRES NC NC RESET NC CONT NC 15 7 The threshold and trigger levels normally are 14 8 two-thirds and one-third, respectively, of VCC. 9 10 11 12 13 These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above NC - No internal connection the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground. The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated ! " # $%! & % & ! '()(*+* "$ ! " & % & ! POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 description/ordering information (continued) ORDERING INFORMATION TA VTHRES MAX VCC = 15 V PACKAGE PDIP (P) Tube of 50 NE555P Tube of 75 NE555D Reel of 2500 NE555DR Reel of 2000 NE555PSR Tube of 150 NE555PW Reel of 2000 NE555PWR Tube of 50 SA555P Tube of 75 SA555D Reel of 2000 SA555DR Tube of 50 SE555P Tube of 75 SE555D Reel of 2500 SE555DR CDIP (JG) Tube of 50 SE555JG LCCC (FK) Tube of55 SE555FK SOIC (D) 0C to 70C 11.2 V SOP (PS) TSSOP (PW) PDIP (P) -40C -40 C to 85 85C C 11.2 V SOIC (D) PDIP (P) -55C 125C -55 C to 125 C 10.6 V ORDERABLE PART NUMBER SOIC (D) TOP-SIDE MARKING NE555P NE555 N555 N555 SA555P SA555 SE555P SE555D SE555JG SE555FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE RESET TRIGGER VOLTAGE THRESHOLD VOLTAGE OUTPUT DISCHARGE SWITCH Low Irrelevant Irrelevant Low On High <1/3 VDD Irrelevant High Off High >1/3 VDD >2/3 VDD Low On High >1/3 VDD <2/3 VDD Voltage levels shown are nominal. 2 POST OFFICE BOX 655303 As previously established * DALLAS, TEXAS 75265 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 functional block diagram VCC 8 CONT 5 RESET 4 I 2 TRIG II R1 6 THRES R S I I 1 I I 3 OUT I I 7 DISCH 1 GND Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: RESET can override TRIG, which can override THRES. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage (CONT, RESET, THRES, and TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 mA Package thermal impedance, JA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85C/W PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149C/W Package thermal impedance, JC (see Notes 4 and 5): FK package . . . . . . . . . . . . . . . . . . . . . . . . . 5.61C/W JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . 300C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) - TC)/JC. Operating at the absolute maximum TJ of 150C can affect reliability. 5. The package thermal impedance is calculated in accordance with MIL-STD-883. recommended operating conditions VCC VI IO TA 4 Supply voltage MIN MAX SA555, NE555 4.5 16 SE555 4.5 18 Input voltage (CONT, RESET, THRES, and TRIG) VCC 200 Output current Operating free-air temperature POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 NE555 0 SA555 -40 85 SE555 -55 125 UNIT V V mA 70 C C SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 electrical characteristics, VCC = 5 V to 15 V, TA = 25C (unless otherwise noted) PARAMETER MIN THRES voltage level VCC = 15 V VCC = 5 V TYP MAX MIN 9.4 10 10.6 2.7 3.3 4 30 250 5 5.2 THRES current (see Note 6) 4.8 VCC = 15 V TA = -55C to 125C TRIG voltage level TRIG current 3 1.45 VCC = 5 V RESET current DISCH switch off-state current 9.6 TA = -55C to 125C Low-level output voltage TA = -55C to 125C TA = -55C to 125C VCC = 15 V, IOL = 50 mA TA = -55C to 125C VCC = 5 V, IOH = -100 mA Output high, No load 4.2 30 250 4.5 5 5.6 1.1 1.67 2.2 0.5 2 0.7 1 0.3 V 0.1 0.4 -0.4 -1 -0.4 -1.5 20 100 10 10.4 A V 20 100 9 10 11 2.6 3.3 4 0.1 0.25 0.4 0.75 2 2.5 mA nA 10.4 3.3 3.8 V 3.8 0.15 0.5 2.2 2.7 V 2.5 2.5 0.35 0.1 0.2 0.15 0.25 0.1 0.35 0.15 0.4 0.8 13.3 12.75 13.3 12 12.5 3 TA = -55C to 125C VCC = 15 V nA 1 13 TA = -55C to 125C IOH = -200 mA V 0.2 TA = -55C to 125C IOL = 8 mA VCC = 15 V, 11.2 3.3 0.4 TA = -55C to 125C VCC = 15 V, IOH = -100 mA 10 2.4 0.1 2.9 TA = -55C to 125C IOL = 200 mA VCC = 5 V, Supply current 1 2 VCC = 5 V, IOL = 5 mA Output low, No load 0.9 0.7 0.4 VCC = 15 V, IOL = 100 mA 1.9 0.5 0.1 VCC = 15 V, IOL = 10 mA VCC = 15 V, VCC = 5 V, IOL = 3.5 mA High-level output voltage 1.67 9.6 2.9 VCC = 5 V 8.8 1.1 RESET at 0 V CONT voltage (open circuit) MAX 1.9 TA = -55C to 125C RESET at VCC VCC = 15 V UNIT TYP 6 TA = -55C to 125C TRIG at 0 V 0.3 RESET voltage level NE555 SA555 SE555 TEST CONDITIONS 12.5 3.3 2.75 V 3.3 2 VCC = 5 V VCC = 15 V 10 12 10 15 3 5 3 6 9 10 9 13 mA VCC = 5 V 2 4 2 5 NOTE 6: This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. For example, when VCC = 5 V, the maximum value is R = RA + RB 3.4 M, and for VCC = 15 V, the maximum value is 10 M. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 operating characteristics, VCC = 5 V and 15 V TEST CONDITIONS PARAMETER Initial error of timing interval Each timer, monostable Each timer, astable TA = 25C Temperature coefficient of timing interval Each timer, monostable Each timer, astable TA = MIN to MAX Supply-voltage sensitivity of timing interval Each timer, monostable Each timer, astable TA = 25C NE555 SA555 SE555 MIN TYP MAX 0.5 1.5* 1.5 30 UNIT TYP MAX 1 3 % 2.25 100* 90 0.05 MIN 50 ppm/C 150 0.2* 0.15 0.1 0.5 %/V 0.3 Output-pulse rise time CL = 15 pF, TA = 25C 100 200* 100 300 ns Output-pulse fall time CL = 15 pF, TA = 25C 100 200* 100 300 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. Values specified are for a device in a monostable circuit similar to Figure 9, with the following component values: RA = 2 k to 100 k, C = 0.1 F. Values specified are for a device in an astable circuit similar to Figure 12, with the following component values: RA = 1 k to 100 k, C = 0.1 F. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 2 1 0.7 0.4 IIII IIIII IIIII III IIIII IIIII IIII IIII IIII IIII IIII 10 7 VCC = 5 V TA = -55C TA = 25C IIII TA = 125C 0.2 0.1 0.07 0.04 VOL - Low-Level Output Voltage - V VOL - Low-Level Output Voltage - V 10 7 VCC = 10 V 4 2 TA = 25C 1 0.7 TA= -55C TA = 125C 0.4 0.2 0.1 0.07 0.04 0.02 0.02 0.01 0.01 1 2 4 7 10 20 40 1 70 100 2 TA = -55C 1 0.7 TA = 25C 0.2 TA = 125C 0.1 0.07 0.04 1.6 1.2 0.8 0.6 0.4 0.01 0 4 7 10 20 40 70 100 IOL - Low-Level Output Current - mA TA = 125C 1 0.2 2 70 100 TA = 25C 1.4 0.02 1 40 TA = -55C 1.8 2 0.4 20 IIII IIII IIII IIII 2.0 VCC = 15 V ( VCC - VOH) - Voltage Drop - V VOL - Low-Level Output Voltage - V 4 10 DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT IIIII IIIII 7 Figure 2 Figure 1 10 7 4 IOL - Low-Level Output Current - mA IOL - Low-Level Output Current - mA IIIIII IIIIII VCC = 5 V to 15 V 1 2 4 7 10 20 40 70 100 IOH - High-Level Output Current - mA Figure 3 Figure 4 Data for temperatures below 0C and above 70C are applicable for SE555 circuits only. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 TYPICAL CHARACTERISTICS NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs SUPPLY VOLTAGE SUPPLY CURRENT vs SUPPLY VOLTAGE Pulse Duration Relative to Value at VCC = 10 V 10 Output Low, No Load 9 I CC - Supply Current - mA 8 TA = 25C 7 6 5 TA = -55C 4 TA = 125C 3 2 1 0 5 6 7 8 9 10 12 11 13 14 1.015 1.010 1.005 1 0.995 0.990 0.985 15 0 5 VCC - Supply Voltage - V Figure 5 PROPAGATION DELAY TIME vs LOWEST VOLTAGE LEVEL OF TRIGGER PULSE 300 1.015 VCC = 10 V tPD - Propagation Delay Time - ns Pulse Duration Relative to Value at TA = 25C 20 Figure 6 NORMALIZED OUTPUT PULSE DURATION (MONOSTABLE OPERATION) vs FREE-AIR TEMPERATURE 1.010 1.005 1 0.995 0.990 250 TA = -55C 200 TA = 0C 150 100 TA = 25C TA = 70C 50 TA = 125C 0.985 -75 0 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C 0 0.1 x VCC 0.2 x VCC 0.3 x VCC 0.4 x VCC Lowest Voltage Level of Trigger Pulse Figure 7 Figure 8 Data for temperatures below 0C and above 70C are applicable for SE555 series circuits only. 8 15 10 VCC - Supply Voltage - V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 APPLICATION INFORMATION monostable operation For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high, and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1. IIIII IIIII IIIII IIIII RA = 9.1 k CL = 0.01 F RL = 1 k See Figure 9 RA 5 II 4 7 6 Input 2 8 CONT VCC RL RESET DISCH OUT 3 Input Voltage Voltage - 2 V/div VCC (5 V to 15 V) Output Output Voltage THRES TRIG IIIIII GND 1 Capacitor Voltage Pin numbers shown are for the D, JG, P, PS, and PW packages. Time - 0.1 ms/div Figure 9. Circuit for Monostable Operation Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC. POST OFFICE BOX 655303 10 RA = 10 M 1 tw - Output Pulse Duration - s Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the sequence ends only if TRIG is high at the end of the timing interval. Because of the threshold level and saturation voltage of Q1, the output pulse duration is approximately tw = 1.1RAC. Figure 11 is a plot of the time constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is constant during the time interval. Figure 10. Typical Monostable Waveforms RA = 1 M 10-1 10-2 10-3 RA = 100 k RA = 10 k 10-4 RA = 1 k 10-5 0.001 0.01 0.1 1 10 100 C - Capacitance - F Figure 11. Output Pulse Duration vs Capacitance * DALLAS, TEXAS 75265 9 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 APPLICATION INFORMATION astable operation As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB. This astable connection results in capacitor C charging and discharging between the threshold-voltage level (0.67 x VCC) and the trigger-voltage level (0.33 x VCC). As in the monostable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. IIIIIIIII IIIIIIIII IIIIIIIII VCC (5 V to 15 V) RA = 5 kW RB = 3 kW C = 0.15 F RA RB Open (see Note A) 5 CONT 4 RESET 7 DISCH 8 VCC I 6 2 RL 3 OUT Output tH THRES TRIG Output Voltage tL GND C Voltage - 1 V/div 0.01 F 1 Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications. Figure 12. Circuit for Astable Operation 10 RL = 1 kW See Figure 12 POST OFFICE BOX 655303 Capacitor Voltage Time - 0.5 ms/div Figure 13. Typical Astable Waveforms * DALLAS, TEXAS 75265 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 APPLICATION INFORMATION astable operation (continued) Figure 13 shows typical waveforms generated during astable operation. The output high-level duration tH and low-level duration tL can be calculated as follows: 100 k RA + 2 RB = 1 k + 0.693 (R ) R C A B) t + 0.693 (R C L B) H Other useful relationships are shown below. period + t ) t + 0.693 (R ) 2R ) C H L A B 1.44 frequency [ (R ) 2R ) C A B Output driver duty cycle + t R L B + t )t R ) 2R H L A B Output waveform duty cycle R t B H + 1- + t )t R ) 2R H L A B R t B Low-to-high ratio + L + t R ) R H A B POST OFFICE BOX 655303 f - Free-Running Frequency - Hz t RA + 2 RB = 10 k 10 k RA + 2 RB = 100 k 1k 100 10 1 RA + 2 RB = 1 M RA + 2 RB = 10 M 0.1 0.001 0.01 0.1 1 10 100 C - Capacitance - F Figure 14. Free-Running Frequency * DALLAS, TEXAS 75265 11 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 APPLICATION INFORMATION missing-pulse detector The circuit shown in Figure 15 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure 16. VCC (5 V to 15 V) Input 2 8 VCC OUT 0.01 F 3 TRIG DISCH 5 RL CONT THRES GND VCC = 5 V RA = 1 k C = 0.1 F See Figure 15 RA III Output 7 6 Voltage - 2 V/div 4 RESET IIIII IIIII IIIII IIIII Input Voltage IIIII IIIII C Output Voltage 1 A5T3644 Capacitor Voltage Pin numbers shown are shown for the D, JG, P, PS, and PW packages. Figure 15. Circuit for Missing-Pulse Detector 12 POST OFFICE BOX 655303 Time - 0.1 ms/div Figure 16. Completed-Timing Waveforms for Missing-Pulse Detector * DALLAS, TEXAS 75265 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 APPLICATION INFORMATION frequency divider By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency divider. Figure 17 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. IIIII IIIII IIIII IIIII Voltage - 2 V/div VCC = 5 V RA = 1250 C = 0.02 F See Figure 9 Input Voltage Output Voltage Capacitor Voltage Time - 0.1 ms/div Figure 17. Divide-by-Three Circuit Waveforms pulse-width modulation The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 19 shows the resulting output pulse-width modulation. While a sine-wave modulation signal is shown, any wave shape could be used. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 APPLICATION INFORMATION VCC (5 V to 15 V) RESET 2 Clock Input RL 8 VCC OUT TRIG 5 CONT Output 7 THRES IIIIIIII IIIIIIII IIIIII IIIIII 6 Clock Input Voltage IIIII IIIII IIIIII GND C 1 RA = 3 k C = 0.02 F RL = 1 k See Figure 18 Modulation Input Voltage 3 DISCH Modulation Input (see Note A) RA Voltage - 2 V/div 4 IIII IIII IIII Output Voltage Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Capacitor Voltage Time - 0.5 ms/div Figure 19. Pulse-Width-Modulation Waveforms Figure 18. Circuit for Pulse-Width Modulation pulse-position modulation As shown in Figure 20, any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 21 shows a triangular-wave modulation signal for such a circuit; however, any wave shape could be used. VCC (5 V to 15 V) 8 RESET 2 VCC OUT RA 3 Output TRIG DISCH Modulation Input 5 (see Note A) RL RA = 3 k RB = 500 RL = 1 k See Figure 20 CONT THRES 7 6 RB GND C Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. Figure 20. Circuit for Pulse-Position Modulation 14 POST OFFICE BOX 655303 Voltage - 2 V/div 4 IIIII IIIII IIIII IIIII IIIIIIII IIIIIIII Modulation Input Voltage IIIII IIIII IIIIII IIIIII Output Voltage Capacitor Voltage Time - 0.1 ms/div Figure 21. Pulse-Position-Modulation Waveforms * DALLAS, TEXAS 75265 SLFS022E - SEPTEMBER 1973 - REVISED MARCH 2004 APPLICATION INFORMATION sequential timer Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 22 shows a sequencer circuit with possible applications in many systems, and Figure 23 shows the output waveforms. VCC 4 RESET 2 8 VCC 3 OUT TRIG S DISCH 5 CONT 4 RESET RA 33 k 2 0.001 F 7 1 0.01 F 6 TRIG CONT 0.01 F CA CA = 10 F RA = 100 k RB Output A THRES GND 1 CB 2 0.01 F Output B 8 VCC 3 OUT TRIG DISCH 5 6 CB = 4.7 F RB = 100 k 4 RESET 33 k 0.001 F DISCH 7 5 THRES GND 8 VCC 3 OUT CONT THRES GND 1 RC 7 6 CC CC = 14.7 F RC = 100 k Output C Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0. Figure 22. Sequential Timer Circuit IIIII II IIIIII See Figure 22 Voltage - 5 V/div Output A IIIII II II IIIIII tw A twA = 1.1 RACA tw B IIII IIII twB = 1.1 RBCB Output B IIII IIIIIIII Output C tw C twC = 1.1 RCCC II II t=0 t - Time - 1 s/div Figure 23. Sequential Timer Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2006 PACKAGING INFORMATION Orderable Device Status (1) JM38510/10901BPA NE555D Pins Package Eco Plan (2) Qty Package Drawing ACTIVE CDIP JG 8 1 TBD A42 SNPB ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type NE555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type NE555PSLE OBSOLETE SO PS 8 NE555PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PWE4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NE555Y OBSOLETE TBD Call TI SA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SE555D ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM SE555DR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-1-220C-UNLIM TBD 0 Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) Package Type Call TI N / A for Pkg Type Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2006 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SE555FKB ACTIVE LCCC FK 20 1 TBD SE555JG ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type SE555JGB ACTIVE CDIP JG 8 1 TBD A42 SNPB N / A for Pkg Type SE555N OBSOLETE PDIP N 8 TBD Call TI SE555P ACTIVE PDIP P 8 Pb-Free (RoHS) CU NIPDAU 50 Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type Call TI N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MPDI001A - JANUARY 1995 - REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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