3.0 kV RMS/3.75 kV RMS
Quad Digital Isolators
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I Document Feedback
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FEATURES
High common-mode transient immunity: 100 kV/µs
High robustness to radiated and conducted noise
Low propagation delay
13 ns maximum for 5 V operation
15 ns maximum for 1.8 V operation
150 Mbps maximum guaranteed data rate
Safety and regulatory approvals
UL recognition
3000 V rms/3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak
CQC certification per GB4943.1-2011
Backward compatibility
ADuM140E1/ADuM141E1/ADuM142E1 pin-compatible
with ADuM1400/ADuM1401/ADuM1402
Low dynamic power consumption
1.8 V to 5 V level translation
High temperature operation: 125°C
Fail-safe high or low options
16-lead, RoHS compliant, SOIC package
Qualified for automotive applications
APPLICATIONS
General-purpose multichannel isolation
Serial peripheral interface (SPI)/data converter isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E1 are quad-channel digital isolators
based on Analog Devices, Inc., iCoupler® technology. Combining
high speed, complementary metal-oxide semiconductor (CMOS)
and monolithic air core transformer technology, these isolation
components provide outstanding performance characteristics
superior to alternatives such as optocoupler devices and other
integrated couplers. The maximum propagation delay is 13 ns
with a pulse width distortion of less than 3 ns at 5 V operation.
Channel matching is tight at 3.0 ns maximum.
The ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E data channels are independent and
are available in a variety of configurations with a withstand
voltage rating of 3.0 kV rms or 3.75 kV rms (see the Ordering
Guide). The devices operate with the supply voltage on either
side ranging from 1.8 V to 5 V, providing compatibility with
lower voltage systems as well as enabling voltage translation
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
IC
V
ID
DISABLE
1
/NIC
GND
1
V
DD2
GND
2
ADuM140D/ADuM140E
V
OA
V
OB
V
OC
V
OD
NIC/V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
13119-101
NOTES
1. NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.
2. PIN 7 IS DISABLE
1
AND PIN 10 IS NIC FOR THE ADuM140D, AND
PIN 7 IS NIC AND PIN 10 IS V
E2
FOR THE ADuM140E.
Figure 1. ADuM140D/ADuM140E Functional Block Diagram
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
IC
V
OD
DISABLE
1
/V
E1
GND
1
V
DD2
GND
2
ADuM141D/ADuM141E
V
OA
V
OB
V
OC
V
ID
DISABLE
2
/V
E2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
13119-102
NOTES
1. PIN 7 IS DISABLE
1
AND PIN 10 IS DISABLE
2
FOR THE ADuM141D,
AND PIN 7 IS V
E1
AND PIN 10 IS V
E2
FOR THE ADuM141E.
Figure 2. ADuM141D/ADuM141E Functional Block Diagram
DECODE ENCODE
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VOC
VOD
DISABLE1/VE1
GND1
VDD2
GND2
ADuM142D/ADuM142E
VOA
VOB
VIC
VID
DISABLE2/VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
13119-103
NOTES
1. PIN 7 IS DISABLE1AND PIN 10 IS DISABLE2FOR THE ADuM142D,
AND PIN 7 IS VE1 AND PIN 10 IS VE2 FOR THE ADuM142E.
Figure 3. ADuM142D/ADuM142E Functional Block Diagram
functionality across the isolation barrier.
Unlike other optocoupler alternatives, dc correctness is ensured
in the absence of input logic transitions. Two different fail-safe
options are available, by which the outputs transition to a pre-
determined state when the input power supply is not applied or the
inputs are disabled. The ADuM140E1/ADuM141E1/ADuM142E1
are pin-compatible with the ADuM1400/ADuM1401/ADuM1402.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
Other patents are pending.
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 2 of 30
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics—5 V Operation................................ 4
Electrical Characteristics—3.3 V Operation ............................ 6
Electrical Characteristics—2.5 V Operation ............................ 8
Electrical Characteristics—1.8 V Operation .......................... 10
Insulation and Safety Related Specifications .......................... 12
Package Characteristics ............................................................. 12
Regulatory Information ............................................................. 13
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 14
Recommended Operating Conditions .................................... 16
Absolute Maximum Ratings ......................................................... 17
ESD Caution................................................................................ 17
Tr uth Tabl es................................................................................. 18
Pin Configurations and Function Descriptions ......................... 19
Typical Performance Characteristics ........................................... 22
Applications Information .............................................................. 24
Overview ..................................................................................... 24
Printed Circuit Board (PCB) Layout ....................................... 24
Propagation Delay Related Parameters ................................... 25
Jitter Measurement ..................................................................... 25
Insulation Lifetime ..................................................................... 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 28
Automotive Products ................................................................. 30
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 3 of 30
REVISION HISTORY
8/2018—Rev. H to Rev. I
Changes to Table 13 ........................................................................ 13
Changes to Table 15 ........................................................................ 14
Changes to Ordering Guide ........................................................... 28
Change to Automotive Products Section ..................................... 30
12/2017—Rev. G to Rev. H
Changes to Ordering Guide ........................................................... 28
7/2017—Rev. F to Rev. G
Changes to Ordering Guide ........................................................... 28
6/2017—Rev. E to Rev. F
Changes to Ordering Guide ........................................................... 28
2/2017—Re v. D to Re v. E
Added RQ-16 Package ....................................................... Universal
Added Table 11; Renumbered Sequentially ................................. 12
Changes to Table 12 ........................................................................ 12
Changes to Table 13 and Table 14 ................................................. 13
Added Table 15 ................................................................................ 14
Added Table 18 ................................................................................ 15
Added Figure 6; Renumbered Sequentially ................................. 16
Added Table 23 ................................................................................ 18
Added Figure 29 .............................................................................. 28
Updated Outline Dimensions ........................................................ 28
Changes to Ordering Guide ........................................................... 28
Changes to Automotive Products Section ................................... 29
10/2016—Rev. C to Rev. D
Changes to Features Section ............................................................ 1
Changes to Table 12 and Table 13 ................................................. 12
4/2016—Rev. B to Rev. C
Changes to Features Section ............................................................ 1
Changes to Ordering Guide ........................................................... 26
Added Automotive Products Section ........................................... 27
11/2015—Rev. A to Rev. B
Added 16-Lead, Narrow Body SOIC Package ................ Universal
Changes to Title, Features Section, and General Description
Section ................................................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Table 5 ............................................................................ 7
Changes to Table 7 ............................................................................ 9
Added Table 9; Renumbered Sequentially ................................... 11
Changes to Table 10 and Table 11 ................................................. 11
Changes to Regulator Information Section ................................. 12
Changes to Table 12 ........................................................................ 12
Added Table 13 ................................................................................ 12
Changes to Table 14 ........................................................................ 13
Added Table 15 and Figure 4; Renumbered Sequentially ................ 14
Changes to Figure 5 Caption ................................................................. 14
Changes to Endnote 3, Table 17, and Table 19 Title .......................... 15
Added Table 18 ......................................................................................... 15
Changes to Surface Tracking Section ................................................... 23
Changes to Calculation and Use of Parameters Example Section ..... 24
Updated Outline Dimensions ............................................................... 25
Changes to Ordering Guide ................................................................... 26
9/2015—Re v. 0 to Rev. A
Added ADuM141D/ADuM141E ..................................... Universal
Added ADuM142D/ADuM142E ..................................... Universal
Changes to Features and Figure 1 ................................................... 1
Delete Figure 2; Renumbered Sequentially ................................... 1
Added Figure 2 and Figure 3; Renumbered Sequentially ............ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 6
Changes to Table 5 ............................................................................ 7
Change to Table 6 .............................................................................. 8
Changes to Table 7 ............................................................................ 9
Changes to Table 8 .......................................................................... 10
Changes to Table 11 ........................................................................ 11
Changes to Table 12 ........................................................................ 12
Changes Table 15 ............................................................................. 13
Changes to Table 17 ........................................................................ 14
Added Figure 7, Figure 8, and Table 19; Renumbered
Sequentially ...................................................................................... 16
Added Figure 9, Figure 10, and Table 20...................................... 16
Added Figure 13 and Figure 16 ..................................................... 18
Changes to Figure 17 and Figure 18 ............................................. 19
Changes to Overview Section and Figure 19 .............................. 20
Updated Outline Dimensions ........................................................ 23
Changes to Ordering Guide ........................................................... 23
4/2015—Revision 0: Initial Version
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 4 of 30
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. M inimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
6.6
ns
Within pulse width distortion (PWD) limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output
Pulse Width Distortion PWD 0.5 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.1 ns Between any two units at the
same temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.5 3.0 ns
Opposing Direction tPSKOD 0.5 3.0 ns
Jitter 490 ps p-p See the Jitter Measurement section
70 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx −
0.2
V IOx2 = −4 mA, VIx = VIxH3
Logic Low
V
OL
0.0
0.1
V
I
Ox2
= 20 µA, V
Ix
= V
IxL4
0.2 0.4 V IOx2 = 4 mA, VIx = VIxL4
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
VE2 Enable Input Pull-Up Current IPU −10 −3 µA VE2 = 0 V
DISABLE1 Input Pull-Down Current IPD 9 15 µA DISABLE1 = VDDx
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx
Quiescent Supply Current
ADuM140D/ADuM140E
IDD1 (Q) 1.2 2.2 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 2.0 2.72 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 12.0 20.0 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
I
DD2 (Q)
2.0
2.92
mA
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
ADuM141D/ADuM141E
IDD1 (Q) 1.6 2.46 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.9 2.62 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 10.0 17.0 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 6.0 10.0 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM142D/ADuM142E
IDD1 (Q) 1.6 2.46 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.6 2.46 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 7.2 11.5 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 8.4 11.5 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 5 of 30
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.02 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive V
DDx
Threshold
V
DDxUV+
1.6
V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity7
|CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, or D.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 is the ADuM140E0/ADuM141E0/ADuM142E0 models, D0 is the ADuM140D0/ADuM141D0/ADuM142D0 models, E1 is the ADuM140E1/ADuM141E1/ADuM142E1
models, and D1 is the ADuM140D1/ADuM141D1/ADuM142D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 2. Total Supply Current vs. Data Throughput
1 Mbps
25 Mbps
100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM140D/ADuM140E
Supply Current Side 1 IDD1 6.8 10 7.8 12 11.8 17.4 mA
Supply Current Side 2 IDD2 2.1 3.7 3.9 5.7 9.2 13 mA
ADuM141D/ADuM141E
Supply Current Side 1
I
DD1
5.8
10.3
7.0
10.9
11.4
15.9
mA
Supply Current Side 2 IDD2 4.0 6.85 5.5 8.5 10.3 14.0 mA
ADuM142D/ADuM142E
Supply Current Side 1 IDD1 4.3 7.7 6.0 9.3 10.3 14.2 mA
Supply Current Side 2 IDD2 5.3 8.7 6.7 10.1 11.0 14.9 mA
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 6 of 30
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 4.8 6.8 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.5 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.7 3.0 ns
Opposing Direction tPSKOD 0.7 3.0 ns
Jitter 580 ps p-p See the Jitter Measurement section
120 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 2 mA, VIx = VIxL4
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
VE2 Enable Input Pull-Up Current IPU −10 −3 µA VE2 = 0 V
DISABLE1 Input Pull-Down Current IPD 9 15 µA DISABLE1 = VDDx
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx
Quiescent Supply Current
ADuM140D/ADuM140E
IDD1 (Q) 1.2 2.12 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
I
DD2 (Q)
2.0
2.68
mA
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
IDD1 (Q) 12.0 19.6 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 2.0 2.8 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM141D/ADuM141E
IDD1 (Q) 1.5 2.36 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.8 2.52 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 9.8 16.7 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 5.7 9.7 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM142D/ADuM142E
IDD1 (Q) 1.6 2.4 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.6 2.4 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
I
DD1 (Q)
7.2
11.2
mA
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
IDD2 (Q) 8.4 11.2 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 7 of 30
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive V
DDx
Threshold
V
DDxUV+
1.6
V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, or D.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 is the ADuM140E0/ADuM141E0/ADuM142E0 models, D0 is the ADuM140D0/ADuM141D0/ADuM142D0 models, E1 is the ADuM140E1/ADuM141E1/ADuM142E1
models, and D1 is the ADuM140D1/ADuM141D1/ADuM142D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 4. Total Supply Current vs. Data Throughput
1 Mbps
25 Mbps
100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM140D/ADuM140E
Supply Current Side 1 IDD1 6.6 9.8 7.4 11.2 10.7 15.9 mA
Supply Current Side 2 IDD2 2.0 3.7 3.5 5.5 8.2 11.6 mA
ADuM141D/ADuM141E
Supply Current Side 1
I
DD1
5.65
10.1
6.65
10.5
10.4
14.9
mA
Supply Current Side 2 IDD2 3.9 6.65 5.2 8.0 9.4 12.8 mA
ADuM142D/ADuM142E
Supply Current Side 1 IDD1 4.3 7.7 5.6 9.0 9.1 13 mA
Supply Current Side 2 IDD2 5.0 8.4 6.2 9.6 9.8 13.7 mA
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 8 of 30
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 5.0 7.0 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 6.8 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional tPSKCD 0.7 3.0 ns
Opposing Direction tPSKOD 0.7 3.0 ns
Jitter 800 ps p-p See the Jitter Measurement section
190 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 2 mA, VIx = VIxL4
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
VE2 Enable Input Pull-Up Current IPU −10 −3 µA VE2 = 0 V
DISABLE1 Input Pull-Down Current IPD 9 15 µA DISABLE1 = VDDx
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx
Quiescent Supply Current
ADuM140D/ADuM140E
IDD1 (Q) 1.2 2.0 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
I
DD2 (Q)
2.0
2.64
mA
V
I5
= 0 (E0, D0), 1 (E1, D1)
6
IDD1 (Q) 1.2 19.6 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 2.0 2.76 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM141D/ADuM141E
IDD1 (Q) 1.46 2.32 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.75 2.47 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 9.7 16.6 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 5.67 9.67 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM142D/ADuM142E
IDD1 (Q) 1.6 2.32 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.6 2.32 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
I
DD1 (Q)
7.2
11.2
mA
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
IDD2 (Q) 8.4 11.2 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 9 of 30
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Undervoltage Lockout
Positive VDDx Threshold VDDxUV+ 1.6 V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, or D.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 is the ADuM140E0/ADuM141E0/ADuM142E0 models, D0 is the ADuM140D0/ADuM141D0/ADuM142D0 models, E1 is the ADuM140E1/ADuM141E1/ADuM142E1
models, and D1 is the ADuM140D1/ADuM141D1/ADuM142D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 6. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM140D/ADuM140E
Supply Current Side 1 IDD1 6.5 9.8 7.3 11.1 10.4 15.5 mA
Supply Current Side 2 IDD2 2.0 3.6 3.3 5.2 7.3 10.2 mA
ADuM141D/ADuM141E
Supply Current Side 1 IDD1 5.6 10.0 6.4 10.4 9.7 14.5 mA
Supply Current Side 2 IDD2 3.8 6.55 4.8 7.7 8.3 11.5 mA
ADuM142D/ADuM142E
Supply Current Side 1
I
DD1
4.3
7.7
5.4
8.8
8.8
12.7
mA
Supply Current Side 2 IDD2 5.0 8.4 6.1 9.5 9.5 13.4 mA
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 10 of 30
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ VDD1 ≤ 1.9 V, 1.7 V ≤ VDD2 ≤ 1.9 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate1 150 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |tPLH − tPHL|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew tPSK 7.0 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional
t
PSKCD
0.7
3.0
ns
Opposing Direction tPSKOD 0.7 3.0 ns
Jitter 470 ps p-p See the Jitter Measurement section
70 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High VIH 0.7 × VDDx V
Logic Low VIL 0.3 × VDDx V
Output Voltage
Logic High VOH VDDx − 0.1 VDDx V IOx2 = −20 µA, VIx = VIxH3
VDDx − 0.4 VDDx − 0.2 V IOx2 = −2 mA, VIx = VIxH3
Logic Low VOL 0.0 0.1 V IOx2 = 20 µA, VIx = VIxL4
0.2 0.4 V IOx2 = 2 mA, VIx = VIxL4
Input Current per Channel II −10 +0.01 +10 µA 0 V ≤ VIx ≤ VDDx
V
E2
Enable Input Pull-Up Current
I
PU
−10
−3
µA
V
E2
= 0 V
DISABLE1 Input Pull-Down Current IPD 9 15 µA DISABLE1 = VDDx
Tristate Output Current per Channel IOZ −10 +0.01 +10 µA 0 V ≤ VOx ≤ VDDx
Quiescent Supply Current
ADuM140D/ADuM140E
IDD1 (Q) 1.2 1.92 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 2.0 2.64 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 12.0 19.6 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 2.0 2.76 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM141D/ADuM141E
IDD1 (Q) 1.4 2.28 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
I
DD2 (Q)
1.73
2.45
mA
V
I
5 = 0 (E0, D0), 1 (E1, D1)6
IDD1 (Q) 9.6 16.5 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
IDD2 (Q) 5.6 9.6 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
ADuM142D/ADuM142E
IDD1 (Q) 1.6 2.28 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
IDD2 (Q) 1.6 2.28 mA VI5 = 0 (E0, D0), 1 (E1, D1)6
I
DD1 (Q)
7.2
11.2
mA
V
I5
= 1 (E0, D0), 0 (E1, D1)
6
IDD2 (Q) 8.4 11.2 mA VI5 = 1 (E0, D0), 0 (E1, D1)6
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 11 of 30
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Dynamic Supply Current
Dynamic Input IDDI (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output IDDO (D) 0.01 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive V
DDx
Threshold
V
DDxUV+
1.6
V
Negative VDDx Threshold VDDxUV− 1.5 V
VDDx Hysteresis VDDxUVH 0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity7 |CMH| 75 100 kV/µs VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CML| 75 100 kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
1 150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2 IOx is the Channel x output current, where x = A, B, C, or D.
3 VIxH is the input side logic high.
4 VIxL is the input side logic low.
5 VI is the voltage input.
6 E0 is the ADuM140E0/ADuM141E0/ADuM142E0 models, D0 is the ADuM140D0/ADuM141D0/ADuM142D0 models, E1 is the ADuM140E1/ADuM141E1/ADuM142E1
models, and D1 is the ADuM140D1/ADuM141D1/ADuM142D1 models. See the Ordering Guide section.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-
mode voltage slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 8. Total Supply Current vs. Data Throughput
1 Mbps
25 Mbps
100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM140D/ADuM140E
Supply Current Side 1 IDD1 6.4 9.8 7.2 11 10.2 15.2 mA
Supply Current Side 2 IDD2 1.9 3.5 3.1 5.0 6.8 10 mA
ADuM141D/ADuM141E
Supply Current Side 1
I
DD1
5.5
9.1
6.3
10.0
9.6
14.0
mA
Supply Current Side 2 IDD2 3.72 6.45 4.8 7.5 8.4 11.2 mA
ADuM142D/ADuM142E
Supply Current Side 1 IDD1 4.3 7.7 5.3 8.7 8.6 12.6 mA
Supply Current Side 2 IDD2 4.9 8.3 6.0 9.4 9.3 13.3 mA
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 12 of 30
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 9. R-16 Narrow Body [SOIC_N] Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 4.0 mm min Measured from input terminals to output terminals, shortest
distance through air
Minimum External Tracking (Creepage) L (I02) 4.0 mm min Measured from input terminals to output terminals, shortest
distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB)
4.5
mm min
Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Minimum Internal Gap (Internal Clearance) 25.5 μm min Minimum distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
Table 10. RW-16 Wide Body [SOIC_W] Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 3750 V rms 1-minute duration
Minimum External Air Gap (Clearance) L (I01) 7.8 mm min Measured from input terminals to output terminals, shortest
distance through air
Minimum External Tracking (Creepage)
L (I02)
7.8
mm min
Measured from input terminals to output terminals, shortest
distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 8.3 mm min Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Minimum Internal Gap (Internal Clearance) 25.5 μm min Minimum distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
Table 11. RQ-16 [QSOP] Package
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 3000 V rms 1-minute duration
Minimum External Air Gap (Clearance)
L (I01)
3.2
mm min
Measured from input terminals to output terminals, shortest
distance through air
Minimum External Tracking (Creepage) L (I02) 3.2 mm min Measured from input terminals to output terminals, shortest
distance path along body
Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)
L (PCB) 3.8 mm min Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Minimum Internal Gap (Internal Clearance) 25.5 μm min Minimum distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 12.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)1 RI-O 1013 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction to Ambient Thermal Resistance
R-16 Narrow Body [SOIC_N] Package θJA 76 °C/W Thermocouple located at center of package underside
RW-16 Wide Body [SOIC_W] Package θJA 45 °C/W Thermocouple located at center of package underside
RQ-16 [QSOP] Package θJA 76 °C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 13 of 30
REGULATORY INFORMATION
See Table 21 for the SOIC_N package or Tabl e 22 for the SOIC_W package and the Insulation Lifetime section for details regarding
recommended maximum working voltages for specific cross isolation waveforms and insulation levels.
Table 13. R-16 Narrow Body [SOIC_N] Package
UL CSA VDE CQC
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Certified under
CQC11-471543-2012
Single Protection, 3000 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC 60950-1,
second edition, +A1+A2:
Reinforced insulation, VIORM =
565 V peak, VIOSM = 6000 V peak
GB4943.1-2011:
Basic insulation at 400 V rms (565 V peak) Basic insulation, VIORM =
565 V peak, VIOSM = 10 kV peak
Basic insulation at
770 V rms (1089 V peak)
Reinforced insulation at 200 V rms
(283 V peak)
Reinforced insulation at
385 V rms (545 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (one means of patient
protection (1 MOPP)), 250 V rms
(354 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains,
400 V rms secondary (565 V peak)
Reinforced insulation at 300 V rms mains,
200 V secondary (282 V peak)
File E214100 File 205078 File 2471900-4880-0001 File CQC16001147385
1 In accordance with UL 1577, each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the R-16 narrow body [SOIC_N] package is proof tested by
applying an insulation test voltage ≥ 3600 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the R-16 narrow body [SOIC_N] package is
proof tested by applying an insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component
designates DIN V VDE V 0884-10 approval.
Table 14. RW-16 Wide Body [SOIC_W] Package
UL CSA VDE CQC
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Certified under
CQC11-471543-2012
Single Protection, 3750 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC 60950-1,
second edition, +A1+A2:
Reinforced insulation, VIORM =
849 V peak, VIOSM = 6000 V peak
GB4943.1-2011:
Basic insulation at 780 V rms
(1103 V peak)
Basic insulation, VIORM =
849 V peak, VIOSM = 10 kV peak
Basic insulation at
780 V rms (1103 V peak)
Reinforced insulation at 390 V rms
(552 V peak)
Reinforced insulation at
390 V rms (552 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 means of patient
protection (MOPP)), 490 V rms (693 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains, 780 V
secondary (1103 V peak)
Reinforced insulation at 300 V rms mains,
390 V secondary (552 V peak)
File E214100 File 205078 File 2471900-4880-0001 File CQC16001147385
1 In accordance with UL 1577, each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the RW-16 wide body [SOIC_W] package is proof tested by
applying an insulation test voltage ≥ 4500 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the RW-16 wide body [SOIC_W] package is
proof tested by applying an insulation test voltage ≥ 1592 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component
designates DIN V VDE V 0884-10 approval.
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 14 of 30
Table 15. RQ-16 [QSOP] Package
UL (Pending) CSA (Pending) VDE (Pending) CQC
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-122
Certified under
CQC11-471543-2012
Single Protection, 3000 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC 60950-1,
second edition, +A1+A2:
Reinforced insulation, 636 V peak,
VIOSM = 6 kV peak
GB4943.1-2011:
Basic insulation at 320 V rms (450 V peak) Basic insulation 636 V peak,
VIOSM = 10 kV peak
Basic insulation at
320 V rms (450 V peak)
Reinforced insulation at 160 V rms
(225 V peak)
Reinforced insulation at
160Vrms (225 Vpeak)
IEC 60601-1 Edition 3.1:
Basic insulation (1MOPP), 250 V rms
(354 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300V rms mains,
320 V rms (450 V peak)
Reinforced insulation at 150 V rms mains,
160 V rms (225 V peak) secondary
File E214100 File 205078 File 2471900-4880-0001 File CQC18001192421
1 In accordance with UL 1577, each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the RQ-16 [QSOP] package is proof tested by applying an
insulation test voltage ≥ 3600 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E in the RQ-16 [QSOP] package is proof tested by
applying an insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V
0884-10 approval.
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 16. R-16 Narrow Body [SOIC_N] Package
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to III
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 565 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd (m) 1059 V peak
Input to Output Test Voltage, Method A Vpd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
848 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
678 V peak
Highest Allowable Overvoltage VIOTM 4200 V peak
Surge Isolation Voltage Basic V peak = 10 kV, 1.2 μs rise time, 50 μs,
50% fall time
VIOSM 10000 V peak
Surge Isolation Voltage Reinforced V peak = 10 kV, 1.2 μs rise time, 50 μs,
50% fall time
VIOSM 6000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 4)
Maximum Junction Temperature TS150 °C
Total Power Dissipation at 25°C PS1.64 W
Insulation Resistance at TS VIO = 500 V RS>109Ω
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 15 of 30
Table 17. RW-16 Wide Body [SOIC_W] Package
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to IV
Climatic Classification
40/125/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 849 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd (m) 1592 V peak
Input to Output Test Voltage, Method A
V
pd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1274 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1019 V peak
Highest Allowable Overvoltage VIOTM 7000 V peak
Surge Isolation Voltage Basic
V peak = 12.8 kV, 1.2 µs rise time, 50 µs,
50% fall time
V
IOSM
12000
V peak
Surge Isolation Voltage Reinforced V peak = 12.8 kV, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM 8000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 5)
Maximum Junction Temperature TS 150 °C
Total Power Dissipation at 25°C PS 2.78 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
Table 18. RQ-16 [QSOP] Package
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 600 V rms I to IV
Climatic Classification 40/125/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage VIORM 565 V peak
Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd (m) 1059 V peak
Input to Output Test Voltage, Method A Vpd (m)
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
848 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
678 V peak
Highest Allowable Overvoltage VIOTM 4242 V peak
Surge Isolation Voltage Basic V peak = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM 10000 V peak
Surge Isolation Voltage Reinforced V peak = 10 kV, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM 6000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 5)
Maximum Junction Temperature TS 150 °C
Total Power Dissipation at 25°C
P
S
1.64
W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 16 of 30
1.8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 50 100 150 200
SAFE OPERATING P
VDD1
, P
VDDA
OR P
VDDB
POWER (W)
AMBI E NT T E M P E RATURE ( °C)
13119-202
Figure 4. Thermal Derating Curve for R-16 Narrow Body [SOIC_N] Package,
Dependence of Safety Limiting Values with Ambient Temperature per
DIN V VDE V 0884-10
3.0
2.5
2.0
1.5
0.5
1.0
00 20015010050
SAFE LIMITING POWER (W)
AMBIENT TEMPERAT URE (°C)
13119-003
Figure 5. Thermal Derating Curve for RW-16 Wide Body [SOIC_W] Package,
Dependence of Safety Limiting Values with Ambient Temperature per
DIN V VDE V 0884-10
1.8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
050100150200
AMBI ENT TEM P E R ATURE ( °C)
13119-203
SAFE LIMITING POWER (W)
Figure 6. Thermal Derating Curve for RQ-16 [QSOP] Package,
Dependence of Safety Limiting Values with Ambient Temperature per
DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 19.
Parameter Symbol Rating
Operating Temperature TA −40°C to +125°C
Supply Voltages VDD1, VDD2 1.7 V to 5.5 V
Input Signal Rise and Fall Times 1.0 ms
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 17 of 30
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 20.
Parameter Rating
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature
(TA) Range
−40°C to +125°C
Supply Voltages (VDD1, VDD2) −0.5 V to +7.0 V
Input Voltages (VIA, VIB, VIC, VID, VE1,
VE2, DISABLE1, DISABLE2)
−0.5 V to VDDI1 + 0.5 V
Output Voltages (V
OA
, V
OB
, V
OC
, V
OD
)
−0.5 V to V
DDO
2 + 0.5 V
Average Output Current per Pin3
Side 1 Output Current (IO1) −10 mA to +10 mA
Side 2 Output Current (IO2) −10 mA to +10 mA
Common-Mode Transients4 −150 kV/μs to +150 kV/μs
1 VDDI is the input side supply voltage.
2 VDDO is the output side supply voltage.
3 See Figure 4 for the R-16 narrow body [SOIC_N] package, Figure 5 for the
RW-16 wide body [SOIC_W] package, or Figure 6 for the RQ-16 [QSOP]
package for the maximum rated current values at various temperatures.
4 Refers to the common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings may
cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Table 21. Maximum Continuous Working Voltage R-16 Narrow Body [SOIC_N] Package1
Parameter Rating Constraint2
AC Voltage
Bipolar Waveform
Basic Insulation 789 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 403 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Unipolar Waveform
Basic Insulation 909 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation
469 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation 558 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 285V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
2 Insulation lifetime for the specified test condition is greater than 50 years.
Table 22. Maximum Continuous Working Voltage RW-16 Wide Body [SOIC_W] Package1
Parameter Rating Constraint2
AC Voltage
Bipolar Waveform
Basic Insulation
849 V peak
50-year minimum insulation lifetime
Reinforced Insulation 768 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Unipolar Waveform
Basic Insulation 1698 V peak 50-year minimum insulation lifetime
Reinforced Insulation 885 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation 1092 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 543 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
2 Insulation lifetime for the specified test condition is greater than 50 years.
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 18 of 30
Table 23. Maximum Continuous Working Voltage RQ-16 [QSOP] Package1
Parameter Rating Constraint2
AC Voltage
Bipolar Waveform
Basic Insulation 636 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 318 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Unipolar Waveform
Basic Insulation 734 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation 367 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
DC Voltage
Basic Insulation 450 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
Reinforced Insulation
225 V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
2 Insulation lifetime for the specified test condition is greater than 50 years.
TRUTH TABLES
Table 24. ADuM140D/ADuM141D/ADuM142D Truth Table (Positive Logic)
VIx Input1, 2 VDISABLEx Input1, 2 VDDI State2 VDDO State2
Default Low (D0),
VOx Output1, 2, 3
Default High (D1),
VOx Output1, 2, 3 Test Conditions/Comments
L L or NC Powered Powered L L Normal operation
H L or NC Powered Powered H H Normal operation
X H Powered Powered L H Inputs disabled, fail-safe output
X
4
X
4
Unpowered
Powered
L
H
Fail-safe output
X4 X4 Powered Unpowered Indeterminate Indeterminate
1 L means low, H means high, X means don’t care, and NC means not connected.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VDISABLEx refers to the input disable signal on the same side as the VIx inputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
3 D0 is the ADuM140D0/ADuM141D0/ADuM142D0 models, and D1 is the ADuM140D1/ADuM141D1/ADuM142D1 models. See the Ordering Guide section.
4 Input pins (VIx, DISABLE1, and DISABLE2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection
circuitry.
Table 25. ADuM140E/ADuM141E/ADuM142E Truth Table (Positive Logic)
VIx Input1, 2 VEx Input1, 2 VDDI State2 VDDO State2
Default Low (E0),
VOx Output1, 2, 3
Default High (E1),
VOx Output1, 2, 3 Test Conditions/Comments
L H or NC Powered Powered L L Normal operation
H H or NC Powered Powered H H Normal operation
X L Powered Powered Z Z Outputs disabled
L
H or NC
Unpowered
Powered
L
H
Fail-safe output
X4 L4 Unpowered Powered Z Z Outputs disabled
X4 X4 Powered Unpowered Indeterminate Indeterminate
1 L means low, H means high, X means don’t care, NC means not connected, and Z means high impedance.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
3 E0 is the ADuM140E0/ADuM141E0/ADuM142E0 models, and E1 is the ADuM140E1/ADuM141E1/ADuM142E1 models. See the Ordering Guide section.
4 Input pins (VIx, VE1, and VE2) on the same side as an unpowered supply must be in a low state to avoid powering the device through its ESD protection circuitry.
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 19 of 30
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM140D
TOP VIEW
(Not to S cale)
V
DD1
GND
1
V
IA
V
IB
V
IC
V
ID
DISABLE
1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
OD
NIC
GND
2
13119-004
NOTES
1. NI C = NO I NTERNAL CO NNE CTI ON.
LEAVE THIS PIN FLOATING.
Figure 7. ADuM140D Pin Configuration
1
2
3
4
16
15
14
13
512
6 11
710
89
V
DD1
GND
1
V
IA
V
IB
V
IC
V
ID
NIC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
OD
V
E2
GND
2
13119-005
ADuM140E
TOP VIEW
(Not to S cale)
NOTES
1. NI C = NO I NTERNAL CO NNE CTI ON.
LEAVE THIS PIN FLOATING.
Figure 8. ADuM140E Pin Configuration
Table 26. Pin Function Descriptions
Pin No.1
ADuM140D ADuM140E Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1.
2, 8 2, 8 GND1 Ground Reference for Isolator Side 1.
3 3 VIA Logic Input A.
4 4 VIB Logic Input B.
5 5 VIC Logic Input C.
6 6 VID Logic Input D.
7 Not applicable DISABLE1 Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state
determined by the fail-safe option shown in the Ordering Guide.
9, 15
9, 15
GND
2
Ground Reference for Isolator Side 2.
10 7 NIC No Internal Connection. Leave this pin floating.
Not applicable 10 VE2 Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA, VOB,
VOC, and VOD outputs are enabled. When VE2 is low, the VOA, VOB, VOC, and VOD outputs
are disabled to the high-Z state.
11 11 VOD Logic Output D.
12
12
V
OC
Logic Output C.
13 13 VOB Logic Output B.
14 14 VOA Logic Output A.
16 16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 20 of 30
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM141D
TOP VI EW
(No t t o Scale)
V
DD1
GND
1
V
IA
V
IB
V
IC
V
OD
DISABLE
1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
ID
DISABLE
2
GND
2
13119-104
Figure 9. ADuM141D Pin Configuration
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM141E
TOP VI EW
(No t t o Scale)
V
DD1
GND
1
V
IA
V
IB
V
IC
V
OD
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
V
ID
V
E2
GND
2
13119-105
Figure 10. ADuM141E Pin Configuration
Table 27. Pin Function Descriptions
Pin No.
1
ADuM141D ADuM141E Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1.
2, 8 2, 8 GND1 Ground Reference for Isolator Side 1.
3
3
V
IA
Logic Input A.
4 4 VIB Logic Input B.
5 5 VIC Logic Input C.
6 6 VOD Logic Output D.
7 Not applicable DISABLE1 Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state
determined by the fail-safe option shown in the Ordering Guide.
Not applicable 7 VE1 Output Enable 1. Active high logic input. When VE1 is high or disconnected, the VOD
output is enabled. When VE1 is low, the VOD output is disabled to the high-Z state.
9, 15 9, 15 GND2 Ground Reference for Isolator Side 2.
10 Not applicable DISABLE2 Input Disable 2. This pin disables the isolator inputs. Outputs take on the logic state
determined by the fail-safe option shown in the Ordering Guide.
Not applicable 10 VE2 Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA, VOB,
and VOC outputs are enabled. When VE2 is low, the VOA, VOB, and VOC outputs are disabled
to the high-Z state.
11 11 VID Logic Input D.
12 12 VOC Logic Output C.
13 13 VOB Logic Output B.
14
14
V
OA
Logic Output A.
16 16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 21 of 30
1
2
3
4
16
15
14
13
512
611
710
8 9
ADuM142D
TOP VI EW
(No t t o Scale)
V
DD1
GND
1
V
IA
V
IB
V
OC
V
OD
DISABLE
1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
V
ID
DISABLE
2
GND
2
13119-106
Figure 11. ADuM142D Pin Configuration
1
2
3
4
16
15
14
13
512
611
710
89
ADuM142E
TOP VI EW
(No t t o Scale)
V
DD1
GND
1
V
IA
V
IB
V
OC
V
OD
V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
V
ID
V
E2
GND
2
13119-107
Figure 12. ADuM142E Pin Configuration
Table 28. Pin Function Descriptions
Pin No.
1
ADuM142D ADuM142E Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1.
2, 8 2, 8 GND1 Ground Reference for Isolator Side 1.
3
3
V
IA
Logic Input A.
4 4 VIB Logic Input B.
5 5 VOC Logic Output C.
6 6 VOD Logic Output D.
7 Not applicable DISABLE1 Input Disable 1. This pin disables the isolator inputs. Outputs take on the logic state
determined by the fail-safe option shown in the Ordering Guide.
Not applicable
7
V
E1
Output Enable 1. Active high logic input. When VE1 is high or disconnected, the VOC and VOD
outputs are enabled. When VE1 is low, the VOC and VOD outputs are disabled to the
high-Z state.
9, 15 9, 15 GND2 Ground Reference for Isolator Side 2.
10 Not applicable DISABLE2 Input Disable 2. This pin disables the isolator inputs. Outputs take on the logic state
determined by the fail-safe option shown in the Ordering Guide.
Not applicable 10 VE2 Output Enable 2. Active high logic input. When VE2 is high or disconnected, the VOA and
VOB outputs are enabled. When VE2 is low, the VOA and VOB outputs are disabled to the
high-Z state.
11 11 VID Logic Input D.
12 12 VIC Logic Input C.
13
13
V
OB
Logic Output B.
14 14 VOA Logic Output A.
16 16 VDD2 Supply Voltage for Isolator Side 2.
1 Reference the AN-1109 Application Note for specific layout guidelines.
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 22 of 30
TYPICAL PERFORMANCE CHARACTERISTICS
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
I
DD1
SUPPLY CURRENT ( mA)
DATA RATE (Mbp s)
VDD1 = VDD2 = 5V
VDD1 = VDD2 = 3.3V
VDD1 = VDD2 = 2.5V
VDD1 = VDD2 = 1.8V
13119-006
Figure 13. ADuM140D/ADuM140E IDD1 Supply Current vs. Data Rate at
Various Voltages
DATA RATE (Mbps)
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
I
DD2
SUPPLY CURRENT ( mA)
13119-007
V
DD1
= V
DD2
= 5V
V
DD1
= V
DD2
= 3.3V
V
DD1
= V
DD2
= 2.5V
V
DD1
= V
DD2
= 1.8V
Figure 14. ADuM140D/ADuM140E IDD2 Supply Current vs. Data Rate at
Various Voltages
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
I
DD1
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
V
DD1
= V
DD2
= 5V
V
DD1
= V
DD2
= 3.3V
V
DD1
= V
DD2
= 2.5V
V
DD1
= V
DD2
= 1.8V
13119-113
Figure 15. ADuM141D/ADuM141E IDD1 Supply Current vs. Data Rate at
Various Voltages
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
I
DD2
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
V
DD1
= V
DD2
= 5V
V
DD1
= V
DD2
= 3.3V
V
DD1
= V
DD2
= 2.5V
V
DD1
= V
DD2
= 1.8V
13119-114
Figure 16. ADuM141D/ADuM141E IDD2 Supply Current vs. Data Rate at
Various Voltages
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
I
DD1
SUPPLY CURRENT (mA)
DATA RATE (Mbps)
V
DD1
= V
DD2
= 5V
V
DD1
= V
DD2
= 3.3V
V
DD1
= V
DD2
= 2.5V
V
DD1
= V
DD2
= 1.8V
13119-115
Figure 17. ADuM142D/ADuM142E IDD1 Supply Current vs. Data Rate at
Various Voltages
0
2
4
6
8
10
12
14
16
020 40 60 80 100 120 140 160
IDD2 SUPPLY CURRENT ( mA)
DATA RATE (Mbps)
VDD1 = VDD2 = 5V
VDD1 = VDD2 = 3.3V
VDD1 = VDD2 = 2.5V
VDD1 = VDD2 = 1.8V
13119-116
Figure 18. ADuM142D/ADuM142E IDD2 Supply Current vs. Data Rate at
Various Voltages
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 23 of 30
0
2
4
6
8
10
12
14
–40 –20 020 40 60 80 100 120 140
PROPAGATION DELAY,
t
PHL
(n s)
TEMPERATURE ( °C)
13119-008
V
DD1
= V
DD2
= 5V
V
DD1
= V
DD2
= 3.3V
V
DD1
= V
DD2
= 2.5V
V
DD1
= V
DD2
= 1.8V
Figure 19. Propagation Delay, tPLH vs. Temperature at Various Voltages
–40 –20 020 40 60 80 100 120 140
0
2
4
6
8
10
12
14
TEMPERATURE ( °C)
PROPAGATION DELAY, t
PHL
(n s)
13119-009
V
DD1
= V
DD2
= 5V
V
DD1
= V
DD2
= 3.3V
V
DD1
= V
DD2
= 2.5V
V
DD1
= V
DD2
= 1.8V
Figure 20. Propagation Delay, tPHL vs. Temperature at Various Voltages
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 24 of 30
APPLICATIONS INFORMATION
OVERVIEW
The ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E use a high frequency carrier to
transmit data across the isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide isolation.
Using an on/off keying (OOK) technique and the differential
architecture shown in Figure 22 and Figure 23, the ADuM140D/
ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
have very low propagation delay and high speed. Internal regulators
and input/output design techniques allow logic and supply voltages
over a wide range from 1.7 V to 5.5 V, offering voltage translation of
1.8 V, 2.5 V, 3.3 V, and 5 V logic. The architecture is designed for
high common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and
other techniques.
Figure 22 illustrates the waveforms for models of the ADuM140D/
ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
that have the condition of the fail-safe output state equal to low,
where the carrier waveform is off when the input state is low. If
the input side is off or not operating, the low fail-safe output state
(ADuM140D0/ADuM140E0/ADuM141D0/ADuM141E0/
ADuM142D0/ADuM142E0) sets the output to low. For the
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/
ADuM142E that have a high fail-safe output state, Figure 23
illustrates the conditions where the carrier waveform is off when
the input state is high. When the input side is off or not operating,
the fail-safe output state of high (ADuM140D1/ADuM140E1/
ADuM141D1/ADuM141E1/ADuM142D1/ADuM142E1) sets the
output to high. See the Ordering Guide for the model numbers
that have the fail-safe output state of low or the fail-safe output
state of high.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at the input and output supply pins
(see Figure 21). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The recommended bypass capacitor value is between
0.01 µF and 0.1 µF. The total lead length between both ends of
the capacitor and the input power supply pin must not exceed
10 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 must also be considered, unless the ground pair on
each package side is connected close to the package.
V
DD1
GND
1
V
IA
V
IB
V
IC
/V
OC
V
ID
/V
OD
DISABLE
1
/V
E1
/NIC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
IC
/V
OC
V
ID
/V
OD
DISABLE
2
/V
E2
/NIC
GND
2
13119-010
Figure 21. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
13119-014
Figure 22. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
13119-015
Figure 23. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 25 of 30
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time
required for a logic signal to propagate through a component.
The propagation delay to a Logic 0 output may differ from the
propagation delay to a Logic 1 output.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
13119-011
Figure 24. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how accurately
the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation delay
differs between channels within a single ADuM140D/ADuM140E/
ADuM141D/ADuM141E/ADuM142D/ADuM142E component.
Propagation delay skew is the maximum amount the propagation
delay that differs between multiple ADuM140D/ADuM140E/
ADuM141D/ADuM141E/ADuM142D/ADuM142E components
operating under the same conditions.
JITTER MEASUREMENT
Figure 25 shows the eye diagram for the ADuM140D/ADuM140E/
ADuM141D/ADuM141E/ADuM142D/ADuM142E. The
measurement was taken using an Agilent 81110A pulse pattern
generator at 150 Mbps with pseudorandom bit sequences (PRBS)
2(n − 1), n = 14, for 5 V supplies. Jitter was measured with the
Tektronix Model 5104B oscilloscope, 1 GHz, 10 GSPS with the
DPOJET jitter and eye diagram analysis tools. The result shows a
typical measurement on the ADuM140D/ADuM140E/
ADuM141D/ADuM141E/ADuM142D/ADuM142E with
490 ps p-p jitter.
105
0
1
2
3
4
VOL
T
AGE ( V )
5
0
TIME (ns)
–5–10
13119-012
Figure 25. ADuM140D/ADuM140E/ADuM141D/ADuM141E/
ADuM142D/ADuM142E Eye Diagram
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation as well as on the materials
and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in
each system level standard and is based on the total rms voltage
across the isolation, pollution degree, and material group. The
material group and creepage for the ADuM140D/ADuM140E/
ADuM141D/ADuM141E/ADuM142D/ADuM142E isolators are
presented in Table 9 for the R-16 narrow body [SOIC_N] package
or Table 10 for the RW-16 wide body [SOIC_W] package.
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
Testing and modeling have shown that the primary driver of
long-term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the insul-
ation can be broken down into broad categories, such as dc stress,
which causes very little wear out because there is no displacement
current, and an ac component time varying voltage stress, which
causes wear out.
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 26 of 30
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as is
shown in Equation 2. For insulation wear out with the polyimide
materials used in these products, the ac rms voltage determines
the product lifetime.
22
DCRMSACRMS
VVV +=
(1)
or
22
AC RMS RMS DC
V VV= −
(2)
where:
VAC RMS is the time varying portion of the working voltage.
VRMS is the total rms working voltage.
VDC is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 V dc bus voltage is present
on the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance and lifetime of a device, see Figure 26 and
the following equations.
ISOLATION VOLTAGE
TIME
V
AC RMS
V
RMS
V
DC
V
PEAK
13119-013
Figure 26. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
22
DCRMSACRMS
VVV +=
2
2
400
240 +
=
RMS
V
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the creepage
required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
22
AC RMS RMS DC
V VV= −
22 400466 −=
RMSAC
V
VAC RMS = 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Tabl e 21 for the SOIC_N package or Table 22 for the
SOIC_W package, for the expected lifetime, which is less than a
60 Hz sine wave, and it is well within the limit for a 50-year
service life.
Note that the dc working voltage limit is set by the creepage of
the package as specified in IEC 60664-1. This value can differ
for specific system level standards.
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 27 of 30
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONSARE I N M IL LIM E TERS ; INCH DI M E NS IO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REF E RENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JE DE C S TANDARDS MS-012-AC
10.00 ( 0.3937)
9.80 ( 0.3858)
16 9
8
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
Figure 27. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMEN
SIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 28. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 28 of 30
COMPLIANT TO JE DE C S TANDARDS MO-137- AB
CONTROLLING DIMENSIONSARE IN INCHES; MILLI MET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED- OF F I NCH E QUIVALENTS FOR
REF E RENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
16 9
8
1
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025 (0. 64)
BSC
0.041 (1. 04)
REF
0.010 ( 0.25)
0.006 ( 0.15)
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
8°
0°
COPLANARITY
0.004 ( 0.10)
0.065 (1.65)
0.049 (1.25) 0.069 (1. 75)
0.053 (1. 35)
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
09-12-2014-A
Figure 29. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1, 2
Temperature
Range
No. of
Inputs,
VDD1
Side
No. of
Inputs,
VDD2
Side
Withstand
Voltage
Rating
(kV rms)
Fail-Safe
Output
State
Input
Disable
Output
Enable
Package
Description
Package
Option
ADuM140D1BRZ
−40°C to +125°C
4
0
3.0
High
Yes
No
16-Lead SOIC_N
R-16
ADuM140D1BRZ-RL7
−40°C to +125°C
4
0
3.0
High
Yes
No
16-Lead SOIC_N
R-16
ADuM140D0BRZ
−40°C to +125°C
4
0
3.0
Low
Yes
No
16-Lead SOIC_N
R-16
ADuM140D0BRZ-RL7
−40°C to +125°C
4
0
3.0
Low
Yes
No
16-Lead SOIC_N
R-16
ADuM140E1BRZ
−40°C to +125°C
4
0
3.0
High
No
Yes
16-Lead SOIC_N
R-16
ADuM140E1BRZ-RL7
−40°C to +125°C
4
0
3.0
High
No
Yes
16-Lead SOIC_N
R-16
ADuM140E0BRZ −40°C to +125°C 4 0 3.0 Low No Yes 16-Lead SOIC_N R-16
ADuM140E0BRZ-RL7 −40°C to +125°C 4 0 3.0 Low No Yes 16-Lead SOIC_N R-16
ADuM140D1BRWZ −40°C to +125°C 4 0 3.75 High Yes No 16-Lead SOIC_W RW-16
ADuM140D1BRWZ-RL −40°C to +125°C 4 0 3.75 High Yes No 16-Lead SOIC_W RW-16
ADuM140D0BRWZ
−40°C to +125°C
4
0
3.75
Low
Yes
No
16-Lead SOIC_W
RW-16
ADuM140D0BRWZ-RL
−40°C to +125°C
4
0
3.75
Low
Yes
No
16-Lead SOIC_W
RW-16
ADuM140D1BRQZ
−40°C to +125°C
4
0
3.0
High
Yes
No
16-Lead QSOP
RQ-16
ADuM140D1BRQZ-RL7
−40°C to +125°C
4
0
3.0
High
Yes
No
16-Lead QSOP
RQ-16
ADuM140D0BRQZ
−40°C to +125°C
4
0
3.0
Low
Yes
No
16-Lead QSOP
RQ-16
ADuM140D0BRQZ-RL7 −40°C to +125°C 4 0 3.0 Low Yes No 16-Lead QSOP RQ-16
ADuM140E1BRWZ −40°C to +125°C 4 0 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM140E1BRWZ-RL −40°C to +125°C 4 0 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM140E1WBRWZ −40°C to +125°C 4 0 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM140E1WBRWZ-RL
−40°C to +125°C
4
0
3.75
High
No
Yes
16-Lead SOIC_W
RW-16
ADuM140E0BRWZ
−40°C to +125°C
4
0
3.75
Low
No
Yes
16-Lead SOIC_W
RW-16
ADuM140E0BRWZ-RL
−40°C to +125°C
4
0
3.75
Low
No
Yes
16-Lead SOIC_W
RW-16
ADuM140E1BRQZ
−40°C to +125°C
4
0
3.0
High
No
Yes
16-Lead QSOP
RQ-16
ADuM140E1BRQZ-RL7
−40°C to +125°C
4
0
3.0
High
No
Yes
16-Lead QSOP
RQ-16
ADuM140E0BRQZ −40°C to +125°C 4 0 3.0 Low No Yes 16-Lead QSOP RQ-16
ADuM140E0BRQZ-RL7 −40°C to +125°C 4 0 3.0 Low No Yes 16-Lead QSOP RQ-16
ADuM141D1BRZ
−40°C to +125°C
3
1
3.0
High
Yes
No
16-Lead SOIC_N
R-16
ADuM141D1BRZ-RL7
−40°C to +125°C
3
1
3.0
High
Yes
No
16-Lead SOIC_N
R-16
ADuM141D0BRZ −40°C to +125°C 3 1 3.0 Low Yes No 16-Lead SOIC_N R-16
ADuM141D0BRZ-RL7 −40°C to +125°C 3 1 3.0 Low Yes No 16-Lead SOIC_N R-16
ADuM141E1BRZ −40°C to +125°C 3 1 3.0 High No Yes 16-Lead SOIC_N R-16
ADuM141E1BRZ-RL7 −40°C to +125°C 3 1 3.0 High No Yes 16-Lead SOIC_N R-16
Data Sheet ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E
Rev. I | Page 29 of 30
Model1, 2
Temperature
Range
No. of
Inputs,
VDD1
Side
No. of
Inputs,
VDD2
Side
Withstand
Voltage
Rating
(kV rms)
Fail-Safe
Output
State
Input
Disable
Output
Enable
Package
Description
Package
Option
ADuM141E0BRZ
−40°C to +125°C
3
1
3.0
Low
No
Yes
16-Lead SOIC_N
R-16
ADuM141E0BRZ-RL7 −40°C to +125°C 3 1 3.0 Low No Yes 16-Lead SOIC_N R-16
ADuM141D1BRWZ −40°C to +125°C 3 1 3.75 High Yes No 16-Lead SOIC_W RW-16
ADuM141D1BRWZ-RL −40°C to +125°C 3 1 3.75 High Yes No 16-Lead SOIC_W RW-16
ADuM141D0BRWZ −40°C to +125°C 3 1 3.75 Low Yes No 16-Lead SOIC_W RW-16
ADuM141D0BRWZ-RL
−40°C to +125°C
3
1
3.75
Low
Yes
No
16-Lead SOIC_W
RW-16
ADuM141D1BRQZ
−40°C to +125°C
3
1
3.0
High
Yes
No
16-Lead QSOP
RQ-16
ADuM141D1BRQZ-RL7
−40°C to +125°C
3
1
3.0
High
Yes
No
16-Lead QSOP
RQ-16
ADuM141D0BRQZ
−40°C to +125°C
3
1
3.0
Low
Yes
No
16-Lead QSOP
RQ-16
ADuM141D0BRQZ-RL7
−40°C to +125°C
3
1
3.0
Low
Yes
No
16-Lead QSOP
RQ-16
ADuM141E1BRWZ −40°C to +125°C 3 1 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM141E1BRWZ-RL −40°C to +125°C 3 1 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM141E1WBRWZ −40°C to +125°C 3 1 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM141E1WBRWZ-RL −40°C to +125°C 3 1 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM141E0BRWZ
−40°C to +125°C
3
1
3.75
Low
No
Yes
16-Lead SOIC_W
RW-16
ADuM141E0BRWZ-RL
−40°C to +125°C
3
1
3.75
Low
No
Yes
16-Lead SOIC_W
RW-16
ADuM141E1BRQZ
−40°C to +125°C
3
1
3.0
High
No
Yes
16-Lead QSOP
RQ-16
ADuM141E1BRQZ-RL7
−40°C to +125°C
3
1
3.0
High
No
Yes
16-Lead QSOP
RQ-16
ADuM141E0BRQZ
−40°C to +125°C
3
1
3.0
Low
No
Yes
16-Lead QSOP
RQ-16
ADuM141E0BRQZ-RL7 −40°C to +125°C 3 1 3.0 Low No Yes 16-Lead QSOP RQ-16
ADuM141E1WBRQZ −40°C to +125°C 3 1 3.0 High No Yes 16-Lead QSOP RQ-16
ADuM141E1WBRQZ-RL7 −40°C to +125°C 3 1 3.0 High No Yes 16-Lead QSOP RQ-16
ADuM142D1BRZ
−40°C to +125°C
2
2
3.0
High
Yes
No
16-Lead SOIC_N
R-16
ADuM142D1BRZ-RL7 −40°C to +125°C 2 2 3.0 High Yes No 16-Lead SOIC_N R-16
ADuM142D0BRZ −40°C to +125°C 2 2 3.0 Low Yes No 16-Lead SOIC_N R-16
ADuM142D0BRZ-RL7 −40°C to +125°C 2 2 3.0 Low Yes No 16-Lead SOIC_N R-16
ADuM142E1BRZ −40°C to +125°C 2 2 3.0 High No Yes 16-Lead SOIC_N R-16
ADuM142E1BRZ-RL7
−40°C to +125°C
2
2
3.0
High
No
Yes
16-Lead SOIC_N
R-16
ADuM142E0BRZ
−40°C to +125°C
2
2
3.0
Low
No
Yes
16-Lead SOIC_N
R-16
ADuM142E0BRZ-RL7
−40°C to +125°C
2
2
3.0
Low
No
Yes
16-Lead SOIC_N
R-16
ADuM142D1BRWZ
−40°C to +125°C
2
2
3.75
High
Yes
No
16-Lead SOIC_W
RW-16
ADuM142D1BRWZ-RL
−40°C to +125°C
2
2
3.75
High
Yes
No
16-Lead SOIC_W
RW-16
ADuM142D0BRWZ −40°C to +125°C 2 2 3.75 Low Yes No 16-Lead SOIC_W RW-16
ADuM142D0BRWZ-RL −40°C to +125°C 2 2 3.75 Low Yes No 16-Lead SOIC_W RW-16
ADuM142D1BRQZ −40°C to +125°C 2 2 3.0 High Yes No 16-Lead QSOP RQ-16
ADuM142D1BRQZ-RL7 −40°C to +125°C 2 2 3.0 High Yes No 16-Lead QSOP RQ-16
ADuM142D0BRQZ
−40°C to +125°C
2
2
3.0
Low
Yes
No
16-Lead QSOP
RQ-16
ADuM142D0BRQZ-RL7
−40°C to +125°C
2
2
3.0
Low
Yes
No
16-Lead QSOP
RQ-16
ADuM142E1BRWZ
−40°C to +125°C
2
2
3.75
High
No
Yes
16-Lead SOIC_W
RW-16
ADuM142E1BRWZ-RL
−40°C to +125°C
2
2
3.75
High
No
Yes
16-Lead SOIC_W
RW-16
ADuM142E1WBRWZ
−40°C to +125°C
2
2
3.75
High
No
Yes
16-Lead SOIC_W
RW-16
ADuM142E1WBRWZ-RL −40°C to +125°C 2 2 3.75 High No Yes 16-Lead SOIC_W RW-16
ADuM142E0BRWZ −40°C to +125°C 2 2 3.75 Low No Yes 16-Lead SOIC_W RW-16
ADuM142E0BRWZ-RL −40°C to +125°C 2 2 3.75 Low No Yes 16-Lead SOIC_W RW-16
ADuM142E1BRQZ −40°C to +125°C 2 2 3.0 High No Yes 16-Lead QSOP RQ-16
ADuM142E1BRQZ-RL7
−40°C to +125°C
2
2
3.0
High
No
Yes
16-Lead QSOP
RQ-16
ADuM142E0BRQZ
−40°C to +125°C
2
2
3.0
Low
No
Yes
16-Lead QSOP
RQ-16
ADuM142E0BRQZ-RL7
−40°C to +125°C
2
2
3.0
Low
No
Yes
16-Lead QSOP
RQ-16
ADuM142E1WBRQZ −40°C to +125°C 2 2 3.0 High No Yes 16-Lead QSOP RQ-16
ADuM142E1WBRQZ-RL7
−40°C to +125°C
2
2
3.0
High
No
Yes
16-Lead QSOP
RQ-16
1 Z = RoHS Compliant Part.
2 The ADuM140E1WBRWZ, ADuM140E1WBRWZ-RL, ADuM141E1WBRWZ, ADuM141E1WBRWZ-RL, ADuM141E1WBRQZ, ADuM141E1WBRQZ-RL7, ADuM142E1WBRWZ,
ADuM142E1WBRWZ-RL, ADuM142E1WBRQZ, and ADuM142E1WBRQZ-RL7 are qualified for automotive applications.
ADuM140D/ADuM140E/ADuM141D/ADuM141E/ADuM142D/ADuM142E Data Sheet
Rev. I | Page 30 of 30
AUTOMOTIVE PRODUCTS
The ADuM140E1W, ADuM141E1W and ADuM142E1W models are available with controlled manufacturing to support the quality and
reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the
commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade
products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific
product ordering information and to obtain the specific Automotive Reliability reports for these models.
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13119-0-8/18(I)
