Econ es7a20, 072 PAL16R8 Family 20-Pin TTL Programmable Array Logic al Advanced Micro Devices DISTINCTIVE CHARACTERISTICS M@ As fast as 4.5 ns maximum propagation delay @ Popular 20-pin architectures: 16L8, 16R8, 16R6, 16R4 M@ Programmable replacement for high-speed TTL logic B Register preload for testability @ Power-up reset for initialization @ Extensive third-party software and programmer support through FusionPLD partners M@ 20-Pin DIP and PLCC packages save space @ 28-Pin PLCC-4 package provides ultra-clean high-speed signals GENERAL DESCRIPTION The PAL16R8 Family (PAL16L8, PAL16R8, PAL16R6, PAL16R4) includes the PAL16R8-5/4 Series which pro- vides the highest speed in the 20-pin TTL PAL device family, making the series ideal for high-performance ap- plications. The PAL16R8 Family is provided with stan- dard 20-pin DIP and PLCC pinouts and a 28-pin PLCC pinout. The 28-pin PLCC pinout contains seven extra ground pins interleaved between the outputs to reduce noise and increase speed. The devices provide user-programmable logic for re- placing conventional SSI/MSI gates and flip-flops at a reduced chip count. The family allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections be- tween gates, which previously required time-consuming layout, are lifted from the PC board and placed on sili- con, where they can be easily modified during proto- typing or production. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device iS a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. In addition, the PAL device provides the following options: Variable input/output pin ratio Programmable three-state outputs Registers with feedback Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. Registers consist of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock. Un- used input pins should be tied to Vcc or GND. The entire PAL device family is supported by the FusionPLD partners. The PAL family is programmed on conventional PAL device programmers with appropriate personality and socket adapter modules. Once the PAL device is programmed and verified, an additional con- nection may be opened to prevent pattern readout. This feature secures proprietary circuits. PRODUCT SELECTOR GUIDE Dedicated Product Terms/ Device Inputs Outputs Output Feedback Enable PAL16L8 10 6 comb. 7 VO prog. 2 comb. 7 - prog. PAL16R8 8 8 reg. 8 reg. pin PAL16R6 8 6 reg. 8 reg. pin 2 comb. 7 vO Prog. PAL16R4 8 4 reg. 8 reg. pin 4 comb. 7 vO prog. Publication# 16492 Rev.0 Amendment/0 Issue Date: February 1996 2-3 M! 0257526 OO3bb08 Soy mmal AMD BLOCK DIAGRAMS PALI6L8 INPUTS 10 Programmable AND Array (32 x 64) LE biadddd /Os VOs VO7 7 Oa L Os = Os = Oo O2 16492D-1 PAL16R8 CLK INPUTS <$a9 Programmable AND Array (32 x 64) G of 9 RR OK EG oO 9 HH? ORE of 2 RHO OFC EH ol Le 9 Ho OFC ERS bse 419 oH CE rr D Q Os 16492D-2 9 eH OF CES Li oat CE PAL16R8 Family Mm 0257526 0036609 480AMD cl BLOCK DIAGRAMS PAL16R6 CLK INPUTS OE Programmable AND Array (32 x 64) ys p of C4 aL 5 D Pag Ou D [ts a a Pa a VO, Os Os oO, VOa 16492D-3 CLK PALI6R4 DE 8 VY Programmable AND Array (32 x 64) | ul j : a t t ' ' 5 D D D D . Ye TG ab en VOz Oa Os Os Os VOr VOs 16492D-4 PAL16R8 Family 2-5 M 0257526 O03bb10 1T?cl AMD CONNECTION DIAGRAMS Top View DIP 20-Pin PLCC (Note 1) []1 20 [7] Voc nt2 19{_] (Note 10) 3 18[_] (Note 9) isf]4 17[] (Note 8) Os 16|_] (Note 7) (Note 9) s 15|_] (Note 6) 17] (Note 8) ts (7 141] (Note 5) 16]] (Note 7) Us 13]_] (Note 4) 15] (Note 6) iso 12[_] (Note 3) 141] (Note 5) GND [10 1111] (Note 2) 16492D-5 2QaeF $228 zZ22z 28-Pin PLCC reae0's PIN DESIGNATIONS CLK = Clock GND =~ Ground I = Input VO = Input/Output QO = Output OE = Output Enable Vec = Supply Voltage Note: Pin 1 is marked for orientation. 2 o Z 16492D-7 Note 16L8 16R8 16R6 16R4 1 lo CLK CLK CLK 2 lo OE OE GE 3 O1 Or VO; VO 4 VO2 Oz O2 VO2 5 VOz3 Qs Qa Os 6 VOs Oa Os O4 7 VOs Os Os Os 8 VOs Os Oc Os 9 VOr O7 Or VOr 10 Os Os er) VOs 2-6 PAL16R8 Family M@ 0257526 0036611 035ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial ai (Valid Combination) is formed by a combination of: PAL FAMILY TYPE PAL = Programmable Array Logic NUMBER OF ARRAY INPUTS OUTPUT TYPE R = Registered L = Active-Low Combinatorial NUMBER OF OUTPUTS 16 R 8 5 SPEED -4=4.5nstpp -5 =5ns tep -7 =7.5 ns teo D= 10 ns tpp VERSION Blank = First Revision /2 = Second Revision Valid Combinations PAL16L8 PAL16R8 PAL16R6 PAL16R4 -6PC, -5JC, -4JC PAL16L8-7 PAL16R8-7 PAL16R6-7 PAL16R4-7 PC, JC, DC PAL16L8D/2 PAL16A8D/2 PAL16R6D/2 PAL16R4D/2 PC, JC AMD al pplications are available with several ordering options. The ordernumber PC L OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial (0C to +75C) PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) 28-Pin Plastic Leaded Chip Carrier for -4 (PL 028) 20-Pin Ceramic DIP (CD 020) 0 iT) Valid Combinations Valid Combinations lists configurations planned to be supportedin volume for this device. Consultthe local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. PAL16R8-4/5/7, D/2 (Coml) M@@ 0257526 OO3bble T75 a a a aaa 2-7cl AMD ORDERINGINFORMATION Commercial Products (MMI Marking Only) AMD programmable logic productsforcommercialapplications are available with several ordering options. The ordernumber (Valid Combination) is fommedby a combination of: PAL 16 R&B -2C N FAMILY TYPE PAL =Programmable Array Logic NUMBER OF ARRAY INPUTS OUTPUT TYPE R = Registered L = Active-LowCombinatorial NUMBER OF OUTPUTS SPEED B = Very High Speed (15ns-35nst pp) A = High Speed (25ns35nst pp) POWER Blank = Full Power (155 mA-180 mAI cc) -2 = Half Power (80 mA-90 mAI cc) -4 = Quarter Power (55 mA Icc) L_ OPTIONAL PROCESSING Blank =Standard Processing PACKAGE TYPE N= 20-Pin Plastic DIP (PD020) NL = 20-PinPlasticLeaded Chip Carrier (PL 020) J = = 20-Pin Ceramic DIP (CD 020) OPERATING CONDITIONS C = Commercial (0C to +75 C) Valid Combinations Valid Combinations ValidCombinationslists configurationsplanned to PAL16L8 be supported in volume for this device. Consult the localAMDsalesofficeto confirmavailability of PALi16R8 specific validcombinationsandtocheckon newly B, B-2,A, | CN, CNL, GJ teleasedcombinations. PAL16R6 B-4 Note: Marked with MMI logo. PAL16R4 2-8 PAL16R8/B/B-2/A/B-4 (Coml) @ 0257526 003bb13 301FUNCTIONAL DESCRIPTION Standard 20-Pin PAL Family The standard bipolar 20-pin PAL family devices have common electrical characteristics and programming procedures. Four different devices are available, includ- ing both registered and combinatorial devices. All parts are produced with a fuse link at each input to the AND gate array, and connections may be selectively re- moved by applying appropriate voltages to the circuit. Utilizing an easily-impiemented programming algo- rithm, these products can be rapidly programmed to any customized pattern. Extra test words are pre- programmed during manufacturing to ensure extremely high field programming yields, and provide extra test paths to achieve excellent parametric correlation. Pinouts The PAL16R8 Family is available in the standard 20-pin DIP and PLCC pinouts and the PAL16R8-4 Series is available in the new 28-pin PLCC pinout. The 28-pin PLCC pinout gives the designer the cleanest possible signal with only 4.5 ns delay. The PAL16R8-4 pinout has been designed to minimize the noise that can be generated by high-speed signals. Because of its inherently shorter leads, the PLCC pack- age is the best package for use in high-speed designs. The short leads and multiple ground signals reduce the effective lead inductance, minimizing ground bounce. Placing the ground pins between the outputs optimizes the ground bounce protection, and also isolates the out- puts from each other, eliminating cross-talk. This pinout can reduce the effective propagation delay by as much as 20% from a standard DIP pinout. Design files for PAL16R8-4 Series devices are written as if the device had a standard 20-pin DIP pinout for most design soft- ware packages. Variable Input/Output Pin Ratio The registered devices have eight dedicated input lines, and each combinatorial output is an V/O pin. The PAL16L8 has ten dedicated input lines and six of the eight combinatorial outputs are I/O pins. Buffers for de- vice inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to Vcc or GND. Programmable Three-State Outputs Each output has a three-state output buffer with three- state control. On combinatorial outputs, a product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feed- back. The combinatorial output provides a bidirectional V/O pin and may be configured as a dedicated input if the output buffer is always disabled. On registered outputs, an input pin controls the enabling of the three-state outputs. AMD al Registers with Feedback Registered outputs are provided for data storage and synchronization. Registers are composed of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock input. Register Preload The register on the AMD marked 16R8, 16R6, and 16R4 devices can be preloaded from the output pins to facili- tate functional testing of complex state machine de- signs. This feature allows direct loading of arbitrary States, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Power-Up Reset All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the PAL16R8 Family will be HIGH due to the active-low outputs. The Vcc rise must be monotonic and the reset delay time is 1000 ns maximum. Security Fuse After programming and verification, a PAL16R8 Family design can be secured by programming the security fuse. Once programmed, this fuse defeats readback of the internal programmed pattern by a device program- mer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed. Quality and Testability The PAL16R8 Family offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest pro- gramming yields and post-programming functional yields in the industry. Technology The PAL16R8-5, -7 and D/2 are fabricated with AMDs oxide isolated bipolar process. The array connections are formed with highly reliable PtSi fuses. The PAL16R8B, B-2, A and B-4 series are fabricated with AMDs advanced trench-isolated bipolar process. The array connections are formed with proven TiW fuses for reliable operation. These processes reduce parasitic capacitances and minimum geometries to provide higher performance. PAL16R8 Family 2-9 MH 0257526 0036614 648 a aat AMD LOGIC DIAGRAM DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts 16L8 (-4) Voc (23) (24) 0 34 78 #1112 #1816 1920 2324 2728 H Og (22) i {Jano (25) = (21) VO, (20) ae Lew (26) = (49) Vg (18) Ig [4 ct]eno (27) * 47) VOs, (16) 14 cL]anp (28) = (15) Vec] (14) 5 cL] np * (13) (12) Ig _cL]enp = (11) UO, (10) l Leno 01 Ig tj lg 3) GND (6) = 3.4 78 1112 1816 1920 2324 2728 31 16492D-8 2-10 PAL16R8 Family Mi 0257526 OO3bb615 784AMD al LOGIC DIAGRAM DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts 16R8 (-4) Voc 34 78 1112 1516 1920 2324 2728 41 (23) CLK [14 Og (22) 1, [2 c{_]enp ~ (21) 07 (20) Ig ct/anp * (19) 06 (18) Ig [4 c{_] np * (7) 05 (16) 4 ct] 6np Voc CO 4 (14) '5 6 {| ano Og (12) 'g cL] GND 02 (10) '7 [8 {_]enp 'g [9 0 34 78 1112 1516 1920 2324 2728 31 GND [10} 6) i - 16492D-9 PAL16R8 Family 2-11 M 02575eb OO3bb1b b10at AMD LOGIC DIAGRAM DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts 16R6 (-4) 0 34 7 8 1112 #1816 1920 2324 2728 31 Voc 0 34 #78 #1112 1616 1920 2324 2728 31 GND ) = 16492D-10 2-12 PAL16R8 Family M@ 0257526 0036617 557AMD cl LOGIC DIAGRAM DIP and 20-Pin PLCC (28-Pin PLCC) Pinouts 16R4 (-4) 0 34 #78 41112 #1516 1920 2324 2728 31 (7) 0 34 78 #1112 1816 1920 2324 2728 31 GND @ 4 16492D-11 PAL16R8 Family 2-13 ME 0257526 OO3bb1a 443 aaaP| AMD ABSOLUTE MAXIMUM RATINGS Ambient Temperature with Power Applied ............... -65C to +150C Storage Temperature .......... 55C to +125C Supply Voltage with Respect to Ground ............. 0.5 Vto+7.0V DC Input Voltage .......... -1.2 V to Vcc + 0.5 V DC Input Current ............. -30 mAto+5mA DC Output or I/O Pin Voltage .. 0... eee eee 0.5 V to Vec + 0.5 V Static Discharge Voltage .............4. 2001 V Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (Ta) Operating in Free Air ........... 0005 0C to +75C Supply Voltage (Vcc) with Respect to Ground ......... 44.75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit Vou Output HIGH Voltage lon =-3.2 mA Vin = Vin or Vit 2.4 Vv Vee = Min . Vor Output LOW Voltage lo. = 24 mA Vin = Vin or Vit 0.5 v Veo = Min Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 v Voltage for all Inputs (Note 1) Vi Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voitage for all Inputs (Note 1) vi Input Clamp Voltage lin=18 mA, Voc = Min -1.2 v lin Input HIGH Current Vin = 2.7 V, Voc = Max (Note 2) 25 pA In Input LOW Current Vin = 0.4 V, Voc = Max (Note 2) -250 pA h Maximum Input Current Vin = 5.5 V, Voc = Max 1 mA lozx Off-State Output Leakage Vout = 2.7 V, Vec = Max 100 HA Current HIGH Vin = Vin or Vic (Note 2) loz. Off-State Output Leakage Vout = 0.4 V, Veco = Max -100 pA Current LOW Vin = Vin or Vic (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max (Note 3) 30 -130 mA Ice Supply Current Vin= 0 V, Outputs Open (lour = 0 mA) 210 | mA Voc = Max Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. VO pin leakage is the worst case of Ii, and lozt (or ln and lozn). 3. Notmore than one output should be tested at a time. Duration of the short-circuit should not exceed one second, VouT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-14 PAL16R8-4/5 (Coml) MB 0257526 0036619 JetAMD at CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cw Input Capacitance |_CLK, OE Vin = 2.0 Veo = .0V 8 livle Ta = 25C pF Court Output Capacitance Vout = 2.0 V f=1MHz 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) 5 4 Parameter Min Min Symbol Parameter Description (Note 3){| Max | (Note 3)] Max | Unit tep Input or Feedback to Combinatorial Output 16L8, 16R8, 1 5 1 45 | ns 16A4 ts Setup Time from Input or Feedback to Clock 45 45 ns tH Hold Time 0 0 ns tco Clock to Output 1 4.0 1 3.5 ns tskewr Skew Between Registered Outputs (Note 4) 1 05 ns ton LOW ee {4 4 ns Clock Width two HIGH 4 4 ns . Extemal Feedback | 1/(ts + tco) 117 125 MHz Maximum fmax Frequency | InternalFeedback | 1/(ts + tcr) 425 125 MHz (Note 5) (fenr) (Note 6) No Feedback A(twH + two) 125 125 MHz tezx OE to Output Enable 1 6.5 1 6.5 | ns texz OE to Output Disable 1 5 1 5 ns tea Input to Output Enable Using 2 6.5 2 6.5 ns Product Term Control 16L8, 16R6 ten Input to Output Disable Using 16R4 2 5 2 5 ns Product Term Control Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for tpo, tco, trzx, texz, tea, and ten are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation Purposes only. 4. Skew testing takes into account pattern and switching direction differences between outputs. 5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 6. tcr is a calculated value and is not guaranteed. tcr can be found using the following equation: tcr = 1/uax (internal feedback) ts. PAL16R8-4/5 (Com'l) 2-15 MB 0257526 OO3bb2e0 O41 SS aaaat AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... -65C to +150C Ambient Temperature with Power Applied ...............0. 55C to +125C Supply Voltage with Respect to Ground ............. -0.5Vto+7.0V DC input Voltage ............... -12Vto+7.0V DC input Current ....... 0.00068 ~30 mA to+5mA DC Output or I/O Pin Voltage ....... ee eee eee -0.5 V to Ver + 0.5 V Static Discharge Voltage ...............6. 2001 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (Ta) Operating in Free Air .............. 0C to +75C Supply Voltage (Vcc) with Respect to Ground ........ +4,75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max | Unit Vor Output HIGH Voltage lon =-3.2 MA Vin = Vin or Vit 24 Vv Vcc = Min Vor Output LOW Voltage lo. = 24 mA Vin = Vie or Vit 0.5 Vv Vec = Min Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all inputs (Note 1) Vi Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) Vi Input Clamp Voltage lin=-18 MA, Voc = Min -1.2 Vv In Input HIGH Current Vin = 2.7 V, Voc = Max (Note 2) 25 pA Ii Input LOW Current Vin = 0.4 V, Vec = Max (Note 2) -250 pA fi Maximum Input Current Vin = 5.5 V, Voc = Max 1 mA lozH Off-State Output Leakage Vout = 2.7 V, Vec = Max 100 pA Current HIGH Vin = Vin or Vit (Note 2) loz Off-State Output Leakage Vout = 0.4 V, Vcc = Max -100 | pA Current LOW Vin = Vin or Vi (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max (Note 3) -30 -130 mA lec Supply Current Vin= 0 V, Outputs Open (lout = 0 mA) 180 mA Vcc = Max Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. W/O pin leakage is the worst case of li and loz. (or ln and lozH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vour = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-16 PAL16R8-7 (Coml) M@ 0257526 OO3bb21 T4658AMD at CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin=2.0V Voc =5.0V 5 oF Cour Output Capacitance Vout = 2.0 V Ta = 25C 8 f=1 MHz Note: 1. These parameters ara not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Min Symbol Parameter Description (Note 3) Max Unit t Input or Feedback to 16L8, 16R6, 3 75 PO Combinatorial Output 1 Output Switching 16R4 3 7 ns ts Setup Time from Input or Feedback to Clock 7 ns tk Hold Time 0 ns tco Clock to Output 1 65 ns {skew Skew Between Registered Outputs (Note 4) 16R8, 16R6, 1 ns | two Clock Width LOW 16R4 5 ns twH HIGH ns Maximum External Feedback _|{1/(ts + tco) 74 MHz | fax Frequency intemal Feedback (ts + ter) 100 MHz | (Note 5) (font) (Note 6) No Feedback 1/(twH + two) 100 MHz tezx OE to Output Enable 1 ns texz OE to Output Disable 1 ns tea Input to Output Enable Using Product Term Control 16L8, 16R6, 3 10 ns ter Input to Output Disable Using Product Term Control 16R4 3 10 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for teo, tco, tezx, texz, tea, and ten are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 4, Skew is measured with all outputs Switching in the same direction. 5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 6. ter is a calculated value and is not guaranteed. ter can be found using the following equation: tce = 1/fvax (intemal feedback) ts. PAL16R8-7 (Coml) 2-17 M@ 0257526 OO3bbe2 114 EE EEE ee LL eeat AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... -65C to +150C Ambient Temperature with Power Applied ................. -55C to +125C Supply Voltage with Respect to Ground ............. 0.5 Vte+7.0V DC Input Voltage .............6. -1.5Vto+5.5V DC Output or I/O Pin Voltage ..... -0.5 Vto+5.5V Static Discharge Voltage ..... 00... cen 2001 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (Ta) Operating in Free Air ............6. 0C to +75C Supply Voltage (Vcc) with Respect to Ground ........ +4.75 V to +5.25 V Operating ranges define those limits between which the fune- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit Vou Output HIGH Voltage lox =-3.2 MA Vin = Vin or Vit 24 Vv Vcc = Min Vor Output LOW Voltage lo. = 24 mA Vin = Vin or Vit 0.5 Vv Vcc = Min Vin ~ Input HIGH Voltage Guaranteed input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vi input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) vi Input Clamp Voltage lin = 18 mA, Voc = Min -1.5 v lie Input HIGH Current Vin = 2.4 V, Veo = Max (Note 2) 25 pA I Input LOW Current Vin = 0.4 V, Vcc = Max (Note 2) -250 yA hi Maximum Input Current Vin = 5.5 V, Voc = Max 100 pA lozH Off-State Output Leakage Vout = 2.4 V, Veco = Max 100 pA Current HIGH Vin = Vin or Vit (Note 2) loz. Off-State Output Leakage Vout = 0.4 V, Vec = Max ~100 pA Current LOW Vin = Viror Vit (Note 2) Ise Output Short-Circuit Current Vout = 0.5 V, Voc = Max (Note 3) -30 -130 mA lec Supply Current Vin= 0 V, Outputs Open (lout = 0 mA} 180 mA Veco = Max Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. W/O pin leakage is the worst case of Itt and lozt (or lit and lozn). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-18 PAL16R8D/2 (Com!) MM 0257526 O03bbe3 650AMD ol CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin=2.0V Vcc = 5.0V 5 Ta = 25C pF Cour Output Capacitance Vout = 2.0 V f=1 MHz 8 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Min Symbol Parameter Description (Note 3) Max Unit tep Input or Feedback to Combinatorial Output 16L8, 16R6, 3 10 ns 16R4 ts Setup Time from Input or Feedback to Clock 10 ns ty Hold Time 0 ns tco Clock to Output 3 7 ns twe Clock Width LOW 8 ns tw HIGH 16R8, 16R6, 8 ns . Extemal Feedback V{ts + tco) 16R4 58.8 MHz Maximum {max Frequency Internal Feedback {ts + ter) 60 MHz (Note 4) (font) (Note 5) No Feedback (two + two) 62.5 MHz tpzx OE to Output Enable 2 10 ns texz OE to Output Disable 2 10 ns tea Input to Output Enable Using Product Term Control 16L8, 16R6, 3 10 ns ter Input to Output Disable Using Product Term Control 16R4 3 10 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums for teo, tco, tpzx, texz, tea, and ter are defined under best case conditions. Future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. 5. tcr is a calculated value and is not guaranteed, tcr can be found using the following equation: ter = tax (intemal feedback) ts. PAL16R8D/2 (Com'l) 2-19 WM 0257526 003bb24 797 aacl AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... 65C to +150C Ambient Temperature with Power Applied ................. 55C to +126C Supply Voltage with Respect to Ground ............. 0.5 V to +7.0V DC Input Voltage ........... -1.5V to Vcc +0.5V DC Output or I/O Pin Voltage ....... cece cee eee -0.5 V to Veo + 0.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (Ta) Operating in Free Air .............. 0C to +75C Supply Voltage (Vcc) with Respect to Ground ........ +4.75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max | Unit Vou Output HIGH Voltage lon =-3.2 mA Vin = Vin or Vir 2.4 Vv Vcc = Min Vor Output LOW Voltage lo. = 24 mA Vin = Vin or Vic 0.5 Vv Vcc = Min Vin input HIGH Voltage Guaranteed Input Logical HIGH 2.0 v Voltage for all Inputs (Note 1) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 v Voltage for all Inputs (Note 1) vi Input Clamp Voltage lin=18 MA, Vcc = Min 1.2 Vv I Input HIGH Current Vin = 2.4 V, Voc = Max (Note 2) 25 HA Ie Input LOW Current Vin = 0.4 V, Vcc = Max (Note 2) ~250 pA h Maximum Input Current Vin = 5.5 V, Voc = Max 100 pA loz Off-State Output Leakage Vout = 2.4 V, Vcc = Max 100 HA Current HIGH Vin = Vinor Vit (Note 2) loz. Off-State Output Leakage Vout = 0.4 V, Voc = Max ~100 pA Current LOW Vin = Vinor Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vcc = Max (Note 3) -30 | -130 mA lec Supply Current Vin= 0 V, Outputs Open (lour = 0 mA) 180 mA Vec = Max Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of lit and lozt (or fH and lozH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-20 PAL16R8B (Coml) M 0257526 003bb25 besAMD zt CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin=2.0V Veco = 5.0 V 8 Ta = 25C pF Court Output Capacitance Vout = 2.0 V f= 1 MHz 9 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitancemaybe affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Unit trp Input or Feedback to Combinatorial Output 16L8, 16R6, 15 ns 16R4 ts Setup Time from Input or Feedback to Clock 15 ns tH Hold Time 0 ns tco Clock to Output or Feedback 12 ns two Clock Width LOW 10 ns tw HIGH rors eRe, 40 ns Maximum Extemal Feedback AKts + tco) 37 MHz faax Frequency (Note 3) No Feedback 1A(twu + tw.) 50 MHz tezx GE to Output Enable 15 ns texz GE to Output Disable 15 ns tea Input to Output Enabie Using Product Term Control 16R8,16R6 15 ns ter Input to Output Disable Using Product Term Control 16R4 15 ns Notes: 2. See Switching Test Circuit fortest conditions. 3. These parameters are not 100% tested, but are evaluated at initial characterization andat any time the design is modified where capacitancemaybe affected. PAL16R8B (Coml) 2-21 Mi 02575eb OO3bbeb SET aaat AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... 65C to +150C Ambient Temperature with Power Applied ................. 55C to +125C Supply Voltage with Respect to Ground ............. -0.5Vto+7.0V DC Input Voltage ........... -1.5 V to Vec + 0.5 V DC Output or I/O Pin Voltage ......-...-...00.. 0.5 V to Veco + 0.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality ator above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (Ta) Operating in Free Air .............. 0C to +75C Supply Voltage (Vcc) with Respect to Ground ........ +4.75 V to +5.25 V Operating ranges detine those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit Vou Output HIGH Voltage lon =-3.2mMA Vin = Vin or Vit 2.4 Vv Vec = Min Vo. Output LOW Voltage lo. = 24mA Vin = Vin or Vit 0.5 Vv Vcc = Min Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vir Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) Vi Input Clamp Voltage lin = 18 mA, Vec = Min -1.2 Vv ti Input HIGH Current Vin = 2.7 V, Voc = Max (Note 2) 25 pA he Input LOW Current Vin = 0.4 V, Vec = Max (Note 2) -100 pA hi Maximum Input Current Vin = 5.5 V, Voc = Max 100 pA lozH Off-State Output Leakage Vout = 2.7 V, Voc = Max 100 pA Current HIGH Vin = Vin or Vii (Note 2) loz. Off-State Output Leakage Vout = 0.4 V, Voc = Max -100 LA Current LOW Vin = Vinor Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max (Note 3) -30 -130 mA lec Supply Current Vin= 0 V, Outputs Open (lour = 0 mA) 90 mA Vec = Max Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of lit and lozz (or lin and lozn). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-22 PAL16R8B-2 (Com!) M 0257526 OO3bbe7? 4ThAMD cl CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin = 2.0 V Vec = 5.0 V 7 Ta = 25C pF Court Output Capacitance Vout = 2.0 V f= 1 MHz 7 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Unit tep Input or Feedback to Combinatorial Output 16L8, 16R6, 25 ns 16R4 ts Setup Time from Input or Feedback to Clock 25 ns ty Hold Time 0 ns tco Clock to Output 15 ns tw Clock Width LOW 15 ns 16R8, 16R6, twH HIGH 16R4 15 ns Maximum Extemai Feedback | 1/(ts + tco) 25 MHz fax Frequency intemal Feedback | 1/(ts + tcr) 28.5 MHz (Note 4) (font) (Note 5) No Feedback 1/(twu + tw.) 33 MHz tezx OE to Output Enable 20 ns texz OE to Output Disable 20 ns tea Input to Output Enable Using Product Term Control 16R8, 16R6, 25 ns ter Input to Output Disable Using Product Term Control 16R4 25 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Calculated from measured fyax intemal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. ter is a calculated value and is not guaranteed. ter can be found using the following equation: ter = 1/fyax (intemal feedback) - ts. PAL16R8B-2 (Coml) 2-23 MB 0257S5eb 003bb2e6 332 a a acl AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... 65C to +150C Ambient Temperature with Power Applied ................. ~55C to +125C Supply Voltage with Respect to Ground ............. 0.5Vt0o+7.0V DC Input Voltage ........... -1.5V to Vcc +0.5V DC Output or I/O Pin A(o)| C-\ | - 0.5 V to Veco + 0.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (Ta) Operating in Free Air .............. 0C to +75C Supply Voltage (Vcc) with Respect to Ground ........ +4.75 V to +6.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max | Unit Vou Output HIGH Voltage lon =-3.2 MA Vin = Vin or ViL 2.4 v Vcc = Min Vor Output LOW Voltage lo. = 24 mA Vin = Vin or Vi 0.5 v Vec = Min Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vir Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) vi Input Clamp Voltage lin=18 MA, Veco = Min -1.2 v hy Input HIGH Current Vin = 2.7 V, Vcc = Max (Note 2) 25 pA te Input LOW Current Vin = 0.4 V, Vcc = Max (Note 2) -250 pA hi Maximum Input Current Vin = 5.5 V, Vcc = Max 100 pA loz Off-State Output Leakage Vout = 2.7 V, Voc = Max 100 pA Current HIGH Vin = Vin.or Vit (Note 2) loz. Off-State Output Leakage Vout = 0.4 V, Vec = Max 100 pA Current LOW Vin = Vin or Vic (Note 2) Isc Output Short-Circuit Current Vour = 0.5 V, Vcc = Max (Note 3) -30 -130 mA loo Supply Current 16L8 Vin = 0 V, Outputs Open (lour= 0 mA) 155 mA 16R8/6/4 Vcc = Max 180 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. 1/0 pin leakage is the worst case of In. and lozz (or hn and lozp). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vcc = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-24 PAL16R8A (Coml) MB 0257526 0036625 275AMD al CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin=2.0V Vee = 5.0V 7 Ta = 25C pF Cour Output Capacitance Vout = 2.0 V f=1MHz 7 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Unit tep Input or Feedback to Combinatorial Output 16L8, 16R6, 25 ns 16R4 ts Setup Time from Input or Feedback to Clock 25 ns tH Hold Time 0 ns tco Clock to Output 15 ns tw Clock Width LOW 15 ns twu HIGH 15 ns 16R8, 16R6, Maximum Extemal Feedback | 1/(ts + tco) 16R4 25 MHz fax Frequency Internal Feedback =| 1/(ts + tor) 28.5 MHz (Note 4) (fent) (Note 5) No Feedback W(twu + tw) 33 MHz tezx OE to Output Enable 20 ns texz OE to Output Disable 20 ns tea Input to Output Enable Using Product Term Control 16R8, 16R6, 25 ns ter Input to Output Disable Using Product Term Control 16R4 25 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Calculated from measured fyax intemal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. tcr is a calculated value and is not guaranteed. tcr can be found using the following equation: tcr = 1uax (intemal feedback) - ts. PAL16R8A (Coml) 2-25 M@@ 6257526 0036630 TI0 ee,cl AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... -65C to +150C Ambient Temperature with Power Applied ................. 55C to +125C Supply Voltage with Respect to Ground ............. -0.5Vt0+7.0V DC Input Voltage ..............- -1.5Vto+5.5V DC Output or I/O Pin Voltage ...........06. 5.5V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (Ta) Operating in Free Air .............. 0C to +75C Supply Voltage (Vcc) with Respect to Ground ........ +4.75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max | Unit Vou Output HIGH Voltage lon = -1 MA Vin = Vin or Vit 2.4 Vv Vec = Min Vor Output LOW Voltage lo. = 8 MA Vin = Vin or Vic 0.5 Vv Vee = Min Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vir Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) Mi Input Clamp Voltage lin=-18 MA, Voc = Min -1.5 Vv tin Input HIGH Current Vin = 2.4 V, Vcc = Max (Note 2} 25 pA be Input LOW Current Vin = 0.4 V, Voc = Max (Note 2) -250 pA h Maximum Input Current Vin = 5.5 V, Voc = Max 100 pA loz Off-State Output Leakage Vout = 2.4 V, Vec = Max 100 pA Current HIGH Vin = Vinor Vic (Note 2) loz Off-State Output Leakage Vout = 0.4 V, Vcc = Max -100 | pA Current LOW Vin = Vinor Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max (Note 3) -30 ~250 mA lec Supply Current Vin= 0 V, Outputs Open (lout = 0 mA) 55 mA Vec = Max Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. VO pin leakage is the worst case of In, and lozz (or li and lozx). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V as been chosen to avoid test problems caused by tester ground degradation. 2-26 PAL16R8B-4 (Coml) Me 02575eb 0036631 127SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) AMD el Parameter Symbol Parameter Description Min Max Unit tep Input or Feedback to Combinatorial Output 16L8, 16R6, 35 ns 16R4 ts Setup Time from Input or Feedback to Clock 35 ns tu Hold Time 0 ns tco Clock to Output or Feedback 16R8, 16R6, 25 ns tw. Clock Width LOW 16R4 25 ns two HIGH 25 ns Maximum Extemal Feedback | 1/(ts + tco) 16 MHz fraax Frequency (Note 2) No Feedback 1(twu + twi) 20 MHz tezx OE to Output Enable 25 ns texz OE to Output Disable 25 ns tea Input to Output Enable Using Product Term Control 16L8, 16R6, 35 ns fer Input to Output Disable Using Product Term Control 16R4 35 ns Notes: 1. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. PAL16R8B-4 (Com'l) MH 02575eb 003bb32 5643 AA aaa 2-27al AMD SWITCHING WAVEFORMS Input or Feedback Vt ts tH Input or Feedback Vr V1 tpp Clock tco Combinatorial X XX Y | Reaistered Output Vr Output Vt 16492D-12 16492D-13 Combinatorial Output Registered Output Clock / Registered Output 1 VT twH tSKEWR Clock Vr Registered Output 2 Vt twe 16492D-14 16492D-15 Registered Output Skew Clock Width Input VT _. VT OE ten t t fea tpxz tPZx Vk Vor 0.50/77 Vik Vou 0.5W/77 it Vv Vv Output TFB. + 0sv\XXK Outpt Vo + osvWAK 16492D-16 16492D-17 Input to Output Disable/Enable GE to Output Disable/Enable Notes: 1.Vr=1.5V 2. Input pulse amplitude 0 V to 3.0 V 3. Input rise and fall times 2 ns3 ns typical. 2-28 PAL16R8 Family MM 0257526 0036633 7TTKEY TO SWITCHING WAVEFORMS AMD cl WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Wilt be Change Changing from H to L from H to L May Will be Change Changing from L to H from L to H Dont Care, Changing, Any Change State Pennitted Unknown Does Not Center Apply Line is High- Impedance Off State KS000010-PAL SWITCHING TEST CIRCUIT 5Vv Si Ri Output Test Point : IL : = = 16492D-18 Commercial Measured Specification Si CL Ri Re Output Value tpp, tco Closed All but B-4: Allbut B-4: 1.5V {Pzx, tEA Z H: Open 50 pF 200 2 390 2 1.5V ZL: Closed tpxz, tER H-Z: Open 5 pF B-4: B-4: HZ: Von-0.5V LZ: Closed 800 Q 1.56 kQ LZ: VoL+0.5V M8 0257526 0036634 b3b PAL16R8 Family 2-29 a a aaaal AMD MEASURED SWITCHING CHARACTERISTICS for the PAL16R8-5 Vcc = 4.75 V, Ta = 75C (Note 1) 5.0 T 5 45 T teo,ns 49 PE 3.5 3.0 | t t t t t 1 1 2 3 4 5 6 7 8 Number of Outputs Switching 16492D-19 tpp vs. Number of Outputs Switching 10 T 8 _ tpo,ns 8 +5 4 _ 2 t t_+_++ t-+_+__ + 0 50 100 150 200 250 Cu, pF 16492D-20 treo vs. Load Capacitance Vcc = 5.25 V, Ta = 25C Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where tpp may be affected. 2-30 PAL16R8-5 M@@ 0257526 0036635 572AMD al CURRENT VS. VOLTAGE (Il-V) CHARACTERISTICS for the PAL16R8-4/5 Veco = 5.0 V, Ta = 25C lot, MA 15 T 10 7 5 _ | i $ t { | VoL, V 0.6 -0.4 -0.2 0. 04 06 -5 -_ | 16492D-21 Output, LOW 20 lon, MA + i | / i 1 Vou Vv 3 -2 1 0 16492D-22 Output, HIGH It, pA 20 T 1 2 3 ++ t+ viv 3 4-2 +4 | F -50 - 100 - 150 + -200 16492D-23 input PAL16R8-5 2-31 Me 02S75eb 0036636 409 See LLal AMD MEASURED SWITCHING CHARACTERISTICS for the PAL16R8-7 Voc = 4.75 V, Ta = 75C (Note 1) 757 tpp, ns 6 t | tt -+_1 1 2 3 4 5 6 7 8 NUMBER OF OUTPUTS SWITCHING 16492D-24 tpp vs. Number of Outputs Switching tPD, ns 54 t t t t | t t t t 1 10 30 50 70 90 110 Cu, pF 16492D-25 tpp vs. Load Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where tpp may be affected. 2-32 PAL 1&R&A-7 mM 0257526 0036637 345AMD cl CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS for the PAL16R8-7 Veo = 5.0 V, Ta = 25C lor, MA 15 + 10 7 5 _ ++4 tt++ vou,v 0.6 -0.4 -0.2 02/04 06 5+ -15 + 16492D-26 Output, LOW low, MA 20 T {+ + Von, V 3 -2 1 2 - -20 - 40 16492D-27 Output, HIGH i, pA 20 T 1 2 3 l i 4 1 l t T T T VV 3 2-1 | - -20 + 40 L 60 + 80 16492D-28 input PAL16R8-7 2-33 MH 0257526 0036638 281 a aaaat AMD INPUT/OUTPUT EQUIVALENT SCHEMATICS Vee Input Program/Verify Circuitry 16492D-29 Typical Input ? Voc 40 2 NOM Output mp Program/Verify/ Pi Test Circuitry ins Preload Circuitry 16492D-30 Typical Output 2-34 PAL16R8-5 WM 0257526 0036639 116M@ 0257526 OO3bb40 43T a a a aaa POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will be HIGH due to the inverting output buffer. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous opera- tion of the power-up reset and the wide range of ways AMD at Vcc can rise to its steady state, two conditions are required to ensure a valid power-up reset. These condi- tions are: The Vcc rise must be monotonic. @ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feed- back setup times are met. Parameter Symbol Parameter Description Max Unit ter Power-Up Reset Time 1000 ns ts Input or Feedback Setup Time See Switching tw Clock Width LOW Characteristics 4Vv Veco Power tpR Registered / /- y Active-Low j Output ts Clock \\\ a tw _ 16492D-31 Power-Up Reset Waveform PAL16R8 Family 2-35