Features * High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture * * * * * * * - 131 Powerful Instructions - Most Single-clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments - 16K Bytes of In-System Self-programmable Flash program memory - 512 Bytes EEPROM - 1K Bytes Internal SRAM - Write/Erase cycles: 10,000 Flash/100,000 EEPROM - Data retention: 20 years at 85C/100 years at 25C(1) - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - Up to 64K Bytes Optional External Memory Space - Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and Capture Modes - Real Time Counter with Separate Oscillator - Six PWM Channels - Dual Programmable Serial USARTs - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby I/O and Packages - 35 Programmable I/O Lines - 40-pin PDIP, 44-lead TQFP, and 44-pad MLF Operating Voltages - 1.8 - 5.5V for ATmega162V - 2.7 - 5.5V for ATmega162 Speed Grades - 0 - 8 MHz for ATmega162V (see Figure 113 on page 266) - 0 - 16 MHz for ATmega162 (see Figure 114 on page 266) 8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATmega162 ATmega162V 2513L-AVR-03/2013 Pin Configurations Figure 1. Pinout ATmega162 PDIP (OC0/T0) PB0 (OC2/T1) PB1 (RXD1/AIN0) PB2 (TXD1/AIN1) PB3 (SS/OC3B) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 (TXD0) PD1 (INT0/XCK1) PD2 (INT1/ICP3) PD3 (TOSC1/XCK0/OC3A) PD4 (OC1A/TOSC2) PD5 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PA0 (AD0/PCINT0) PA1 (AD1/PCINT1) PA2 (AD2/PCINT2) PA3 (AD3/PCINT3) PA4 (AD4/PCINT4) PA5 (AD5/PCINT5) PA6 (AD6/PCINT6) PA7 (AD7/PCINT7) PE0 (ICP1/INT2) PE1 (ALE) PE2 (OC1B) PC7 (A15/TDI/PCINT15) PC6 (A14/TDO/PCINT14) PC5 (A13/TMS/PCINT13) PC4 (A12/TCK/PCINT12) PC3 (A11/PCINT11) PC2 (A10/PCINT10) PC1 (A9/PCINT9) PC0 (A8/PCINT8) PB4 (SS/OC3B) PB3 (TXD1/AIN1) PB2 (RXD1/AIN0) PB1 (OC2/T1) PB0 (OC0/T0) GND VCC PA0 (AD0/PCINT0) PA1 (AD1/PCINT1) PA2 (AD2/PCINT2) PA3 (AD3/PCINT3) TQFP/MLF NOTE: MLF bottom pad should be soldered to ground. Disclaimer 2 44 42 40 38 36 34 43 41 39 37 35 33 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 13 15 17 19 21 12 14 16 18 20 22 PA4 (AD4/PCINT4) PA5 (AD5/PCINT5) PA6 (AD6/PCINT6) PA7 (AD7/PCINT7) PE0 (ICP1/INT2) GND PE1 (ALE) PE2 (OC1B) PC7 (A15/TDI/PCINT15) PC6 (A14/TDO/PCINT14) PC5 (A13/TMS/PCINT13) (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND VCC (A8/PCINT8) PC0 (A9/PCINT9) PC1 (A10/PCINT10) PC2 (A11/PCINT11) PC3 (TCK/A12/PCINT12) PC4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 VCC (TXD0) PD1 (INT0/XCK1) PD2 (INT1/ICP3) PD3 (TOSC1/XCK0/OC3A) PD4 (OC1A/TOSC2) PD5 Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATmega162/V 2513L-AVR-03/2013 ATmega162/V Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2. Block Diagram PA0 - PA7 PE0 - PE2 PC0 - PC7 PORTA DRIVERS/BUFFERS PORTE DRIVERS/ BUFFERS PORTC DRIVERS/BUFFERS PORTA DIGITAL INTERFACE PORTE DIGITAL INTERFACE PORTC DIGITAL INTERFACE VCC GND PROGRAM COUNTER STACK POINTER INTERNAL OSCILLATOR XTAL1 PROGRAM FLASH SRAM WATCHDOG TIMER OSCILLATOR XTAL2 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS MCU CTRL. & TIMING X INSTRUCTION DECODER Y INTERRUPT UNIT INTERNAL CALIBRATED OSCILLATOR TIMERS/ COUNTERS OSCILLATOR Z CONTROL LINES ALU AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART0 COMP. INTERFACE USART1 + - RESET PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTB DRIVERS/BUFFERS PORTD DRIVERS/BUFFERS PB0 - PB7 PD0 - PD7 3 2513L-AVR-03/2013 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega162 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an external memory interface, 35 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, four flexible Timer/Counters with compare modes, internal and external interrupts, two serial programmable USARTs, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot Program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. ATmega161 and ATmega162 Compatibility The ATmega162 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure back-ward compatibility with the ATmega161, all I/O locations present in ATmega161 have the same locations in ATmega162. Some additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega161 users. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega161 compatibility mode can be selected by programming the fuse M161C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega161. Also, the Extended Interrupt Vec-tors are removed. The ATmega162 is 100% pin compatible with ATmega161, and can replace the ATmega161 on current Printed Circuit Boards. However, the location of Fuse bits and the electrical characteristics differs between the two devices. ATmega161 Compatibility Mode Programming the M161C will change the following functionality: 4 * The extended I/O map will be configured as internal RAM once the M161C Fuse is programmed. ATmega162/V 2513L-AVR-03/2013 ATmega162/V * The timed sequence for changing the Watchdog Time-out period is disabled. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 56 for details. * The double buffering of the USART Receive Registers is disabled. See "AVR USART vs. AVR UART - Compatibility" on page 168 for details. * Pin change interrupts are not supported (Control Registers are located in Extended I/O). * One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible. Note that the shared UBRRHI Register in ATmega161 is split into two separate registers in ATmega162, UBRR0H and UBRR1H. The location of these registers will not be affected by the ATmega161 compatibility fuse. Pin Descriptions VCC Digital supply voltage GND Ground Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega162 as listed on page 72. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega162 as listed on page 72. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be activated even if a Reset occurs. Port C also serves the functions of the JTAG interface and other special features of the ATmega162 as listed on page 75. 5 2513L-AVR-03/2013 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega162 as listed on page 78. Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega162 as listed on page 81. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 18 on page 48. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the Inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the Inverting Oscillator amplifier. 6 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention 1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. 7 2513L-AVR-03/2013 About Code Examples 8 This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. ATmega162/V 2513L-AVR-03/2013 ATmega162/V AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registrers Control Lines Direct Addressing Instruction Decoder Indirect Addressing Instruction Register Interrupt Unit SPI Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers 9 2513L-AVR-03/2013 can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register - SREG - is defined as: Bit 10 7 6 5 4 3 2 1 0 I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG ATmega162/V 2513L-AVR-03/2013 ATmega162/V * Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a half carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. 11 2513L-AVR-03/2013 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input Figure 4 shows the structure of the 32 general purpose working registers in the CPU. Figure 4. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 ... R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 ... R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file. 12 ATmega162/V 2513L-AVR-03/2013 ATmega162/V The X-register, YThe registers R26..R31 have some added functions to their general purpose usage. These regregister, and Z-register isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5. The X-, Y-, and Z-registers 15 X - register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z - register 0 R26 (0x1A) 15 Y - register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 2513L-AVR-03/2013 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section "Memory Programming" on page 231 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 57. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to "Interrupts" on page 57 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by pro- 14 ATmega162/V 2513L-AVR-03/2013 ATmega162/V gramming the BOOTRST Fuse, see "Boot Loader Support - Read-While-Write Selfprogramming" on page 217. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< ... xxx ... When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code 0x000 RESET: ldi r16,high(RAMEND) ; Main program start Comments 0x001 out SPH,r16 0x002 ldi r16,low(RAMEND) 0x003 out SPL,r16 0x004 sei 0x005 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx ; .org 0x1C02 0x1C02 jmp EXT_INT0 ; IRQ0 Handler 0x1C04 jmp EXT_INT1 ; IRQ1 Handler SPM_RDY ; Store Program Memory Ready Handler ... .... 0x1C36 .. jmp ; When the BOOTRST Fuse is programmed and the boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org 0x002 0x002 jmp EXT_INT0 ; IRQ0 Handler jmp EXT_INT1 ; IRQ1 Handler jmp SPM_RDY ; Store Program Memory Ready Handler .org 0x1C00 0x1C00 RESET: ldi r16,high(RAMEND) ; Main program start 0x1C01 out SPH,r16 0x1C02 ldi r16,low(RAMEND) 0x1C03 out SPL,r16 0x1C04 sei 0x1C05 0x004 ... .... 0x036 .. ; ; 60 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx ATmega162/V 2513L-AVR-03/2013 ATmega162/V When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org 0x1C00 0x1C00 0x1C02 jmp jmp RESET EXT_INT0 ; Reset handler ; IRQ0 Handler 0x1C04 jmp EXT_INT1 ; IRQ1 Handler jmp SPM_RDY ; Store Program Memory Ready Handler ldi r16,high(RAMEND) ; Main program start 0x1C39 out SPH,r16 0x1C3A ldi r16,low(RAMEND) 0x1C3B out SPL,r16 0x1C3C sei 0x1C3D ... .... 0x1C36 .. ; ; 0x1C38 Moving Interrupts Between Application and Boot Space General Interrupt Control Register - GICR RESET: ; Set Stack Pointer to top of RAM ; Enable interrupts xxx The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit 7 6 5 4 3 2 1 0 INT1 INT0 INT2 PCIE1 PCIE0 - IVSEL IVCE Read/Write R/W R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GICR * Bit 1 - IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash section is determined by the BOOTSZ Fuses. Refer to the section "Boot Loader Support - Read-While-Write Self-programming" on page 217 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section "Boot Loader Support - Read-While-Write Self-programming" on page 217 for details on Boot Lock bits. 61 2513L-AVR-03/2013 * Bit 0 - IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1< CSn2:0 > 1). The number of system clock cycles from when the Timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024, additional selections for Timer/Counter3: 32 and 64). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it is connected to. External Clock Source An external clock source applied to the Tn/T0 pin can be used as Timer/Counter clock (clkT1/clkT0) for Timer/Counter1 and Timer/Counter0. The Tn/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 44 shows a functional equivalent block diagram of the Tn/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 44. Tn/T0 Pin Sampling Tn D Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. 104 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 45. Prescaler for Timer/Counter0, Timer/Counter1, and Timer/Counter3(1) CK PSR321 T1 0 Special Function IO Register - SFIOR T0 0 0 CS30 CS10 CS00 CS31 CS11 CS01 CS32 CS12 CS02 TIMER/COUNTER3 CLOCK SOURCE clkT3 Note: CK/1024 CK/256 CK/64 CK/32 CK/8 CK/16 10-BIT T/C PRESCALER Clear TIMER/COUNTER1 CLOCK SOURCE clkT1 TIMER/COUNTER1 CLOCK SOURCE clkT0 1. The synchronization logic on the input pins (Tn/T0) is shown in Figure 44. Bit 7 6 5 4 3 2 1 0 TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR * Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR310 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR310 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. * Bit 0 - PSR310: Prescaler Reset Timer/Counter3, Timer/Counter1, and Timer/Counter0 When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect all three timers. 105 2513L-AVR-03/2013 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: * True 16-bit Design (i.e., allows 16-bit PWM) * Two Independent Output Compare Units * Double Buffered Output Compare Registers * One Input Capture Unit * Input Capture Noise Canceler * Clear Timer on Compare Match (Auto Reload) * Glitch-free, Phase Correct Pulse Width Modulator (PWM) * Variable PWM Period * Frequency Generator * External Event Counter * Eight Independent Interrupt Sources (TOV1, OCF1A, OCF1B, ICF1, TOV3, OCF3A, OCF3B, and ICF3) Restriction in ATmega161 Compatibility Mode Note that in ATmega161 compatibility mode, only one 16-bits Timer/Counter is available (Timer/Counter1). Overview Most register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, and a lower case "x" replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46. For the actual placement of I/O pins, refer to "Pinout ATmega162" on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "16-bit Timer/Counter Register Description" on page 128. 106 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 46. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATABUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1. Refer to Figure 1 on page 2, Table 32 on page 72, and Table 38 on page 78 for Timer/Counter1 pin placement and description. The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16bit registers. These procedures are described in the section "Accessing 16-bit Registers" on page 109. The Timer/Counter Control Registers (TCCRnA/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR) and Extended Timer Interrupt Flag Register (ETIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK) and Extended Timer Interrupt Mask Register (ETIMSK). (E)TIFR and (E)TIMSK are not shown in the figure since these registers are shared by other Timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the Timer Clock (clkTn). The double buffered Output Compare Registers (OCRnA/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B). See "Output Compare Units" on page 114. The Compare Match event will also set the Compare Match Flag (OCFnA/B) which can be used to generate an output compare interrupt request. 107 2513L-AVR-03/2013 The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See "Analog Comparator" on page 195.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used as an alternative, freeing the OCRnA to be used as PWM output. Definitions The following definitions are used extensively throughout the section: Table 52. Definitions Compatibility BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: * All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. * Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. * Interrupt Vectors. The following control bits have changed name, but have same functionality and register location: * PWMn0 is changed to WGMn0. * PWMn1 is changed to WGMn1. * CTCn is changed to WGMn2. The following bits are added to the 16-bit Timer/Counter Control Registers: * FOCnA and FOCnB are added to TCCRnA. * WGMn3 is added to TCCRnB. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 108 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Accessing 16-bit Registers The TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same Temporary Register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCRnA/B 16bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnA/B and ICRn Registers. Note that when using "C", the compiler handles the 16-bit access. Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. 109 2513L-AVR-03/2013 The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B or ICRn Registers can be done by using the same principle. Assembly Code Example(1) TIM16_ReadTCNTn: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into i */ i = TCNTn; /* Restore Global Interrupt Flag */ SREG = sreg; return i; } Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The assembly code example returns the TCNTn value in the r17:r16 register pair. 110 ATmega162/V 2513L-AVR-03/2013 ATmega162/V The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B or ICRn Registers can be done by using the same principle. Assembly Code Example(1) TIM16_WriteTCNTn: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Set TCNTn to r17:r16 out TCNTnH,r17 out TCNTnL,r16 ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNTn( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn to i */ TCNTn = i; /* Restore Global Interrupt Flag */ SREG = sreg; } Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNTn. Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. 111 2513L-AVR-03/2013 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details on clock sources and prescaler, see "Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers" on page 104. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 47 shows a block diagram of the counter and its surroundings. Figure 47. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count Increment or decrement TCNTn by 1. Direction Select between increment and decrement. Clear Clear TCNTn (set all bits to zero). clkTn Timer/Counter clock. TOP Signalize that TCNTn has reached maximum value. BOTTOM Signalize that TCNTn has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNTn Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each Timer Clock (clk Tn). The clkTn can be generated from an external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the Timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 118. 112 ATmega162/V 2513L-AVR-03/2013 ATmega162/V The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 48. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small "n" in register and bit names indicates the Timer/Counter number. Figure 48. Input Capture Unit Block Diagram(1) DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO* Analog Comparator ACIC* TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) ICPn Note: 1. The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP - not Timer/Counter3. When a change of the logic level (an event) occurs on the Input Capture pin (ICPn), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn = 1), the Input Capture Flag generates an Input Capture interrupt. The ICFn Flag is automatically cleared when the interrupt is executed. Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter's TOP value. In these cases the Waveform Genera- 113 2513L-AVR-03/2013 tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 109. Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICPn). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the Tn pin (Figure 44 on page 104). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to define TOP. An Input Capture can be triggered by software by controlling the port of the ICPn pin. Noise Canceler The Noise Canceler improves noise immunity by using a simple digital filtering scheme. The Noise Canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The Noise Canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICRn Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICRn Register before the next event occurs, the ICRn will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). Output Compare Units 114 The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an output compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ- ATmega162/V 2513L-AVR-03/2013 ATmega162/V ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See "Modes of Operation" on page 118.) A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 49 shows a block diagram of the output compare unit. The small "n" in the register and bit names indicates the device number (n = n for Timer/Counter n), and the "x" indicates output compare unit (A/B). The elements of the block diagram that are not directly a part of the output compare unit are gray shaded. Figure 49. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be 115 2513L-AVR-03/2013 updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper eight bits of either the OCRnx buffer or OCRnx Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to "Accessing 16-bit Registers" on page 109. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing Compare Match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare Match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or toggled). Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNTn when using any of the output compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCnx value is to use the Force Output Compare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 116 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses the COMnx1:0 bits for defining the output compare (OCnx) state at the next Compare Match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 50 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a System Reset occur, the OCnx Register is reset to "0". Figure 50. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the output compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 53, Table 54 and Table 55 for details. The design of the output compare pin logic allows initialization of the OCnx state before the output is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See "16-bit Timer/Counter Register Description" on page 128. The COMnx1:0 bits have no effect on the Input Capture unit. 117 2513L-AVR-03/2013 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next Compare Match. For Compare Output actions in the non-PWM modes refer to Table 53 on page 128. For fast PWM mode refer to Table 54 on page 129, and for phase correct and phase and frequency correct PWM refer to Table 55 on page 129. A change of the COMnx1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a Compare Match (See "Compare Match Output Unit" on page 117.) For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 126. Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 51. The counter value (TCNTn) increases until a Compare Match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. 118 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 51. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is defined by the following equation: f clk_I/O f OCnA = --------------------------------------------------2 N 1 + OCRnA The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). For Timer/Counter3 also prescaler factors 16 and 32 are available. As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 119 2513L-AVR-03/2013 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is set on the Compare Match between TCNTn and OCRnx, and cleared at TOP. In inverting Compare Output mode output is cleared on Compare Match and set at TOP. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log TOP + 1 R FPWM = ----------------------------------log 2 In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 52. The figure shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Compare Match occurs. Figure 52. Fast PWM Mode, Timing Diagram OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the com- 120 ATmega162/V 2513L-AVR-03/2013 ATmega162/V pare registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the Compare Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table on page 129). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ----------------------------------N 1 + TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For Timer/Counter3 also prescaler factors 16 and 32 are available. The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COMnx1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnA to toggle its logical level on each Compare Match (COMnA1:0 = 1). This applies only if OCRnA is used to define the TOP value (WGMn3:0 = 15). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. 121 2513L-AVR-03/2013 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx while up-counting, and set on the Compare Match while down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log TOP + 1 R PCPWM = ----------------------------------log 2 In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 53. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Compare Match occurs. Figure 53. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer 122 ATmega162/V 2513L-AVR-03/2013 ATmega162/V value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 53 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table 55 on page 129). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at Compare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For Timer/Counter3 also prescaler factors 16 and 32 are available. The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 11) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx while up-counting, and set on the Compare Match while down-counting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 53 and Figure 54). 123 2513L-AVR-03/2013 The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log TOP + 1 R PFCPWM = ----------------------------------log 2 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 54. The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Compare Match occurs. Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a Compare Match will never occur between the TCNTn and the OCRnx. As Figure 54 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. 124 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table 55 on page 129). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at Compare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For Timer/Counter3 also prescaler factors 16 and 32 are available. The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. 125 2513L-AVR-03/2013 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 55 shows a timing diagram for the setting of OCFnx. Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 56 shows the same timing data, but with the prescaler enabled. Figure 56. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 57 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. 126 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 57. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 58 shows the same timing data, but with the prescaler enabled. Figure 58. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 127 2513L-AVR-03/2013 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A - TCCR1A Timer/Counter3 Control Register A - TCCR3A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COM3A1 COM3A0 COM3B1 COM3B0 FOC3A FOC3B WGM31 WGM30 Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A TCCR3A * Bit 7:6 - COMnA1:0: Compare Output Mode for channel A * Bit 5:4 - COMnB1:0: Compare Output Mode for channel B The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA or OCnB pin must be set in order to enable the output driver. When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 53 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). Table 53. Compare Output Mode, non-PWM 128 COMnA1/ COMnB1 COMnA0/ COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 Toggle OCnA/OCnB on Compare Match. 1 0 Clear OCnA/OCnB on Compare Match (Set output to low level). 1 1 Set OCnA/OCnB on Compare Match (Set output to high level). Description ATmega162/V 2513L-AVR-03/2013 ATmega162/V Table 54 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 54. Compare Output Mode, Fast PWM(1) COMnA1/ COMnB1 COMnA0/ COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation). For all other WGMn settings, normal port operation, OCnA/OCnB disconnected. 1 0 Clear OCnA/OCnB on Compare Match, set OCnA/OCnB at TOP. 1 1 Set OCnA/OCnB on Compare Match, clear OCnA/OCnB at TOP. Note: Description 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In this case the Compare Match is ignored, but the set or clear is done at TOP. See "Fast PWM Mode" on page 120. for more details. Table 55 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 55. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COMnA1/ COMnB1 COMnA0 COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 9 or 14: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation). For all other WGMn settings, normal port operation, OCnA/OCnB disconnected. 1 0 Clear OCnA/OCnB on Compare Match when up-counting. Set OCnA/OCnB on Compare Match when down-counting. 1 1 Set OCnA/OCnB on Compare Match when up-counting. Clear OCnA/OCnB on Compare Match when down-counting. Note: Description 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See "Phase Correct PWM Mode" on page 122. for more details. * Bit 3 - FOCnA: Force Output Compare for channel A * Bit 2 - FOCnB: Force Output Compare for channel B The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCRnA is written when operating in a PWM mode. When writing a logical one to the FOCnA/FOCnB bit, an immediate Compare Match is forced on the Waveform Generation unit. The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 129 2513L-AVR-03/2013 * Bit 1:0 - WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 56. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See "Modes of Operation" on page 118.) Table 56. Waveform Generation Mode Bit Description(1) Mode WGMn3 WGMn2 (CTCn) WGMn1 (PWMn1) WGMn0 (PWMn0) Timer/Counter Mode of Operation TOP Update of OCRnx at TOVn Flag Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCRnA Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICRn BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCRnA BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM 12 1 1 0 0 CTC ICRn Immediate MAX 13 1 1 0 1 Reserved - - - 14 1 1 1 0 Fast PWM ICRn TOP TOP 15 1 1 1 1 Fast PWM OCRnA TOP TOP Note: 130 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega162/V 2513L-AVR-03/2013 ATmega162/V Timer/Counter1 Control Register B - TCCR1B Timer/Counter3 Control Register B - TCCR3B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ICNC3 ICES3 - WGM33 WGM32 CS32 CS31 CS30 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B TCCR3B * Bit 7 - ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture noise canceler. When the noise canceler is activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. * Bit 6 - ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Capture function is disabled. * Bit 5 - Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. * Bit 4:3 - WGMn3:2: Waveform Generation Mode See TCCRnA Register description. 131 2513L-AVR-03/2013 * Bit 2:0 - CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 55 and Figure 56. Table 57. Clock Select Bit Description Timer/Counter1 CS12 CS11 CS10 Description 0 0 0 No clock source. (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.. Table 58. Clock Select Bit Description Timer/Counter3 132 Description CS32 CS31 CS30 0 0 0 No clock source. (Timer/Counter stopped). 0 0 1 clkI/O / 1 (No prescaling) 0 1 0 clkI/O / 8 (From prescaler). 0 1 1 clkI/O / 64 (From prescaler). 1 0 0 clkI/O / 256 (From prescaler). 1 0 1 clkI/O / 1024 (From prescaler). 1 1 0 clkI/O / 16 (From prescaler). 1 1 1 clkI/O / 32 (From prescaler). ATmega162/V 2513L-AVR-03/2013 ATmega162/V Timer/Counter1 - TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] Timer/Counter3 - TCNT3H and TCNT3L TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCNT3[15:8] TCNT3H TCNT3[7:0] TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 109. Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a Compare Match between TCNTn and one of the OCRnx Registers. Writing to the TCNTn Register blocks (removes) the Compare Match on the following timer clock for all compare units. Output Compare Register 1 A - OCR1AH and OCR1AL Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] Output Compare Register 1 B - OCR1BH and OCR1BL OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] Output Compare Register 3 A - OCR3AH and OCR3AL OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR3A[15:8] OCR3AH OCR3A[7:0] Output Compare Register 3 B - OCR3BH and OCR3BL OCR3AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR3B[15:8] OCR3BH OCR3B[7:0] OCR3BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 133 2513L-AVR-03/2013 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OCnx pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16bit registers. See "Accessing 16-bit Registers" on page 109. Input Capture Register 1 - ICR1H and ICR1L Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] Input Capture Register 3 - ICR3H and ICR3L ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ICR3[15:8] ICR3H ICR3[7:0] ICR3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers" on page 109. Timer/Counter Interrupt Mask Register - TIMSK(1) Bit 7 6 5 4 3 2 1 0 TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIMSK 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective Timer sections. * Bit 7 - TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 57.) is executed when the TOV1 Flag, located in TIFR, is set. * Bit 6 - OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 57.) is executed when the OCF1A Flag, located in TIFR, is set. * Bit 5 - OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding 134 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Interrupt Vector (See "Interrupts" on page 57.) is executed when the OCF1B Flag, located in TIFR, is set. * Bit 3 - TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 57.) is executed when the ICF1 Flag, located in TIFR, is set. Extended Timer/Counter Interrupt Mask Register - ETIMSK(1) Bit 7 6 5 4 3 2 1 TICIE3 OCIE3A OCIE3B TOIE3 - 0 - Read/Write R R R/W R/W R/W R/W R R Initial Value 0 0 0 0 0 0 0 0 Note: ETIMSK 1. This register contains interrupt control bits for several Timer/Counters, but only Timer3 bits are described in this section. The remaining bits are described in their respective Timer sections. * Bit 5 - TICIE3: Timer/Counter3, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 57.) is executed when the ICF3 Flag, located in TIFR, is set. * Bit 4 - OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 57.) is executed when the OCF3A Flag, located in TIFR, is set. * Bit 3 - OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 57.) is executed when the OCF3B Flag, located in TIFR, is set. * Bit 2 - TOIE3: Timer/Counter3, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter3 overflow interrupt is enabled. The corresponding Interrupt Vector (See "Interrupts" on page 57.) is executed when the TOV3 Flag, located in TIFR, is set. Timer/Counter Interrupt Flag Register - TIFR(1) Bit 7 6 5 4 3 2 1 0 TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIFR 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective Timer sections. * Bit 7 - TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Table 56 on page 130 for the TOV1 Flag behavior when using another WGMn3:0 bit setting. 135 2513L-AVR-03/2013 TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. * Bit 6 - OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. * Bit 5 - OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. * Bit 3 - ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. 136 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Extended Timer/Counter Interrupt Flag Register - ETIFR(1) Bit 7 6 5 4 3 2 1 ICF3 OCF3A OC3FB TOV3 - 0 - Read/Write R R R/W R/W R/W R/W R R Initial Value 0 0 0 0 0 0 0 0 Note: ETIFR 1. This register contains flag bits for several Timer/Counters, but only Timer3 bits are described in this section. The remaining bits are described in their respective Timer sections. * Bit 5 - ICF3: Timer/Counter3, Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is set by the WGMn3:0 to be used as the TOP value, the ICF3 Flag is set when the counter reaches the TOP value. ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing a logic one to its bit location. * Bit 4 - OCF3A: Timer/Counter3, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register A (OCR3A). Note that a Forced Output Compare (FOC3A) strobe will not set the OCF3A Flag. OCF3A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF3A can be cleared by writing a logic one to its bit location. * Bit 3 - OCF3B: Timer/Counter3, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register B (OCR3B). Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B Flag. OCF3B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF3B can be cleared by writing a logic one to its bit location. * Bit 2 - TOV3: Timer/Counter3, Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTC modes, the TOV3 Flag is set when the timer overflows. Refer to Table 56 on page 130 for the TOV3 Flag behavior when using another WGMn3:0 bit setting. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location. 137 2513L-AVR-03/2013 8-bit Timer/Counter2 with PWM and Asynchronous operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: * Single Channel Counter * Clear Timer on Compare Match (Auto Reload) * Glitch-free, Phase Correct Pulse Width Modulator (PWM) * Frequency Generator * 10-bit Clock Prescaler * Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) * Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 59. For the actual placement of I/O pins, refer to "Pinout ATmega162" on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "8-bit Timer/Counter Register Description" on page 149. Figure 59. 8-bit Timer/Counter Block Diagram TCCRn count TOVn (Int.Req.) clear Control Logic direction clkTn TOSC1 BOTTOM TOP Prescaler T/C Oscillator TOSC2 Timer/Counter TCNTn =0 = 0xFF OCn (Int.Req.) Waveform Generation = clkI/O OCn DATABUS OCRn Synchronized Status flags clkI/O Synchronization Unit clkASY Status flags ASSRn asynchronous mode select (ASn) Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by 138 ATmega162/V 2513L-AVR-03/2013 ATmega162/V the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the Timer Clock (clkT2). The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC2). See "Output Compare Unit" on page 140. for details. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an output compare interrupt request. Definitions Many register and bit references in this document are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used i.e., TCNT2 for accessing Timer/Counter2 counter value and so on. The definitions in Table 59 are also used extensively throughout the section. Table 59. Definitions Timer/Counter Clock Sources BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation. The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see "Asynchronous Status Register - ASSR" on page 152. For details on clock sources and prescaler, see "Timer/Counter Prescaler" on page 156. 139 2513L-AVR-03/2013 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 60 shows a block diagram of the counter and its surrounding environment. Figure 60. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC2. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 143. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an output compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ("Modes of Operation" on page 143). Figure 61 shows a block diagram of the output compare unit. 140 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 61. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom Waveform Generator OCxy FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled). Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be missed, resulting in incorrect Waveform Generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is down-counting. 141 2513L-AVR-03/2013 The Setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 62 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. Figure 62. Compare Match Output Unit, Schematic COMn1 COMn0 FOCn Waveform Generator D Q 1 OCn DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See "8-bit Timer/Counter Register Description" on page 149. 142 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the Waveform Generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the nonPWM modes refer to Table 61 on page 150. For fast PWM mode, refer to Table 62 on page 150, and for phase correct PWM refer to Table 63 on page 150. A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See "Compare Match Output Unit" on page 142.). For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 147. Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 143 2513L-AVR-03/2013 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 63. The counter value (TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. Figure 63. CTC Mode, Timing Diagram OCn Interrupt Flag Set TCNTn OCn (Toggle) Period (COMn1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCn = ----------------------------------------------2 N 1 + OCRn The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 144 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 1) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 64. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 64. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to three (See Table 62 on page 150). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnPWM = -----------------N 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). 145 2513L-AVR-03/2013 The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 3) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while up-counting, and set on the Compare Match while downcounting. In inverting output compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 65. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 65. Phase Correct PWM Mode, Timing Diagram OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to three (See Table 63 on page 150). The 146 ATmega162/V 2513L-AVR-03/2013 ATmega162/V actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = -----------------N 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 65 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without a Compare Match. Timer/Counter Timing Diagrams * OCR2 changes its value from MAX, like in Figure 65. When the OCR2 value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match. * The timer starts counting from a value higher than the one in OCR2, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 66 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 66. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 67 shows the same timing data, but with the prescaler enabled. 147 2513L-AVR-03/2013 Figure 67. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 68 shows the setting of OCF2 in all modes except CTC mode. Figure 68. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 69 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 69. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRn TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFn 148 ATmega162/V 2513L-AVR-03/2013 ATmega162/V 8-bit Timer/Counter Register Description Timer/Counter Control Register - TCCR2 Bit 7 6 5 4 3 2 1 0 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2 * Bit 7 - FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. * Bit 6, 3 - WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 60 and "Modes of Operation" on page 143. Table 60. Waveform Generation Mode Bit Description(1) Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation TOP Update of OCR2 at TOV2 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF TOP MAX Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. 149 2513L-AVR-03/2013 * Bit 5:4 - COM21:0: Compare Match Output Mode These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 61 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 61. Compare Output Mode, non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Toggle OC2 on Compare Match. 1 0 Clear OC2 on Compare Match. 1 1 Set OC2 on Compare Match. Table 62 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 62. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match, set OC2 at TOP. 1 1 Set OC2 on Compare Match, clear OC2 at TOP. Note: Description 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Fast PWM Mode" on page 145 for more details. Table 63 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 63. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when down-counting. 1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when down-counting. Note: 150 Description 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 146 for more details. ATmega162/V 2513L-AVR-03/2013 ATmega162/V * Bit 2:0 - CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 64. Table 64. Clock Select Bit Description Timer/Counter Register - TCNT2 Description CS22 CS21 CS20 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkT2S/(No prescaling) 0 1 0 clkT2S/8 (From prescaler) 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) Bit 7 6 5 4 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register. Output Compare Register - OCR2 Bit 7 6 5 4 3 2 1 0 OCR2[7:0] OCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. 151 2513L-AVR-03/2013 Asynchronous operation of the Timer/Counter Asynchronous Status Register - ASSR Bit 7 6 5 4 3 2 1 0 - - - - AS2 TCN2UB OCR2UB TCR2UB Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR * Bit 3 - AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted. * Bit 2 - TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. * Bit 1 - OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set. When OCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value. * Bit 0 - TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set. When TCCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 Registers while its update Busy Flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read. 152 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. * Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2, and TCCR2. 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. * The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. * When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g., writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register - ASSR has been implemented. * When entering Power-save or Extended Standby mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up. * If Timer/Counter2 is used to wake the device up from Power-save or Extended Standby mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and reentering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Powersave or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2, TCNT2, or OCR2. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or Extended Standby mode. * When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon startup, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. * Description of wake up from Power-save or Extended Standby mode when the Timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the Timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for 153 2513L-AVR-03/2013 four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. * Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Powersave mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2 or TCCR2. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. * Timer/Counter Interrupt Mask Register - TIMSK During asynchronous operation, the synchronization of the Interrupt Flags for the Asynchronous Timer takes three processor cycles plus one timer cycle. The Timer is therefore advanced by at least one before the processor can read the Timer value causing the setting of the Interrupt Flag. The output compare pin is changed on the Timer clock and is not synchronized to the processor clock. Bit 7 6 5 4 3 2 1 0 TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK * Bit 4 - OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. * Bit 2 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. 154 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Timer/Counter Interrupt Flag Register - TIFR Bit 7 6 5 4 3 2 1 0 TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR * Bit 4 - OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed. * Bit 2 - TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 155 2513L-AVR-03/2013 Figure 70. Prescaler for Timer/Counter2 clkT2S PSR2 clkT2S/1024 clkT2S/256 clkT2S/8 AS2 clkT2S/128 10-BIT T/C PRESCALER Clear TOSC1 clkT2S/64 clkI/O clkT2S/32 Timer/Counter Prescaler 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port D. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter2, the possible prescaled selections are: clk T2S /8, clk T2S /32, clk T2S /64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. Special Function IO Register - SFIOR Bit 7 6 5 4 3 2 1 0 TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR * Bit 1 - PSR2: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the "Bit 7 - TSM: Timer/Counter Synchronization Mode" on page 105 for a description of the Timer/Counter Synchronization mode. 156 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega162 and peripheral devices or between several AVR devices. The ATmega162 SPI includes the following features: * Full-duplex, Three-wire Synchronous Data Transfer * Master or Slave Operation * LSB First or MSB First Data Transfer * Seven Programmable Bit Rates * End of Transmission Interrupt Flag * Write Collision Flag Protection * Wake-up from Idle Mode * Double Speed (CK/2) Master SPI Mode Figure 71. SPI Block Diagram(1) SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: 1. Refer to Figure 1 on page 2, and Table 32 on page 72 for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in Figure 72. The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a 157 2513L-AVR-03/2013 byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the End of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the buffer register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the End of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 72. SPI Master-slave Interconnection MSB MASTER LSB MISO MISO 8-BIT SHIFT REGISTER MSB SLAVE LSB 8-BIT SHIFT REGISTER MOSI MOSI SHIFT ENABLE SPI CLOCK GENERATOR SCK SS VCC SCK SS The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low periods: Longer than 2 CPU clock cycles. High periods: Longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 65. For more details on automatic port overrides, refer to "Alternate Port Functions" on page 68. Table 65. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 158 1. See "Alternate Functions Of Port B" on page 72 for a detailed description of how to define the direction of the user defined SPI pins. ATmega162/V 2513L-AVR-03/2013 ATmega162/V The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO, and DD_SCK must be replaced by the actual data direction bits for these pins. E.g., if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 159 2513L-AVR-03/2013 Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. The example code assumes that the part specific header file is included. 177 2513L-AVR-03/2013 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates. Receiver Error Flags The USART Receiver has three Error Flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (UPE). All can be accessed by reading UCSRA. Common for the Error Flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the Error Flags can generate interrupts. The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC since the receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. The Data OverRun (DOR) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If parity check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see "Parity Bit Calculation" on page 171 and "Parity Checker" on page 179. 178 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPE) Flag can then be read by software to check if the frame had a Parity Error. The UPE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the receiver will no longer override the normal function of the RxD port pin. The receiver buffer FIFO will be flushed when the receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared. The following code example shows how to flush the receive buffer. Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz SPI Serial Programming Algorithm When writing serial data to the ATmega162, data is clocked on the rising edge of SCK. When reading data from the ATmega162, data is clocked on the falling edge of SCK. See Figure 106. To program and verify the ATmega162 in the SPI Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 110): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". 2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming Enable serial instruction to pin MOSI. 3. The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The page size is found in Table 105 on page 236. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 109.) Accessing the SPI serial programming interface before the Flash write operation completes can result in incorrect programming. 5. The EEPROM array can either be programmed one page at a time or it can be programmed byte by byte. For Page Programming, the following algorithm is used: The EEPROM memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next page. (See Table 99.) Accessing the SPI Serial Programming interface before the EEPROM write operation completes can result in incorrect programming. Alternatively, the EEPROM can be programmed bytewise: The EEPROM array is programmed one byte at a time by supplying the address and data together with the Write EEPROM instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 109.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 246 ATmega162/V 2513L-AVR-03/2013 ATmega162/V 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. Table 109. Minimum Wait Delay before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms Figure 106. SPI Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 247 2513L-AVR-03/2013 Table 110. SPI Serial Programming Instruction Set(1) Instruction Programming Enable Chip Erase Instruction Format Operation Byte 1 Byte 2 Byte 3 Byte4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming after RESET goes low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0010 H000 00aa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b. 0100 H000 00xx xxxx xxbb bbbb iiii iiii Write H (high or low) data i to Program Memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address. 0100 1100 00aa aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at address a:b. 1010 0000 00xx xxaa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a:b. 1100 0000 00xx xxaa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b. 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page. 1100 0010 00xx xxaa bbbb bb00 xxxx xxxx Write EEPROM page at address a:b. 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. "0" = programmed, "1" = unprogrammed. See Table 96 on page 231 for details. 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = "0" to program Lock bits. See Table 96 on page 231 for details. 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = "0" to program, "1" to unprogram. See Table 100 on page 233 for details. 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = "0" to program, "1" to unprogram. See Table 99 on page 233 for details. 1010 1100 1010 0100 xxxx xxxx xxxx xxii Set bits = "0" to program, "1" to unprogram. See Table 98 on page 232 for details. 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. "0" = programmed, "1" = unprogrammed. See Table 100 on page 233 for details. Read Program Memory Load Program Memory Page Write Program Memory Page Read EEPROM Memory Write EEPROM Memory (byte access) Load EEPROM Memory Page (page access) Write EEPROM Memory Page (page access) Read Lock Bits Write Lock Bits Read Signature Byte Write Fuse Bits Write Fuse High Bits Write Extended Fuse Bits Read Fuse Bits 248 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Table 110. SPI Serial Programming Instruction Set(1) (Continued) Instruction Instruction Format Operation Byte 1 Byte 2 Byte 3 Byte4 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. "0" = programmed, "1" = unprogrammed. See Table 99 on page 233 for details. 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. "0" = pro-grammed, "1" = unprogrammed. See Table 98 on page 232 for details. 0011 1000 00xx xxxx 0000 0000 oooo oooo Read Calibration Byte 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = "1", a programming operation is still busy. Wait until this bit returns to "0" before applying another command. Read Fuse High Bits Read Extended Fuse Bits Read Calibration Byte Poll RDY/BSY Note: 1. a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care SPI Serial Programming Characteristics For characteristics of the SPI module, see "SPI Timing Characteristics" on page 268. 249 2513L-AVR-03/2013 Programming via Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, the JTAG Interface TMS, TDI, and TDO. Control of the Reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in running mode while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose. As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers. Programming Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for Programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 107. 250 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 107. State machine sequence for changing the instruction word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 1 Exit1-IR 0 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 251 2513L-AVR-03/2013 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as data register. Note that the reset will be active as long as there is a logic "one" in the Reset Chain. The output from this chain is not latched. The active states are: * PROG_ENABLE (0x4) PROG_COMMANDS (0x5) PROG_PAGELOAD (0x6) Shift-DR: The Reset Register is shifted by the TCK input. The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16bit Programming Enable Register is selected as data register. The active states are the following: * Shift-DR: The programming enable signature is shifted into the Data Register. * Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid. The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as data register. The active states are the following: * Capture-DR: The result of the previous command is loaded into the Data Register. * Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command. * Update-DR: The programming command is applied to the Flash inputs. * Run-Test/Idle: One clock cycle is generated, executing the applied command (not always required, see Table 111 below). The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. The 1024 bit Virtual Flash Page Load Register is selected as register. This is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the Shift Register. The data are automatically transferred to the Flash page buffer byte-by-byte in the Shift-DR state by an internal state machine. This is the only active state: * Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically loaded into the Flash page one byte at a time. Note: PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port. The 1032 bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer data to the Shift Register. The data are automatically transferred from the Flash page buffer byte-by-byte in the Shift-DR state by an internal state machine. This is the only active state: * Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the TCK input. The TDI input is ignored. Note: 252 The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used. The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used. ATmega162/V 2513L-AVR-03/2013 ATmega162/V Data Registers Reset Register The Data Registers are selected by the JTAG Instruction Registers described in section "Programming Specific JTAG Instructions" on page 250. The Data Registers relevant for programming operations are: * Reset Register * Programming Enable Register. * Programming Command Register. * Virtual Flash Page Load Register. * Virtual Flash Page Read Register. The Reset Register is a test data register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the fuse settings for the clock options, the part will remain reset for a Reset Time-out period (refer to "Clock Sources" on page 36) after releasing the Reset Register. The output from this data register is not latched, so the reset will take place immediately, as shown in Figure 86 on page 206. Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 108. Programming Enable Register TDI D A T A 0xA370 = D Q Programming Enable ClockDR & PROG_ENABLE TDO 253 2513L-AVR-03/2013 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 111. The state sequence when shifting in the programming commands is illustrated in Figure 110. Figure 109. Programming Command Register TDI S T R O B E S A D D R E S S / D A T A Flash EEPROM Fuses Lock Bits TDO 254 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Table 111. JTAG Programming Instruction Set Instruction TDI sequence TDO sequence Notes 1a. Chip eRase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx 2f. Latch Data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2g. Write Flash Page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. Poll for Page Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3d. Read Data Low and High Byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 4e. Latch Data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. Write EEPROM Page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4g. Poll for Page Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx (2) (9) (9) low byte high byte (9) (9) 255 2513L-AVR-03/2013 Table 111. JTAG Programming Instruction Set (Continued) Instruction TDI sequence TDO sequence 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. Write Fuse Extended Byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. Write Fuse High byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. Write Fuse Low Byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. Poll for Fuse Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. Load Data Byte(9) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4) 7c. Write Lock Bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. Read Fuse Extended Byte 0111010_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8c. Read Fuse High Byte(7) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8d. Read Fuse Low Byte(8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo 6a. Enter Fuse Write 6b. Load Data Low Byte 6e. Load Data Low Byte 6h. Load Data Low Byte (6) (7) (8) (6) 256 Notes (5) ATmega162/V 2513L-AVR-03/2013 ATmega162/V Table 111. JTAG Programming Instruction Set (Continued) Instruction TDI sequence TDO sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse ext. byte Fuse high byte Fuse low byte Lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c. Read Signature Byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 11a. Load No Operation Command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = "1". 3. Set bits to "0" to program the corresponding Fuse, "1" to unprogram the Fuse. 4. Set bits to "0" to program the corresponding lock bit, "1" to leave the Lock bit unchanged. 5. "0" = programmed, "1" = unprogrammed. 6. The bit mapping for Fuses Extended byte is listed in Table 98 on page 232. 7. The bit mapping for Fuses High byte is listed in Table 99 on page 233. 8. The bit mapping for Fuses Low byte is listed in Table 100 on page 233. 9. The bit mapping for Lock Bits byte is listed in Table 96 on page 231. 10. Address bits exceeding PCMSB and EEAMSB (Table 105 and Table 106) are don't care Note: a = address high bits b = address low bits H = 0 - Low byte, 1 - High Byte o = data out i = data in x = don't care 257 2513L-AVR-03/2013 Figure 110. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 258 0 Pause-IR 1 Virtual Flash Page Load Register 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically transferred to the Flash page buffer byte-by-byte. Shift in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to load the entire Flash page buffer before executing Page Write. ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 111. Virtual Flash Page Load Register STROBES State Machine ADDRESS TDI Flash EEPROM Fuses Lock Bits D A T A TDO Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte-by-byte. The first eight cycles are used to transfer the first byte to the internal Shift Register, and the bits that are shifted out during these right cycles should be ignored. Following this initialization, data are shifted out starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to read one full Flash page to verify programming. 259 2513L-AVR-03/2013 Figure 112. Virtual Flash Page Read Register STROBES State Machine ADDRESS TDI Flash EEPROM Fuses Lock Bits D A T A TDO Programming Algorithm All references below of type "1a", "1b", and so on, refer to Table 111. Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift one in the Reset Register. Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the Programming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 107 on page 244). Programming the Flash Before programming the Flash a Chip Erase must be performed. See "Performing Chip Erase" on page 260. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address high byte using programming instruction 2b. 4. Load address low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 260 ATmega162/V 2513L-AVR-03/2013 ATmega162/V 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH_FLASH (refer to Table 107 on page 244). 9. Repeat steps 3 to 7 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 105 on page 236) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH_FLASH (refer to Table 107 on page 244). 9. Repeat steps 3 to 8 until all data have been programmed. Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 105 on page 236) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Remember that the first 8 bits shifted out should be ignored. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 261 2513L-AVR-03/2013 Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed. See "Performing Chip Erase" on page 260. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address high byte using programming instruction 4b. 4. Load address low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table 107 on page 244). 9. Repeat steps 3 to 8 until all data have been programmed. Note: Reading the EEPROM The PROG_PAGELOAD instruction can not be used when programming the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note: Programming the Fuses The PROG_PAGEREAD instruction can not be used when reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data low byte using programming instructions 6b. A bit value of "0" will program the corresponding Fuse, a "1" will unprogram the Fuse. 4. Write Fuse extended byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 107 on page 244). 6. Load data low byte using programming instructions 6e. A bit value of "0" will program the corresponding Fuse, a "1" will unprogram the Fuse. 7. Write Fuse High byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 107 on page 244). 9. Load data low byte using programming instructions 6h. A "0" will program the Fuse, a "1" will unprogram the Fuse. 10. Write Fuse Low byte using programming instruction 6i. 11. Poll for Fuse write complete using programming instruction 6j, or wait for tWLRH (refer to Table 107 on page 244). Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of "0" will program the corresponding Lock bit, a "1" will leave the Lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 107 on page 244). 262 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8f. To only read Fuse Extended byte, use programming instruction 8b. To only read Fuse High byte, use programming instruction 8c. To only read Fuse Low byte, use programming instruction 8d. To only read Lock bits, use programming instruction 8e. Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address 0x00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address 0x00 using programming instruction 10b. 4. Read the calibration byte using programming instruction 10c. 263 2513L-AVR-03/2013 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins...................... 200.0 mA PDIP, 400 mA TQFP/MLF DC Characteristics TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Units (1) VIL Input Low Voltage, Except XTAL1 and RESETpin VCC = 1.8 - 2.4V VCC = 2.4 - 5.5V -0.5 -0.5 0.2 VCC 0.3 VCC(1) V VIH Input High Voltage, Except XTAL1 and RESET pin VCC = 1.8 - 2.4V VCC = 2.4 - 5.5V 0.7 VCC(2) 0.6 VCC(2) VCC + 0.5 VCC + 0.5 V VIL1 Input Low Voltage, XTAL1 pin VCC = 1.8 - 5.5V -0.5 0.1 VCC(1) V (2) VIH1 Input High Voltage, XTAL1 pin VCC = 1.8 - 2.4V VCC = 2.4 - 5.5V 0.8 VCC 0.7 VCC(2) VCC + 0.5 VCC + 0.5 V VIL2 Input Low Voltage, RESET pin VCC = 1.8 - 5.5V -0.5 0.2 VCC V VIH2 Input High Voltage, RESET pin VCC = 1.8 - 5.5V 0.9 VCC(2) VCC + 0.5 V 0.7 0.5 V V (3) VOL Output Low Voltage , Ports A, B, C, D, and E IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V VOH Output High Voltage(4), Ports A, B, C, D, and E IOL = -20 mA, VCC = 5V IOL = -10 mA, VCC = 3V IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) 1 A IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) 1 A RRST Reset Pull-up Resistor 30 60 k Rpu I/O Pin Pull-up Resistor 20 50 k 264 4.2 2.3 V V ATmega162/V 2513L-AVR-03/2013 ATmega162/V TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Active 1 MHz, VCC = 2V (ATmega162V) 0.8 mA Active 4 MHz, VCC = 3V (ATmega162/V) 5 mA Active 8 MHz, VCC = 5V (ATmega162) 16 mA Idle 1 MHz, VCC = 2V (ATmega162V) 0.3 mA Idle 4 MHz, VCC = 3V (ATmega162/V) 2 mA Idle 8 MHz, VCC = 5V (ATmega162) 8 mA Power Supply Current ICC Power-down mode WDT Enabled, VCC = 3.0V < 10 14 A WDT Disabled, VCC = 3.0V < 1.5 2 A < 10 40 mV 50 nA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: -50 750 500 ns 1. "Max" means the highest value where the pin is guaranteed to be read as low 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP Package: 1] The sum of all IOL, for all ports, should not exceed 200 mA. 2] The sum of all IOL, for port B0 - B7, D0 - D7, and XTAL2, should not exceed 100 mA. 3] The sum of all IOL, for ports A0 - A7, E0 - E2, C0 - C7, should not exceed 100 mA. TQFP and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 200 mA. 3] The sum of all IOL, for ports C0 - C7 and E1 - E2, should not exceed 200 mA. 4] The sum of all IOL, for ports A0 - A7 and E0, should not exceed 200 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP Package: 1] The sum of all IOH, for all ports, should not exceed 200 mA. 2] The sum of all IOH, for port B0 - B7, D0 - D7, and XTAL2, should not exceed 100 mA. 3] The sum of all IOH, for ports A0 - A7, E0 - E2, C0 - C7, should not exceed 100 mA. TQFP and MLF Package: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 200 mA. 3] The sum of all IOH, for ports C0 - C7 and E1 - E2, should not exceed 200 mA. 4] The sum of all IOH, for ports A0 - A7 and E0, should not exceed 200 mA. 265 2513L-AVR-03/2013 If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Figure 113. Absolute Maximum Frequency as a function of VCC, ATmega162V Frequency 16 MHz 8 MHz Safe Operating Area 1 MHz VCC 1.8V 2.4V 2.7V 4.5V 5.5V Figure 114. Absolute Maximum Frequency as a function of VCC, ATmega162 Frequency 16 MHz 8 MHz Safe Operating Area 1 MHz VCC 1.8V 266 2.4V 2.7V 4.5V 5.5V ATmega162/V 2513L-AVR-03/2013 ATmega162/V External Clock Drive Waveforms Figure 115. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 112. External Clock Drive VCC = 1.8 - 5.5V VCC =2.7 - 5.5V VCC = 4.5 - 5.5V Symbol Parameter Min. Max. Min. Max. Min. Max. Units 1/tCLCL Oscillator Frequency 0 1 0 8 0 16 MHz tCLCL Clock Period 1000 125 62.5 ns tCHCX High Time 400 50 25 ns tCLCX Low Time 400 50 25 ns tCLCH Rise Time 2.0 1.6 0.5 s tCHCL Fall Time 2.0 1.6 0.5 s 2 2 2 % tCLCL Change in period from one clock cycle to the next 267 2513L-AVR-03/2013 SPI Timing Characteristics See Figure 116 and Figure 117 for details. Table 113. SPI Timing Parameters Description Mode 1 SCK period Master See Table 68 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 * tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 * tck Slave 2 * tck (1) 11 SCK high/low Min 12 Rise/Fall time Slave 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 16 SCK to SS high Slave 17 SS high to tri-state Slave 18 SS low to SCK Slave Note: Typ Max ns 1.6 s 15 ns 20 10 2 * tck 1. In SPI Programming mode, the minimum SCK high/low period is: - 2 tCLCL for fCK < 12 MHz - 3 tCLCL for fCK > 12 MHz. Figure 116. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) 268 MSB ... LSB ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 117. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 17 15 MISO (Data Output) MSB ... LSB X 269 2513L-AVR-03/2013 External Data Memory Timing Table 114. External Data Memory Characteristics, 4.5 - 5.5 Volts, no Wait-state 8 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 1 tLHLL ALE Pulse Width 115 1.0tCLCL-10 ns 2 tAVLL Address Valid A to ALE Low 57.5 0.5tCLCL-5(1) ns 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 ns ns (1) 4 tAVLLC Address Valid C to ALE Low 57.5 0.5tCLCL-5 ns 5 tAVRL Address Valid to RD Low 115 1.0tCLCL-10 ns 6 tAVWL Address Valid to WR Low 115 1.0tCLCL-10 ns 7 tLLWL ALE Low to WR Low 47.5 8 tLLRL ALE Low to RD Low 9 tDVRH Data Setup to RD High 10 tRLDV Read Low to Data Valid 11 tRHDX Data Hold After RD High 12 tRLRH RD Pulse Width 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns 67.5 (2) (2) ns 40 0.5tCLCL-15 0.5tCLCL+5 40 ns 75 1.0tCLCL-50 0 0 115 1.0tCLCL-10 ns ns 13 tDVWL Data Setup to WR Low 42.5 14 tWHDX Data Hold After WR High 115 1.0tCLCL-10 ns 15 tDVWH Data Valid to WR High 125 1.0tCLCL ns 16 tWLWH WR Pulse Width 115 1.0tCLCL-10 ns Notes: 0.5tCLCL-20 ns (1) ns 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. Table 115. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state 8 MHz Oscillator Symbol Parameter 0 1/tCLCL Oscillator Frequency 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 240 2.0tCLCL-10 ns 15 tDVWH Data Valid to WR High 240 2.0tCLCL ns 16 tWLWH WR Pulse Width 240 2.0tCLCL-10 ns 270 Min Max Variable Oscillator Min Max Unit 0.0 16 MHz 200 2.0tCLCL-50 ns ATmega162/V 2513L-AVR-03/2013 ATmega162/V Table 116. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns 15 tDVWH Data Valid to WR High 375 3.0tCLCL ns 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns 325 3.0tCLCL-50 ns Table 117. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns 14 tWHDX Data Hold After WR High 240 2.0tCLCL-10 ns 15 tDVWH Data Valid to WR High 375 3.0tCLCL ns 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns 325 3.0tCLCL-50 ns Table 118. External Data Memory Characteristics, 2.7 - 5.5 Volts, no Wait-state 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 8 MHz 1 tLHLL ALE Pulse Width 235 tCLCL-15 ns 2 tAVLL Address Valid A to ALE Low 115 0.5tCLCL-10(1) ns 3a tLLAX_ST Address Hold After ALE Low, write access 5 5 3b tLLAX_LD Address Hold after ALE Low, read access 5 5 ns (1) 4 tAVLLC Address Valid C to ALE Low 115 5 tAVRL Address Valid to RD Low 235 1.0tCLCL-15 6 tAVWL Address Valid to WR Low 235 1.0tCLCL-15 7 tLLWL ALE Low to WR Low 115 8 tLLRL ALE Low to RD Low 115 9 tDVRH Data Setup to RD High 45 10 tRLDV Read Low to Data Valid 11 tRHDX Data Hold After RD High 0.5tCLCL-10 ns 130 130 0.5tCLCL-10 (2) 0.5tCLCL-10 (2) ns ns 0.5tCLCL+5 (2) ns 0.5tCLCL+5 (2) ns 45 190 0 ns ns 1.0tCLCL-60 0 ns ns 271 2513L-AVR-03/2013 Table 118. External Data Memory Characteristics, 2.7 - 5.5 Volts, no Wait-state (Continued) 4 MHz Oscillator 12 Symbol Parameter Min tRLRH RD Pulse Width 235 Max Variable Oscillator Min Max 1.0tCLCL-15 Unit ns (1) 13 tDVWL Data Setup to WR Low 105 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 ns 15 tDVWH Data Valid to WR High 250 1.0tCLCL ns 0.5tCLCL-20 ns WR Pulse Width 235 1.0tCLCL-15 16 tWLWH Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. ns Table 119. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 8 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 485 2.0tCLCL-15 ns 15 tDVWH Data Valid to WR High 500 2.0tCLCL ns 16 tWLWH WR Pulse Width 485 2.0tCLCL-15 ns 440 2.0tCLCL-60 ns Table 120. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 8 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns 15 tDVWH Data Valid to WR High 750 3.0tCLCL ns 16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns 690 3.0tCLCL-60 ns Table 121. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 4 MHz Oscillator Symbol Parameter 0 1/tCLCL Oscillator Frequency 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns 14 tWHDX Data Hold After WR High 485 2.0tCLCL-15 ns 15 tDVWH Data Valid to WR High 750 3.0tCLCL ns 16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns 272 Min Max Variable Oscillator Min Max Unit 0.0 8 MHz 690 3.0tCLCL-60 ns ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 118. External Memory Timing (SRWn1 = 0, SRWn0 = 0 T1 T2 T3 T4 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Data 5 Read Address 11 10 8 12 RD Figure 119. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 DA7:0 Prev. data 3a Address 13 Data XX 14 16 6 Write 2 WR 9 3b Address 11 Data 5 Read DA7:0 (XMBK = 0) 10 8 12 RD 273 2513L-AVR-03/2013 Figure 120. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T5 T4 T6 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Address 11 5 Read Data 10 8 12 RD Figure 121. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T6 T5 T7 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev. data 13 3a Address XX Data 14 16 6 Write 2 WR 9 3b Address 11 Data 5 Read DA7:0 (XMBK = 0) 10 8 12 RD Note: 274 1. The ALE pulse in the last period (T4 - T7) is only present if the next instruction accesses the RAM (internal or external). ATmega162/V 2513L-AVR-03/2013 ATmega162/V ATmega162 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The CKSEL Fuses are programmed to select external clock. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: Operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Active Supply Current Figure 122. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 3 5.5V 2.5 5.0V ICC (mA) 2 4.5V 4.0V 1.5 3.3V 1 2.7V 1.8V 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 275 2513L-AVR-03/2013 Figure 123. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1- 20 MHz ICC (mA) 45 40 5.5V 35 5.0V 30 4.5V 25 4.0V 20 15 3.3V 10 2.7V 5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 124. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. V CC INTERNAL RC OSCILLATOR, 8 MHz 20 18 85C 25C -40C 16 14 ICC (mA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 276 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 125. Active Supply Current vs. VCC (32 kHz External Oscillator) ACTIVE SUPPLY CURRENT vs. V CC 32kHz EXTERNAL OSCILLATOR 300 250 25C 85C ICC (uA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 126. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 1.2 5.5V 1 5.0V ICC (mA) 0.8 4.5V 0.6 4.0V 3.3V 0.4 2.7V 0.2 1.8V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 277 2513L-AVR-03/2013 Figure 127. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 25 5.5V 20 5.0V 15 ICC (mA) 4.5V 10 4.0V 3.3V 5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 128. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 9 85C 25C -40C 8 7 ICC (mA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 278 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 129. Idle Supply Current vs. VCC (32 kHz External Oscillator) IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 70 60 85C 25C ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 130. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 3 85C 2.5 ICC (uA) 2 1.5 1 -40C 25C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 279 2513L-AVR-03/2013 Figure 131. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. V CC WATCHDOG TIMER ENABLED 25 85C 20 25C -40C ICC (uA) 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 132. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 30 85C 25C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 280 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Standby Supply Current Figure 133. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 455 kHz RESONATOR, WATCHDOG TIMER DISABLED 70 60 ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 134. Standby Supply Current vs. VCC (1 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 1 MHz RESONATOR, WATCHDOG TIMER DISABLED 60 50 ICC (uA) 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 281 2513L-AVR-03/2013 Figure 135. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 2 MHz XTAL, WATCHDOG TIMER DISABLED 90 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 136. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 2 MHz XTAL, WATCHDOG TIMER DISABLED 90 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 282 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 137. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 4 MHz RESONATOR, WATCHDOG TIMER DISABLED 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 138. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 4 MHz XTAL, WATCHDOG TIMER DISABLED 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 283 2513L-AVR-03/2013 Figure 139. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 6 MHz RESONATOR, WATCHDOG TIMER DISABLED 180 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 140. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 6 MHz XTAL, WATCHDOG TIMER DISABLED 200 180 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 284 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Pin Pull-up Figure 141. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 160 85C 140 25C 120 -40C IIO (uA) 100 80 60 40 20 0 0 1 2 3 4 5 6 VIO (V) Figure 142. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 80 85C 25C 70 -40C 60 IIO (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VIO (V) 285 2513L-AVR-03/2013 Figure 143. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 1.8V 60 50 85C 25C IOP (uA) 40 -40C 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 144. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 120 -40C 25C 100 85C IRESET (uA) 80 60 40 20 0 0 1 2 3 4 5 6 VRESET (V) 286 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 145. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 -40C 25C 50 85C IRESET (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 146. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 1.8V 40 -40C 35 25C 30 85C IRESET (uA) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) 287 2513L-AVR-03/2013 Pin Driver Strength Figure 147. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 80 -40C 70 25C IOH (mA) 60 85C 50 40 30 20 10 0 0 1 2 3 4 5 6 VOH (V) Figure 148. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40C 25 25C 85C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) 288 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 149. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) -40C I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 8 25C 7 85C 6 IOH (mA) 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Figure 150. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 -40C 80 70 25C IOL (mA) 60 85C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) 289 2513L-AVR-03/2013 Figure 151. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 35 -40C 30 25C IOL (mA) 25 85C 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 152. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 12 -40C 10 25C 8 IOL (mA) 85C 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) 290 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Pin Thresholds and Hysteresis Figure 153. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as "1") I/O PIN INPUT THRESHOLD VOLTAGE vs. V CC VIH, I/O PIN READ AS '1' 3 85C 25C -40C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 154. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as "0") I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, I/O PIN READ AS '0' 3 85C 25C -40C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 291 2513L-AVR-03/2013 Figure 155. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.6 -40C 0.5 25C Threshold (V) 0.4 85C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 156. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as "1") RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 3 2.5 Threshold (V) 2 -40C 1.5 25C 85C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 292 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 157. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as "0") RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 Threshold (V) 2 1.5 1 0.5 85C 25C -40C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 158. Reset Input Pin Hysteresis vs. VCC RESET INPUT PIN HYSTERESIS vs. VCC 0.7 -40C 0.6 Threshold (V) 0.5 25C 0.4 0.3 85C 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 293 2513L-AVR-03/2013 BOD Thresholds and Analog Comparator Offset Figure 159. BOD Thresholds vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3V 4.6 4.5 Rising VCC Threshold (V) 4.4 Falling VCC 4.3 4.2 4.1 4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 90 100 Temperature (C) Figure 160. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 3 2.9 Rising VCC Threshold (V) 2.8 Falling VCC 2.7 2.6 2.5 2.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) 294 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 161. BOD Thresholds vs. Temperature (BOD Level is 2.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.3V 2.6 2.5 Rising VCC Threshold (V) 2.4 Falling VCC 2.3 2.2 2.1 2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 90 100 Temperature (C) Figure 162. BOD Thresholds vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V 2.1 2 Rising VCC Threshold (V) 1.9 1.8 Falling VCC 1.7 1.6 1.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) 295 2513L-AVR-03/2013 Figure 163. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. VCC 1.14 Bandgap Voltage (V) 1.13 1.12 1.11 85C 25C -40C 1.1 1.09 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 164. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V 0.01 85C Comparator Offset Voltage (V) 0.009 25C 0.008 -40C 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) 296 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 165. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V 0.006 85C Comparator Offset Voltage (V) 0.005 25C 0.004 -40C 0.003 0.002 0.001 0 -0.001 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Internal Oscillator Speed Figure 166. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1300 -40C 25C 85C 1250 FRC (kHz) 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 297 2513L-AVR-03/2013 Figure 167. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.4 5.5V 4.0V 2.7V 1.8V 8.3 8.2 FRC (MHz) 8.1 8 7.9 7.8 7.7 7.6 7.5 -60 -40 -20 0 20 40 60 80 100 Ta (C) Figure 168. Calibrated 8 MHz RC Oscillator Frequency vs.VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 10 9.5 9 FRC (MHz) 8.5 85C 25C 8 -40C 7.5 7 6.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 298 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 169. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 16 14 FRC (MHz) 12 10 8 6 4 0 16 32 48 64 80 96 112 OSCCAL VALUE Current Consumption of Peripheral Units Figure 170. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 35 -40C 85C 25C 30 25 ICC (uA) 20 15 10 5 0 -5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 299 2513L-AVR-03/2013 Figure 171. 32 kHz TOSC Current vs. VCC (Watchdog Timer Disabled) 32kHz TOSC CURRENT vs. VCC WATCHDOG TIMER DISABLED 30 85C 25C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 172. Watchdog TImer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 20 85C 25C -40C 18 16 14 ICC (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 300 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 173. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 80 70 -40C 60 25C 85C ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 174. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 25 -40C 20 25C ICC (mA) 15 85C 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 301 2513L-AVR-03/2013 Current Consumption in Reset and Reset Pulsewidth Figure 175. Reset Supply Current vs. Frequency (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 4.5 5.5V ICC (mA) 4 3.5 5.0V 3 4.5V 4.0V 2.5 3.3V 2 2.7V 1.5 1.8V 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 176. Reset Supply Current vs. Frequency (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 35 5.5V 30 5.0V ICC (mA) 25 4.5V 20 4.0V 15 10 3.3V 5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 302 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Figure 177. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. VCC 2500 Pulsewidth (ns) 2000 1500 1000 500 85C 25C -40C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 303 2513L-AVR-03/2013 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved - - - - - - - - 304 .. Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - (0x9C) Reserved - - - - - - - - (0x9B) Reserved - - - - - - - - (0x9A) Reserved - - - - - - - - (0x99) Reserved - - - - - - - - (0x98) Reserved - - - - - - - - (0x97) Reserved - - - - - - - - (0x96) Reserved - - - - - - - - (0x95) Reserved - - - - - - - - (0x94) Reserved - - - - - - - - (0x93) Reserved - - - - - - - - (0x92) Reserved - - - - - - - - (0x91) Reserved - - - - - - - - (0x90) Reserved - - - - - - - - (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 FOC3A FOC3B WGM31 WGM30 (0x8A) TCCR3B ICNC3 ICES3 - WGM33 WGM32 CS32 CS31 CS30 (0x89) TCNT3H Page 131 128 Timer/Counter3 - Counter Register High Byte 133 133 (0x88) TCNT3L Timer/Counter3 - Counter Register Low Byte (0x87) OCR3AH Timer/Counter3 - Output Compare Register A High Byte 133 (0x86) OCR3AL Timer/Counter3 - Output Compare Register A Low Byte 133 (0x85) OCR3BH Timer/Counter3 - Output Compare Register B High Byte 133 (0x84) OCR3BL Timer/Counter3 - Output Compare Register B Low Byte 133 (0x83) Reserved - - - - - - - - (0x82) Reserved - - - - - - - - (0x81) ICR3H Timer/Counter3 - Input Capture Register High Byte (0x80) ICR3L Timer/Counter3 - Input Capture Register Low Byte (0x7F) Reserved - - - - - 134 134 - - - (0x7E) Reserved - - - - - - - - (0x7D) ETIMSK - - TICIE3 OCIE3A OCIE3B TOIE3 - - 135 (0x7C) ETIFR - - ICF3 OCF3A OCF3B TOV3 - - 135 (0x7B) Reserved - - - - - - - - (0x7A) Reserved - - - - - - - - (0x79) Reserved - - - - - - - - (0x78) Reserved - - - - - - - - (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) Reserved - - - - - - - - (0x72) Reserved - - - - - - - - (0x71) Reserved - - - - - - - - (0x70) Reserved - - - - - - - - (0x6F) Reserved - - - - - - - - (0x6E) Reserved - - - - - - - - (0x6D) Reserved - - - - - - - - (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 88 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 88 (0x6A) Reserved - - - - - - - - (0x69) Reserved - - - - - - - - (0x68) Reserved - - - - - - - - (0x67) Reserved - - - - - - - - (0x66) Reserved - - - - - - - - (0x65) Reserved - - - - - - - - (0x64) Reserved - - - - - - - - (0x63) Reserved - - - - - - - - (0x62) Reserved - - - - - - - - (0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 41 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x60) Reserved - - - - - - - - 0x3F (0x5F) SREG I T H S V N Z C 10 0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 13 SP6 SP5 SP4 SP3 SP2 SP1 UBRR1[11:8] SP0 0x3D (0x5D) (2) (2) 0x3C (0x5C) Page SPL SP7 UBRR1H URSEL1 UCSR1C URSEL1 UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 189 GICR INT1 INT0 INT2 PCIE1 PCIE0 - IVSEL IVCE 61, 86 0x3B (0x5B) 13 190 0x3A (0x5A) GIFR INTF1 INTF0 INTF2 PCIF1 PCIF0 - - - 87 0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 102, 134, 154 103, 135, 155 0x38 (0x58) TIFR TOV1 OCF1A OCF1B OCF2 ICF1 TOV2 TOV0 OCF0 0x37 (0x57) SPMCR SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN 221 0x36 (0x56) EMCUCR SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 30,44,85 0x35 (0x55) MCUCR SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 30,43,84 0x34 (0x54) MCUCSR JTD - SM2 JTRF WDRF BORF EXTRF PORF 43,51,207 0x33 (0x53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 0x32 (0x52) 0x31 (0x51) TCNT0 0x30 (0x50) SFIOR TSM XMBK XMM2 XMM1 Timer/Counter0 (8 Bits) OCR0 100 102 Timer/Counter0 Output Compare Register 102 XMM0 PUD PSR2 PSR310 32,70,105,156 128 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 0x2E (0x4E) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 0x2D (0x4D) TCNT1H Timer/Counter1 - Counter Register High Byte 131 133 0x2C (0x4C) TCNT1L Timer/Counter1 - Counter Register Low Byte 133 0x2B (0x4B) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 133 0x2A (0x4A) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 133 0x29 (0x49) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 133 0x28 (0x48) OCR1BL 0x27 (0x47) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 149 - - - - AS2 TCN2UB OCR2UB TCR2UB 152 Timer/Counter1 - Output Compare Register B Low Byte 133 0x26 (0x46) ASSR 0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte 0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 134 0x23 (0x43) TCNT2 Timer/Counter2 (8 Bits) 151 0x22 (0x42) OCR2 0x21 (0x41) WDTCR - - - WDCE UBRR0H URSEL0 - - - (2) 0x20 (0x40) (2) 134 Timer/Counter2 Output Compare Register WDE 151 WDP2 WDP1 WDP0 UBRR0[11:8] 53 190 UCSR0C URSEL0 UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 189 0x1F (0x3F) EEARH - - - - - - - EEAR8 20 0x1E (0x3E) EEARL EEPROM Address Register Low Byte 20 0x1D (0x3D) EEDR EEPROM Data Register 21 0x1C (0x3C) EECR - - - - EERIE EEMWE EEWE EERE 0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 21 82 0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 82 0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 82 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 82 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 82 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 82 0x15 (0x35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 82 0x14 (0x34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 82 0x13 (0x33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 83 0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 83 0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 83 0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 0x0F (0x2F) SPDR SPI Data Register 83 164 0x0E (0x2E) SPSR SPIF WCOL - - - - - SPI2X 164 0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 162 0x0C (0x2C) UDR0 0x0B (0x2B) UCSR0A RXC0 TXC0 UDRE0 186 0x0A (0x2A) UCSR0B RXCIE0 TXCIE0 UDRIE0 0x09 (0x29) UBRR0L USART0 I/O Data Register 186 FE0 DOR0 UPE0 U2X0 MPCM0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 USART0 Baud Rate Register Low Byte 187 190 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 0x07 (0x27) PORTE - - - - - PORTE2 PORTE1 PORTE0 83 0x06 (0x26) DDRE - - - - - DDE2 DDE1 DDE0 83 PINE - - - - - PINE2 PINE1 PINE0 83 OSCCAL - CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 39 0x05 (0x25) 0x04(1) (0x24)(1) OCDR On-chip Debug Register 0x03 (0x23) UDR1 USART1 I/O Data Register 0x02 (0x22) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 195 202 186 UPE1 U2X1 MPCM1 186 305 2513L-AVR-03/2013 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x01 (0x21) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 187 0x00 (0x20) UBRR1L Notes: 306 USART1 Baud Rate Register Low Byte 190 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. ATmega162/V 2513L-AVR-03/2013 ATmega162/V Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 1 AND Rd, Rr Logical AND Registers Rd Rd Rr Z,N,V ANDI Rd, K Logical AND Register and Constant Rd Rd K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One's Complement Rd 0xFF Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd x Rr) << Z,C 2 FMULS Rd, Rr Fractional Multiply Signed Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 Z,C 2 Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC Z None 2 3 BRANCH INSTRUCTIONS RJMP k IJMP JMP k Direct Jump PC k None RCALL k Relative Subroutine Call PC PC + k + 1 None 3 Indirect Call to (Z) PC Z None 3 ICALL Direct Subroutine Call PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I if (Rd = Rr) PC PC + 2 or 3 None CALL k 4 CPSE Rd,Rr Compare, Skip if Equal 1/2/3 CP Rd,Rr Compare Rd Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd Rr C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 307 2513L-AVR-03/2013 Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd Rr Rd+1:Rd Rr+1:Rr LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 2 LD Rd, Y Load Indirect Rd (Y) None LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 2 LDS Rd, k Load Direct from SRAM Rd (k) None ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Store Program Memory (Z) R1:R0 None - In Port Rd P None 1 SPM IN Rd, P OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 1 SEC Set Carry C1 C CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I 0 I 1 1 SES Set Signed Test Flag S1 S CLS Clear Signed Test Flag S0 S 1 SEV Set Twos Complement Overflow. V1 V 1 CLV Clear Twos Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH Set Half Carry Flag in SREG H1 H 1 308 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Mnemonics Operands CLH Description Operation Clear Half Carry Flag in SREG H0 Flags #Clocks H 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1 BREAK Break For On-chip Debug Only None N/A 309 2513L-AVR-03/2013 Ordering Information Speed (MHz) 8(3) (4) 16 Notes: Package(1) Operation Range 1.8 - 5.5V ATmega162V-8AU ATmega162V-8PU ATmega162V-8MU 44A 40P6 44M1 Industrial (-40C to 85C) 2.7 - 5.5V ATmega162-16AU ATmega162-16PU ATmega162-16MU 44A 40P6 44M1 Industrial (-40C to 85C) Power Supply Ordering Code(2) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. See Figure 113 on page 266. 4. See Figure 114 on page 266. Package Type 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (QFN/MLF) 310 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Packaging Information 44A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0~7 A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 - 0.45 C 0.09 - 0.20 L 0.45 - 0.75 e NOTE Note 2 Note 2 0.80 TYP 2010-10-20 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (TQFP) DRAWING NO. REV. 44A C 311 2513L-AVR-03/2013 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0 ~ 15 C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A - - 4.826 A1 0.381 - - D 52.070 - 52.578 E 15.240 - 15.875 E1 13.462 - 13.970 B 0.356 - 0.559 B1 1.041 - 1.651 L 3.048 - 3.556 C 0.203 - 0.381 eB 15.494 - 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). e NOTE Note 2 Note 2 2.540 TYP 09/28/01 R 312 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B ATmega162/V 2513L-AVR-03/2013 ATmega162/V 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 - 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. NOTE 0.50 BSC L 0.59 0.64 0.69 K 0.20 0.26 0.41 9/26/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 44M1, 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (VQFN) GPC ZWS DRAWING NO. REV. 44M1 H 313 2513L-AVR-03/2013 Errata The revision letter in this section refers to the revision of the ATmega162 device. ATmega162, all rev. There are no errata for this revision of ATmega162. However, a proposal for solving problems regarding the JTAG instruction IDCODE is presented below. * IDCODE masks data from TDI input * Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request * Interrupts may be lost when writing the timer register in asynchronous timer 1. IDCODE masks data from TDI input The public but optional JTAG instruction IDCODE is not implemented correctly according to IEEE1149.1; a logic one is scanned into the shift register instead of the TDI input while shifting the Device ID Register. Hence, captured data from the preceding devices in the boundary scan chain are lost and replaced by all-ones, and data to succeeding devices are replaced by all-ones during Update-DR. If ATmega162 is the only device in the scan chain, the problem is not visible. Problem Fix / Workaround Select the Device ID Register of the ATmega162 (Either by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller) to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Note that data to succeeding devices cannot be entered during this scan, but data to preceding devices can. Issue the BYPASS instruction to the ATmega162 to select its Bypass Register while reading the Device ID Registers of preceding devices of the boundary scan chain. Never read data from succeeding devices in the boundary scan chain or upload data to the succeeding devices while the Device ID Register is selected for the ATmega162. Note that the IDCODE instruction is the default instruction selected by the Test-Logic-Reset state of the TAP-controller. Alternative Problem Fix / Workaround If the Device IDs of all devices in the boundary scan chain must be captured simultaneously (for instance if blind interrogation is used), the boundary scan chain can be connected in such way that the ATmega162 is the first device in the chain. Update-DR will still not work for the succeeding devices in the boundary scan chain as long as IDCODE is present in the JTAG Instruction Register, but the Device ID registered cannot be uploaded in any case. 2. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. 3. Interrupts may be lost when writing the timer register in asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix / Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 314 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 1. Updated "Ordering Information" on page 310: Removed -AI, -PI and -MI ordering codes. Only Pb-free package options are available. 2513K-08/07 to Rev. 2513L-03/13 Changes from Rev. 1. Updated "Errata" on page 314. 2513J-08/07 to 2. Updated the last page with Atmel's new addresses. Rev. 2513K-07/09 Changes from Rev. 1. Updated "Features" on page 1. 2513I-04/07 to Rev. 2. Added "Data Retention" on page 7. 2513J-08/07 3. Updated "Errata" on page 314. 4. Updated "Version" on page 205. 5. Updated "C Code Example(1)" on page 172. 6. Updated Figure 18 on page 35. 7. Updated "Clock Distribution" on page 35. 8. Updated "SPI Serial Programming Algorithm" on page 246. 9. Updated "Slave Mode" on page 162. Changes from Rev. 1. Updated "Using all 64KB Locations of External Memory" on page 34. 2513H-04/06 to 2. Updated "Bit 6 - ACBG: Analog Comparator Bandgap Select" on page 195. Rev. 2513I-04/07 3. Updated VOH conditions in"DC Characteristics" on page 264. Changes from Rev. 1. Added "Resources" on page 7. 2513G-03/05 to 2. Updated "Calibrated Internal RC Oscillator" on page 38. Rev. 2513H-04/06 3. Updated note for Table 19 on page 50. 4. Updated "Serial Peripheral Interface - SPI" on page 157. Changes from Rev. 1. MLF-package alternative changed to "Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF". 2513F-09/03 to Rev. 2513G-03/05 2. Updated "Electrical Characteristics" on page 264 3. Updated "Ordering Information" on page 310 315 2513L-AVR-03/2013 Changes from Rev. 1. Removed "Preliminary" from the datasheet. 2513D-04/03 to 2. Added note on Figure 1 on page 2. Rev. 2513E-09/03 3. Renamed and updated "On-chip Debug System" to "JTAG Interface and On-chip Debug System" on page 46. 4. Updated Table 18 on page 48 and Table 19 on page 50. 5. Updated "Test Access Port - TAP" on page 197 regarding JTAGEN. 6. Updated description for the JTD bit on page 207. 7. Added note on JTAGEN in Table 99 on page 233. 8. Updated Absolute Maximum Ratings* and DC Characteristics in "Electrical Characteristics" on page 264. 9. Added a proposal for solving problems regarding the JTAG instruction IDCODE in "Errata" on page 314. Changes from Rev. 1. Updated the "Ordering Information" on page 310 and "Packaging Information" on page 311. 2513C-09/02 to Rev. 2513D-04/03 2. Updated "Features" on page 1. 3. Added characterization plots under "ATmega162 Typical Characteristics" on page 275. 4. Added Chip Erase as a first step under "Programming the Flash" on page 260 and "Programming the EEPROM" on page 262. 5. Changed CAL7, the highest bit in the OSCCAL Register, to a reserved bit on page 39 and in "Register Summary" on page 304. 6. Changed CPCE to CLKPCE on page 41. 7. Corrected code examples on page 55. 8. Corrected OCn waveforms in Figure 52 on page 120. 9. Various minor Timer1 corrections. 10. Added note under "Filling the Temporary Buffer (Page Loading)" on page 224 about writing to the EEPROM during an SPM Page Load. 11. Added section "EEPROM Write During Power-down Sleep Mode" on page 24. 12. Added information about PWM symmetry for Timer0 on page 98 and Timer2 on page 147. 13. Updated Table 18 on page 48, Table 20 on page 50, Table 36 on page 77, Table 83 on page 205, Table 109 on page 247, Table 112 on page 267, and Table 113 on page 268. 316 ATmega162/V 2513L-AVR-03/2013 ATmega162/V 14. Added Figures for "Absolute Maximum Frequency as a function of VCC, ATmega162" on page 266. 15. Updated Figure 29 on page 64, Figure 32 on page 68, and Figure 88 on page 210. 16. Removed Table 114, "External RC Oscillator, Typical Frequencies(1)," on page 265. 17. Updated "Electrical Characteristics" on page 264. Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. 2513B-09/02 to Rev. 2513C-09/02 Changes from Rev. 1. Added information for ATmega162U. 2513A-05/02 to Information about ATmega162U included in "Features" on page 1, Table 19, "BODLEVEL Fuse Coding," on page 50, and "Ordering Information" on page 310. Rev. 2513B-09/02 317 2513L-AVR-03/2013 318 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Table of Contents Features 1 Pin Configurations 2 Disclaimer 2 Overview 3 Block Diagram 3 ATmega161 and ATmega162 Compatibility 4 Pin Descriptions 5 Resources 7 Data Retention 7 About Code Examples 8 AVR CPU Core 9 Introduction 9 Architectural Overview 9 ALU - Arithmetic Logic Unit 10 Status Register 10 General Purpose Register File 12 Stack Pointer 13 Instruction Execution Timing 14 Reset and Interrupt Handling 14 AVR ATmega162 Memories 17 In-System Reprogrammable Flash Program Memory 17 SRAM Data Memory 18 EEPROM Data Memory 19 I/O Memory 25 External Memory Interface 26 XMEM Register Description 30 System Clock and Clock Options 35 Clock Systems and their Distribution 35 Clock Sources 36 Default Clock Source 36 Crystal Oscillator 36 Low-frequency Crystal Oscillator 38 Calibrated Internal RC Oscillator 38 External Clock 40 Clock output buffer 40 Timer/Counter Oscillator 41 1 2513L-AVR-03/2013 System Clock Prescaler 41 Power Management and Sleep Modes 43 Idle Mode 44 Power-down Mode 44 Power-save Mode 45 Standby Mode 45 Extended Standby Mode 45 Minimizing Power Consumption 46 System Control and Reset 47 Internal Voltage Reference 52 Watchdog Timer 52 Timed Sequences for Changing the Configuration of the Watchdog Timer 56 Interrupts 57 Interrupt Vectors in ATmega162 57 I/O-Ports 63 Introduction 63 Ports as General Digital I/O 63 Alternate Port Functions 68 Register Description for I/O-Ports 82 External Interrupts 84 8-bit Timer/Counter0 with PWM 89 Overview 89 Timer/Counter Clock Sources 90 Counter Unit 91 Output Compare Unit 91 Compare Match Output Unit 93 Modes of Operation 94 Timer/Counter Timing Diagrams 98 8-bit Timer/Counter Register Description 100 Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers 104 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 106 Restriction in ATmega161 Compatibility Mode 106 Overview 106 Accessing 16-bit Registers 109 Timer/Counter Clock Sources 112 Counter Unit 112 Input Capture Unit 113 Output Compare Units 114 2 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Compare Match Output Unit 117 Modes of Operation 118 Timer/Counter Timing Diagrams 126 16-bit Timer/Counter Register Description 128 8-bit Timer/Counter2 with PWM and Asynchronous operation 138 Overview 138 Timer/Counter Clock Sources 139 Counter Unit 140 Output Compare Unit 140 Compare Match Output Unit 142 Modes of Operation 143 Timer/Counter Timing Diagrams 147 8-bit Timer/Counter Register Description 149 Asynchronous operation of the Timer/Counter 152 Timer/Counter Prescaler 156 Serial Peripheral Interface - SPI 157 SS Pin Functionality 162 Data Modes 165 USART 166 Dual USART 166 Clock Generation 168 Frame Formats 171 USART Initialization 172 Data Transmission - The USART Transmitter 173 Data Reception - The USART Receiver 175 Asynchronous Data Reception 179 Multi-processor Communication Mode 182 Accessing UBRRH/ UCSRC Registers 184 USART Register Description 186 Examples of Baud Rate Setting 191 Analog Comparator 195 JTAG Interface and On-chip Debug System 197 Features 197 Overview 197 Test Access Port - TAP 197 TAP Controller 200 Using the Boundary-scan Chain 200 Using the On-chip Debug system 201 On-chip debug specific JTAG instructions 202 On-chip Debug Related Register in I/O Memory 202 3 2513L-AVR-03/2013 Using the JTAG Programming Capabilities 202 Bibliography 203 IEEE 1149.1 (JTAG) Boundary-scan 204 Features 204 System Overview 204 Data Registers 205 Boundary-scan Specific JTAG Instructions 206 Boundary-scan Chain 208 ATmega162 Boundary-scan Order 213 Boundary-scan Description Language Files 216 Boot Loader Support - Read-While-Write Self-programming 217 Features 217 Application and Boot Loader Flash Sections 217 Read-While-Write and No Read-While-Write Flash Sections 217 Boot Loader Lock Bits 219 Entering the Boot Loader Program 221 Addressing the Flash During Self-programming 223 Self-programming the Flash 224 Memory Programming 231 Program And Data Memory Lock Bits 231 Fuse Bits 232 Signature Bytes 234 Calibration Byte 234 Parallel Programming Parameters, Pin Mapping, and Commands 234 Parallel Programming 236 Serial Downloading 245 SPI Serial Programming Pin Mapping 245 Programming via the JTAG Interface 250 Electrical Characteristics 264 Absolute Maximum Ratings* 264 DC Characteristics 264 External Clock Drive Waveforms 267 External Clock Drive 267 SPI Timing Characteristics 268 External Data Memory Timing 270 ATmega162 Typical Characteristics 275 Register Summary 304 Instruction Set Summary 307 4 ATmega162/V 2513L-AVR-03/2013 ATmega162/V Ordering Information 310 Packaging Information 311 44A 311 40P6 312 44M1 313 Errata 314 ATmega162, all rev. 314 Datasheet Revision History 315 Changes from Rev. 2513K-08/07 to Rev. 2513L-03/13 315 Changes from Rev. 2513J-08/07 to Rev. 2513K-07/09 315 Changes from Rev. 2513I-04/07 to Rev. 2513J-08/07 315 Changes from Rev. 2513H-04/06 to Rev. 2513I-04/07 315 Changes from Rev. 2513G-03/05 to Rev. 2513H-04/06 315 Changes from Rev. 2513F-09/03 to Rev. 2513G-03/05 315 Changes from Rev. 2513D-04/03 to Rev. 2513E-09/03 316 Changes from Rev. 2513C-09/02 to Rev. 2513D-04/03 316 Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02 317 Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02 317 5 2513L-AVR-03/2013 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. 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